drivers/spi/spi-ti-qspi.c

   1 /*
   2  * TI QSPI driver
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  * Author: Sourav Poddar <sourav.poddar@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GPLv2.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/device.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/omap-dma.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/err.h>
  27 #include <linux/clk.h>
  28 #include <linux/io.h>
  29 #include <linux/slab.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/pinctrl/consumer.h>
  34
  35 #include <linux/spi/spi.h>
  36
  37 struct ti_qspi_regs {
  38         u32 clkctrl;
  39 };
  40
  41 struct ti_qspi {
  42         struct completion       transfer_complete;
  43
  44         /* list synchronization */
  45         struct mutex            list_lock;
  46
  47         struct spi_master       *master;
  48         void __iomem            *base;
  49         struct clk              *fclk;
  50         struct device           *dev;
  51
  52         struct ti_qspi_regs     ctx_reg;
  53
  54         u32 spi_max_frequency;
  55         u32 cmd;
  56         u32 dc;
  57 };
  58
  59 #define QSPI_PID                        (0x0)
  60 #define QSPI_SYSCONFIG                  (0x10)
  61 #define QSPI_INTR_STATUS_RAW_SET        (0x20)
  62 #define QSPI_INTR_STATUS_ENABLED_CLEAR  (0x24)
  63 #define QSPI_INTR_ENABLE_SET_REG        (0x28)
  64 #define QSPI_INTR_ENABLE_CLEAR_REG      (0x2c)
  65 #define QSPI_SPI_CLOCK_CNTRL_REG        (0x40)
  66 #define QSPI_SPI_DC_REG                 (0x44)
  67 #define QSPI_SPI_CMD_REG                (0x48)
  68 #define QSPI_SPI_STATUS_REG             (0x4c)
  69 #define QSPI_SPI_DATA_REG               (0x50)
  70 #define QSPI_SPI_SETUP0_REG             (0x54)
  71 #define QSPI_SPI_SWITCH_REG             (0x64)
  72 #define QSPI_SPI_SETUP1_REG             (0x58)
  73 #define QSPI_SPI_SETUP2_REG             (0x5c)
  74 #define QSPI_SPI_SETUP3_REG             (0x60)
  75 #define QSPI_SPI_DATA_REG_1             (0x68)
  76 #define QSPI_SPI_DATA_REG_2             (0x6c)
  77 #define QSPI_SPI_DATA_REG_3             (0x70)
  78
  79 #define QSPI_COMPLETION_TIMEOUT         msecs_to_jiffies(2000)
  80
  81 #define QSPI_FCLK                       192000000
  82
  83 /* Clock Control */
  84 #define QSPI_CLK_EN                     (1 << 31)
  85 #define QSPI_CLK_DIV_MAX                0xffff
  86
  87 /* Command */
  88 #define QSPI_EN_CS(n)                   (n << 28)
  89 #define QSPI_WLEN(n)                    ((n - 1) << 19)
  90 #define QSPI_3_PIN                      (1 << 18)
  91 #define QSPI_RD_SNGL                    (1 << 16)
  92 #define QSPI_WR_SNGL                    (2 << 16)
  93 #define QSPI_RD_DUAL                    (3 << 16)
  94 #define QSPI_RD_QUAD                    (7 << 16)
  95 #define QSPI_INVAL                      (4 << 16)
  96 #define QSPI_WC_CMD_INT_EN                      (1 << 14)
  97 #define QSPI_FLEN(n)                    ((n - 1) << 0)
  98
  99 /* STATUS REGISTER */
 100 #define WC                              0x02
 101
 102 /* INTERRUPT REGISTER */
 103 #define QSPI_WC_INT_EN                          (1 << 1)
 104 #define QSPI_WC_INT_DISABLE                     (1 << 1)
 105
 106 /* Device Control */
 107 #define QSPI_DD(m, n)                   (m << (3 + n * 8))
 108 #define QSPI_CKPHA(n)                   (1 << (2 + n * 8))
 109 #define QSPI_CSPOL(n)                   (1 << (1 + n * 8))
 110 #define QSPI_CKPOL(n)                   (1 << (n * 8))
 111
 112 #define QSPI_FRAME                      4096
 113
 114 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
 115
 116 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
 117                 unsigned long reg)
 118 {
 119         return readl(qspi->base + reg);
 120 }
 121
 122 static inline void ti_qspi_write(struct ti_qspi *qspi,
 123                 unsigned long val, unsigned long reg)
 124 {
 125         writel(val, qspi->base + reg);
 126 }
 127
 128 static int ti_qspi_setup(struct spi_device *spi)
 129 {
 130         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 131         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
 132         int clk_div = 0, ret;
 133         u32 clk_ctrl_reg, clk_rate, clk_mask;
 134
 135         if (spi->master->busy) {
 136                 dev_dbg(qspi->dev, "master busy doing other trasnfers\n");
 137                 return -EBUSY;
 138         }
 139
 140         if (!qspi->spi_max_frequency) {
 141                 dev_err(qspi->dev, "spi max frequency not defined\n");
 142                 return -EINVAL;
 143         }
 144
 145         clk_rate = clk_get_rate(qspi->fclk);
 146
 147         clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
 148
 149         if (clk_div < 0) {
 150                 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
 151                 return -EINVAL;
 152         }
 153
 154         if (clk_div > QSPI_CLK_DIV_MAX) {
 155                 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
 156                                 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
 157                 return -EINVAL;
 158         }
 159
 160         dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
 161                         qspi->spi_max_frequency, clk_div);
 162
 163         ret = pm_runtime_get_sync(qspi->dev);
 164         if (ret < 0) {
 165                 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
 166                 return ret;
 167         }
 168
 169         clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
 170
 171         clk_ctrl_reg &= ~QSPI_CLK_EN;
 172
 173         /* disable SCLK */
 174         ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
 175
 176         /* enable SCLK */
 177         clk_mask = QSPI_CLK_EN | clk_div;
 178         ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
 179         ctx_reg->clkctrl = clk_mask;
 180
 181         pm_runtime_mark_last_busy(qspi->dev);
 182         ret = pm_runtime_put_autosuspend(qspi->dev);
 183         if (ret < 0) {
 184                 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
 185                 return ret;
 186         }
 187
 188         return 0;
 189 }
 190
 191 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
 192 {
 193         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
 194
 195         ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
 196 }
 197
 198 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
 199 {
 200         int wlen, count, ret;
 201         unsigned int cmd;
 202         const u8 *txbuf;
 203
 204         txbuf = t->tx_buf;
 205         cmd = qspi->cmd | QSPI_WR_SNGL;
 206         count = t->len;
 207         wlen = t->bits_per_word;
 208
 209         while (count) {
 210                 switch (wlen) {
 211                 case 8:
 212                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
 213                                         cmd, qspi->dc, *txbuf);
 214                         writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
 215                         ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
 216                         ret = wait_for_completion_timeout(&qspi->transfer_complete,
 217                                         QSPI_COMPLETION_TIMEOUT);
 218                         if (ret == 0) {
 219                                 dev_err(qspi->dev, "write timed out\n");
 220                                 return -ETIMEDOUT;
 221                         }
 222                         txbuf += 1;
 223                         count -= 1;
 224                         break;
 225                 case 16:
 226                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
 227                                         cmd, qspi->dc, *txbuf);
 228                         writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
 229                         ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
 230                         ret = wait_for_completion_timeout(&qspi->transfer_complete,
 231                                 QSPI_COMPLETION_TIMEOUT);
 232                         if (ret == 0) {
 233                                 dev_err(qspi->dev, "write timed out\n");
 234                                 return -ETIMEDOUT;
 235                         }
 236                         txbuf += 2;
 237                         count -= 2;
 238                         break;
 239                 case 32:
 240                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
 241                                         cmd, qspi->dc, *txbuf);
 242                         writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
 243                         ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
 244                         ret = wait_for_completion_timeout(&qspi->transfer_complete,
 245                                 QSPI_COMPLETION_TIMEOUT);
 246                         if (ret == 0) {
 247                                 dev_err(qspi->dev, "write timed out\n");
 248                                 return -ETIMEDOUT;
 249                         }
 250                         txbuf += 4;
 251                         count -= 4;
 252                         break;
 253                 }
 254         }
 255
 256         return 0;
 257 }
 258
 259 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
 260 {
 261         int wlen, count, ret;
 262         unsigned int cmd;
 263         u8 *rxbuf;
 264
 265         rxbuf = t->rx_buf;
 266         cmd = qspi->cmd;
 267         switch (t->rx_nbits) {
 268         case SPI_NBITS_DUAL:
 269                 cmd |= QSPI_RD_DUAL;
 270                 break;
 271         case SPI_NBITS_QUAD:
 272                 cmd |= QSPI_RD_QUAD;
 273                 break;
 274         default:
 275                 cmd |= QSPI_RD_SNGL;
 276                 break;
 277         }
 278         count = t->len;
 279         wlen = t->bits_per_word;
 280
 281         while (count) {
 282                 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
 283                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
 284                 ret = wait_for_completion_timeout(&qspi->transfer_complete,
 285                                 QSPI_COMPLETION_TIMEOUT);
 286                 if (ret == 0) {
 287                         dev_err(qspi->dev, "read timed out\n");
 288                         return -ETIMEDOUT;
 289                 }
 290                 switch (wlen) {
 291                 case 8:
 292                         *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
 293                         rxbuf += 1;
 294                         count -= 1;
 295                         break;
 296                 case 16:
 297                         *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
 298                         rxbuf += 2;
 299                         count -= 2;
 300                         break;
 301                 case 32:
 302                         *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
 303                         rxbuf += 4;
 304                         count -= 4;
 305                         break;
 306                 }
 307         }
 308
 309         return 0;
 310 }
 311
 312 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t)
 313 {
 314         int ret;
 315
 316         if (t->tx_buf) {
 317                 ret = qspi_write_msg(qspi, t);
 318                 if (ret) {
 319                         dev_dbg(qspi->dev, "Error while writing\n");
 320                         return ret;
 321                 }
 322         }
 323
 324         if (t->rx_buf) {
 325                 ret = qspi_read_msg(qspi, t);
 326                 if (ret) {
 327                         dev_dbg(qspi->dev, "Error while reading\n");
 328                         return ret;
 329                 }
 330         }
 331
 332         return 0;
 333 }
 334
 335 static int ti_qspi_start_transfer_one(struct spi_master *master,
 336                 struct spi_message *m)
 337 {
 338         struct ti_qspi *qspi = spi_master_get_devdata(master);
 339         struct spi_device *spi = m->spi;
 340         struct spi_transfer *t;
 341         int status = 0, ret;
 342         int frame_length;
 343
 344         /* setup device control reg */
 345         qspi->dc = 0;
 346
 347         if (spi->mode & SPI_CPHA)
 348                 qspi->dc |= QSPI_CKPHA(spi->chip_select);
 349         if (spi->mode & SPI_CPOL)
 350                 qspi->dc |= QSPI_CKPOL(spi->chip_select);
 351         if (spi->mode & SPI_CS_HIGH)
 352                 qspi->dc |= QSPI_CSPOL(spi->chip_select);
 353
 354         frame_length = (m->frame_length << 3) / spi->bits_per_word;
 355
 356         frame_length = clamp(frame_length, 0, QSPI_FRAME);
 357
 358         /* setup command reg */
 359         qspi->cmd = 0;
 360         qspi->cmd |= QSPI_EN_CS(spi->chip_select);
 361         qspi->cmd |= QSPI_FLEN(frame_length);
 362         qspi->cmd |= QSPI_WC_CMD_INT_EN;
 363
 364         ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
 365         ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
 366
 367         mutex_lock(&qspi->list_lock);
 368
 369         list_for_each_entry(t, &m->transfers, transfer_list) {
 370                 qspi->cmd |= QSPI_WLEN(t->bits_per_word);
 371
 372                 ret = qspi_transfer_msg(qspi, t);
 373                 if (ret) {
 374                         dev_dbg(qspi->dev, "transfer message failed\n");
 375                         mutex_unlock(&qspi->list_lock);
 376                         return -EINVAL;
 377                 }
 378
 379                 m->actual_length += t->len;
 380         }
 381
 382         mutex_unlock(&qspi->list_lock);
 383
 384         m->status = status;
 385         spi_finalize_current_message(master);
 386
 387         ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
 388
 389         return status;
 390 }
 391
 392 static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
 393 {
 394         struct ti_qspi *qspi = dev_id;
 395         u16 int_stat;
 396         u32 stat;
 397
 398         irqreturn_t ret = IRQ_HANDLED;
 399
 400         int_stat = ti_qspi_read(qspi, QSPI_INTR_STATUS_ENABLED_CLEAR);
 401         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 402
 403         if (!int_stat) {
 404                 dev_dbg(qspi->dev, "No IRQ triggered\n");
 405                 ret = IRQ_NONE;
 406                 goto out;
 407         }
 408
 409         ti_qspi_write(qspi, QSPI_WC_INT_DISABLE,
 410                                 QSPI_INTR_STATUS_ENABLED_CLEAR);
 411         if (stat & WC)
 412                 complete(&qspi->transfer_complete);
 413 out:
 414         return ret;
 415 }
 416
 417 static int ti_qspi_runtime_resume(struct device *dev)
 418 {
 419         struct ti_qspi      *qspi;
 420         struct spi_master       *master;
 421
 422         master = dev_get_drvdata(dev);
 423         qspi = spi_master_get_devdata(master);
 424         ti_qspi_restore_ctx(qspi);
 425
 426         return 0;
 427 }
 428
 429 static const struct of_device_id ti_qspi_match[] = {
 430         {.compatible = "ti,dra7xxx-qspi" },
 431         {.compatible = "ti,am4372-qspi" },
 432         {},
 433 };
 434 MODULE_DEVICE_TABLE(of, ti_qspi_match);
 435
 436 static int ti_qspi_probe(struct platform_device *pdev)
 437 {
 438         struct  ti_qspi *qspi;
 439         struct spi_master *master;
 440         struct resource         *r;
 441         struct device_node *np = pdev->dev.of_node;
 442         u32 max_freq;
 443         int ret = 0, num_cs, irq;
 444
 445         master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
 446         if (!master)
 447                 return -ENOMEM;
 448
 449         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
 450
 451         master->bus_num = -1;
 452         master->flags = SPI_MASTER_HALF_DUPLEX;
 453         master->setup = ti_qspi_setup;
 454         master->auto_runtime_pm = true;
 455         master->transfer_one_message = ti_qspi_start_transfer_one;
 456         master->dev.of_node = pdev->dev.of_node;
 457         master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
 458
 459         if (!of_property_read_u32(np, "num-cs", &num_cs))
 460                 master->num_chipselect = num_cs;
 461
 462         qspi = spi_master_get_devdata(master);
 463         qspi->master = master;
 464         qspi->dev = &pdev->dev;
 465         platform_set_drvdata(pdev, qspi);
 466
 467         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 468
 469         irq = platform_get_irq(pdev, 0);
 470         if (irq < 0) {
 471                 dev_err(&pdev->dev, "no irq resource?\n");
 472                 return irq;
 473         }
 474
 475         mutex_init(&qspi->list_lock);
 476
 477         qspi->base = devm_ioremap_resource(&pdev->dev, r);
 478         if (IS_ERR(qspi->base)) {
 479                 ret = PTR_ERR(qspi->base);
 480                 goto free_master;
 481         }
 482
 483         ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0,
 484                         dev_name(&pdev->dev), qspi);
 485         if (ret < 0) {
 486                 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
 487                                 irq);
 488                 goto free_master;
 489         }
 490
 491         qspi->fclk = devm_clk_get(&pdev->dev, "fck");
 492         if (IS_ERR(qspi->fclk)) {
 493                 ret = PTR_ERR(qspi->fclk);
 494                 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
 495         }
 496
 497         init_completion(&qspi->transfer_complete);
 498
 499         pm_runtime_use_autosuspend(&pdev->dev);
 500         pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
 501         pm_runtime_enable(&pdev->dev);
 502
 503         if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
 504                 qspi->spi_max_frequency = max_freq;
 505
 506         ret = devm_spi_register_master(&pdev->dev, master);
 507         if (ret)
 508                 goto free_master;
 509
 510         return 0;
 511
 512 free_master:
 513         spi_master_put(master);
 514         return ret;
 515 }
 516
 517 static int ti_qspi_remove(struct platform_device *pdev)
 518 {
 519         struct spi_master *master;
 520         struct ti_qspi *qspi;
 521         int ret;
 522
 523         master = platform_get_drvdata(pdev);
 524         qspi = spi_master_get_devdata(master);
 525
 526         ret = pm_runtime_get_sync(qspi->dev);
 527         if (ret < 0) {
 528                 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
 529                 return ret;
 530         }
 531
 532         ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG);
 533
 534         pm_runtime_put(qspi->dev);
 535         pm_runtime_disable(&pdev->dev);
 536
 537         spi_unregister_master(master);
 538
 539         return 0;
 540 }
 541
 542 static const struct dev_pm_ops ti_qspi_pm_ops = {
 543         .runtime_resume = ti_qspi_runtime_resume,
 544 };
 545
 546 static struct platform_driver ti_qspi_driver = {
 547         .probe  = ti_qspi_probe,
 548         .remove = ti_qspi_remove,
 549         .driver = {
 550                 .name   = "ti,dra7xxx-qspi",
 551                 .owner  = THIS_MODULE,
 552                 .pm =   &ti_qspi_pm_ops,
 553                 .of_match_table = ti_qspi_match,
 554         }
 555 };
 556
 557 module_platform_driver(ti_qspi_driver);
 558
 559 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
 560 MODULE_LICENSE("GPL v2");
 561 MODULE_DESCRIPTION("TI QSPI controller driver");