drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  *  $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
  15  */
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/sched.h>
  20 #include <linux/string.h>
  21 #include <linux/kernel.h>
  22 #include <linux/slab.h>
  23 #include <linux/delay.h>
  24 #include <linux/tty.h>
  25 #include <linux/serial_core.h>
  26 #include <linux/8250_pci.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/byteorder.h>
  30 #include <asm/io.h>
  31
  32 #include "8250.h"
  33
  34 #undef SERIAL_DEBUG_PCI
  35
  36 /*
  37  * init function returns:
  38  *  > 0 - number of ports
  39  *  = 0 - use board->num_ports
  40  *  < 0 - error
  41  */
  42 struct pci_serial_quirk {
  43         u32     vendor;
  44         u32     device;
  45         u32     subvendor;
  46         u32     subdevice;
  47         int     (*init)(struct pci_dev *dev);
  48         int     (*setup)(struct serial_private *, struct pciserial_board *,
  49                          struct uart_port *, int);
  50         void    (*exit)(struct pci_dev *dev);
  51 };
  52
  53 #define PCI_NUM_BAR_RESOURCES   6
  54
  55 struct serial_private {
  56         struct pci_dev          *dev;
  57         unsigned int            nr;
  58         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  59         struct pci_serial_quirk *quirk;
  60         int                     line[0];
  61 };
  62
  63 static void moan_device(const char *str, struct pci_dev *dev)
  64 {
  65         printk(KERN_WARNING "%s: %s\n"
  66                KERN_WARNING "Please send the output of lspci -vv, this\n"
  67                KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  68                KERN_WARNING "manufacturer and name of serial board or\n"
  69                KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
  70                pci_name(dev), str, dev->vendor, dev->device,
  71                dev->subsystem_vendor, dev->subsystem_device);
  72 }
  73
  74 static int
  75 setup_port(struct serial_private *priv, struct uart_port *port,
  76            int bar, int offset, int regshift)
  77 {
  78         struct pci_dev *dev = priv->dev;
  79         unsigned long base, len;
  80
  81         if (bar >= PCI_NUM_BAR_RESOURCES)
  82                 return -EINVAL;
  83
  84         base = pci_resource_start(dev, bar);
  85
  86         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  87                 len =  pci_resource_len(dev, bar);
  88
  89                 if (!priv->remapped_bar[bar])
  90                         priv->remapped_bar[bar] = ioremap(base, len);
  91                 if (!priv->remapped_bar[bar])
  92                         return -ENOMEM;
  93
  94                 port->iotype = UPIO_MEM;
  95                 port->iobase = 0;
  96                 port->mapbase = base + offset;
  97                 port->membase = priv->remapped_bar[bar] + offset;
  98                 port->regshift = regshift;
  99         } else {
 100                 port->iotype = UPIO_PORT;
 101                 port->iobase = base + offset;
 102                 port->mapbase = 0;
 103                 port->membase = NULL;
 104                 port->regshift = 0;
 105         }
 106         return 0;
 107 }
 108
 109 /*
 110  * AFAVLAB uses a different mixture of BARs and offsets
 111  * Not that ugly ;) -- HW
 112  */
 113 static int
 114 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
 115               struct uart_port *port, int idx)
 116 {
 117         unsigned int bar, offset = board->first_offset;
 118
 119         bar = FL_GET_BASE(board->flags);
 120         if (idx < 4)
 121                 bar += idx;
 122         else {
 123                 bar = 4;
 124                 offset += (idx - 4) * board->uart_offset;
 125         }
 126
 127         return setup_port(priv, port, bar, offset, board->reg_shift);
 128 }
 129
 130 /*
 131  * HP's Remote Management Console.  The Diva chip came in several
 132  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 133  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 134  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 135  * one Diva chip, but it has been expanded to 5 UARTs.
 136  */
 137 static int pci_hp_diva_init(struct pci_dev *dev)
 138 {
 139         int rc = 0;
 140
 141         switch (dev->subsystem_device) {
 142         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 143         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 144         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 145         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 146                 rc = 3;
 147                 break;
 148         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 149                 rc = 2;
 150                 break;
 151         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 152                 rc = 4;
 153                 break;
 154         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 155         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 156                 rc = 1;
 157                 break;
 158         }
 159
 160         return rc;
 161 }
 162
 163 /*
 164  * HP's Diva chip puts the 4th/5th serial port further out, and
 165  * some serial ports are supposed to be hidden on certain models.
 166  */
 167 static int
 168 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
 169               struct uart_port *port, int idx)
 170 {
 171         unsigned int offset = board->first_offset;
 172         unsigned int bar = FL_GET_BASE(board->flags);
 173
 174         switch (priv->dev->subsystem_device) {
 175         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 176                 if (idx == 3)
 177                         idx++;
 178                 break;
 179         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 180                 if (idx > 0)
 181                         idx++;
 182                 if (idx > 2)
 183                         idx++;
 184                 break;
 185         }
 186         if (idx > 2)
 187                 offset = 0x18;
 188
 189         offset += idx * board->uart_offset;
 190
 191         return setup_port(priv, port, bar, offset, board->reg_shift);
 192 }
 193
 194 /*
 195  * Added for EKF Intel i960 serial boards
 196  */
 197 static int pci_inteli960ni_init(struct pci_dev *dev)
 198 {
 199         unsigned long oldval;
 200
 201         if (!(dev->subsystem_device & 0x1000))
 202                 return -ENODEV;
 203
 204         /* is firmware started? */
 205         pci_read_config_dword(dev, 0x44, (void*) &oldval);
 206         if (oldval == 0x00001000L) { /* RESET value */
 207                 printk(KERN_DEBUG "Local i960 firmware missing");
 208                 return -ENODEV;
 209         }
 210         return 0;
 211 }
 212
 213 /*
 214  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 215  * that the card interrupt be explicitly enabled or disabled.  This
 216  * seems to be mainly needed on card using the PLX which also use I/O
 217  * mapped memory.
 218  */
 219 static int pci_plx9050_init(struct pci_dev *dev)
 220 {
 221         u8 irq_config;
 222         void __iomem *p;
 223
 224         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 225                 moan_device("no memory in bar 0", dev);
 226                 return 0;
 227         }
 228
 229         irq_config = 0x41;
 230         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 231             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
 232                 irq_config = 0x43;
 233         }
 234         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 235             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
 236                 /*
 237                  * As the megawolf cards have the int pins active
 238                  * high, and have 2 UART chips, both ints must be
 239                  * enabled on the 9050. Also, the UARTS are set in
 240                  * 16450 mode by default, so we have to enable the
 241                  * 16C950 'enhanced' mode so that we can use the
 242                  * deep FIFOs
 243                  */
 244                 irq_config = 0x5b;
 245         }
 246
 247         /*
 248          * enable/disable interrupts
 249          */
 250         p = ioremap(pci_resource_start(dev, 0), 0x80);
 251         if (p == NULL)
 252                 return -ENOMEM;
 253         writel(irq_config, p + 0x4c);
 254
 255         /*
 256          * Read the register back to ensure that it took effect.
 257          */
 258         readl(p + 0x4c);
 259         iounmap(p);
 260
 261         return 0;
 262 }
 263
 264 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 265 {
 266         u8 __iomem *p;
 267
 268         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 269                 return;
 270
 271         /*
 272          * disable interrupts
 273          */
 274         p = ioremap(pci_resource_start(dev, 0), 0x80);
 275         if (p != NULL) {
 276                 writel(0, p + 0x4c);
 277
 278                 /*
 279                  * Read the register back to ensure that it took effect.
 280                  */
 281                 readl(p + 0x4c);
 282                 iounmap(p);
 283         }
 284 }
 285
 286 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 287 static int
 288 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
 289                 struct uart_port *port, int idx)
 290 {
 291         unsigned int bar, offset = board->first_offset;
 292
 293         bar = 0;
 294
 295         if (idx < 4) {
 296                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 297                 offset += idx * board->uart_offset;
 298         } else if (idx < 8) {
 299                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 300                 offset += idx * board->uart_offset + 0xC00;
 301         } else /* we have only 8 ports on PMC-OCTALPRO */
 302                 return 1;
 303
 304         return setup_port(priv, port, bar, offset, board->reg_shift);
 305 }
 306
 307 /*
 308 * This does initialization for PMC OCTALPRO cards:
 309 * maps the device memory, resets the UARTs (needed, bc
 310 * if the module is removed and inserted again, the card
 311 * is in the sleep mode) and enables global interrupt.
 312 */
 313
 314 /* global control register offset for SBS PMC-OctalPro */
 315 #define OCT_REG_CR_OFF          0x500
 316
 317 static int sbs_init(struct pci_dev *dev)
 318 {
 319         u8 __iomem *p;
 320
 321         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 322
 323         if (p == NULL)
 324                 return -ENOMEM;
 325         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 326         writeb(0x10,p + OCT_REG_CR_OFF);
 327         udelay(50);
 328         writeb(0x0,p + OCT_REG_CR_OFF);
 329
 330         /* Set bit-2 (INTENABLE) of Control Register */
 331         writeb(0x4, p + OCT_REG_CR_OFF);
 332         iounmap(p);
 333
 334         return 0;
 335 }
 336
 337 /*
 338  * Disables the global interrupt of PMC-OctalPro
 339  */
 340
 341 static void __devexit sbs_exit(struct pci_dev *dev)
 342 {
 343         u8 __iomem *p;
 344
 345         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 346         if (p != NULL) {
 347                 writeb(0, p + OCT_REG_CR_OFF);
 348         }
 349         iounmap(p);
 350 }
 351
 352 /*
 353  * SIIG serial cards have an PCI interface chip which also controls
 354  * the UART clocking frequency. Each UART can be clocked independently
 355  * (except cards equiped with 4 UARTs) and initial clocking settings
 356  * are stored in the EEPROM chip. It can cause problems because this
 357  * version of serial driver doesn't support differently clocked UART's
 358  * on single PCI card. To prevent this, initialization functions set
 359  * high frequency clocking for all UART's on given card. It is safe (I
 360  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 361  * with other OSes (like M$ DOS).
 362  *
 363  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 364  *
 365  * There is two family of SIIG serial cards with different PCI
 366  * interface chip and different configuration methods:
 367  *     - 10x cards have control registers in IO and/or memory space;
 368  *     - 20x cards have control registers in standard PCI configuration space.
 369  *
 370  * Note: all 10x cards have PCI device ids 0x10..
 371  *       all 20x cards have PCI device ids 0x20..
 372  *
 373  * There are also Quartet Serial cards which use Oxford Semiconductor
 374  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 375  *
 376  * Note: some SIIG cards are probed by the parport_serial object.
 377  */
 378
 379 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 380 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 381
 382 static int pci_siig10x_init(struct pci_dev *dev)
 383 {
 384         u16 data;
 385         void __iomem *p;
 386
 387         switch (dev->device & 0xfff8) {
 388         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 389                 data = 0xffdf;
 390                 break;
 391         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 392                 data = 0xf7ff;
 393                 break;
 394         default:                        /* 1S1P, 4S */
 395                 data = 0xfffb;
 396                 break;
 397         }
 398
 399         p = ioremap(pci_resource_start(dev, 0), 0x80);
 400         if (p == NULL)
 401                 return -ENOMEM;
 402
 403         writew(readw(p + 0x28) & data, p + 0x28);
 404         readw(p + 0x28);
 405         iounmap(p);
 406         return 0;
 407 }
 408
 409 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 410 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 411
 412 static int pci_siig20x_init(struct pci_dev *dev)
 413 {
 414         u8 data;
 415
 416         /* Change clock frequency for the first UART. */
 417         pci_read_config_byte(dev, 0x6f, &data);
 418         pci_write_config_byte(dev, 0x6f, data & 0xef);
 419
 420         /* If this card has 2 UART, we have to do the same with second UART. */
 421         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 422             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 423                 pci_read_config_byte(dev, 0x73, &data);
 424                 pci_write_config_byte(dev, 0x73, data & 0xef);
 425         }
 426         return 0;
 427 }
 428
 429 static int pci_siig_init(struct pci_dev *dev)
 430 {
 431         unsigned int type = dev->device & 0xff00;
 432
 433         if (type == 0x1000)
 434                 return pci_siig10x_init(dev);
 435         else if (type == 0x2000)
 436                 return pci_siig20x_init(dev);
 437
 438         moan_device("Unknown SIIG card", dev);
 439         return -ENODEV;
 440 }
 441
 442 static int pci_siig_setup(struct serial_private *priv,
 443                           struct pciserial_board *board,
 444                           struct uart_port *port, int idx)
 445 {
 446         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 447
 448         if (idx > 3) {
 449                 bar = 4;
 450                 offset = (idx - 4) * 8;
 451         }
 452
 453         return setup_port(priv, port, bar, offset, 0);
 454 }
 455
 456 /*
 457  * Timedia has an explosion of boards, and to avoid the PCI table from
 458  * growing *huge*, we use this function to collapse some 70 entries
 459  * in the PCI table into one, for sanity's and compactness's sake.
 460  */
 461 static const unsigned short timedia_single_port[] = {
 462         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 463 };
 464
 465 static const unsigned short timedia_dual_port[] = {
 466         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 467         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 468         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 469         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 470         0xD079, 0
 471 };
 472
 473 static const unsigned short timedia_quad_port[] = {
 474         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 475         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 476         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 477         0xB157, 0
 478 };
 479
 480 static const unsigned short timedia_eight_port[] = {
 481         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 482         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 483 };
 484
 485 static const struct timedia_struct {
 486         int num;
 487         const unsigned short *ids;
 488 } timedia_data[] = {
 489         { 1, timedia_single_port },
 490         { 2, timedia_dual_port },
 491         { 4, timedia_quad_port },
 492         { 8, timedia_eight_port }
 493 };
 494
 495 static int pci_timedia_init(struct pci_dev *dev)
 496 {
 497         const unsigned short *ids;
 498         int i, j;
 499
 500         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 501                 ids = timedia_data[i].ids;
 502                 for (j = 0; ids[j]; j++)
 503                         if (dev->subsystem_device == ids[j])
 504                                 return timedia_data[i].num;
 505         }
 506         return 0;
 507 }
 508
 509 /*
 510  * Timedia/SUNIX uses a mixture of BARs and offsets
 511  * Ugh, this is ugly as all hell --- TYT
 512  */
 513 static int
 514 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
 515                   struct uart_port *port, int idx)
 516 {
 517         unsigned int bar = 0, offset = board->first_offset;
 518
 519         switch (idx) {
 520         case 0:
 521                 bar = 0;
 522                 break;
 523         case 1:
 524                 offset = board->uart_offset;
 525                 bar = 0;
 526                 break;
 527         case 2:
 528                 bar = 1;
 529                 break;
 530         case 3:
 531                 offset = board->uart_offset;
 532                 /* FALLTHROUGH */
 533         case 4: /* BAR 2 */
 534         case 5: /* BAR 3 */
 535         case 6: /* BAR 4 */
 536         case 7: /* BAR 5 */
 537                 bar = idx - 2;
 538         }
 539
 540         return setup_port(priv, port, bar, offset, board->reg_shift);
 541 }
 542
 543 /*
 544  * Some Titan cards are also a little weird
 545  */
 546 static int
 547 titan_400l_800l_setup(struct serial_private *priv,
 548                       struct pciserial_board *board,
 549                       struct uart_port *port, int idx)
 550 {
 551         unsigned int bar, offset = board->first_offset;
 552
 553         switch (idx) {
 554         case 0:
 555                 bar = 1;
 556                 break;
 557         case 1:
 558                 bar = 2;
 559                 break;
 560         default:
 561                 bar = 4;
 562                 offset = (idx - 2) * board->uart_offset;
 563         }
 564
 565         return setup_port(priv, port, bar, offset, board->reg_shift);
 566 }
 567
 568 static int pci_xircom_init(struct pci_dev *dev)
 569 {
 570         msleep(100);
 571         return 0;
 572 }
 573
 574 static int pci_netmos_init(struct pci_dev *dev)
 575 {
 576         /* subdevice 0x00PS means <P> parallel, <S> serial */
 577         unsigned int num_serial = dev->subsystem_device & 0xf;
 578
 579         if (num_serial == 0)
 580                 return -ENODEV;
 581         return num_serial;
 582 }
 583
 584 static int
 585 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
 586                   struct uart_port *port, int idx)
 587 {
 588         unsigned int bar, offset = board->first_offset, maxnr;
 589
 590         bar = FL_GET_BASE(board->flags);
 591         if (board->flags & FL_BASE_BARS)
 592                 bar += idx;
 593         else
 594                 offset += idx * board->uart_offset;
 595
 596         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
 597                 (board->reg_shift + 3);
 598
 599         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 600                 return 1;
 601
 602         return setup_port(priv, port, bar, offset, board->reg_shift);
 603 }
 604
 605 /* This should be in linux/pci_ids.h */
 606 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
 607 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
 608 #define PCI_DEVICE_ID_OCTPRO            0x0001
 609 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
 610 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
 611 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
 612 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
 613
 614 /*
 615  * Master list of serial port init/setup/exit quirks.
 616  * This does not describe the general nature of the port.
 617  * (ie, baud base, number and location of ports, etc)
 618  *
 619  * This list is ordered alphabetically by vendor then device.
 620  * Specific entries must come before more generic entries.
 621  */
 622 static struct pci_serial_quirk pci_serial_quirks[] = {
 623         /*
 624          * AFAVLAB cards - these may be called via parport_serial
 625          *  It is not clear whether this applies to all products.
 626          */
 627         {
 628                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
 629                 .device         = PCI_ANY_ID,
 630                 .subvendor      = PCI_ANY_ID,
 631                 .subdevice      = PCI_ANY_ID,
 632                 .setup          = afavlab_setup,
 633         },
 634         /*
 635          * HP Diva
 636          */
 637         {
 638                 .vendor         = PCI_VENDOR_ID_HP,
 639                 .device         = PCI_DEVICE_ID_HP_DIVA,
 640                 .subvendor      = PCI_ANY_ID,
 641                 .subdevice      = PCI_ANY_ID,
 642                 .init           = pci_hp_diva_init,
 643                 .setup          = pci_hp_diva_setup,
 644         },
 645         /*
 646          * Intel
 647          */
 648         {
 649                 .vendor         = PCI_VENDOR_ID_INTEL,
 650                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
 651                 .subvendor      = 0xe4bf,
 652                 .subdevice      = PCI_ANY_ID,
 653                 .init           = pci_inteli960ni_init,
 654                 .setup          = pci_default_setup,
 655         },
 656         /*
 657          * Panacom
 658          */
 659         {
 660                 .vendor         = PCI_VENDOR_ID_PANACOM,
 661                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
 662                 .subvendor      = PCI_ANY_ID,
 663                 .subdevice      = PCI_ANY_ID,
 664                 .init           = pci_plx9050_init,
 665                 .setup          = pci_default_setup,
 666                 .exit           = __devexit_p(pci_plx9050_exit),
 667         },
 668         {
 669                 .vendor         = PCI_VENDOR_ID_PANACOM,
 670                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
 671                 .subvendor      = PCI_ANY_ID,
 672                 .subdevice      = PCI_ANY_ID,
 673                 .init           = pci_plx9050_init,
 674                 .setup          = pci_default_setup,
 675                 .exit           = __devexit_p(pci_plx9050_exit),
 676         },
 677         /*
 678          * PLX
 679          */
 680         {
 681                 .vendor         = PCI_VENDOR_ID_PLX,
 682                 .device         = PCI_DEVICE_ID_PLX_9030,
 683                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
 684                 .subdevice      = PCI_ANY_ID,
 685                 .setup          = pci_default_setup,
 686         },
 687         {
 688                 .vendor         = PCI_VENDOR_ID_PLX,
 689                 .device         = PCI_DEVICE_ID_PLX_9050,
 690                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
 691                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
 692                 .init           = pci_plx9050_init,
 693                 .setup          = pci_default_setup,
 694                 .exit           = __devexit_p(pci_plx9050_exit),
 695         },
 696         {
 697                 .vendor         = PCI_VENDOR_ID_PLX,
 698                 .device         = PCI_DEVICE_ID_PLX_9050,
 699                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
 700                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
 701                 .init           = pci_plx9050_init,
 702                 .setup          = pci_default_setup,
 703                 .exit           = __devexit_p(pci_plx9050_exit),
 704         },
 705         {
 706                 .vendor         = PCI_VENDOR_ID_PLX,
 707                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
 708                 .subvendor      = PCI_VENDOR_ID_PLX,
 709                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
 710                 .init           = pci_plx9050_init,
 711                 .setup          = pci_default_setup,
 712                 .exit           = __devexit_p(pci_plx9050_exit),
 713         },
 714         /*
 715          * SBS Technologies, Inc., PMC-OCTALPRO 232
 716          */
 717         {
 718                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 719                 .device         = PCI_DEVICE_ID_OCTPRO,
 720                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 721                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
 722                 .init           = sbs_init,
 723                 .setup          = sbs_setup,
 724                 .exit           = __devexit_p(sbs_exit),
 725         },
 726         /*
 727          * SBS Technologies, Inc., PMC-OCTALPRO 422
 728          */
 729         {
 730                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 731                 .device         = PCI_DEVICE_ID_OCTPRO,
 732                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 733                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
 734                 .init           = sbs_init,
 735                 .setup          = sbs_setup,
 736                 .exit           = __devexit_p(sbs_exit),
 737         },
 738         /*
 739          * SBS Technologies, Inc., P-Octal 232
 740          */
 741         {
 742                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 743                 .device         = PCI_DEVICE_ID_OCTPRO,
 744                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 745                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
 746                 .init           = sbs_init,
 747                 .setup          = sbs_setup,
 748                 .exit           = __devexit_p(sbs_exit),
 749         },
 750         /*
 751          * SBS Technologies, Inc., P-Octal 422
 752          */
 753         {
 754                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 755                 .device         = PCI_DEVICE_ID_OCTPRO,
 756                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 757                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
 758                 .init           = sbs_init,
 759                 .setup          = sbs_setup,
 760                 .exit           = __devexit_p(sbs_exit),
 761         },
 762         /*
 763          * SIIG cards - these may be called via parport_serial
 764          */
 765         {
 766                 .vendor         = PCI_VENDOR_ID_SIIG,
 767                 .device         = PCI_ANY_ID,
 768                 .subvendor      = PCI_ANY_ID,
 769                 .subdevice      = PCI_ANY_ID,
 770                 .init           = pci_siig_init,
 771                 .setup          = pci_siig_setup,
 772         },
 773         /*
 774          * Titan cards
 775          */
 776         {
 777                 .vendor         = PCI_VENDOR_ID_TITAN,
 778                 .device         = PCI_DEVICE_ID_TITAN_400L,
 779                 .subvendor      = PCI_ANY_ID,
 780                 .subdevice      = PCI_ANY_ID,
 781                 .setup          = titan_400l_800l_setup,
 782         },
 783         {
 784                 .vendor         = PCI_VENDOR_ID_TITAN,
 785                 .device         = PCI_DEVICE_ID_TITAN_800L,
 786                 .subvendor      = PCI_ANY_ID,
 787                 .subdevice      = PCI_ANY_ID,
 788                 .setup          = titan_400l_800l_setup,
 789         },
 790         /*
 791          * Timedia cards
 792          */
 793         {
 794                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 795                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
 796                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
 797                 .subdevice      = PCI_ANY_ID,
 798                 .init           = pci_timedia_init,
 799                 .setup          = pci_timedia_setup,
 800         },
 801         {
 802                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 803                 .device         = PCI_ANY_ID,
 804                 .subvendor      = PCI_ANY_ID,
 805                 .subdevice      = PCI_ANY_ID,
 806                 .setup          = pci_timedia_setup,
 807         },
 808         /*
 809          * Xircom cards
 810          */
 811         {
 812                 .vendor         = PCI_VENDOR_ID_XIRCOM,
 813                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
 814                 .subvendor      = PCI_ANY_ID,
 815                 .subdevice      = PCI_ANY_ID,
 816                 .init           = pci_xircom_init,
 817                 .setup          = pci_default_setup,
 818         },
 819         /*
 820          * Netmos cards - these may be called via parport_serial
 821          */
 822         {
 823                 .vendor         = PCI_VENDOR_ID_NETMOS,
 824                 .device         = PCI_ANY_ID,
 825                 .subvendor      = PCI_ANY_ID,
 826                 .subdevice      = PCI_ANY_ID,
 827                 .init           = pci_netmos_init,
 828                 .setup          = pci_default_setup,
 829         },
 830         /*
 831          * Default "match everything" terminator entry
 832          */
 833         {
 834                 .vendor         = PCI_ANY_ID,
 835                 .device         = PCI_ANY_ID,
 836                 .subvendor      = PCI_ANY_ID,
 837                 .subdevice      = PCI_ANY_ID,
 838                 .setup          = pci_default_setup,
 839         }
 840 };
 841
 842 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
 843 {
 844         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
 845 }
 846
 847 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
 848 {
 849         struct pci_serial_quirk *quirk;
 850
 851         for (quirk = pci_serial_quirks; ; quirk++)
 852                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
 853                     quirk_id_matches(quirk->device, dev->device) &&
 854                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
 855                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
 856                         break;
 857         return quirk;
 858 }
 859
 860 static inline int get_pci_irq(struct pci_dev *dev,
 861                                 struct pciserial_board *board)
 862 {
 863         if (board->flags & FL_NOIRQ)
 864                 return 0;
 865         else
 866                 return dev->irq;
 867 }
 868
 869 /*
 870  * This is the configuration table for all of the PCI serial boards
 871  * which we support.  It is directly indexed by the pci_board_num_t enum
 872  * value, which is encoded in the pci_device_id PCI probe table's
 873  * driver_data member.
 874  *
 875  * The makeup of these names are:
 876  *  pbn_bn{_bt}_n_baud{_offsetinhex}
 877  *
 878  *  bn          = PCI BAR number
 879  *  bt          = Index using PCI BARs
 880  *  n           = number of serial ports
 881  *  baud        = baud rate
 882  *  offsetinhex = offset for each sequential port (in hex)
 883  *
 884  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
 885  *
 886  * Please note: in theory if n = 1, _bt infix should make no difference.
 887  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
 888  */
 889 enum pci_board_num_t {
 890         pbn_default = 0,
 891
 892         pbn_b0_1_115200,
 893         pbn_b0_2_115200,
 894         pbn_b0_4_115200,
 895         pbn_b0_5_115200,
 896
 897         pbn_b0_1_921600,
 898         pbn_b0_2_921600,
 899         pbn_b0_4_921600,
 900
 901         pbn_b0_2_1130000,
 902
 903         pbn_b0_4_1152000,
 904
 905         pbn_b0_2_1843200,
 906         pbn_b0_4_1843200,
 907
 908         pbn_b0_2_1843200_200,
 909         pbn_b0_4_1843200_200,
 910         pbn_b0_8_1843200_200,
 911
 912         pbn_b0_bt_1_115200,
 913         pbn_b0_bt_2_115200,
 914         pbn_b0_bt_8_115200,
 915
 916         pbn_b0_bt_1_460800,
 917         pbn_b0_bt_2_460800,
 918         pbn_b0_bt_4_460800,
 919
 920         pbn_b0_bt_1_921600,
 921         pbn_b0_bt_2_921600,
 922         pbn_b0_bt_4_921600,
 923         pbn_b0_bt_8_921600,
 924
 925         pbn_b1_1_115200,
 926         pbn_b1_2_115200,
 927         pbn_b1_4_115200,
 928         pbn_b1_8_115200,
 929
 930         pbn_b1_1_921600,
 931         pbn_b1_2_921600,
 932         pbn_b1_4_921600,
 933         pbn_b1_8_921600,
 934
 935         pbn_b1_2_1250000,
 936
 937         pbn_b1_bt_2_921600,
 938
 939         pbn_b1_1_1382400,
 940         pbn_b1_2_1382400,
 941         pbn_b1_4_1382400,
 942         pbn_b1_8_1382400,
 943
 944         pbn_b2_1_115200,
 945         pbn_b2_2_115200,
 946         pbn_b2_8_115200,
 947
 948         pbn_b2_1_460800,
 949         pbn_b2_4_460800,
 950         pbn_b2_8_460800,
 951         pbn_b2_16_460800,
 952
 953         pbn_b2_1_921600,
 954         pbn_b2_4_921600,
 955         pbn_b2_8_921600,
 956
 957         pbn_b2_bt_1_115200,
 958         pbn_b2_bt_2_115200,
 959         pbn_b2_bt_4_115200,
 960
 961         pbn_b2_bt_2_921600,
 962         pbn_b2_bt_4_921600,
 963
 964         pbn_b3_2_115200,
 965         pbn_b3_4_115200,
 966         pbn_b3_8_115200,
 967
 968         /*
 969          * Board-specific versions.
 970          */
 971         pbn_panacom,
 972         pbn_panacom2,
 973         pbn_panacom4,
 974         pbn_exsys_4055,
 975         pbn_plx_romulus,
 976         pbn_oxsemi,
 977         pbn_intel_i960,
 978         pbn_sgi_ioc3,
 979         pbn_nec_nile4,
 980         pbn_computone_4,
 981         pbn_computone_6,
 982         pbn_computone_8,
 983         pbn_sbsxrsio,
 984         pbn_exar_XR17C152,
 985         pbn_exar_XR17C154,
 986         pbn_exar_XR17C158,
 987 };
 988
 989 /*
 990  * uart_offset - the space between channels
 991  * reg_shift   - describes how the UART registers are mapped
 992  *               to PCI memory by the card.
 993  * For example IER register on SBS, Inc. PMC-OctPro is located at
 994  * offset 0x10 from the UART base, while UART_IER is defined as 1
 995  * in include/linux/serial_reg.h,
 996  * see first lines of serial_in() and serial_out() in 8250.c
 997 */
 998
 999 static struct pciserial_board pci_boards[] __devinitdata = {
1000         [pbn_default] = {
1001                 .flags          = FL_BASE0,
1002                 .num_ports      = 1,
1003                 .base_baud      = 115200,
1004                 .uart_offset    = 8,
1005         },
1006         [pbn_b0_1_115200] = {
1007                 .flags          = FL_BASE0,
1008                 .num_ports      = 1,
1009                 .base_baud      = 115200,
1010                 .uart_offset    = 8,
1011         },
1012         [pbn_b0_2_115200] = {
1013                 .flags          = FL_BASE0,
1014                 .num_ports      = 2,
1015                 .base_baud      = 115200,
1016                 .uart_offset    = 8,
1017         },
1018         [pbn_b0_4_115200] = {
1019                 .flags          = FL_BASE0,
1020                 .num_ports      = 4,
1021                 .base_baud      = 115200,
1022                 .uart_offset    = 8,
1023         },
1024         [pbn_b0_5_115200] = {
1025                 .flags          = FL_BASE0,
1026                 .num_ports      = 5,
1027                 .base_baud      = 115200,
1028                 .uart_offset    = 8,
1029         },
1030
1031         [pbn_b0_1_921600] = {
1032                 .flags          = FL_BASE0,
1033                 .num_ports      = 1,
1034                 .base_baud      = 921600,
1035                 .uart_offset    = 8,
1036         },
1037         [pbn_b0_2_921600] = {
1038                 .flags          = FL_BASE0,
1039                 .num_ports      = 2,
1040                 .base_baud      = 921600,
1041                 .uart_offset    = 8,
1042         },
1043         [pbn_b0_4_921600] = {
1044                 .flags          = FL_BASE0,
1045                 .num_ports      = 4,
1046                 .base_baud      = 921600,
1047                 .uart_offset    = 8,
1048         },
1049
1050         [pbn_b0_2_1130000] = {
1051                 .flags          = FL_BASE0,
1052                 .num_ports      = 2,
1053                 .base_baud      = 1130000,
1054                 .uart_offset    = 8,
1055         },
1056
1057         [pbn_b0_4_1152000] = {
1058                 .flags          = FL_BASE0,
1059                 .num_ports      = 4,
1060                 .base_baud      = 1152000,
1061                 .uart_offset    = 8,
1062         },
1063
1064         [pbn_b0_2_1843200] = {
1065                 .flags          = FL_BASE0,
1066                 .num_ports      = 2,
1067                 .base_baud      = 1843200,
1068                 .uart_offset    = 8,
1069         },
1070         [pbn_b0_4_1843200] = {
1071                 .flags          = FL_BASE0,
1072                 .num_ports      = 4,
1073                 .base_baud      = 1843200,
1074                 .uart_offset    = 8,
1075         },
1076
1077         [pbn_b0_2_1843200_200] = {
1078                 .flags          = FL_BASE0,
1079                 .num_ports      = 2,
1080                 .base_baud      = 1843200,
1081                 .uart_offset    = 0x200,
1082         },
1083         [pbn_b0_4_1843200_200] = {
1084                 .flags          = FL_BASE0,
1085                 .num_ports      = 4,
1086                 .base_baud      = 1843200,
1087                 .uart_offset    = 0x200,
1088         },
1089         [pbn_b0_8_1843200_200] = {
1090                 .flags          = FL_BASE0,
1091                 .num_ports      = 8,
1092                 .base_baud      = 1843200,
1093                 .uart_offset    = 0x200,
1094         },
1095
1096         [pbn_b0_bt_1_115200] = {
1097                 .flags          = FL_BASE0|FL_BASE_BARS,
1098                 .num_ports      = 1,
1099                 .base_baud      = 115200,
1100                 .uart_offset    = 8,
1101         },
1102         [pbn_b0_bt_2_115200] = {
1103                 .flags          = FL_BASE0|FL_BASE_BARS,
1104                 .num_ports      = 2,
1105                 .base_baud      = 115200,
1106                 .uart_offset    = 8,
1107         },
1108         [pbn_b0_bt_8_115200] = {
1109                 .flags          = FL_BASE0|FL_BASE_BARS,
1110                 .num_ports      = 8,
1111                 .base_baud      = 115200,
1112                 .uart_offset    = 8,
1113         },
1114
1115         [pbn_b0_bt_1_460800] = {
1116                 .flags          = FL_BASE0|FL_BASE_BARS,
1117                 .num_ports      = 1,
1118                 .base_baud      = 460800,
1119                 .uart_offset    = 8,
1120         },
1121         [pbn_b0_bt_2_460800] = {
1122                 .flags          = FL_BASE0|FL_BASE_BARS,
1123                 .num_ports      = 2,
1124                 .base_baud      = 460800,
1125                 .uart_offset    = 8,
1126         },
1127         [pbn_b0_bt_4_460800] = {
1128                 .flags          = FL_BASE0|FL_BASE_BARS,
1129                 .num_ports      = 4,
1130                 .base_baud      = 460800,
1131                 .uart_offset    = 8,
1132         },
1133
1134         [pbn_b0_bt_1_921600] = {
1135                 .flags          = FL_BASE0|FL_BASE_BARS,
1136                 .num_ports      = 1,
1137                 .base_baud      = 921600,
1138                 .uart_offset    = 8,
1139         },
1140         [pbn_b0_bt_2_921600] = {
1141                 .flags          = FL_BASE0|FL_BASE_BARS,
1142                 .num_ports      = 2,
1143                 .base_baud      = 921600,
1144                 .uart_offset    = 8,
1145         },
1146         [pbn_b0_bt_4_921600] = {
1147                 .flags          = FL_BASE0|FL_BASE_BARS,
1148                 .num_ports      = 4,
1149                 .base_baud      = 921600,
1150                 .uart_offset    = 8,
1151         },
1152         [pbn_b0_bt_8_921600] = {
1153                 .flags          = FL_BASE0|FL_BASE_BARS,
1154                 .num_ports      = 8,
1155                 .base_baud      = 921600,
1156                 .uart_offset    = 8,
1157         },
1158
1159         [pbn_b1_1_115200] = {
1160                 .flags          = FL_BASE1,
1161                 .num_ports      = 1,
1162                 .base_baud      = 115200,
1163                 .uart_offset    = 8,
1164         },
1165         [pbn_b1_2_115200] = {
1166                 .flags          = FL_BASE1,
1167                 .num_ports      = 2,
1168                 .base_baud      = 115200,
1169                 .uart_offset    = 8,
1170         },
1171         [pbn_b1_4_115200] = {
1172                 .flags          = FL_BASE1,
1173                 .num_ports      = 4,
1174                 .base_baud      = 115200,
1175                 .uart_offset    = 8,
1176         },
1177         [pbn_b1_8_115200] = {
1178                 .flags          = FL_BASE1,
1179                 .num_ports      = 8,
1180                 .base_baud      = 115200,
1181                 .uart_offset    = 8,
1182         },
1183
1184         [pbn_b1_1_921600] = {
1185                 .flags          = FL_BASE1,
1186                 .num_ports      = 1,
1187                 .base_baud      = 921600,
1188                 .uart_offset    = 8,
1189         },
1190         [pbn_b1_2_921600] = {
1191                 .flags          = FL_BASE1,
1192                 .num_ports      = 2,
1193                 .base_baud      = 921600,
1194                 .uart_offset    = 8,
1195         },
1196         [pbn_b1_4_921600] = {
1197                 .flags          = FL_BASE1,
1198                 .num_ports      = 4,
1199                 .base_baud      = 921600,
1200                 .uart_offset    = 8,
1201         },
1202         [pbn_b1_8_921600] = {
1203                 .flags          = FL_BASE1,
1204                 .num_ports      = 8,
1205                 .base_baud      = 921600,
1206                 .uart_offset    = 8,
1207         },
1208         [pbn_b1_2_1250000] = {
1209                 .flags          = FL_BASE1,
1210                 .num_ports      = 2,
1211                 .base_baud      = 1250000,
1212                 .uart_offset    = 8,
1213         },
1214
1215         [pbn_b1_bt_2_921600] = {
1216                 .flags          = FL_BASE1|FL_BASE_BARS,
1217                 .num_ports      = 2,
1218                 .base_baud      = 921600,
1219                 .uart_offset    = 8,
1220         },
1221
1222         [pbn_b1_1_1382400] = {
1223                 .flags          = FL_BASE1,
1224                 .num_ports      = 1,
1225                 .base_baud      = 1382400,
1226                 .uart_offset    = 8,
1227         },
1228         [pbn_b1_2_1382400] = {
1229                 .flags          = FL_BASE1,
1230                 .num_ports      = 2,
1231                 .base_baud      = 1382400,
1232                 .uart_offset    = 8,
1233         },
1234         [pbn_b1_4_1382400] = {
1235                 .flags          = FL_BASE1,
1236                 .num_ports      = 4,
1237                 .base_baud      = 1382400,
1238                 .uart_offset    = 8,
1239         },
1240         [pbn_b1_8_1382400] = {
1241                 .flags          = FL_BASE1,
1242                 .num_ports      = 8,
1243                 .base_baud      = 1382400,
1244                 .uart_offset    = 8,
1245         },
1246
1247         [pbn_b2_1_115200] = {
1248                 .flags          = FL_BASE2,
1249                 .num_ports      = 1,
1250                 .base_baud      = 115200,
1251                 .uart_offset    = 8,
1252         },
1253         [pbn_b2_2_115200] = {
1254                 .flags          = FL_BASE2,
1255                 .num_ports      = 2,
1256                 .base_baud      = 115200,
1257                 .uart_offset    = 8,
1258         },
1259         [pbn_b2_8_115200] = {
1260                 .flags          = FL_BASE2,
1261                 .num_ports      = 8,
1262                 .base_baud      = 115200,
1263                 .uart_offset    = 8,
1264         },
1265
1266         [pbn_b2_1_460800] = {
1267                 .flags          = FL_BASE2,
1268                 .num_ports      = 1,
1269                 .base_baud      = 460800,
1270                 .uart_offset    = 8,
1271         },
1272         [pbn_b2_4_460800] = {
1273                 .flags          = FL_BASE2,
1274                 .num_ports      = 4,
1275                 .base_baud      = 460800,
1276                 .uart_offset    = 8,
1277         },
1278         [pbn_b2_8_460800] = {
1279                 .flags          = FL_BASE2,
1280                 .num_ports      = 8,
1281                 .base_baud      = 460800,
1282                 .uart_offset    = 8,
1283         },
1284         [pbn_b2_16_460800] = {
1285                 .flags          = FL_BASE2,
1286                 .num_ports      = 16,
1287                 .base_baud      = 460800,
1288                 .uart_offset    = 8,
1289          },
1290
1291         [pbn_b2_1_921600] = {
1292                 .flags          = FL_BASE2,
1293                 .num_ports      = 1,
1294                 .base_baud      = 921600,
1295                 .uart_offset    = 8,
1296         },
1297         [pbn_b2_4_921600] = {
1298                 .flags          = FL_BASE2,
1299                 .num_ports      = 4,
1300                 .base_baud      = 921600,
1301                 .uart_offset    = 8,
1302         },
1303         [pbn_b2_8_921600] = {
1304                 .flags          = FL_BASE2,
1305                 .num_ports      = 8,
1306                 .base_baud      = 921600,
1307                 .uart_offset    = 8,
1308         },
1309
1310         [pbn_b2_bt_1_115200] = {
1311                 .flags          = FL_BASE2|FL_BASE_BARS,
1312                 .num_ports      = 1,
1313                 .base_baud      = 115200,
1314                 .uart_offset    = 8,
1315         },
1316         [pbn_b2_bt_2_115200] = {
1317                 .flags          = FL_BASE2|FL_BASE_BARS,
1318                 .num_ports      = 2,
1319                 .base_baud      = 115200,
1320                 .uart_offset    = 8,
1321         },
1322         [pbn_b2_bt_4_115200] = {
1323                 .flags          = FL_BASE2|FL_BASE_BARS,
1324                 .num_ports      = 4,
1325                 .base_baud      = 115200,
1326                 .uart_offset    = 8,
1327         },
1328
1329         [pbn_b2_bt_2_921600] = {
1330                 .flags          = FL_BASE2|FL_BASE_BARS,
1331                 .num_ports      = 2,
1332                 .base_baud      = 921600,
1333                 .uart_offset    = 8,
1334         },
1335         [pbn_b2_bt_4_921600] = {
1336                 .flags          = FL_BASE2|FL_BASE_BARS,
1337                 .num_ports      = 4,
1338                 .base_baud      = 921600,
1339                 .uart_offset    = 8,
1340         },
1341
1342         [pbn_b3_2_115200] = {
1343                 .flags          = FL_BASE3,
1344                 .num_ports      = 2,
1345                 .base_baud      = 115200,
1346                 .uart_offset    = 8,
1347         },
1348         [pbn_b3_4_115200] = {
1349                 .flags          = FL_BASE3,
1350                 .num_ports      = 4,
1351                 .base_baud      = 115200,
1352                 .uart_offset    = 8,
1353         },
1354         [pbn_b3_8_115200] = {
1355                 .flags          = FL_BASE3,
1356                 .num_ports      = 8,
1357                 .base_baud      = 115200,
1358                 .uart_offset    = 8,
1359         },
1360
1361         /*
1362          * Entries following this are board-specific.
1363          */
1364
1365         /*
1366          * Panacom - IOMEM
1367          */
1368         [pbn_panacom] = {
1369                 .flags          = FL_BASE2,
1370                 .num_ports      = 2,
1371                 .base_baud      = 921600,
1372                 .uart_offset    = 0x400,
1373                 .reg_shift      = 7,
1374         },
1375         [pbn_panacom2] = {
1376                 .flags          = FL_BASE2|FL_BASE_BARS,
1377                 .num_ports      = 2,
1378                 .base_baud      = 921600,
1379                 .uart_offset    = 0x400,
1380                 .reg_shift      = 7,
1381         },
1382         [pbn_panacom4] = {
1383                 .flags          = FL_BASE2|FL_BASE_BARS,
1384                 .num_ports      = 4,
1385                 .base_baud      = 921600,
1386                 .uart_offset    = 0x400,
1387                 .reg_shift      = 7,
1388         },
1389
1390         [pbn_exsys_4055] = {
1391                 .flags          = FL_BASE2,
1392                 .num_ports      = 4,
1393                 .base_baud      = 115200,
1394                 .uart_offset    = 8,
1395         },
1396
1397         /* I think this entry is broken - the first_offset looks wrong --rmk */
1398         [pbn_plx_romulus] = {
1399                 .flags          = FL_BASE2,
1400                 .num_ports      = 4,
1401                 .base_baud      = 921600,
1402                 .uart_offset    = 8 << 2,
1403                 .reg_shift      = 2,
1404                 .first_offset   = 0x03,
1405         },
1406
1407         /*
1408          * This board uses the size of PCI Base region 0 to
1409          * signal now many ports are available
1410          */
1411         [pbn_oxsemi] = {
1412                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
1413                 .num_ports      = 32,
1414                 .base_baud      = 115200,
1415                 .uart_offset    = 8,
1416         },
1417
1418         /*
1419          * EKF addition for i960 Boards form EKF with serial port.
1420          * Max 256 ports.
1421          */
1422         [pbn_intel_i960] = {
1423                 .flags          = FL_BASE0,
1424                 .num_ports      = 32,
1425                 .base_baud      = 921600,
1426                 .uart_offset    = 8 << 2,
1427                 .reg_shift      = 2,
1428                 .first_offset   = 0x10000,
1429         },
1430         [pbn_sgi_ioc3] = {
1431                 .flags          = FL_BASE0|FL_NOIRQ,
1432                 .num_ports      = 1,
1433                 .base_baud      = 458333,
1434                 .uart_offset    = 8,
1435                 .reg_shift      = 0,
1436                 .first_offset   = 0x20178,
1437         },
1438
1439         /*
1440          * NEC Vrc-5074 (Nile 4) builtin UART.
1441          */
1442         [pbn_nec_nile4] = {
1443                 .flags          = FL_BASE0,
1444                 .num_ports      = 1,
1445                 .base_baud      = 520833,
1446                 .uart_offset    = 8 << 3,
1447                 .reg_shift      = 3,
1448                 .first_offset   = 0x300,
1449         },
1450
1451         /*
1452          * Computone - uses IOMEM.
1453          */
1454         [pbn_computone_4] = {
1455                 .flags          = FL_BASE0,
1456                 .num_ports      = 4,
1457                 .base_baud      = 921600,
1458                 .uart_offset    = 0x40,
1459                 .reg_shift      = 2,
1460                 .first_offset   = 0x200,
1461         },
1462         [pbn_computone_6] = {
1463                 .flags          = FL_BASE0,
1464                 .num_ports      = 6,
1465                 .base_baud      = 921600,
1466                 .uart_offset    = 0x40,
1467                 .reg_shift      = 2,
1468                 .first_offset   = 0x200,
1469         },
1470         [pbn_computone_8] = {
1471                 .flags          = FL_BASE0,
1472                 .num_ports      = 8,
1473                 .base_baud      = 921600,
1474                 .uart_offset    = 0x40,
1475                 .reg_shift      = 2,
1476                 .first_offset   = 0x200,
1477         },
1478         [pbn_sbsxrsio] = {
1479                 .flags          = FL_BASE0,
1480                 .num_ports      = 8,
1481                 .base_baud      = 460800,
1482                 .uart_offset    = 256,
1483                 .reg_shift      = 4,
1484         },
1485         /*
1486          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1487          *  Only basic 16550A support.
1488          *  XR17C15[24] are not tested, but they should work.
1489          */
1490         [pbn_exar_XR17C152] = {
1491                 .flags          = FL_BASE0,
1492                 .num_ports      = 2,
1493                 .base_baud      = 921600,
1494                 .uart_offset    = 0x200,
1495         },
1496         [pbn_exar_XR17C154] = {
1497                 .flags          = FL_BASE0,
1498                 .num_ports      = 4,
1499                 .base_baud      = 921600,
1500                 .uart_offset    = 0x200,
1501         },
1502         [pbn_exar_XR17C158] = {
1503                 .flags          = FL_BASE0,
1504                 .num_ports      = 8,
1505                 .base_baud      = 921600,
1506                 .uart_offset    = 0x200,
1507         },
1508 };
1509
1510 /*
1511  * Given a complete unknown PCI device, try to use some heuristics to
1512  * guess what the configuration might be, based on the pitiful PCI
1513  * serial specs.  Returns 0 on success, 1 on failure.
1514  */
1515 static int __devinit
1516 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1517 {
1518         int num_iomem, num_port, first_port = -1, i;
1519
1520         /*
1521          * If it is not a communications device or the programming
1522          * interface is greater than 6, give up.
1523          *
1524          * (Should we try to make guesses for multiport serial devices
1525          * later?)
1526          */
1527         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1528              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1529             (dev->class & 0xff) > 6)
1530                 return -ENODEV;
1531
1532         num_iomem = num_port = 0;
1533         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1534                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1535                         num_port++;
1536                         if (first_port == -1)
1537                                 first_port = i;
1538                 }
1539                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1540                         num_iomem++;
1541         }
1542
1543         /*
1544          * If there is 1 or 0 iomem regions, and exactly one port,
1545          * use it.  We guess the number of ports based on the IO
1546          * region size.
1547          */
1548         if (num_iomem <= 1 && num_port == 1) {
1549                 board->flags = first_port;
1550                 board->num_ports = pci_resource_len(dev, first_port) / 8;
1551                 return 0;
1552         }
1553
1554         /*
1555          * Now guess if we've got a board which indexes by BARs.
1556          * Each IO BAR should be 8 bytes, and they should follow
1557          * consecutively.
1558          */
1559         first_port = -1;
1560         num_port = 0;
1561         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1562                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1563                     pci_resource_len(dev, i) == 8 &&
1564                     (first_port == -1 || (first_port + num_port) == i)) {
1565                         num_port++;
1566                         if (first_port == -1)
1567                                 first_port = i;
1568                 }
1569         }
1570
1571         if (num_port > 1) {
1572                 board->flags = first_port | FL_BASE_BARS;
1573                 board->num_ports = num_port;
1574                 return 0;
1575         }
1576
1577         return -ENODEV;
1578 }
1579
1580 static inline int
1581 serial_pci_matches(struct pciserial_board *board,
1582                    struct pciserial_board *guessed)
1583 {
1584         return
1585             board->num_ports == guessed->num_ports &&
1586             board->base_baud == guessed->base_baud &&
1587             board->uart_offset == guessed->uart_offset &&
1588             board->reg_shift == guessed->reg_shift &&
1589             board->first_offset == guessed->first_offset;
1590 }
1591
1592 struct serial_private *
1593 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1594 {
1595         struct uart_port serial_port;
1596         struct serial_private *priv;
1597         struct pci_serial_quirk *quirk;
1598         int rc, nr_ports, i;
1599
1600         nr_ports = board->num_ports;
1601
1602         /*
1603          * Find an init and setup quirks.
1604          */
1605         quirk = find_quirk(dev);
1606
1607         /*
1608          * Run the new-style initialization function.
1609          * The initialization function returns:
1610          *  <0  - error
1611          *   0  - use board->num_ports
1612          *  >0  - number of ports
1613          */
1614         if (quirk->init) {
1615                 rc = quirk->init(dev);
1616                 if (rc < 0) {
1617                         priv = ERR_PTR(rc);
1618                         goto err_out;
1619                 }
1620                 if (rc)
1621                         nr_ports = rc;
1622         }
1623
1624         priv = kmalloc(sizeof(struct serial_private) +
1625                        sizeof(unsigned int) * nr_ports,
1626                        GFP_KERNEL);
1627         if (!priv) {
1628                 priv = ERR_PTR(-ENOMEM);
1629                 goto err_deinit;
1630         }
1631
1632         memset(priv, 0, sizeof(struct serial_private) +
1633                         sizeof(unsigned int) * nr_ports);
1634
1635         priv->dev = dev;
1636         priv->quirk = quirk;
1637
1638         memset(&serial_port, 0, sizeof(struct uart_port));
1639         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1640         serial_port.uartclk = board->base_baud * 16;
1641         serial_port.irq = get_pci_irq(dev, board);
1642         serial_port.dev = &dev->dev;
1643
1644         for (i = 0; i < nr_ports; i++) {
1645                 if (quirk->setup(priv, board, &serial_port, i))
1646                         break;
1647
1648 #ifdef SERIAL_DEBUG_PCI
1649                 printk("Setup PCI port: port %x, irq %d, type %d\n",
1650                        serial_port.iobase, serial_port.irq, serial_port.iotype);
1651 #endif
1652
1653                 priv->line[i] = serial8250_register_port(&serial_port);
1654                 if (priv->line[i] < 0) {
1655                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1656                         break;
1657                 }
1658         }
1659
1660         priv->nr = i;
1661
1662         return priv;
1663
1664  err_deinit:
1665         if (quirk->exit)
1666                 quirk->exit(dev);
1667  err_out:
1668         return priv;
1669 }
1670 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1671
1672 void pciserial_remove_ports(struct serial_private *priv)
1673 {
1674         struct pci_serial_quirk *quirk;
1675         int i;
1676
1677         for (i = 0; i < priv->nr; i++)
1678                 serial8250_unregister_port(priv->line[i]);
1679
1680         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1681                 if (priv->remapped_bar[i])
1682                         iounmap(priv->remapped_bar[i]);
1683                 priv->remapped_bar[i] = NULL;
1684         }
1685
1686         /*
1687          * Find the exit quirks.
1688          */
1689         quirk = find_quirk(priv->dev);
1690         if (quirk->exit)
1691                 quirk->exit(priv->dev);
1692
1693         kfree(priv);
1694 }
1695 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1696
1697 void pciserial_suspend_ports(struct serial_private *priv)
1698 {
1699         int i;
1700
1701         for (i = 0; i < priv->nr; i++)
1702                 if (priv->line[i] >= 0)
1703                         serial8250_suspend_port(priv->line[i]);
1704 }
1705 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1706
1707 void pciserial_resume_ports(struct serial_private *priv)
1708 {
1709         int i;
1710
1711         /*
1712          * Ensure that the board is correctly configured.
1713          */
1714         if (priv->quirk->init)
1715                 priv->quirk->init(priv->dev);
1716
1717         for (i = 0; i < priv->nr; i++)
1718                 if (priv->line[i] >= 0)
1719                         serial8250_resume_port(priv->line[i]);
1720 }
1721 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1722
1723 /*
1724  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
1725  * to the arrangement of serial ports on a PCI card.
1726  */
1727 static int __devinit
1728 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1729 {
1730         struct serial_private *priv;
1731         struct pciserial_board *board, tmp;
1732         int rc;
1733
1734         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1735                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1736                         ent->driver_data);
1737                 return -EINVAL;
1738         }
1739
1740         board = &pci_boards[ent->driver_data];
1741
1742         rc = pci_enable_device(dev);
1743         if (rc)
1744                 return rc;
1745
1746         if (ent->driver_data == pbn_default) {
1747                 /*
1748                  * Use a copy of the pci_board entry for this;
1749                  * avoid changing entries in the table.
1750                  */
1751                 memcpy(&tmp, board, sizeof(struct pciserial_board));
1752                 board = &tmp;
1753
1754                 /*
1755                  * We matched one of our class entries.  Try to
1756                  * determine the parameters of this board.
1757                  */
1758                 rc = serial_pci_guess_board(dev, board);
1759                 if (rc)
1760                         goto disable;
1761         } else {
1762                 /*
1763                  * We matched an explicit entry.  If we are able to
1764                  * detect this boards settings with our heuristic,
1765                  * then we no longer need this entry.
1766                  */
1767                 memcpy(&tmp, &pci_boards[pbn_default],
1768                        sizeof(struct pciserial_board));
1769                 rc = serial_pci_guess_board(dev, &tmp);
1770                 if (rc == 0 && serial_pci_matches(board, &tmp))
1771                         moan_device("Redundant entry in serial pci_table.",
1772                                     dev);
1773         }
1774
1775         priv = pciserial_init_ports(dev, board);
1776         if (!IS_ERR(priv)) {
1777                 pci_set_drvdata(dev, priv);
1778                 return 0;
1779         }
1780
1781         rc = PTR_ERR(priv);
1782
1783  disable:
1784         pci_disable_device(dev);
1785         return rc;
1786 }
1787
1788 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1789 {
1790         struct serial_private *priv = pci_get_drvdata(dev);
1791
1792         pci_set_drvdata(dev, NULL);
1793
1794         pciserial_remove_ports(priv);
1795
1796         pci_disable_device(dev);
1797 }
1798
1799 #ifdef CONFIG_PM
1800 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1801 {
1802         struct serial_private *priv = pci_get_drvdata(dev);
1803
1804         if (priv)
1805                 pciserial_suspend_ports(priv);
1806
1807         pci_save_state(dev);
1808         pci_set_power_state(dev, pci_choose_state(dev, state));
1809         return 0;
1810 }
1811
1812 static int pciserial_resume_one(struct pci_dev *dev)
1813 {
1814         struct serial_private *priv = pci_get_drvdata(dev);
1815
1816         pci_set_power_state(dev, PCI_D0);
1817         pci_restore_state(dev);
1818
1819         if (priv) {
1820                 /*
1821                  * The device may have been disabled.  Re-enable it.
1822                  */
1823                 pci_enable_device(dev);
1824
1825                 pciserial_resume_ports(priv);
1826         }
1827         return 0;
1828 }
1829 #endif
1830
1831 static struct pci_device_id serial_pci_tbl[] = {
1832         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1833                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1834                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1835                 pbn_b1_8_1382400 },
1836         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1837                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1838                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1839                 pbn_b1_4_1382400 },
1840         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1841                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1842                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1843                 pbn_b1_2_1382400 },
1844         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1845                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1846                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1847                 pbn_b1_8_1382400 },
1848         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1849                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1850                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1851                 pbn_b1_4_1382400 },
1852         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1853                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1854                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1855                 pbn_b1_2_1382400 },
1856         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1857                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1858                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1859                 pbn_b1_8_921600 },
1860         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1861                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1862                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1863                 pbn_b1_8_921600 },
1864         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1865                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1866                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1867                 pbn_b1_4_921600 },
1868         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1869                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1870                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1871                 pbn_b1_4_921600 },
1872         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1873                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1874                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1875                 pbn_b1_2_921600 },
1876         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1877                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1878                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1879                 pbn_b1_8_921600 },
1880         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1881                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1882                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1883                 pbn_b1_8_921600 },
1884         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1885                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1886                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1887                 pbn_b1_4_921600 },
1888         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1889                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1890                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
1891                 pbn_b1_2_1250000 },
1892         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1893                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1894                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
1895                 pbn_b0_2_1843200 },
1896         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1897                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1898                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
1899                 pbn_b0_4_1843200 },
1900         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1901                 PCI_VENDOR_ID_AFAVLAB,
1902                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
1903                 pbn_b0_4_1152000 },
1904         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1905                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1906                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
1907                 pbn_b0_2_1843200_200 },
1908         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1909                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1910                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
1911                 pbn_b0_4_1843200_200 },
1912         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1913                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1914                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
1915                 pbn_b0_8_1843200_200 },
1916         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1917                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1918                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
1919                 pbn_b0_2_1843200_200 },
1920         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1921                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1922                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
1923                 pbn_b0_4_1843200_200 },
1924         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1925                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1926                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
1927                 pbn_b0_8_1843200_200 },
1928         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1929                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1930                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
1931                 pbn_b0_2_1843200_200 },
1932         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1933                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1934                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
1935                 pbn_b0_4_1843200_200 },
1936         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1937                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1938                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
1939                 pbn_b0_8_1843200_200 },
1940         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1941                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1942                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
1943                 pbn_b0_2_1843200_200 },
1944         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1945                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1946                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
1947                 pbn_b0_4_1843200_200 },
1948         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1949                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1950                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
1951                 pbn_b0_8_1843200_200 },
1952
1953         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1954                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1955                 pbn_b2_bt_1_115200 },
1956         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1957                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1958                 pbn_b2_bt_2_115200 },
1959         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1960                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1961                 pbn_b2_bt_4_115200 },
1962         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1963                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1964                 pbn_b2_bt_2_115200 },
1965         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1966                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1967                 pbn_b2_bt_4_115200 },
1968         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1969                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1970                 pbn_b2_8_115200 },
1971         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1972                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1973                 pbn_b2_8_115200 },
1974
1975         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1976                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1977                 pbn_b2_bt_2_115200 },
1978         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1979                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1980                 pbn_b2_bt_2_921600 },
1981         /*
1982          * VScom SPCOM800, from sl@s.pl
1983          */
1984         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1985                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1986                 pbn_b2_8_921600 },
1987         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1988                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1989                 pbn_b2_4_921600 },
1990         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1991                 PCI_SUBVENDOR_ID_KEYSPAN,
1992                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1993                 pbn_panacom },
1994         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1995                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1996                 pbn_panacom4 },
1997         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1998                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1999                 pbn_panacom2 },
2000         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2001                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2002                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2003                 pbn_b2_4_460800 },
2004         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2005                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2006                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2007                 pbn_b2_8_460800 },
2008         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2009                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2010                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2011                 pbn_b2_16_460800 },
2012         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2013                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2014                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2015                 pbn_b2_16_460800 },
2016         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2017                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2018                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2019                 pbn_b2_4_460800 },
2020         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2021                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2022                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2023                 pbn_b2_8_460800 },
2024         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2025                 PCI_SUBVENDOR_ID_EXSYS,
2026                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2027                 pbn_exsys_4055 },
2028         /*
2029          * Megawolf Romulus PCI Serial Card, from Mike Hudson
2030          * (Exoray@isys.ca)
2031          */
2032         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2033                 0x10b5, 0x106a, 0, 0,
2034                 pbn_plx_romulus },
2035         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2036                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2037                 pbn_b1_4_115200 },
2038         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2039                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2040                 pbn_b1_2_115200 },
2041         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2042                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2043                 pbn_b1_8_115200 },
2044         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2045                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2046                 pbn_b1_8_115200 },
2047         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2048                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
2049                 pbn_b0_4_921600 },
2050         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2051                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
2052                 pbn_b0_4_1152000 },
2053
2054                 /*
2055                  * The below card is a little controversial since it is the
2056                  * subject of a PCI vendor/device ID clash.  (See
2057                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2058                  * For now just used the hex ID 0x950a.
2059                  */
2060         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2061                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2062                 pbn_b0_2_1130000 },
2063         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2064                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2065                 pbn_b0_4_115200 },
2066         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2067                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2068                 pbn_b0_bt_2_921600 },
2069
2070         /*
2071          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2072          * from skokodyn@yahoo.com
2073          */
2074         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2075                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2076                 pbn_sbsxrsio },
2077         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2078                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2079                 pbn_sbsxrsio },
2080         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2081                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2082                 pbn_sbsxrsio },
2083         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2084                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2085                 pbn_sbsxrsio },
2086
2087         /*
2088          * Digitan DS560-558, from jimd@esoft.com
2089          */
2090         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2091                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2092                 pbn_b1_1_115200 },
2093
2094         /*
2095          * Titan Electronic cards
2096          *  The 400L and 800L have a custom setup quirk.
2097          */
2098         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2099                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2100                 pbn_b0_1_921600 },
2101         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2102                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2103                 pbn_b0_2_921600 },
2104         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2105                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2106                 pbn_b0_4_921600 },
2107         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2108                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2109                 pbn_b0_4_921600 },
2110         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2111                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2112                 pbn_b1_1_921600 },
2113         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2114                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2115                 pbn_b1_bt_2_921600 },
2116         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2117                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2118                 pbn_b0_bt_4_921600 },
2119         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2120                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2121                 pbn_b0_bt_8_921600 },
2122
2123         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2124                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2125                 pbn_b2_1_460800 },
2126         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2127                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2128                 pbn_b2_1_460800 },
2129         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2130                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2131                 pbn_b2_1_460800 },
2132         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2133                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2134                 pbn_b2_bt_2_921600 },
2135         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2136                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2137                 pbn_b2_bt_2_921600 },
2138         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2139                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2140                 pbn_b2_bt_2_921600 },
2141         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2142                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2143                 pbn_b2_bt_4_921600 },
2144         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2145                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2146                 pbn_b2_bt_4_921600 },
2147         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2148                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2149                 pbn_b2_bt_4_921600 },
2150         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2151                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2152                 pbn_b0_1_921600 },
2153         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2154                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2155                 pbn_b0_1_921600 },
2156         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2157                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2158                 pbn_b0_1_921600 },
2159         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2160                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2161                 pbn_b0_bt_2_921600 },
2162         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2163                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2164                 pbn_b0_bt_2_921600 },
2165         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2166                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2167                 pbn_b0_bt_2_921600 },
2168         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2169                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2170                 pbn_b0_bt_4_921600 },
2171         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2172                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2173                 pbn_b0_bt_4_921600 },
2174         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2175                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2176                 pbn_b0_bt_4_921600 },
2177         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2178                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2179                 pbn_b0_bt_8_921600 },
2180         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2181                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2182                 pbn_b0_bt_8_921600 },
2183         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2184                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2185                 pbn_b0_bt_8_921600 },
2186
2187         /*
2188          * Computone devices submitted by Doug McNash dmcnash@computone.com
2189          */
2190         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2191                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2192                 0, 0, pbn_computone_4 },
2193         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2194                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2195                 0, 0, pbn_computone_8 },
2196         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2197                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2198                 0, 0, pbn_computone_6 },
2199
2200         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2201                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2202                 pbn_oxsemi },
2203         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2204                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2205                 pbn_b0_bt_1_921600 },
2206
2207         /*
2208          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2209          */
2210         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2211                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2212                 pbn_b0_bt_8_115200 },
2213         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2214                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2215                 pbn_b0_bt_8_115200 },
2216
2217         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2218                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2219                 pbn_b0_bt_2_115200 },
2220         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2221                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2222                 pbn_b0_bt_2_115200 },
2223         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2224                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2225                 pbn_b0_bt_2_115200 },
2226         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2227                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2228                 pbn_b0_bt_4_460800 },
2229         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2230                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2231                 pbn_b0_bt_4_460800 },
2232         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2233                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2234                 pbn_b0_bt_2_460800 },
2235         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2236                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2237                 pbn_b0_bt_2_460800 },
2238         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2239                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2240                 pbn_b0_bt_2_460800 },
2241         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2242                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2243                 pbn_b0_bt_1_115200 },
2244         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2245                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2246                 pbn_b0_bt_1_460800 },
2247
2248         /*
2249          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2250          * Cards are identified by their subsystem vendor IDs, which
2251          * (in hex) match the model number.
2252          *
2253          * Note that JC140x are RS422/485 cards which require ox950
2254          * ACR = 0x10, and as such are not currently fully supported.
2255          */
2256         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2257                 0x1204, 0x0004, 0, 0,
2258                 pbn_b0_4_921600 },
2259         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2260                 0x1208, 0x0004, 0, 0,
2261                 pbn_b0_4_921600 },
2262 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2263                 0x1402, 0x0002, 0, 0,
2264                 pbn_b0_2_921600 }, */
2265 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2266                 0x1404, 0x0004, 0, 0,
2267                 pbn_b0_4_921600 }, */
2268         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2269                 0x1208, 0x0004, 0, 0,
2270                 pbn_b0_4_921600 },
2271
2272         /*
2273          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2274          */
2275         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2276                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2277                 pbn_b1_1_1382400 },
2278
2279         /*
2280          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2281          */
2282         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2283                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2284                 pbn_b1_1_1382400 },
2285
2286         /*
2287          * RAStel 2 port modem, gerg@moreton.com.au
2288          */
2289         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2290                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2291                 pbn_b2_bt_2_115200 },
2292
2293         /*
2294          * EKF addition for i960 Boards form EKF with serial port
2295          */
2296         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2297                 0xE4BF, PCI_ANY_ID, 0, 0,
2298                 pbn_intel_i960 },
2299
2300         /*
2301          * Xircom Cardbus/Ethernet combos
2302          */
2303         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2304                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2305                 pbn_b0_1_115200 },
2306         /*
2307          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2308          */
2309         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2310                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2311                 pbn_b0_1_115200 },
2312
2313         /*
2314          * Untested PCI modems, sent in from various folks...
2315          */
2316
2317         /*
2318          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2319          */
2320         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
2321                 0x1048, 0x1500, 0, 0,
2322                 pbn_b1_1_115200 },
2323
2324         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2325                 0xFF00, 0, 0, 0,
2326                 pbn_sgi_ioc3 },
2327
2328         /*
2329          * HP Diva card
2330          */
2331         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2332                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2333                 pbn_b1_1_115200 },
2334         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2335                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2336                 pbn_b0_5_115200 },
2337         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2338                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2339                 pbn_b2_1_115200 },
2340
2341         /*
2342          * NEC Vrc-5074 (Nile 4) builtin UART.
2343          */
2344         {       PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2345                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2346                 pbn_nec_nile4 },
2347
2348         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2349                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2350                 pbn_b3_2_115200 },
2351         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2352                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2353                 pbn_b3_4_115200 },
2354         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2355                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2356                 pbn_b3_8_115200 },
2357
2358         /*
2359          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2360          */
2361         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2362                 PCI_ANY_ID, PCI_ANY_ID,
2363                 0,
2364                 0, pbn_exar_XR17C152 },
2365         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2366                 PCI_ANY_ID, PCI_ANY_ID,
2367                 0,
2368                 0, pbn_exar_XR17C154 },
2369         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2370                 PCI_ANY_ID, PCI_ANY_ID,
2371                 0,
2372                 0, pbn_exar_XR17C158 },
2373
2374         /*
2375          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2376          */
2377         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2378                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2379                 pbn_b0_1_115200 },
2380
2381         /*
2382          * IntaShield IS-200
2383          */
2384         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2385                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
2386                 pbn_b2_2_115200 },
2387
2388         /*
2389          * Perle PCI-RAS cards
2390          */
2391         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2392                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
2393                 0, 0, pbn_b2_4_921600 },
2394         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2395                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
2396                 0, 0, pbn_b2_8_921600 },
2397         /*
2398          * These entries match devices with class COMMUNICATION_SERIAL,
2399          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2400          */
2401         {       PCI_ANY_ID, PCI_ANY_ID,
2402                 PCI_ANY_ID, PCI_ANY_ID,
2403                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2404                 0xffff00, pbn_default },
2405         {       PCI_ANY_ID, PCI_ANY_ID,
2406                 PCI_ANY_ID, PCI_ANY_ID,
2407                 PCI_CLASS_COMMUNICATION_MODEM << 8,
2408                 0xffff00, pbn_default },
2409         {       PCI_ANY_ID, PCI_ANY_ID,
2410                 PCI_ANY_ID, PCI_ANY_ID,
2411                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2412                 0xffff00, pbn_default },
2413         { 0, }
2414 };
2415
2416 static struct pci_driver serial_pci_driver = {
2417         .name           = "serial",
2418         .probe          = pciserial_init_one,
2419         .remove         = __devexit_p(pciserial_remove_one),
2420 #ifdef CONFIG_PM
2421         .suspend        = pciserial_suspend_one,
2422         .resume         = pciserial_resume_one,
2423 #endif
2424         .id_table       = serial_pci_tbl,
2425 };
2426
2427 static int __init serial8250_pci_init(void)
2428 {
2429         return pci_register_driver(&serial_pci_driver);
2430 }
2431
2432 static void __exit serial8250_pci_exit(void)
2433 {
2434         pci_unregister_driver(&serial_pci_driver);
2435 }
2436
2437 module_init(serial8250_pci_init);
2438 module_exit(serial8250_pci_exit);
2439
2440 MODULE_LICENSE("GPL");
2441 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2442 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);