drivers/scsi/pm8001/pm8001_hwi.c

   1 /*
   2  * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm8001_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45
  46 /**
  47  * read_main_config_table - read the configure table and save it.
  48  * @pm8001_ha: our hba card information
  49  */
  50 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
  51 {
  52         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  53         pm8001_ha->main_cfg_tbl.pm8001_tbl.signature    =
  54                                 pm8001_mr32(address, 0x00);
  55         pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
  56                                 pm8001_mr32(address, 0x04);
  57         pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
  58                                 pm8001_mr32(address, 0x08);
  59         pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io   =
  60                                 pm8001_mr32(address, 0x0C);
  61         pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl      =
  62                                 pm8001_mr32(address, 0x10);
  63         pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
  64                                 pm8001_mr32(address, 0x14);
  65         pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset   =
  66                                 pm8001_mr32(address, 0x18);
  67         pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
  68                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
  69         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
  70                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
  71         pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag        =
  72                 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
  73
  74         /* read analog Setting offset from the configuration table */
  75         pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
  76                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
  77
  78         /* read Error Dump Offset and Length */
  79         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
  80                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
  81         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
  82                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
  83         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
  84                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
  85         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
  86                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
  87 }
  88
  89 /**
  90  * read_general_status_table - read the general status table and save it.
  91  * @pm8001_ha: our hba card information
  92  */
  93 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
  94 {
  95         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
  96         pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate   =
  97                                 pm8001_mr32(address, 0x00);
  98         pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0   =
  99                                 pm8001_mr32(address, 0x04);
 100         pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1   =
 101                                 pm8001_mr32(address, 0x08);
 102         pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt          =
 103                                 pm8001_mr32(address, 0x0C);
 104         pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt           =
 105                                 pm8001_mr32(address, 0x10);
 106         pm8001_ha->gs_tbl.pm8001_tbl.rsvd               =
 107                                 pm8001_mr32(address, 0x14);
 108         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0]       =
 109                                 pm8001_mr32(address, 0x18);
 110         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1]       =
 111                                 pm8001_mr32(address, 0x1C);
 112         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2]       =
 113                                 pm8001_mr32(address, 0x20);
 114         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3]       =
 115                                 pm8001_mr32(address, 0x24);
 116         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4]       =
 117                                 pm8001_mr32(address, 0x28);
 118         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5]       =
 119                                 pm8001_mr32(address, 0x2C);
 120         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6]       =
 121                                 pm8001_mr32(address, 0x30);
 122         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7]       =
 123                                 pm8001_mr32(address, 0x34);
 124         pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val     =
 125                                 pm8001_mr32(address, 0x38);
 126         pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0]           =
 127                                 pm8001_mr32(address, 0x3C);
 128         pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1]           =
 129                                 pm8001_mr32(address, 0x40);
 130         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0]        =
 131                                 pm8001_mr32(address, 0x44);
 132         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1]        =
 133                                 pm8001_mr32(address, 0x48);
 134         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2]        =
 135                                 pm8001_mr32(address, 0x4C);
 136         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3]        =
 137                                 pm8001_mr32(address, 0x50);
 138         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4]        =
 139                                 pm8001_mr32(address, 0x54);
 140         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5]        =
 141                                 pm8001_mr32(address, 0x58);
 142         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6]        =
 143                                 pm8001_mr32(address, 0x5C);
 144         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7]        =
 145                                 pm8001_mr32(address, 0x60);
 146 }
 147
 148 /**
 149  * read_inbnd_queue_table - read the inbound queue table and save it.
 150  * @pm8001_ha: our hba card information
 151  */
 152 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 153 {
 154         int i;
 155         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 156         for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
 157                 u32 offset = i * 0x20;
 158                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 159                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 160                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 161                         pm8001_mr32(address, (offset + 0x18));
 162         }
 163 }
 164
 165 /**
 166  * read_outbnd_queue_table - read the outbound queue table and save it.
 167  * @pm8001_ha: our hba card information
 168  */
 169 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 170 {
 171         int i;
 172         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 173         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
 174                 u32 offset = i * 0x24;
 175                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 176                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 177                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 178                         pm8001_mr32(address, (offset + 0x18));
 179         }
 180 }
 181
 182 /**
 183  * init_default_table_values - init the default table.
 184  * @pm8001_ha: our hba card information
 185  */
 186 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 187 {
 188         int i;
 189         u32 offsetib, offsetob;
 190         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 191         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 192
 193         pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd          = 0;
 194         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3     = 0;
 195         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7     = 0;
 196         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3    = 0;
 197         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7    = 0;
 198         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
 199                                                                          0;
 200         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
 201                                                                          0;
 202         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
 203         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
 204         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
 205         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
 206
 207         pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr         =
 208                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 209         pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr         =
 210                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 211         pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size               =
 212                 PM8001_EVENT_LOG_SIZE;
 213         pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option             = 0x01;
 214         pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr     =
 215                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 216         pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr     =
 217                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 218         pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size           =
 219                 PM8001_EVENT_LOG_SIZE;
 220         pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option         = 0x01;
 221         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt          = 0x01;
 222         for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
 223                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 224                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
 225                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 226                         pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
 227                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 228                 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
 229                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 230                         (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
 231                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 232                         pm8001_ha->memoryMap.region[IB + i].total_len;
 233                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 234                         pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
 235                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 236                         pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
 237                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 238                         pm8001_ha->memoryMap.region[CI + i].virt_ptr;
 239                 offsetib = i * 0x20;
 240                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 241                         get_pci_bar_index(pm8001_mr32(addressib,
 242                                 (offsetib + 0x14)));
 243                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 244                         pm8001_mr32(addressib, (offsetib + 0x18));
 245                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 246                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 247         }
 248         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
 249                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 250                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
 251                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 252                         pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
 253                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 254                         pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
 255                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 256                         (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
 257                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 258                         pm8001_ha->memoryMap.region[OB + i].total_len;
 259                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 260                         pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
 261                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 262                         pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
 263                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay       =
 264                         0 | (10 << 16) | (i << 24);
 265                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 266                         pm8001_ha->memoryMap.region[PI + i].virt_ptr;
 267                 offsetob = i * 0x24;
 268                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 269                         get_pci_bar_index(pm8001_mr32(addressob,
 270                         offsetob + 0x14));
 271                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 272                         pm8001_mr32(addressob, (offsetob + 0x18));
 273                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 274                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 275         }
 276 }
 277
 278 /**
 279  * update_main_config_table - update the main default table to the HBA.
 280  * @pm8001_ha: our hba card information
 281  */
 282 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 283 {
 284         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 285         pm8001_mw32(address, 0x24,
 286                 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
 287         pm8001_mw32(address, 0x28,
 288                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
 289         pm8001_mw32(address, 0x2C,
 290                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
 291         pm8001_mw32(address, 0x30,
 292                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
 293         pm8001_mw32(address, 0x34,
 294                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
 295         pm8001_mw32(address, 0x38,
 296                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 297                                         outbound_tgt_ITNexus_event_pid0_3);
 298         pm8001_mw32(address, 0x3C,
 299                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 300                                         outbound_tgt_ITNexus_event_pid4_7);
 301         pm8001_mw32(address, 0x40,
 302                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 303                                         outbound_tgt_ssp_event_pid0_3);
 304         pm8001_mw32(address, 0x44,
 305                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 306                                         outbound_tgt_ssp_event_pid4_7);
 307         pm8001_mw32(address, 0x48,
 308                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 309                                         outbound_tgt_smp_event_pid0_3);
 310         pm8001_mw32(address, 0x4C,
 311                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 312                                         outbound_tgt_smp_event_pid4_7);
 313         pm8001_mw32(address, 0x50,
 314                 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
 315         pm8001_mw32(address, 0x54,
 316                 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
 317         pm8001_mw32(address, 0x58,
 318                 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
 319         pm8001_mw32(address, 0x5C,
 320                 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
 321         pm8001_mw32(address, 0x60,
 322                 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
 323         pm8001_mw32(address, 0x64,
 324                 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
 325         pm8001_mw32(address, 0x68,
 326                 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
 327         pm8001_mw32(address, 0x6C,
 328                 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
 329         pm8001_mw32(address, 0x70,
 330                 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
 331 }
 332
 333 /**
 334  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 335  * @pm8001_ha: our hba card information
 336  */
 337 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 338                                      int number)
 339 {
 340         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 341         u16 offset = number * 0x20;
 342         pm8001_mw32(address, offset + 0x00,
 343                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 344         pm8001_mw32(address, offset + 0x04,
 345                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 346         pm8001_mw32(address, offset + 0x08,
 347                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 348         pm8001_mw32(address, offset + 0x0C,
 349                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 350         pm8001_mw32(address, offset + 0x10,
 351                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 352 }
 353
 354 /**
 355  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 356  * @pm8001_ha: our hba card information
 357  */
 358 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 359                                       int number)
 360 {
 361         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 362         u16 offset = number * 0x24;
 363         pm8001_mw32(address, offset + 0x00,
 364                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 365         pm8001_mw32(address, offset + 0x04,
 366                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 367         pm8001_mw32(address, offset + 0x08,
 368                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 369         pm8001_mw32(address, offset + 0x0C,
 370                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 371         pm8001_mw32(address, offset + 0x10,
 372                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 373         pm8001_mw32(address, offset + 0x1C,
 374                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 375 }
 376
 377 /**
 378  * pm8001_bar4_shift - function is called to shift BAR base address
 379  * @pm8001_ha : our hba card infomation
 380  * @shiftValue : shifting value in memory bar.
 381  */
 382 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
 383 {
 384         u32 regVal;
 385         unsigned long start;
 386
 387         /* program the inbound AXI translation Lower Address */
 388         pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
 389
 390         /* confirm the setting is written */
 391         start = jiffies + HZ; /* 1 sec */
 392         do {
 393                 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
 394         } while ((regVal != shiftValue) && time_before(jiffies, start));
 395
 396         if (regVal != shiftValue) {
 397                 PM8001_INIT_DBG(pm8001_ha,
 398                         pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
 399                         " = 0x%x\n", regVal));
 400                 return -1;
 401         }
 402         return 0;
 403 }
 404
 405 /**
 406  * mpi_set_phys_g3_with_ssc
 407  * @pm8001_ha: our hba card information
 408  * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
 409  */
 410 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
 411                                      u32 SSCbit)
 412 {
 413         u32 value, offset, i;
 414         unsigned long flags;
 415
 416 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
 417 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
 418 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
 419 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
 420 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
 421 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
 422 #define SNW3_PHY_CAPABILITIES_PARITY 31
 423
 424    /*
 425     * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
 426     * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
 427     */
 428         spin_lock_irqsave(&pm8001_ha->lock, flags);
 429         if (-1 == pm8001_bar4_shift(pm8001_ha,
 430                                 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
 431                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 432                 return;
 433         }
 434
 435         for (i = 0; i < 4; i++) {
 436                 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
 437                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 438         }
 439         /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
 440         if (-1 == pm8001_bar4_shift(pm8001_ha,
 441                                 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
 442                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 443                 return;
 444         }
 445         for (i = 4; i < 8; i++) {
 446                 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 447                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 448         }
 449         /*************************************************************
 450         Change the SSC upspreading value to 0x0 so that upspreading is disabled.
 451         Device MABC SMOD0 Controls
 452         Address: (via MEMBASE-III):
 453         Using shifted destination address 0x0_0000: with Offset 0xD8
 454
 455         31:28 R/W Reserved Do not change
 456         27:24 R/W SAS_SMOD_SPRDUP 0000
 457         23:20 R/W SAS_SMOD_SPRDDN 0000
 458         19:0  R/W  Reserved Do not change
 459         Upon power-up this register will read as 0x8990c016,
 460         and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
 461         so that the written value will be 0x8090c016.
 462         This will ensure only down-spreading SSC is enabled on the SPC.
 463         *************************************************************/
 464         value = pm8001_cr32(pm8001_ha, 2, 0xd8);
 465         pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
 466
 467         /*set the shifted destination address to 0x0 to avoid error operation */
 468         pm8001_bar4_shift(pm8001_ha, 0x0);
 469         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 470         return;
 471 }
 472
 473 /**
 474  * mpi_set_open_retry_interval_reg
 475  * @pm8001_ha: our hba card information
 476  * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
 477  */
 478 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
 479                                             u32 interval)
 480 {
 481         u32 offset;
 482         u32 value;
 483         u32 i;
 484         unsigned long flags;
 485
 486 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
 487 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
 488 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
 489 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
 490 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
 491
 492         value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
 493         spin_lock_irqsave(&pm8001_ha->lock, flags);
 494         /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
 495         if (-1 == pm8001_bar4_shift(pm8001_ha,
 496                              OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
 497                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 498                 return;
 499         }
 500         for (i = 0; i < 4; i++) {
 501                 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
 502                 pm8001_cw32(pm8001_ha, 2, offset, value);
 503         }
 504
 505         if (-1 == pm8001_bar4_shift(pm8001_ha,
 506                              OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
 507                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 508                 return;
 509         }
 510         for (i = 4; i < 8; i++) {
 511                 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 512                 pm8001_cw32(pm8001_ha, 2, offset, value);
 513         }
 514         /*set the shifted destination address to 0x0 to avoid error operation */
 515         pm8001_bar4_shift(pm8001_ha, 0x0);
 516         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 517         return;
 518 }
 519
 520 /**
 521  * mpi_init_check - check firmware initialization status.
 522  * @pm8001_ha: our hba card information
 523  */
 524 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 525 {
 526         u32 max_wait_count;
 527         u32 value;
 528         u32 gst_len_mpistate;
 529         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 530         table is updated */
 531         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
 532         /* wait until Inbound DoorBell Clear Register toggled */
 533         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 534         do {
 535                 udelay(1);
 536                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 537                 value &= SPC_MSGU_CFG_TABLE_UPDATE;
 538         } while ((value != 0) && (--max_wait_count));
 539
 540         if (!max_wait_count)
 541                 return -1;
 542         /* check the MPI-State for initialization */
 543         gst_len_mpistate =
 544                 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 545                 GST_GSTLEN_MPIS_OFFSET);
 546         if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
 547                 return -1;
 548         /* check MPI Initialization error */
 549         gst_len_mpistate = gst_len_mpistate >> 16;
 550         if (0x0000 != gst_len_mpistate)
 551                 return -1;
 552         return 0;
 553 }
 554
 555 /**
 556  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 557  * @pm8001_ha: our hba card information
 558  */
 559 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 560 {
 561         u32 value, value1;
 562         u32 max_wait_count;
 563         /* check error state */
 564         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 565         value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 566         /* check AAP error */
 567         if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
 568                 /* error state */
 569                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 570                 return -1;
 571         }
 572
 573         /* check IOP error */
 574         if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
 575                 /* error state */
 576                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 577                 return -1;
 578         }
 579
 580         /* bit 4-31 of scratch pad1 should be zeros if it is not
 581         in error state*/
 582         if (value & SCRATCH_PAD1_STATE_MASK) {
 583                 /* error case */
 584                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 585                 return -1;
 586         }
 587
 588         /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
 589         in error state */
 590         if (value1 & SCRATCH_PAD2_STATE_MASK) {
 591                 /* error case */
 592                 return -1;
 593         }
 594
 595         max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
 596
 597         /* wait until scratch pad 1 and 2 registers in ready state  */
 598         do {
 599                 udelay(1);
 600                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 601                         & SCRATCH_PAD1_RDY;
 602                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 603                         & SCRATCH_PAD2_RDY;
 604                 if ((--max_wait_count) == 0)
 605                         return -1;
 606         } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
 607         return 0;
 608 }
 609
 610 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 611 {
 612         void __iomem *base_addr;
 613         u32     value;
 614         u32     offset;
 615         u32     pcibar;
 616         u32     pcilogic;
 617
 618         value = pm8001_cr32(pm8001_ha, 0, 0x44);
 619         offset = value & 0x03FFFFFF;
 620         PM8001_INIT_DBG(pm8001_ha,
 621                 pm8001_printk("Scratchpad 0 Offset: %x\n", offset));
 622         pcilogic = (value & 0xFC000000) >> 26;
 623         pcibar = get_pci_bar_index(pcilogic);
 624         PM8001_INIT_DBG(pm8001_ha,
 625                 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
 626         pm8001_ha->main_cfg_tbl_addr = base_addr =
 627                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 628         pm8001_ha->general_stat_tbl_addr =
 629                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
 630         pm8001_ha->inbnd_q_tbl_addr =
 631                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
 632         pm8001_ha->outbnd_q_tbl_addr =
 633                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
 634 }
 635
 636 /**
 637  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
 638  * @pm8001_ha: our hba card information
 639  */
 640 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
 641 {
 642         u8 i = 0;
 643         u16 deviceid;
 644         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 645         /* 8081 controllers need BAR shift to access MPI space
 646         * as this is shared with BIOS data */
 647         if (deviceid == 0x8081) {
 648                 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
 649                         PM8001_FAIL_DBG(pm8001_ha,
 650                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 651                                         GSM_SM_BASE));
 652                         return -1;
 653                 }
 654         }
 655         /* check the firmware status */
 656         if (-1 == check_fw_ready(pm8001_ha)) {
 657                 PM8001_FAIL_DBG(pm8001_ha,
 658                         pm8001_printk("Firmware is not ready!\n"));
 659                 return -EBUSY;
 660         }
 661
 662         /* Initialize pci space address eg: mpi offset */
 663         init_pci_device_addresses(pm8001_ha);
 664         init_default_table_values(pm8001_ha);
 665         read_main_config_table(pm8001_ha);
 666         read_general_status_table(pm8001_ha);
 667         read_inbnd_queue_table(pm8001_ha);
 668         read_outbnd_queue_table(pm8001_ha);
 669         /* update main config table ,inbound table and outbound table */
 670         update_main_config_table(pm8001_ha);
 671         for (i = 0; i < PM8001_MAX_INB_NUM; i++)
 672                 update_inbnd_queue_table(pm8001_ha, i);
 673         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++)
 674                 update_outbnd_queue_table(pm8001_ha, i);
 675         /* 8081 controller donot require these operations */
 676         if (deviceid != 0x8081) {
 677                 mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
 678                 /* 7->130ms, 34->500ms, 119->1.5s */
 679                 mpi_set_open_retry_interval_reg(pm8001_ha, 119);
 680         }
 681         /* notify firmware update finished and check initialization status */
 682         if (0 == mpi_init_check(pm8001_ha)) {
 683                 PM8001_INIT_DBG(pm8001_ha,
 684                         pm8001_printk("MPI initialize successful!\n"));
 685         } else
 686                 return -EBUSY;
 687         /*This register is a 16-bit timer with a resolution of 1us. This is the
 688         timer used for interrupt delay/coalescing in the PCIe Application Layer.
 689         Zero is not a valid value. A value of 1 in the register will cause the
 690         interrupts to be normal. A value greater than 1 will cause coalescing
 691         delays.*/
 692         pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
 693         pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
 694         return 0;
 695 }
 696
 697 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
 698 {
 699         u32 max_wait_count;
 700         u32 value;
 701         u32 gst_len_mpistate;
 702         u16 deviceid;
 703         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 704         if (deviceid == 0x8081) {
 705                 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
 706                         PM8001_FAIL_DBG(pm8001_ha,
 707                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 708                                         GSM_SM_BASE));
 709                         return -1;
 710                 }
 711         }
 712         init_pci_device_addresses(pm8001_ha);
 713         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
 714         table is stop */
 715         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
 716
 717         /* wait until Inbound DoorBell Clear Register toggled */
 718         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 719         do {
 720                 udelay(1);
 721                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 722                 value &= SPC_MSGU_CFG_TABLE_RESET;
 723         } while ((value != 0) && (--max_wait_count));
 724
 725         if (!max_wait_count) {
 726                 PM8001_FAIL_DBG(pm8001_ha,
 727                         pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
 728                 return -1;
 729         }
 730
 731         /* check the MPI-State for termination in progress */
 732         /* wait until Inbound DoorBell Clear Register toggled */
 733         max_wait_count = 1 * 1000 * 1000;  /* 1 sec */
 734         do {
 735                 udelay(1);
 736                 gst_len_mpistate =
 737                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 738                         GST_GSTLEN_MPIS_OFFSET);
 739                 if (GST_MPI_STATE_UNINIT ==
 740                         (gst_len_mpistate & GST_MPI_STATE_MASK))
 741                         break;
 742         } while (--max_wait_count);
 743         if (!max_wait_count) {
 744                 PM8001_FAIL_DBG(pm8001_ha,
 745                         pm8001_printk(" TIME OUT MPI State = 0x%x\n",
 746                                 gst_len_mpistate & GST_MPI_STATE_MASK));
 747                 return -1;
 748         }
 749         return 0;
 750 }
 751
 752 /**
 753  * soft_reset_ready_check - Function to check FW is ready for soft reset.
 754  * @pm8001_ha: our hba card information
 755  */
 756 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
 757 {
 758         u32 regVal, regVal1, regVal2;
 759         if (mpi_uninit_check(pm8001_ha) != 0) {
 760                 PM8001_FAIL_DBG(pm8001_ha,
 761                         pm8001_printk("MPI state is not ready\n"));
 762                 return -1;
 763         }
 764         /* read the scratch pad 2 register bit 2 */
 765         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 766                 & SCRATCH_PAD2_FWRDY_RST;
 767         if (regVal == SCRATCH_PAD2_FWRDY_RST) {
 768                 PM8001_INIT_DBG(pm8001_ha,
 769                         pm8001_printk("Firmware is ready for reset .\n"));
 770         } else {
 771                 unsigned long flags;
 772                 /* Trigger NMI twice via RB6 */
 773                 spin_lock_irqsave(&pm8001_ha->lock, flags);
 774                 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
 775                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 776                         PM8001_FAIL_DBG(pm8001_ha,
 777                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 778                                         RB6_ACCESS_REG));
 779                         return -1;
 780                 }
 781                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
 782                         RB6_MAGIC_NUMBER_RST);
 783                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
 784                 /* wait for 100 ms */
 785                 mdelay(100);
 786                 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
 787                         SCRATCH_PAD2_FWRDY_RST;
 788                 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
 789                         regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 790                         regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 791                         PM8001_FAIL_DBG(pm8001_ha,
 792                                 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
 793                                 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
 794                                 regVal1, regVal2));
 795                         PM8001_FAIL_DBG(pm8001_ha,
 796                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
 797                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
 798                         PM8001_FAIL_DBG(pm8001_ha,
 799                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
 800                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
 801                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 802                         return -1;
 803                 }
 804                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 805         }
 806         return 0;
 807 }
 808
 809 /**
 810  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
 811  * the FW register status to the originated status.
 812  * @pm8001_ha: our hba card information
 813  */
 814 static int
 815 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
 816 {
 817         u32     regVal, toggleVal;
 818         u32     max_wait_count;
 819         u32     regVal1, regVal2, regVal3;
 820         u32     signature = 0x252acbcd; /* for host scratch pad0 */
 821         unsigned long flags;
 822
 823         /* step1: Check FW is ready for soft reset */
 824         if (soft_reset_ready_check(pm8001_ha) != 0) {
 825                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
 826                 return -1;
 827         }
 828
 829         /* step 2: clear NMI status register on AAP1 and IOP, write the same
 830         value to clear */
 831         /* map 0x60000 to BAR4(0x20), BAR2(win) */
 832         spin_lock_irqsave(&pm8001_ha->lock, flags);
 833         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
 834                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 835                 PM8001_FAIL_DBG(pm8001_ha,
 836                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 837                         MBIC_AAP1_ADDR_BASE));
 838                 return -1;
 839         }
 840         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
 841         PM8001_INIT_DBG(pm8001_ha,
 842                 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
 843         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
 844         /* map 0x70000 to BAR4(0x20), BAR2(win) */
 845         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
 846                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 847                 PM8001_FAIL_DBG(pm8001_ha,
 848                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 849                         MBIC_IOP_ADDR_BASE));
 850                 return -1;
 851         }
 852         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
 853         PM8001_INIT_DBG(pm8001_ha,
 854                 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
 855         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
 856
 857         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
 858         PM8001_INIT_DBG(pm8001_ha,
 859                 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
 860         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
 861
 862         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
 863         PM8001_INIT_DBG(pm8001_ha,
 864                 pm8001_printk("PCIE - Event Interrupt  = 0x%x\n", regVal));
 865         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
 866
 867         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
 868         PM8001_INIT_DBG(pm8001_ha,
 869                 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
 870         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
 871
 872         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
 873         PM8001_INIT_DBG(pm8001_ha,
 874                 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
 875         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
 876
 877         /* read the scratch pad 1 register bit 2 */
 878         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 879                 & SCRATCH_PAD1_RST;
 880         toggleVal = regVal ^ SCRATCH_PAD1_RST;
 881
 882         /* set signature in host scratch pad0 register to tell SPC that the
 883         host performs the soft reset */
 884         pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
 885
 886         /* read required registers for confirmming */
 887         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 888         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 889                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 890                 PM8001_FAIL_DBG(pm8001_ha,
 891                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 892                         GSM_ADDR_BASE));
 893                 return -1;
 894         }
 895         PM8001_INIT_DBG(pm8001_ha,
 896                 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
 897                 " Reset = 0x%x\n",
 898                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 899
 900         /* step 3: host read GSM Configuration and Reset register */
 901         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 902         /* Put those bits to low */
 903         /* GSM XCBI offset = 0x70 0000
 904         0x00 Bit 13 COM_SLV_SW_RSTB 1
 905         0x00 Bit 12 QSSP_SW_RSTB 1
 906         0x00 Bit 11 RAAE_SW_RSTB 1
 907         0x00 Bit 9 RB_1_SW_RSTB 1
 908         0x00 Bit 8 SM_SW_RSTB 1
 909         */
 910         regVal &= ~(0x00003b00);
 911         /* host write GSM Configuration and Reset register */
 912         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
 913         PM8001_INIT_DBG(pm8001_ha,
 914                 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
 915                 "Configuration and Reset is set to = 0x%x\n",
 916                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 917
 918         /* step 4: */
 919         /* disable GSM - Read Address Parity Check */
 920         regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
 921         PM8001_INIT_DBG(pm8001_ha,
 922                 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
 923                 "Enable = 0x%x\n", regVal1));
 924         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
 925         PM8001_INIT_DBG(pm8001_ha,
 926                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
 927                 "is set to = 0x%x\n",
 928                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
 929
 930         /* disable GSM - Write Address Parity Check */
 931         regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
 932         PM8001_INIT_DBG(pm8001_ha,
 933                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
 934                 " Enable = 0x%x\n", regVal2));
 935         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
 936         PM8001_INIT_DBG(pm8001_ha,
 937                 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
 938                 "Enable is set to = 0x%x\n",
 939                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
 940
 941         /* disable GSM - Write Data Parity Check */
 942         regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
 943         PM8001_INIT_DBG(pm8001_ha,
 944                 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
 945                 " Enable = 0x%x\n", regVal3));
 946         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
 947         PM8001_INIT_DBG(pm8001_ha,
 948                 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
 949                 "is set to = 0x%x\n",
 950         pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
 951
 952         /* step 5: delay 10 usec */
 953         udelay(10);
 954         /* step 5-b: set GPIO-0 output control to tristate anyway */
 955         if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
 956                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 957                 PM8001_INIT_DBG(pm8001_ha,
 958                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 959                                 GPIO_ADDR_BASE));
 960                 return -1;
 961         }
 962         regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
 963                 PM8001_INIT_DBG(pm8001_ha,
 964                                 pm8001_printk("GPIO Output Control Register:"
 965                                 " = 0x%x\n", regVal));
 966         /* set GPIO-0 output control to tri-state */
 967         regVal &= 0xFFFFFFFC;
 968         pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
 969
 970         /* Step 6: Reset the IOP and AAP1 */
 971         /* map 0x00000 to BAR4(0x20), BAR2(win) */
 972         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
 973                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 974                 PM8001_FAIL_DBG(pm8001_ha,
 975                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
 976                         SPC_TOP_LEVEL_ADDR_BASE));
 977                 return -1;
 978         }
 979         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 980         PM8001_INIT_DBG(pm8001_ha,
 981                 pm8001_printk("Top Register before resetting IOP/AAP1"
 982                 ":= 0x%x\n", regVal));
 983         regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
 984         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 985
 986         /* step 7: Reset the BDMA/OSSP */
 987         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 988         PM8001_INIT_DBG(pm8001_ha,
 989                 pm8001_printk("Top Register before resetting BDMA/OSSP"
 990                 ": = 0x%x\n", regVal));
 991         regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 992         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 993
 994         /* step 8: delay 10 usec */
 995         udelay(10);
 996
 997         /* step 9: bring the BDMA and OSSP out of reset */
 998         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 999         PM8001_INIT_DBG(pm8001_ha,
1000                 pm8001_printk("Top Register before bringing up BDMA/OSSP"
1001                 ":= 0x%x\n", regVal));
1002         regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
1003         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1004
1005         /* step 10: delay 10 usec */
1006         udelay(10);
1007
1008         /* step 11: reads and sets the GSM Configuration and Reset Register */
1009         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
1010         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
1011                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1012                 PM8001_FAIL_DBG(pm8001_ha,
1013                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
1014                         GSM_ADDR_BASE));
1015                 return -1;
1016         }
1017         PM8001_INIT_DBG(pm8001_ha,
1018                 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
1019                 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
1020         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
1021         /* Put those bits to high */
1022         /* GSM XCBI offset = 0x70 0000
1023         0x00 Bit 13 COM_SLV_SW_RSTB 1
1024         0x00 Bit 12 QSSP_SW_RSTB 1
1025         0x00 Bit 11 RAAE_SW_RSTB 1
1026         0x00 Bit 9   RB_1_SW_RSTB 1
1027         0x00 Bit 8   SM_SW_RSTB 1
1028         */
1029         regVal |= (GSM_CONFIG_RESET_VALUE);
1030         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1031         PM8001_INIT_DBG(pm8001_ha,
1032                 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
1033                 " Configuration and Reset is set to = 0x%x\n",
1034                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
1035
1036         /* step 12: Restore GSM - Read Address Parity Check */
1037         regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1038         /* just for debugging */
1039         PM8001_INIT_DBG(pm8001_ha,
1040                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
1041                 " = 0x%x\n", regVal));
1042         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
1043         PM8001_INIT_DBG(pm8001_ha,
1044                 pm8001_printk("GSM 0x700038 - Read Address Parity"
1045                 " Check Enable is set to = 0x%x\n",
1046                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
1047         /* Restore GSM - Write Address Parity Check */
1048         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1049         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
1050         PM8001_INIT_DBG(pm8001_ha,
1051                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
1052                 " Enable is set to = 0x%x\n",
1053                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
1054         /* Restore GSM - Write Data Parity Check */
1055         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1056         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
1057         PM8001_INIT_DBG(pm8001_ha,
1058                 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
1059                 "is set to = 0x%x\n",
1060                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
1061
1062         /* step 13: bring the IOP and AAP1 out of reset */
1063         /* map 0x00000 to BAR4(0x20), BAR2(win) */
1064         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1065                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1066                 PM8001_FAIL_DBG(pm8001_ha,
1067                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
1068                         SPC_TOP_LEVEL_ADDR_BASE));
1069                 return -1;
1070         }
1071         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1072         regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1073         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1074
1075         /* step 14: delay 10 usec - Normal Mode */
1076         udelay(10);
1077         /* check Soft Reset Normal mode or Soft Reset HDA mode */
1078         if (signature == SPC_SOFT_RESET_SIGNATURE) {
1079                 /* step 15 (Normal Mode): wait until scratch pad1 register
1080                 bit 2 toggled */
1081                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1082                 do {
1083                         udelay(1);
1084                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1085                                 SCRATCH_PAD1_RST;
1086                 } while ((regVal != toggleVal) && (--max_wait_count));
1087
1088                 if (!max_wait_count) {
1089                         regVal = pm8001_cr32(pm8001_ha, 0,
1090                                 MSGU_SCRATCH_PAD_1);
1091                         PM8001_FAIL_DBG(pm8001_ha,
1092                                 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
1093                                 "MSGU_SCRATCH_PAD1 = 0x%x\n",
1094                                 toggleVal, regVal));
1095                         PM8001_FAIL_DBG(pm8001_ha,
1096                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1097                                 pm8001_cr32(pm8001_ha, 0,
1098                                 MSGU_SCRATCH_PAD_0)));
1099                         PM8001_FAIL_DBG(pm8001_ha,
1100                                 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1101                                 pm8001_cr32(pm8001_ha, 0,
1102                                 MSGU_SCRATCH_PAD_2)));
1103                         PM8001_FAIL_DBG(pm8001_ha,
1104                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1105                                 pm8001_cr32(pm8001_ha, 0,
1106                                 MSGU_SCRATCH_PAD_3)));
1107                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1108                         return -1;
1109                 }
1110
1111                 /* step 16 (Normal) - Clear ODMR and ODCR */
1112                 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1113                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1114
1115                 /* step 17 (Normal Mode): wait for the FW and IOP to get
1116                 ready - 1 sec timeout */
1117                 /* Wait for the SPC Configuration Table to be ready */
1118                 if (check_fw_ready(pm8001_ha) == -1) {
1119                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1120                         /* return error if MPI Configuration Table not ready */
1121                         PM8001_INIT_DBG(pm8001_ha,
1122                                 pm8001_printk("FW not ready SCRATCH_PAD1"
1123                                 " = 0x%x\n", regVal));
1124                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1125                         /* return error if MPI Configuration Table not ready */
1126                         PM8001_INIT_DBG(pm8001_ha,
1127                                 pm8001_printk("FW not ready SCRATCH_PAD2"
1128                                 " = 0x%x\n", regVal));
1129                         PM8001_INIT_DBG(pm8001_ha,
1130                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1131                                 pm8001_cr32(pm8001_ha, 0,
1132                                 MSGU_SCRATCH_PAD_0)));
1133                         PM8001_INIT_DBG(pm8001_ha,
1134                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1135                                 pm8001_cr32(pm8001_ha, 0,
1136                                 MSGU_SCRATCH_PAD_3)));
1137                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1138                         return -1;
1139                 }
1140         }
1141         pm8001_bar4_shift(pm8001_ha, 0);
1142         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1143
1144         PM8001_INIT_DBG(pm8001_ha,
1145                 pm8001_printk("SPC soft reset Complete\n"));
1146         return 0;
1147 }
1148
1149 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1150 {
1151         u32 i;
1152         u32 regVal;
1153         PM8001_INIT_DBG(pm8001_ha,
1154                 pm8001_printk("chip reset start\n"));
1155
1156         /* do SPC chip reset. */
1157         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1158         regVal &= ~(SPC_REG_RESET_DEVICE);
1159         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1160
1161         /* delay 10 usec */
1162         udelay(10);
1163
1164         /* bring chip reset out of reset */
1165         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1166         regVal |= SPC_REG_RESET_DEVICE;
1167         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1168
1169         /* delay 10 usec */
1170         udelay(10);
1171
1172         /* wait for 20 msec until the firmware gets reloaded */
1173         i = 20;
1174         do {
1175                 mdelay(1);
1176         } while ((--i) != 0);
1177
1178         PM8001_INIT_DBG(pm8001_ha,
1179                 pm8001_printk("chip reset finished\n"));
1180 }
1181
1182 /**
1183  * pm8001_chip_iounmap - which maped when initialized.
1184  * @pm8001_ha: our hba card information
1185  */
1186 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1187 {
1188         s8 bar, logical = 0;
1189         for (bar = 0; bar < 6; bar++) {
1190                 /*
1191                 ** logical BARs for SPC:
1192                 ** bar 0 and 1 - logical BAR0
1193                 ** bar 2 and 3 - logical BAR1
1194                 ** bar4 - logical BAR2
1195                 ** bar5 - logical BAR3
1196                 ** Skip the appropriate assignments:
1197                 */
1198                 if ((bar == 1) || (bar == 3))
1199                         continue;
1200                 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1201                         iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1202                         logical++;
1203                 }
1204         }
1205 }
1206
1207 /**
1208  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1209  * @pm8001_ha: our hba card information
1210  */
1211 static void
1212 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1213 {
1214         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1215         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1216 }
1217
1218  /**
1219   * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1220   * @pm8001_ha: our hba card information
1221   */
1222 static void
1223 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1224 {
1225         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1226 }
1227
1228 /**
1229  * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1230  * @pm8001_ha: our hba card information
1231  */
1232 static void
1233 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1234         u32 int_vec_idx)
1235 {
1236         u32 msi_index;
1237         u32 value;
1238         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1239         msi_index += MSIX_TABLE_BASE;
1240         pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1241         value = (1 << int_vec_idx);
1242         pm8001_cw32(pm8001_ha, 0,  MSGU_ODCR, value);
1243
1244 }
1245
1246 /**
1247  * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1248  * @pm8001_ha: our hba card information
1249  */
1250 static void
1251 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1252         u32 int_vec_idx)
1253 {
1254         u32 msi_index;
1255         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1256         msi_index += MSIX_TABLE_BASE;
1257         pm8001_cw32(pm8001_ha, 0,  msi_index, MSIX_INTERRUPT_DISABLE);
1258 }
1259
1260 /**
1261  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1262  * @pm8001_ha: our hba card information
1263  */
1264 static void
1265 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1266 {
1267 #ifdef PM8001_USE_MSIX
1268         pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1269         return;
1270 #endif
1271         pm8001_chip_intx_interrupt_enable(pm8001_ha);
1272
1273 }
1274
1275 /**
1276  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1277  * @pm8001_ha: our hba card information
1278  */
1279 static void
1280 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1281 {
1282 #ifdef PM8001_USE_MSIX
1283         pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1284         return;
1285 #endif
1286         pm8001_chip_intx_interrupt_disable(pm8001_ha);
1287
1288 }
1289
1290 /**
1291  * pm8001_mpi_msg_free_get - get the free message buffer for transfer
1292  * inbound queue.
1293  * @circularQ: the inbound queue  we want to transfer to HBA.
1294  * @messageSize: the message size of this transfer, normally it is 64 bytes
1295  * @messagePtr: the pointer to message.
1296  */
1297 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
1298                             u16 messageSize, void **messagePtr)
1299 {
1300         u32 offset, consumer_index;
1301         struct mpi_msg_hdr *msgHeader;
1302         u8 bcCount = 1; /* only support single buffer */
1303
1304         /* Checks is the requested message size can be allocated in this queue*/
1305         if (messageSize > IOMB_SIZE_SPCV) {
1306                 *messagePtr = NULL;
1307                 return -1;
1308         }
1309
1310         /* Stores the new consumer index */
1311         consumer_index = pm8001_read_32(circularQ->ci_virt);
1312         circularQ->consumer_index = cpu_to_le32(consumer_index);
1313         if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
1314                 le32_to_cpu(circularQ->consumer_index)) {
1315                 *messagePtr = NULL;
1316                 return -1;
1317         }
1318         /* get memory IOMB buffer address */
1319         offset = circularQ->producer_idx * messageSize;
1320         /* increment to next bcCount element */
1321         circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1322                                 % PM8001_MPI_QUEUE;
1323         /* Adds that distance to the base of the region virtual address plus
1324         the message header size*/
1325         msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1326         *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1327         return 0;
1328 }
1329
1330 /**
1331  * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
1332  * FW to tell the fw to get this message from IOMB.
1333  * @pm8001_ha: our hba card information
1334  * @circularQ: the inbound queue we want to transfer to HBA.
1335  * @opCode: the operation code represents commands which LLDD and fw recognized.
1336  * @payload: the command payload of each operation command.
1337  */
1338 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1339                          struct inbound_queue_table *circularQ,
1340                          u32 opCode, void *payload, u32 responseQueue)
1341 {
1342         u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1343         void *pMessage;
1344
1345         if (pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
1346                 &pMessage) < 0) {
1347                 PM8001_IO_DBG(pm8001_ha,
1348                         pm8001_printk("No free mpi buffer\n"));
1349                 return -1;
1350         }
1351         BUG_ON(!payload);
1352         /*Copy to the payload*/
1353         memcpy(pMessage, payload, (pm8001_ha->iomb_size -
1354                                 sizeof(struct mpi_msg_hdr)));
1355
1356         /*Build the header*/
1357         Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1358                 | ((responseQueue & 0x3F) << 16)
1359                 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1360
1361         pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1362         /*Update the PI to the firmware*/
1363         pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1364                 circularQ->pi_offset, circularQ->producer_idx);
1365         PM8001_IO_DBG(pm8001_ha,
1366                 pm8001_printk("INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
1367                         responseQueue, opCode, circularQ->producer_idx,
1368                         circularQ->consumer_index));
1369         return 0;
1370 }
1371
1372 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1373                             struct outbound_queue_table *circularQ, u8 bc)
1374 {
1375         u32 producer_index;
1376         struct mpi_msg_hdr *msgHeader;
1377         struct mpi_msg_hdr *pOutBoundMsgHeader;
1378
1379         msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1380         pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1381                                 circularQ->consumer_idx * pm8001_ha->iomb_size);
1382         if (pOutBoundMsgHeader != msgHeader) {
1383                 PM8001_FAIL_DBG(pm8001_ha,
1384                         pm8001_printk("consumer_idx = %d msgHeader = %p\n",
1385                         circularQ->consumer_idx, msgHeader));
1386
1387                 /* Update the producer index from SPC */
1388                 producer_index = pm8001_read_32(circularQ->pi_virt);
1389                 circularQ->producer_index = cpu_to_le32(producer_index);
1390                 PM8001_FAIL_DBG(pm8001_ha,
1391                         pm8001_printk("consumer_idx = %d producer_index = %d"
1392                         "msgHeader = %p\n", circularQ->consumer_idx,
1393                         circularQ->producer_index, msgHeader));
1394                 return 0;
1395         }
1396         /* free the circular queue buffer elements associated with the message*/
1397         circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1398                                 % PM8001_MPI_QUEUE;
1399         /* update the CI of outbound queue */
1400         pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1401                 circularQ->consumer_idx);
1402         /* Update the producer index from SPC*/
1403         producer_index = pm8001_read_32(circularQ->pi_virt);
1404         circularQ->producer_index = cpu_to_le32(producer_index);
1405         PM8001_IO_DBG(pm8001_ha,
1406                 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1407                 circularQ->producer_index));
1408         return 0;
1409 }
1410
1411 /**
1412  * pm8001_mpi_msg_consume- get the MPI message from outbound queue
1413  * message table.
1414  * @pm8001_ha: our hba card information
1415  * @circularQ: the outbound queue  table.
1416  * @messagePtr1: the message contents of this outbound message.
1417  * @pBC: the message size.
1418  */
1419 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1420                            struct outbound_queue_table *circularQ,
1421                            void **messagePtr1, u8 *pBC)
1422 {
1423         struct mpi_msg_hdr      *msgHeader;
1424         __le32  msgHeader_tmp;
1425         u32 header_tmp;
1426         do {
1427                 /* If there are not-yet-delivered messages ... */
1428                 if (le32_to_cpu(circularQ->producer_index)
1429                         != circularQ->consumer_idx) {
1430                         /*Get the pointer to the circular queue buffer element*/
1431                         msgHeader = (struct mpi_msg_hdr *)
1432                                 (circularQ->base_virt +
1433                                 circularQ->consumer_idx * pm8001_ha->iomb_size);
1434                         /* read header */
1435                         header_tmp = pm8001_read_32(msgHeader);
1436                         msgHeader_tmp = cpu_to_le32(header_tmp);
1437                         if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1438                                 if (OPC_OUB_SKIP_ENTRY !=
1439                                         (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1440                                         *messagePtr1 =
1441                                                 ((u8 *)msgHeader) +
1442                                                 sizeof(struct mpi_msg_hdr);
1443                                         *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1444                                                 >> 24) & 0x1f);
1445                                         PM8001_IO_DBG(pm8001_ha,
1446                                                 pm8001_printk(": CI=%d PI=%d "
1447                                                 "msgHeader=%x\n",
1448                                                 circularQ->consumer_idx,
1449                                                 circularQ->producer_index,
1450                                                 msgHeader_tmp));
1451                                         return MPI_IO_STATUS_SUCCESS;
1452                                 } else {
1453                                         circularQ->consumer_idx =
1454                                                 (circularQ->consumer_idx +
1455                                                 ((le32_to_cpu(msgHeader_tmp)
1456                                                  >> 24) & 0x1f))
1457                                                         % PM8001_MPI_QUEUE;
1458                                         msgHeader_tmp = 0;
1459                                         pm8001_write_32(msgHeader, 0, 0);
1460                                         /* update the CI of outbound queue */
1461                                         pm8001_cw32(pm8001_ha,
1462                                                 circularQ->ci_pci_bar,
1463                                                 circularQ->ci_offset,
1464                                                 circularQ->consumer_idx);
1465                                 }
1466                         } else {
1467                                 circularQ->consumer_idx =
1468                                         (circularQ->consumer_idx +
1469                                         ((le32_to_cpu(msgHeader_tmp) >> 24) &
1470                                         0x1f)) % PM8001_MPI_QUEUE;
1471                                 msgHeader_tmp = 0;
1472                                 pm8001_write_32(msgHeader, 0, 0);
1473                                 /* update the CI of outbound queue */
1474                                 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1475                                         circularQ->ci_offset,
1476                                         circularQ->consumer_idx);
1477                                 return MPI_IO_STATUS_FAIL;
1478                         }
1479                 } else {
1480                         u32 producer_index;
1481                         void *pi_virt = circularQ->pi_virt;
1482                         /* Update the producer index from SPC */
1483                         producer_index = pm8001_read_32(pi_virt);
1484                         circularQ->producer_index = cpu_to_le32(producer_index);
1485                 }
1486         } while (le32_to_cpu(circularQ->producer_index) !=
1487                 circularQ->consumer_idx);
1488         /* while we don't have any more not-yet-delivered message */
1489         /* report empty */
1490         return MPI_IO_STATUS_BUSY;
1491 }
1492
1493 void pm8001_work_fn(struct work_struct *work)
1494 {
1495         struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1496         struct pm8001_device *pm8001_dev;
1497         struct domain_device *dev;
1498
1499         /*
1500          * So far, all users of this stash an associated structure here.
1501          * If we get here, and this pointer is null, then the action
1502          * was cancelled. This nullification happens when the device
1503          * goes away.
1504          */
1505         pm8001_dev = pw->data; /* Most stash device structure */
1506         if ((pm8001_dev == NULL)
1507          || ((pw->handler != IO_XFER_ERROR_BREAK)
1508           && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) {
1509                 kfree(pw);
1510                 return;
1511         }
1512
1513         switch (pw->handler) {
1514         case IO_XFER_ERROR_BREAK:
1515         {       /* This one stashes the sas_task instead */
1516                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1517                 u32 tag;
1518                 struct pm8001_ccb_info *ccb;
1519                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1520                 unsigned long flags, flags1;
1521                 struct task_status_struct *ts;
1522                 int i;
1523
1524                 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1525                         break; /* Task still on lu */
1526                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1527
1528                 spin_lock_irqsave(&t->task_state_lock, flags1);
1529                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1530                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1531                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1532                         break; /* Task got completed by another */
1533                 }
1534                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1535
1536                 /* Search for a possible ccb that matches the task */
1537                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1538                         ccb = &pm8001_ha->ccb_info[i];
1539                         tag = ccb->ccb_tag;
1540                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1541                                 break;
1542                 }
1543                 if (!ccb) {
1544                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1545                         break; /* Task got freed by another */
1546                 }
1547                 ts = &t->task_status;
1548                 ts->resp = SAS_TASK_COMPLETE;
1549                 /* Force the midlayer to retry */
1550                 ts->stat = SAS_QUEUE_FULL;
1551                 pm8001_dev = ccb->device;
1552                 if (pm8001_dev)
1553                         pm8001_dev->running_req--;
1554                 spin_lock_irqsave(&t->task_state_lock, flags1);
1555                 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1556                 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1557                 t->task_state_flags |= SAS_TASK_STATE_DONE;
1558                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1559                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1560                         PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p"
1561                                 " done with event 0x%x resp 0x%x stat 0x%x but"
1562                                 " aborted by upper layer!\n",
1563                                 t, pw->handler, ts->resp, ts->stat));
1564                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1565                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1566                 } else {
1567                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1568                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1569                         mb();/* in order to force CPU ordering */
1570                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1571                         t->task_done(t);
1572                 }
1573         }       break;
1574         case IO_XFER_OPEN_RETRY_TIMEOUT:
1575         {       /* This one stashes the sas_task instead */
1576                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1577                 u32 tag;
1578                 struct pm8001_ccb_info *ccb;
1579                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1580                 unsigned long flags, flags1;
1581                 int i, ret = 0;
1582
1583                 PM8001_IO_DBG(pm8001_ha,
1584                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1585
1586                 ret = pm8001_query_task(t);
1587
1588                 PM8001_IO_DBG(pm8001_ha,
1589                         switch (ret) {
1590                         case TMF_RESP_FUNC_SUCC:
1591                                 pm8001_printk("...Task on lu\n");
1592                                 break;
1593
1594                         case TMF_RESP_FUNC_COMPLETE:
1595                                 pm8001_printk("...Task NOT on lu\n");
1596                                 break;
1597
1598                         default:
1599                                 pm8001_printk("...query task failed!!!\n");
1600                                 break;
1601                         });
1602
1603                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1604
1605                 spin_lock_irqsave(&t->task_state_lock, flags1);
1606
1607                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1608                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1609                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1610                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1611                                 (void)pm8001_abort_task(t);
1612                         break; /* Task got completed by another */
1613                 }
1614
1615                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1616
1617                 /* Search for a possible ccb that matches the task */
1618                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1619                         ccb = &pm8001_ha->ccb_info[i];
1620                         tag = ccb->ccb_tag;
1621                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1622                                 break;
1623                 }
1624                 if (!ccb) {
1625                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1626                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1627                                 (void)pm8001_abort_task(t);
1628                         break; /* Task got freed by another */
1629                 }
1630
1631                 pm8001_dev = ccb->device;
1632                 dev = pm8001_dev->sas_device;
1633
1634                 switch (ret) {
1635                 case TMF_RESP_FUNC_SUCC: /* task on lu */
1636                         ccb->open_retry = 1; /* Snub completion */
1637                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1638                         ret = pm8001_abort_task(t);
1639                         ccb->open_retry = 0;
1640                         switch (ret) {
1641                         case TMF_RESP_FUNC_SUCC:
1642                         case TMF_RESP_FUNC_COMPLETE:
1643                                 break;
1644                         default: /* device misbehavior */
1645                                 ret = TMF_RESP_FUNC_FAILED;
1646                                 PM8001_IO_DBG(pm8001_ha,
1647                                         pm8001_printk("...Reset phy\n"));
1648                                 pm8001_I_T_nexus_reset(dev);
1649                                 break;
1650                         }
1651                         break;
1652
1653                 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1654                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1655                         /* Do we need to abort the task locally? */
1656                         break;
1657
1658                 default: /* device misbehavior */
1659                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1660                         ret = TMF_RESP_FUNC_FAILED;
1661                         PM8001_IO_DBG(pm8001_ha,
1662                                 pm8001_printk("...Reset phy\n"));
1663                         pm8001_I_T_nexus_reset(dev);
1664                 }
1665
1666                 if (ret == TMF_RESP_FUNC_FAILED)
1667                         t = NULL;
1668                 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1669                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n"));
1670         }       break;
1671         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1672                 dev = pm8001_dev->sas_device;
1673                 pm8001_I_T_nexus_event_handler(dev);
1674                 break;
1675         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1676                 dev = pm8001_dev->sas_device;
1677                 pm8001_I_T_nexus_reset(dev);
1678                 break;
1679         case IO_DS_IN_ERROR:
1680                 dev = pm8001_dev->sas_device;
1681                 pm8001_I_T_nexus_reset(dev);
1682                 break;
1683         case IO_DS_NON_OPERATIONAL:
1684                 dev = pm8001_dev->sas_device;
1685                 pm8001_I_T_nexus_reset(dev);
1686                 break;
1687         }
1688         kfree(pw);
1689 }
1690
1691 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1692                                int handler)
1693 {
1694         struct pm8001_work *pw;
1695         int ret = 0;
1696
1697         pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1698         if (pw) {
1699                 pw->pm8001_ha = pm8001_ha;
1700                 pw->data = data;
1701                 pw->handler = handler;
1702                 INIT_WORK(&pw->work, pm8001_work_fn);
1703                 queue_work(pm8001_wq, &pw->work);
1704         } else
1705                 ret = -ENOMEM;
1706
1707         return ret;
1708 }
1709
1710 static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1711                 struct pm8001_device *pm8001_ha_dev)
1712 {
1713         int res;
1714         u32 ccb_tag;
1715         struct pm8001_ccb_info *ccb;
1716         struct sas_task *task = NULL;
1717         struct task_abort_req task_abort;
1718         struct inbound_queue_table *circularQ;
1719         u32 opc = OPC_INB_SATA_ABORT;
1720         int ret;
1721
1722         if (!pm8001_ha_dev) {
1723                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1724                 return;
1725         }
1726
1727         task = sas_alloc_slow_task(GFP_ATOMIC);
1728
1729         if (!task) {
1730                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1731                                                 "allocate task\n"));
1732                 return;
1733         }
1734
1735         task->task_done = pm8001_task_done;
1736
1737         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1738         if (res)
1739                 return;
1740
1741         ccb = &pm8001_ha->ccb_info[ccb_tag];
1742         ccb->device = pm8001_ha_dev;
1743         ccb->ccb_tag = ccb_tag;
1744         ccb->task = task;
1745
1746         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1747
1748         memset(&task_abort, 0, sizeof(task_abort));
1749         task_abort.abort_all = cpu_to_le32(1);
1750         task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1751         task_abort.tag = cpu_to_le32(ccb_tag);
1752
1753         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1754
1755 }
1756
1757 static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha,
1758                 struct pm8001_device *pm8001_ha_dev)
1759 {
1760         struct sata_start_req sata_cmd;
1761         int res;
1762         u32 ccb_tag;
1763         struct pm8001_ccb_info *ccb;
1764         struct sas_task *task = NULL;
1765         struct host_to_dev_fis fis;
1766         struct domain_device *dev;
1767         struct inbound_queue_table *circularQ;
1768         u32 opc = OPC_INB_SATA_HOST_OPSTART;
1769
1770         task = sas_alloc_slow_task(GFP_ATOMIC);
1771
1772         if (!task) {
1773                 PM8001_FAIL_DBG(pm8001_ha,
1774                         pm8001_printk("cannot allocate task !!!\n"));
1775                 return;
1776         }
1777         task->task_done = pm8001_task_done;
1778
1779         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1780         if (res) {
1781                 PM8001_FAIL_DBG(pm8001_ha,
1782                         pm8001_printk("cannot allocate tag !!!\n"));
1783                 return;
1784         }
1785
1786         /* allocate domain device by ourselves as libsas
1787          * is not going to provide any
1788         */
1789         dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1790         if (!dev) {
1791                 PM8001_FAIL_DBG(pm8001_ha,
1792                         pm8001_printk("Domain device cannot be allocated\n"));
1793                 sas_free_task(task);
1794                 return;
1795         } else {
1796                 task->dev = dev;
1797                 task->dev->lldd_dev = pm8001_ha_dev;
1798         }
1799
1800         ccb = &pm8001_ha->ccb_info[ccb_tag];
1801         ccb->device = pm8001_ha_dev;
1802         ccb->ccb_tag = ccb_tag;
1803         ccb->task = task;
1804         pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1805         pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1806
1807         memset(&sata_cmd, 0, sizeof(sata_cmd));
1808         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1809
1810         /* construct read log FIS */
1811         memset(&fis, 0, sizeof(struct host_to_dev_fis));
1812         fis.fis_type = 0x27;
1813         fis.flags = 0x80;
1814         fis.command = ATA_CMD_READ_LOG_EXT;
1815         fis.lbal = 0x10;
1816         fis.sector_count = 0x1;
1817
1818         sata_cmd.tag = cpu_to_le32(ccb_tag);
1819         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1820         sata_cmd.ncqtag_atap_dir_m |= ((0x1 << 7) | (0x5 << 9));
1821         memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1822
1823         res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1824
1825 }
1826
1827 /**
1828  * mpi_ssp_completion- process the event that FW response to the SSP request.
1829  * @pm8001_ha: our hba card information
1830  * @piomb: the message contents of this outbound message.
1831  *
1832  * When FW has completed a ssp request for example a IO request, after it has
1833  * filled the SG data with the data, it will trigger this event represent
1834  * that he has finished the job,please check the coresponding buffer.
1835  * So we will tell the caller who maybe waiting the result to tell upper layer
1836  * that the task has been finished.
1837  */
1838 static void
1839 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1840 {
1841         struct sas_task *t;
1842         struct pm8001_ccb_info *ccb;
1843         unsigned long flags;
1844         u32 status;
1845         u32 param;
1846         u32 tag;
1847         struct ssp_completion_resp *psspPayload;
1848         struct task_status_struct *ts;
1849         struct ssp_response_iu *iu;
1850         struct pm8001_device *pm8001_dev;
1851         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1852         status = le32_to_cpu(psspPayload->status);
1853         tag = le32_to_cpu(psspPayload->tag);
1854         ccb = &pm8001_ha->ccb_info[tag];
1855         if ((status == IO_ABORTED) && ccb->open_retry) {
1856                 /* Being completed by another */
1857                 ccb->open_retry = 0;
1858                 return;
1859         }
1860         pm8001_dev = ccb->device;
1861         param = le32_to_cpu(psspPayload->param);
1862
1863         t = ccb->task;
1864
1865         if (status && status != IO_UNDERFLOW)
1866                 PM8001_FAIL_DBG(pm8001_ha,
1867                         pm8001_printk("sas IO status 0x%x\n", status));
1868         if (unlikely(!t || !t->lldd_task || !t->dev))
1869                 return;
1870         ts = &t->task_status;
1871         /* Print sas address of IO failed device */
1872         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1873                 (status != IO_UNDERFLOW))
1874                 PM8001_FAIL_DBG(pm8001_ha,
1875                         pm8001_printk("SAS Address of IO Failure Drive:"
1876                         "%016llx", SAS_ADDR(t->dev->sas_addr)));
1877
1878         switch (status) {
1879         case IO_SUCCESS:
1880                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1881                         ",param = %d\n", param));
1882                 if (param == 0) {
1883                         ts->resp = SAS_TASK_COMPLETE;
1884                         ts->stat = SAM_STAT_GOOD;
1885                 } else {
1886                         ts->resp = SAS_TASK_COMPLETE;
1887                         ts->stat = SAS_PROTO_RESPONSE;
1888                         ts->residual = param;
1889                         iu = &psspPayload->ssp_resp_iu;
1890                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1891                 }
1892                 if (pm8001_dev)
1893                         pm8001_dev->running_req--;
1894                 break;
1895         case IO_ABORTED:
1896                 PM8001_IO_DBG(pm8001_ha,
1897                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
1898                 ts->resp = SAS_TASK_COMPLETE;
1899                 ts->stat = SAS_ABORTED_TASK;
1900                 break;
1901         case IO_UNDERFLOW:
1902                 /* SSP Completion with error */
1903                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1904                         ",param = %d\n", param));
1905                 ts->resp = SAS_TASK_COMPLETE;
1906                 ts->stat = SAS_DATA_UNDERRUN;
1907                 ts->residual = param;
1908                 if (pm8001_dev)
1909                         pm8001_dev->running_req--;
1910                 break;
1911         case IO_NO_DEVICE:
1912                 PM8001_IO_DBG(pm8001_ha,
1913                         pm8001_printk("IO_NO_DEVICE\n"));
1914                 ts->resp = SAS_TASK_UNDELIVERED;
1915                 ts->stat = SAS_PHY_DOWN;
1916                 break;
1917         case IO_XFER_ERROR_BREAK:
1918                 PM8001_IO_DBG(pm8001_ha,
1919                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1920                 ts->resp = SAS_TASK_COMPLETE;
1921                 ts->stat = SAS_OPEN_REJECT;
1922                 /* Force the midlayer to retry */
1923                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1924                 break;
1925         case IO_XFER_ERROR_PHY_NOT_READY:
1926                 PM8001_IO_DBG(pm8001_ha,
1927                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1928                 ts->resp = SAS_TASK_COMPLETE;
1929                 ts->stat = SAS_OPEN_REJECT;
1930                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1931                 break;
1932         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1933                 PM8001_IO_DBG(pm8001_ha,
1934                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1935                 ts->resp = SAS_TASK_COMPLETE;
1936                 ts->stat = SAS_OPEN_REJECT;
1937                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1938                 break;
1939         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1940                 PM8001_IO_DBG(pm8001_ha,
1941                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1942                 ts->resp = SAS_TASK_COMPLETE;
1943                 ts->stat = SAS_OPEN_REJECT;
1944                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1945                 break;
1946         case IO_OPEN_CNX_ERROR_BREAK:
1947                 PM8001_IO_DBG(pm8001_ha,
1948                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1949                 ts->resp = SAS_TASK_COMPLETE;
1950                 ts->stat = SAS_OPEN_REJECT;
1951                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1952                 break;
1953         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1954                 PM8001_IO_DBG(pm8001_ha,
1955                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1956                 ts->resp = SAS_TASK_COMPLETE;
1957                 ts->stat = SAS_OPEN_REJECT;
1958                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1959                 if (!t->uldd_task)
1960                         pm8001_handle_event(pm8001_ha,
1961                                 pm8001_dev,
1962                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1963                 break;
1964         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1965                 PM8001_IO_DBG(pm8001_ha,
1966                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1967                 ts->resp = SAS_TASK_COMPLETE;
1968                 ts->stat = SAS_OPEN_REJECT;
1969                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1970                 break;
1971         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1972                 PM8001_IO_DBG(pm8001_ha,
1973                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1974                         "NOT_SUPPORTED\n"));
1975                 ts->resp = SAS_TASK_COMPLETE;
1976                 ts->stat = SAS_OPEN_REJECT;
1977                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1978                 break;
1979         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1980                 PM8001_IO_DBG(pm8001_ha,
1981                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1982                 ts->resp = SAS_TASK_UNDELIVERED;
1983                 ts->stat = SAS_OPEN_REJECT;
1984                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1985                 break;
1986         case IO_XFER_ERROR_NAK_RECEIVED:
1987                 PM8001_IO_DBG(pm8001_ha,
1988                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1989                 ts->resp = SAS_TASK_COMPLETE;
1990                 ts->stat = SAS_OPEN_REJECT;
1991                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1992                 break;
1993         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1994                 PM8001_IO_DBG(pm8001_ha,
1995                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1996                 ts->resp = SAS_TASK_COMPLETE;
1997                 ts->stat = SAS_NAK_R_ERR;
1998                 break;
1999         case IO_XFER_ERROR_DMA:
2000                 PM8001_IO_DBG(pm8001_ha,
2001                 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2002                 ts->resp = SAS_TASK_COMPLETE;
2003                 ts->stat = SAS_OPEN_REJECT;
2004                 break;
2005         case IO_XFER_OPEN_RETRY_TIMEOUT:
2006                 PM8001_IO_DBG(pm8001_ha,
2007                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2008                 ts->resp = SAS_TASK_COMPLETE;
2009                 ts->stat = SAS_OPEN_REJECT;
2010                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2011                 break;
2012         case IO_XFER_ERROR_OFFSET_MISMATCH:
2013                 PM8001_IO_DBG(pm8001_ha,
2014                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2015                 ts->resp = SAS_TASK_COMPLETE;
2016                 ts->stat = SAS_OPEN_REJECT;
2017                 break;
2018         case IO_PORT_IN_RESET:
2019                 PM8001_IO_DBG(pm8001_ha,
2020                         pm8001_printk("IO_PORT_IN_RESET\n"));
2021                 ts->resp = SAS_TASK_COMPLETE;
2022                 ts->stat = SAS_OPEN_REJECT;
2023                 break;
2024         case IO_DS_NON_OPERATIONAL:
2025                 PM8001_IO_DBG(pm8001_ha,
2026                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2027                 ts->resp = SAS_TASK_COMPLETE;
2028                 ts->stat = SAS_OPEN_REJECT;
2029                 if (!t->uldd_task)
2030                         pm8001_handle_event(pm8001_ha,
2031                                 pm8001_dev,
2032                                 IO_DS_NON_OPERATIONAL);
2033                 break;
2034         case IO_DS_IN_RECOVERY:
2035                 PM8001_IO_DBG(pm8001_ha,
2036                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2037                 ts->resp = SAS_TASK_COMPLETE;
2038                 ts->stat = SAS_OPEN_REJECT;
2039                 break;
2040         case IO_TM_TAG_NOT_FOUND:
2041                 PM8001_IO_DBG(pm8001_ha,
2042                         pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
2043                 ts->resp = SAS_TASK_COMPLETE;
2044                 ts->stat = SAS_OPEN_REJECT;
2045                 break;
2046         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2047                 PM8001_IO_DBG(pm8001_ha,
2048                         pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
2049                 ts->resp = SAS_TASK_COMPLETE;
2050                 ts->stat = SAS_OPEN_REJECT;
2051                 break;
2052         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2053                 PM8001_IO_DBG(pm8001_ha,
2054                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2055                 ts->resp = SAS_TASK_COMPLETE;
2056                 ts->stat = SAS_OPEN_REJECT;
2057                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2058                 break;
2059         default:
2060                 PM8001_IO_DBG(pm8001_ha,
2061                         pm8001_printk("Unknown status 0x%x\n", status));
2062                 /* not allowed case. Therefore, return failed status */
2063                 ts->resp = SAS_TASK_COMPLETE;
2064                 ts->stat = SAS_OPEN_REJECT;
2065                 break;
2066         }
2067         PM8001_IO_DBG(pm8001_ha,
2068                 pm8001_printk("scsi_status = %x\n ",
2069                 psspPayload->ssp_resp_iu.status));
2070         spin_lock_irqsave(&t->task_state_lock, flags);
2071         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2072         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2073         t->task_state_flags |= SAS_TASK_STATE_DONE;
2074         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2075                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2076                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2077                         " io_status 0x%x resp 0x%x "
2078                         "stat 0x%x but aborted by upper layer!\n",
2079                         t, status, ts->resp, ts->stat));
2080                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2081         } else {
2082                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2083                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2084                 mb();/* in order to force CPU ordering */
2085                 t->task_done(t);
2086         }
2087 }
2088
2089 /*See the comments for mpi_ssp_completion */
2090 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2091 {
2092         struct sas_task *t;
2093         unsigned long flags;
2094         struct task_status_struct *ts;
2095         struct pm8001_ccb_info *ccb;
2096         struct pm8001_device *pm8001_dev;
2097         struct ssp_event_resp *psspPayload =
2098                 (struct ssp_event_resp *)(piomb + 4);
2099         u32 event = le32_to_cpu(psspPayload->event);
2100         u32 tag = le32_to_cpu(psspPayload->tag);
2101         u32 port_id = le32_to_cpu(psspPayload->port_id);
2102         u32 dev_id = le32_to_cpu(psspPayload->device_id);
2103
2104         ccb = &pm8001_ha->ccb_info[tag];
2105         t = ccb->task;
2106         pm8001_dev = ccb->device;
2107         if (event)
2108                 PM8001_FAIL_DBG(pm8001_ha,
2109                         pm8001_printk("sas IO status 0x%x\n", event));
2110         if (unlikely(!t || !t->lldd_task || !t->dev))
2111                 return;
2112         ts = &t->task_status;
2113         PM8001_IO_DBG(pm8001_ha,
2114                 pm8001_printk("port_id = %x,device_id = %x\n",
2115                 port_id, dev_id));
2116         switch (event) {
2117         case IO_OVERFLOW:
2118                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
2119                 ts->resp = SAS_TASK_COMPLETE;
2120                 ts->stat = SAS_DATA_OVERRUN;
2121                 ts->residual = 0;
2122                 if (pm8001_dev)
2123                         pm8001_dev->running_req--;
2124                 break;
2125         case IO_XFER_ERROR_BREAK:
2126                 PM8001_IO_DBG(pm8001_ha,
2127                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2128                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2129                 return;
2130         case IO_XFER_ERROR_PHY_NOT_READY:
2131                 PM8001_IO_DBG(pm8001_ha,
2132                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2133                 ts->resp = SAS_TASK_COMPLETE;
2134                 ts->stat = SAS_OPEN_REJECT;
2135                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2136                 break;
2137         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2138                 PM8001_IO_DBG(pm8001_ha,
2139                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2140                         "_SUPPORTED\n"));
2141                 ts->resp = SAS_TASK_COMPLETE;
2142                 ts->stat = SAS_OPEN_REJECT;
2143                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2144                 break;
2145         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2146                 PM8001_IO_DBG(pm8001_ha,
2147                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2148                 ts->resp = SAS_TASK_COMPLETE;
2149                 ts->stat = SAS_OPEN_REJECT;
2150                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2151                 break;
2152         case IO_OPEN_CNX_ERROR_BREAK:
2153                 PM8001_IO_DBG(pm8001_ha,
2154                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2155                 ts->resp = SAS_TASK_COMPLETE;
2156                 ts->stat = SAS_OPEN_REJECT;
2157                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2158                 break;
2159         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2160                 PM8001_IO_DBG(pm8001_ha,
2161                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2162                 ts->resp = SAS_TASK_COMPLETE;
2163                 ts->stat = SAS_OPEN_REJECT;
2164                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2165                 if (!t->uldd_task)
2166                         pm8001_handle_event(pm8001_ha,
2167                                 pm8001_dev,
2168                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2169                 break;
2170         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2171                 PM8001_IO_DBG(pm8001_ha,
2172                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2173                 ts->resp = SAS_TASK_COMPLETE;
2174                 ts->stat = SAS_OPEN_REJECT;
2175                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2176                 break;
2177         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2178                 PM8001_IO_DBG(pm8001_ha,
2179                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2180                         "NOT_SUPPORTED\n"));
2181                 ts->resp = SAS_TASK_COMPLETE;
2182                 ts->stat = SAS_OPEN_REJECT;
2183                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2184                 break;
2185         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2186                 PM8001_IO_DBG(pm8001_ha,
2187                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2188                 ts->resp = SAS_TASK_COMPLETE;
2189                 ts->stat = SAS_OPEN_REJECT;
2190                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2191                 break;
2192         case IO_XFER_ERROR_NAK_RECEIVED:
2193                 PM8001_IO_DBG(pm8001_ha,
2194                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2195                 ts->resp = SAS_TASK_COMPLETE;
2196                 ts->stat = SAS_OPEN_REJECT;
2197                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2198                 break;
2199         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2200                 PM8001_IO_DBG(pm8001_ha,
2201                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2202                 ts->resp = SAS_TASK_COMPLETE;
2203                 ts->stat = SAS_NAK_R_ERR;
2204                 break;
2205         case IO_XFER_OPEN_RETRY_TIMEOUT:
2206                 PM8001_IO_DBG(pm8001_ha,
2207                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2208                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2209                 return;
2210         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2211                 PM8001_IO_DBG(pm8001_ha,
2212                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2213                 ts->resp = SAS_TASK_COMPLETE;
2214                 ts->stat = SAS_DATA_OVERRUN;
2215                 break;
2216         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2217                 PM8001_IO_DBG(pm8001_ha,
2218                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2219                 ts->resp = SAS_TASK_COMPLETE;
2220                 ts->stat = SAS_DATA_OVERRUN;
2221                 break;
2222         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2223                 PM8001_IO_DBG(pm8001_ha,
2224                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2225                 ts->resp = SAS_TASK_COMPLETE;
2226                 ts->stat = SAS_DATA_OVERRUN;
2227                 break;
2228         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2229                 PM8001_IO_DBG(pm8001_ha,
2230                 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2231                 ts->resp = SAS_TASK_COMPLETE;
2232                 ts->stat = SAS_DATA_OVERRUN;
2233                 break;
2234         case IO_XFER_ERROR_OFFSET_MISMATCH:
2235                 PM8001_IO_DBG(pm8001_ha,
2236                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2237                 ts->resp = SAS_TASK_COMPLETE;
2238                 ts->stat = SAS_DATA_OVERRUN;
2239                 break;
2240         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2241                 PM8001_IO_DBG(pm8001_ha,
2242                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2243                 ts->resp = SAS_TASK_COMPLETE;
2244                 ts->stat = SAS_DATA_OVERRUN;
2245                 break;
2246         case IO_XFER_CMD_FRAME_ISSUED:
2247                 PM8001_IO_DBG(pm8001_ha,
2248                         pm8001_printk("  IO_XFER_CMD_FRAME_ISSUED\n"));
2249                 return;
2250         default:
2251                 PM8001_IO_DBG(pm8001_ha,
2252                         pm8001_printk("Unknown status 0x%x\n", event));
2253                 /* not allowed case. Therefore, return failed status */
2254                 ts->resp = SAS_TASK_COMPLETE;
2255                 ts->stat = SAS_DATA_OVERRUN;
2256                 break;
2257         }
2258         spin_lock_irqsave(&t->task_state_lock, flags);
2259         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2260         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2261         t->task_state_flags |= SAS_TASK_STATE_DONE;
2262         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2263                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2264                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2265                         " event 0x%x resp 0x%x "
2266                         "stat 0x%x but aborted by upper layer!\n",
2267                         t, event, ts->resp, ts->stat));
2268                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2269         } else {
2270                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2271                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2272                 mb();/* in order to force CPU ordering */
2273                 t->task_done(t);
2274         }
2275 }
2276
2277 /*See the comments for mpi_ssp_completion */
2278 static void
2279 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2280 {
2281         struct sas_task *t;
2282         struct pm8001_ccb_info *ccb;
2283         u32 param;
2284         u32 status;
2285         u32 tag;
2286         int i, j;
2287         u8 sata_addr_low[4];
2288         u32 temp_sata_addr_low;
2289         u8 sata_addr_hi[4];
2290         u32 temp_sata_addr_hi;
2291         struct sata_completion_resp *psataPayload;
2292         struct task_status_struct *ts;
2293         struct ata_task_resp *resp ;
2294         u32 *sata_resp;
2295         struct pm8001_device *pm8001_dev;
2296         unsigned long flags;
2297
2298         psataPayload = (struct sata_completion_resp *)(piomb + 4);
2299         status = le32_to_cpu(psataPayload->status);
2300         tag = le32_to_cpu(psataPayload->tag);
2301
2302         if (!tag) {
2303                 PM8001_FAIL_DBG(pm8001_ha,
2304                         pm8001_printk("tag null\n"));
2305                 return;
2306         }
2307         ccb = &pm8001_ha->ccb_info[tag];
2308         param = le32_to_cpu(psataPayload->param);
2309         if (ccb) {
2310                 t = ccb->task;
2311                 pm8001_dev = ccb->device;
2312         } else {
2313                 PM8001_FAIL_DBG(pm8001_ha,
2314                         pm8001_printk("ccb null\n"));
2315                 return;
2316         }
2317
2318         if (t) {
2319                 if (t->dev && (t->dev->lldd_dev))
2320                         pm8001_dev = t->dev->lldd_dev;
2321         } else {
2322                 PM8001_FAIL_DBG(pm8001_ha,
2323                         pm8001_printk("task null\n"));
2324                 return;
2325         }
2326
2327         if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2328                 && unlikely(!t || !t->lldd_task || !t->dev)) {
2329                 PM8001_FAIL_DBG(pm8001_ha,
2330                         pm8001_printk("task or dev null\n"));
2331                 return;
2332         }
2333
2334         ts = &t->task_status;
2335         if (!ts) {
2336                 PM8001_FAIL_DBG(pm8001_ha,
2337                         pm8001_printk("ts null\n"));
2338                 return;
2339         }
2340         /* Print sas address of IO failed device */
2341         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2342                 (status != IO_UNDERFLOW)) {
2343                 if (!((t->dev->parent) &&
2344                         (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) {
2345                         for (i = 0 , j = 4; j <= 7 && i <= 3; i++ , j++)
2346                                 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2347                         for (i = 0 , j = 0; j <= 3 && i <= 3; i++ , j++)
2348                                 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2349                         memcpy(&temp_sata_addr_low, sata_addr_low,
2350                                 sizeof(sata_addr_low));
2351                         memcpy(&temp_sata_addr_hi, sata_addr_hi,
2352                                 sizeof(sata_addr_hi));
2353                         temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2354                                                 |((temp_sata_addr_hi << 8) &
2355                                                 0xff0000) |
2356                                                 ((temp_sata_addr_hi >> 8)
2357                                                 & 0xff00) |
2358                                                 ((temp_sata_addr_hi << 24) &
2359                                                 0xff000000));
2360                         temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2361                                                 & 0xff) |
2362                                                 ((temp_sata_addr_low << 8)
2363                                                 & 0xff0000) |
2364                                                 ((temp_sata_addr_low >> 8)
2365                                                 & 0xff00) |
2366                                                 ((temp_sata_addr_low << 24)
2367                                                 & 0xff000000)) +
2368                                                 pm8001_dev->attached_phy +
2369                                                 0x10);
2370                         PM8001_FAIL_DBG(pm8001_ha,
2371                                 pm8001_printk("SAS Address of IO Failure Drive:"
2372                                 "%08x%08x", temp_sata_addr_hi,
2373                                         temp_sata_addr_low));
2374                 } else {
2375                         PM8001_FAIL_DBG(pm8001_ha,
2376                                 pm8001_printk("SAS Address of IO Failure Drive:"
2377                                 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2378                 }
2379         }
2380         switch (status) {
2381         case IO_SUCCESS:
2382                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2383                 if (param == 0) {
2384                         ts->resp = SAS_TASK_COMPLETE;
2385                         ts->stat = SAM_STAT_GOOD;
2386                         /* check if response is for SEND READ LOG */
2387                         if (pm8001_dev &&
2388                                 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2389                                 /* set new bit for abort_all */
2390                                 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2391                                 /* clear bit for read log */
2392                                 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2393                                 pm8001_send_abort_all(pm8001_ha, pm8001_dev);
2394                                 /* Free the tag */
2395                                 pm8001_tag_free(pm8001_ha, tag);
2396                                 sas_free_task(t);
2397                                 return;
2398                         }
2399                 } else {
2400                         u8 len;
2401                         ts->resp = SAS_TASK_COMPLETE;
2402                         ts->stat = SAS_PROTO_RESPONSE;
2403                         ts->residual = param;
2404                         PM8001_IO_DBG(pm8001_ha,
2405                                 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2406                                 param));
2407                         sata_resp = &psataPayload->sata_resp[0];
2408                         resp = (struct ata_task_resp *)ts->buf;
2409                         if (t->ata_task.dma_xfer == 0 &&
2410                         t->data_dir == PCI_DMA_FROMDEVICE) {
2411                                 len = sizeof(struct pio_setup_fis);
2412                                 PM8001_IO_DBG(pm8001_ha,
2413                                 pm8001_printk("PIO read len = %d\n", len));
2414                         } else if (t->ata_task.use_ncq) {
2415                                 len = sizeof(struct set_dev_bits_fis);
2416                                 PM8001_IO_DBG(pm8001_ha,
2417                                         pm8001_printk("FPDMA len = %d\n", len));
2418                         } else {
2419                                 len = sizeof(struct dev_to_host_fis);
2420                                 PM8001_IO_DBG(pm8001_ha,
2421                                 pm8001_printk("other len = %d\n", len));
2422                         }
2423                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2424                                 resp->frame_len = len;
2425                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2426                                 ts->buf_valid_size = sizeof(*resp);
2427                         } else
2428                                 PM8001_IO_DBG(pm8001_ha,
2429                                         pm8001_printk("response to large\n"));
2430                 }
2431                 if (pm8001_dev)
2432                         pm8001_dev->running_req--;
2433                 break;
2434         case IO_ABORTED:
2435                 PM8001_IO_DBG(pm8001_ha,
2436                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
2437                 ts->resp = SAS_TASK_COMPLETE;
2438                 ts->stat = SAS_ABORTED_TASK;
2439                 if (pm8001_dev)
2440                         pm8001_dev->running_req--;
2441                 break;
2442                 /* following cases are to do cases */
2443         case IO_UNDERFLOW:
2444                 /* SATA Completion with error */
2445                 PM8001_IO_DBG(pm8001_ha,
2446                         pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2447                 ts->resp = SAS_TASK_COMPLETE;
2448                 ts->stat = SAS_DATA_UNDERRUN;
2449                 ts->residual =  param;
2450                 if (pm8001_dev)
2451                         pm8001_dev->running_req--;
2452                 break;
2453         case IO_NO_DEVICE:
2454                 PM8001_IO_DBG(pm8001_ha,
2455                         pm8001_printk("IO_NO_DEVICE\n"));
2456                 ts->resp = SAS_TASK_UNDELIVERED;
2457                 ts->stat = SAS_PHY_DOWN;
2458                 break;
2459         case IO_XFER_ERROR_BREAK:
2460                 PM8001_IO_DBG(pm8001_ha,
2461                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2462                 ts->resp = SAS_TASK_COMPLETE;
2463                 ts->stat = SAS_INTERRUPTED;
2464                 break;
2465         case IO_XFER_ERROR_PHY_NOT_READY:
2466                 PM8001_IO_DBG(pm8001_ha,
2467                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2468                 ts->resp = SAS_TASK_COMPLETE;
2469                 ts->stat = SAS_OPEN_REJECT;
2470                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2471                 break;
2472         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2473                 PM8001_IO_DBG(pm8001_ha,
2474                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2475                         "_SUPPORTED\n"));
2476                 ts->resp = SAS_TASK_COMPLETE;
2477                 ts->stat = SAS_OPEN_REJECT;
2478                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2479                 break;
2480         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2481                 PM8001_IO_DBG(pm8001_ha,
2482                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2483                 ts->resp = SAS_TASK_COMPLETE;
2484                 ts->stat = SAS_OPEN_REJECT;
2485                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2486                 break;
2487         case IO_OPEN_CNX_ERROR_BREAK:
2488                 PM8001_IO_DBG(pm8001_ha,
2489                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2490                 ts->resp = SAS_TASK_COMPLETE;
2491                 ts->stat = SAS_OPEN_REJECT;
2492                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2493                 break;
2494         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2495                 PM8001_IO_DBG(pm8001_ha,
2496                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2497                 ts->resp = SAS_TASK_COMPLETE;
2498                 ts->stat = SAS_DEV_NO_RESPONSE;
2499                 if (!t->uldd_task) {
2500                         pm8001_handle_event(pm8001_ha,
2501                                 pm8001_dev,
2502                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2503                         ts->resp = SAS_TASK_UNDELIVERED;
2504                         ts->stat = SAS_QUEUE_FULL;
2505                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2506                         mb();/*in order to force CPU ordering*/
2507                         spin_unlock_irq(&pm8001_ha->lock);
2508                         t->task_done(t);
2509                         spin_lock_irq(&pm8001_ha->lock);
2510                         return;
2511                 }
2512                 break;
2513         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2514                 PM8001_IO_DBG(pm8001_ha,
2515                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2516                 ts->resp = SAS_TASK_UNDELIVERED;
2517                 ts->stat = SAS_OPEN_REJECT;
2518                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2519                 if (!t->uldd_task) {
2520                         pm8001_handle_event(pm8001_ha,
2521                                 pm8001_dev,
2522                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2523                         ts->resp = SAS_TASK_UNDELIVERED;
2524                         ts->stat = SAS_QUEUE_FULL;
2525                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2526                         mb();/*ditto*/
2527                         spin_unlock_irq(&pm8001_ha->lock);
2528                         t->task_done(t);
2529                         spin_lock_irq(&pm8001_ha->lock);
2530                         return;
2531                 }
2532                 break;
2533         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2534                 PM8001_IO_DBG(pm8001_ha,
2535                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2536                         "NOT_SUPPORTED\n"));
2537                 ts->resp = SAS_TASK_COMPLETE;
2538                 ts->stat = SAS_OPEN_REJECT;
2539                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2540                 break;
2541         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2542                 PM8001_IO_DBG(pm8001_ha,
2543                         pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2544                         "_BUSY\n"));
2545                 ts->resp = SAS_TASK_COMPLETE;
2546                 ts->stat = SAS_DEV_NO_RESPONSE;
2547                 if (!t->uldd_task) {
2548                         pm8001_handle_event(pm8001_ha,
2549                                 pm8001_dev,
2550                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2551                         ts->resp = SAS_TASK_UNDELIVERED;
2552                         ts->stat = SAS_QUEUE_FULL;
2553                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2554                         mb();/* ditto*/
2555                         spin_unlock_irq(&pm8001_ha->lock);
2556                         t->task_done(t);
2557                         spin_lock_irq(&pm8001_ha->lock);
2558                         return;
2559                 }
2560                 break;
2561         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2562                 PM8001_IO_DBG(pm8001_ha,
2563                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2564                 ts->resp = SAS_TASK_COMPLETE;
2565                 ts->stat = SAS_OPEN_REJECT;
2566                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2567                 break;
2568         case IO_XFER_ERROR_NAK_RECEIVED:
2569                 PM8001_IO_DBG(pm8001_ha,
2570                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2571                 ts->resp = SAS_TASK_COMPLETE;
2572                 ts->stat = SAS_NAK_R_ERR;
2573                 break;
2574         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2575                 PM8001_IO_DBG(pm8001_ha,
2576                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2577                 ts->resp = SAS_TASK_COMPLETE;
2578                 ts->stat = SAS_NAK_R_ERR;
2579                 break;
2580         case IO_XFER_ERROR_DMA:
2581                 PM8001_IO_DBG(pm8001_ha,
2582                         pm8001_printk("IO_XFER_ERROR_DMA\n"));
2583                 ts->resp = SAS_TASK_COMPLETE;
2584                 ts->stat = SAS_ABORTED_TASK;
2585                 break;
2586         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2587                 PM8001_IO_DBG(pm8001_ha,
2588                         pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2589                 ts->resp = SAS_TASK_UNDELIVERED;
2590                 ts->stat = SAS_DEV_NO_RESPONSE;
2591                 break;
2592         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2593                 PM8001_IO_DBG(pm8001_ha,
2594                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2595                 ts->resp = SAS_TASK_COMPLETE;
2596                 ts->stat = SAS_DATA_UNDERRUN;
2597                 break;
2598         case IO_XFER_OPEN_RETRY_TIMEOUT:
2599                 PM8001_IO_DBG(pm8001_ha,
2600                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2601                 ts->resp = SAS_TASK_COMPLETE;
2602                 ts->stat = SAS_OPEN_TO;
2603                 break;
2604         case IO_PORT_IN_RESET:
2605                 PM8001_IO_DBG(pm8001_ha,
2606                         pm8001_printk("IO_PORT_IN_RESET\n"));
2607                 ts->resp = SAS_TASK_COMPLETE;
2608                 ts->stat = SAS_DEV_NO_RESPONSE;
2609                 break;
2610         case IO_DS_NON_OPERATIONAL:
2611                 PM8001_IO_DBG(pm8001_ha,
2612                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2613                 ts->resp = SAS_TASK_COMPLETE;
2614                 ts->stat = SAS_DEV_NO_RESPONSE;
2615                 if (!t->uldd_task) {
2616                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2617                                     IO_DS_NON_OPERATIONAL);
2618                         ts->resp = SAS_TASK_UNDELIVERED;
2619                         ts->stat = SAS_QUEUE_FULL;
2620                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2621                         mb();/*ditto*/
2622                         spin_unlock_irq(&pm8001_ha->lock);
2623                         t->task_done(t);
2624                         spin_lock_irq(&pm8001_ha->lock);
2625                         return;
2626                 }
2627                 break;
2628         case IO_DS_IN_RECOVERY:
2629                 PM8001_IO_DBG(pm8001_ha,
2630                         pm8001_printk("  IO_DS_IN_RECOVERY\n"));
2631                 ts->resp = SAS_TASK_COMPLETE;
2632                 ts->stat = SAS_DEV_NO_RESPONSE;
2633                 break;
2634         case IO_DS_IN_ERROR:
2635                 PM8001_IO_DBG(pm8001_ha,
2636                         pm8001_printk("IO_DS_IN_ERROR\n"));
2637                 ts->resp = SAS_TASK_COMPLETE;
2638                 ts->stat = SAS_DEV_NO_RESPONSE;
2639                 if (!t->uldd_task) {
2640                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2641                                     IO_DS_IN_ERROR);
2642                         ts->resp = SAS_TASK_UNDELIVERED;
2643                         ts->stat = SAS_QUEUE_FULL;
2644                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2645                         mb();/*ditto*/
2646                         spin_unlock_irq(&pm8001_ha->lock);
2647                         t->task_done(t);
2648                         spin_lock_irq(&pm8001_ha->lock);
2649                         return;
2650                 }
2651                 break;
2652         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2653                 PM8001_IO_DBG(pm8001_ha,
2654                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2655                 ts->resp = SAS_TASK_COMPLETE;
2656                 ts->stat = SAS_OPEN_REJECT;
2657                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2658         default:
2659                 PM8001_IO_DBG(pm8001_ha,
2660                         pm8001_printk("Unknown status 0x%x\n", status));
2661                 /* not allowed case. Therefore, return failed status */
2662                 ts->resp = SAS_TASK_COMPLETE;
2663                 ts->stat = SAS_DEV_NO_RESPONSE;
2664                 break;
2665         }
2666         spin_lock_irqsave(&t->task_state_lock, flags);
2667         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2668         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2669         t->task_state_flags |= SAS_TASK_STATE_DONE;
2670         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2671                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2672                 PM8001_FAIL_DBG(pm8001_ha,
2673                         pm8001_printk("task 0x%p done with io_status 0x%x"
2674                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2675                         t, status, ts->resp, ts->stat));
2676                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2677         } else if (t->uldd_task) {
2678                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2679                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2680                 mb();/* ditto */
2681                 spin_unlock_irq(&pm8001_ha->lock);
2682                 t->task_done(t);
2683                 spin_lock_irq(&pm8001_ha->lock);
2684         } else if (!t->uldd_task) {
2685                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2686                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2687                 mb();/*ditto*/
2688                 spin_unlock_irq(&pm8001_ha->lock);
2689                 t->task_done(t);
2690                 spin_lock_irq(&pm8001_ha->lock);
2691         }
2692 }
2693
2694 /*See the comments for mpi_ssp_completion */
2695 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2696 {
2697         struct sas_task *t;
2698         struct task_status_struct *ts;
2699         struct pm8001_ccb_info *ccb;
2700         struct pm8001_device *pm8001_dev;
2701         struct sata_event_resp *psataPayload =
2702                 (struct sata_event_resp *)(piomb + 4);
2703         u32 event = le32_to_cpu(psataPayload->event);
2704         u32 tag = le32_to_cpu(psataPayload->tag);
2705         u32 port_id = le32_to_cpu(psataPayload->port_id);
2706         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2707         unsigned long flags;
2708
2709         ccb = &pm8001_ha->ccb_info[tag];
2710
2711         if (ccb) {
2712                 t = ccb->task;
2713                 pm8001_dev = ccb->device;
2714         } else {
2715                 PM8001_FAIL_DBG(pm8001_ha,
2716                         pm8001_printk("No CCB !!!. returning\n"));
2717         }
2718         if (event)
2719                 PM8001_FAIL_DBG(pm8001_ha,
2720                         pm8001_printk("SATA EVENT 0x%x\n", event));
2721
2722         /* Check if this is NCQ error */
2723         if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2724                 /* find device using device id */
2725                 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2726                 /* send read log extension */
2727                 if (pm8001_dev)
2728                         pm8001_send_read_log(pm8001_ha, pm8001_dev);
2729                 return;
2730         }
2731
2732         ccb = &pm8001_ha->ccb_info[tag];
2733         t = ccb->task;
2734         pm8001_dev = ccb->device;
2735         if (event)
2736                 PM8001_FAIL_DBG(pm8001_ha,
2737                         pm8001_printk("sata IO status 0x%x\n", event));
2738         if (unlikely(!t || !t->lldd_task || !t->dev))
2739                 return;
2740         ts = &t->task_status;
2741         PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2742                 "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n",
2743                 port_id, dev_id, tag, event));
2744         switch (event) {
2745         case IO_OVERFLOW:
2746                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2747                 ts->resp = SAS_TASK_COMPLETE;
2748                 ts->stat = SAS_DATA_OVERRUN;
2749                 ts->residual = 0;
2750                 if (pm8001_dev)
2751                         pm8001_dev->running_req--;
2752                 break;
2753         case IO_XFER_ERROR_BREAK:
2754                 PM8001_IO_DBG(pm8001_ha,
2755                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2756                 ts->resp = SAS_TASK_COMPLETE;
2757                 ts->stat = SAS_INTERRUPTED;
2758                 break;
2759         case IO_XFER_ERROR_PHY_NOT_READY:
2760                 PM8001_IO_DBG(pm8001_ha,
2761                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2762                 ts->resp = SAS_TASK_COMPLETE;
2763                 ts->stat = SAS_OPEN_REJECT;
2764                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2765                 break;
2766         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2767                 PM8001_IO_DBG(pm8001_ha,
2768                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2769                         "_SUPPORTED\n"));
2770                 ts->resp = SAS_TASK_COMPLETE;
2771                 ts->stat = SAS_OPEN_REJECT;
2772                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2773                 break;
2774         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2775                 PM8001_IO_DBG(pm8001_ha,
2776                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2777                 ts->resp = SAS_TASK_COMPLETE;
2778                 ts->stat = SAS_OPEN_REJECT;
2779                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2780                 break;
2781         case IO_OPEN_CNX_ERROR_BREAK:
2782                 PM8001_IO_DBG(pm8001_ha,
2783                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2784                 ts->resp = SAS_TASK_COMPLETE;
2785                 ts->stat = SAS_OPEN_REJECT;
2786                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2787                 break;
2788         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2789                 PM8001_IO_DBG(pm8001_ha,
2790                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2791                 ts->resp = SAS_TASK_UNDELIVERED;
2792                 ts->stat = SAS_DEV_NO_RESPONSE;
2793                 if (!t->uldd_task) {
2794                         pm8001_handle_event(pm8001_ha,
2795                                 pm8001_dev,
2796                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2797                         ts->resp = SAS_TASK_COMPLETE;
2798                         ts->stat = SAS_QUEUE_FULL;
2799                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2800                         mb();/*ditto*/
2801                         spin_unlock_irq(&pm8001_ha->lock);
2802                         t->task_done(t);
2803                         spin_lock_irq(&pm8001_ha->lock);
2804                         return;
2805                 }
2806                 break;
2807         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2808                 PM8001_IO_DBG(pm8001_ha,
2809                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2810                 ts->resp = SAS_TASK_UNDELIVERED;
2811                 ts->stat = SAS_OPEN_REJECT;
2812                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2813                 break;
2814         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2815                 PM8001_IO_DBG(pm8001_ha,
2816                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2817                         "NOT_SUPPORTED\n"));
2818                 ts->resp = SAS_TASK_COMPLETE;
2819                 ts->stat = SAS_OPEN_REJECT;
2820                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2821                 break;
2822         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2823                 PM8001_IO_DBG(pm8001_ha,
2824                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2825                 ts->resp = SAS_TASK_COMPLETE;
2826                 ts->stat = SAS_OPEN_REJECT;
2827                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2828                 break;
2829         case IO_XFER_ERROR_NAK_RECEIVED:
2830                 PM8001_IO_DBG(pm8001_ha,
2831                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2832                 ts->resp = SAS_TASK_COMPLETE;
2833                 ts->stat = SAS_NAK_R_ERR;
2834                 break;
2835         case IO_XFER_ERROR_PEER_ABORTED:
2836                 PM8001_IO_DBG(pm8001_ha,
2837                         pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2838                 ts->resp = SAS_TASK_COMPLETE;
2839                 ts->stat = SAS_NAK_R_ERR;
2840                 break;
2841         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2842                 PM8001_IO_DBG(pm8001_ha,
2843                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2844                 ts->resp = SAS_TASK_COMPLETE;
2845                 ts->stat = SAS_DATA_UNDERRUN;
2846                 break;
2847         case IO_XFER_OPEN_RETRY_TIMEOUT:
2848                 PM8001_IO_DBG(pm8001_ha,
2849                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2850                 ts->resp = SAS_TASK_COMPLETE;
2851                 ts->stat = SAS_OPEN_TO;
2852                 break;
2853         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2854                 PM8001_IO_DBG(pm8001_ha,
2855                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2856                 ts->resp = SAS_TASK_COMPLETE;
2857                 ts->stat = SAS_OPEN_TO;
2858                 break;
2859         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2860                 PM8001_IO_DBG(pm8001_ha,
2861                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2862                 ts->resp = SAS_TASK_COMPLETE;
2863                 ts->stat = SAS_OPEN_TO;
2864                 break;
2865         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2866                 PM8001_IO_DBG(pm8001_ha,
2867                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2868                 ts->resp = SAS_TASK_COMPLETE;
2869                 ts->stat = SAS_OPEN_TO;
2870                 break;
2871         case IO_XFER_ERROR_OFFSET_MISMATCH:
2872                 PM8001_IO_DBG(pm8001_ha,
2873                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2874                 ts->resp = SAS_TASK_COMPLETE;
2875                 ts->stat = SAS_OPEN_TO;
2876                 break;
2877         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2878                 PM8001_IO_DBG(pm8001_ha,
2879                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2880                 ts->resp = SAS_TASK_COMPLETE;
2881                 ts->stat = SAS_OPEN_TO;
2882                 break;
2883         case IO_XFER_CMD_FRAME_ISSUED:
2884                 PM8001_IO_DBG(pm8001_ha,
2885                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2886                 break;
2887         case IO_XFER_PIO_SETUP_ERROR:
2888                 PM8001_IO_DBG(pm8001_ha,
2889                         pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2890                 ts->resp = SAS_TASK_COMPLETE;
2891                 ts->stat = SAS_OPEN_TO;
2892                 break;
2893         default:
2894                 PM8001_IO_DBG(pm8001_ha,
2895                         pm8001_printk("Unknown status 0x%x\n", event));
2896                 /* not allowed case. Therefore, return failed status */
2897                 ts->resp = SAS_TASK_COMPLETE;
2898                 ts->stat = SAS_OPEN_TO;
2899                 break;
2900         }
2901         spin_lock_irqsave(&t->task_state_lock, flags);
2902         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2903         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2904         t->task_state_flags |= SAS_TASK_STATE_DONE;
2905         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2906                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2907                 PM8001_FAIL_DBG(pm8001_ha,
2908                         pm8001_printk("task 0x%p done with io_status 0x%x"
2909                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2910                         t, event, ts->resp, ts->stat));
2911                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2912         } else if (t->uldd_task) {
2913                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2914                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2915                 mb();/* ditto */
2916                 spin_unlock_irq(&pm8001_ha->lock);
2917                 t->task_done(t);
2918                 spin_lock_irq(&pm8001_ha->lock);
2919         } else if (!t->uldd_task) {
2920                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2921                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2922                 mb();/*ditto*/
2923                 spin_unlock_irq(&pm8001_ha->lock);
2924                 t->task_done(t);
2925                 spin_lock_irq(&pm8001_ha->lock);
2926         }
2927 }
2928
2929 /*See the comments for mpi_ssp_completion */
2930 static void
2931 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2932 {
2933         u32 param;
2934         struct sas_task *t;
2935         struct pm8001_ccb_info *ccb;
2936         unsigned long flags;
2937         u32 status;
2938         u32 tag;
2939         struct smp_completion_resp *psmpPayload;
2940         struct task_status_struct *ts;
2941         struct pm8001_device *pm8001_dev;
2942
2943         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2944         status = le32_to_cpu(psmpPayload->status);
2945         tag = le32_to_cpu(psmpPayload->tag);
2946
2947         ccb = &pm8001_ha->ccb_info[tag];
2948         param = le32_to_cpu(psmpPayload->param);
2949         t = ccb->task;
2950         ts = &t->task_status;
2951         pm8001_dev = ccb->device;
2952         if (status)
2953                 PM8001_FAIL_DBG(pm8001_ha,
2954                         pm8001_printk("smp IO status 0x%x\n", status));
2955         if (unlikely(!t || !t->lldd_task || !t->dev))
2956                 return;
2957
2958         switch (status) {
2959         case IO_SUCCESS:
2960                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2961                 ts->resp = SAS_TASK_COMPLETE;
2962                 ts->stat = SAM_STAT_GOOD;
2963         if (pm8001_dev)
2964                         pm8001_dev->running_req--;
2965                 break;
2966         case IO_ABORTED:
2967                 PM8001_IO_DBG(pm8001_ha,
2968                         pm8001_printk("IO_ABORTED IOMB\n"));
2969                 ts->resp = SAS_TASK_COMPLETE;
2970                 ts->stat = SAS_ABORTED_TASK;
2971                 if (pm8001_dev)
2972                         pm8001_dev->running_req--;
2973                 break;
2974         case IO_OVERFLOW:
2975                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2976                 ts->resp = SAS_TASK_COMPLETE;
2977                 ts->stat = SAS_DATA_OVERRUN;
2978                 ts->residual = 0;
2979                 if (pm8001_dev)
2980                         pm8001_dev->running_req--;
2981                 break;
2982         case IO_NO_DEVICE:
2983                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2984                 ts->resp = SAS_TASK_COMPLETE;
2985                 ts->stat = SAS_PHY_DOWN;
2986                 break;
2987         case IO_ERROR_HW_TIMEOUT:
2988                 PM8001_IO_DBG(pm8001_ha,
2989                         pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2990                 ts->resp = SAS_TASK_COMPLETE;
2991                 ts->stat = SAM_STAT_BUSY;
2992                 break;
2993         case IO_XFER_ERROR_BREAK:
2994                 PM8001_IO_DBG(pm8001_ha,
2995                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2996                 ts->resp = SAS_TASK_COMPLETE;
2997                 ts->stat = SAM_STAT_BUSY;
2998                 break;
2999         case IO_XFER_ERROR_PHY_NOT_READY:
3000                 PM8001_IO_DBG(pm8001_ha,
3001                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
3002                 ts->resp = SAS_TASK_COMPLETE;
3003                 ts->stat = SAM_STAT_BUSY;
3004                 break;
3005         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
3006                 PM8001_IO_DBG(pm8001_ha,
3007                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
3008                 ts->resp = SAS_TASK_COMPLETE;
3009                 ts->stat = SAS_OPEN_REJECT;
3010                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3011                 break;
3012         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
3013                 PM8001_IO_DBG(pm8001_ha,
3014                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
3015                 ts->resp = SAS_TASK_COMPLETE;
3016                 ts->stat = SAS_OPEN_REJECT;
3017                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3018                 break;
3019         case IO_OPEN_CNX_ERROR_BREAK:
3020                 PM8001_IO_DBG(pm8001_ha,
3021                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
3022                 ts->resp = SAS_TASK_COMPLETE;
3023                 ts->stat = SAS_OPEN_REJECT;
3024                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
3025                 break;
3026         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
3027                 PM8001_IO_DBG(pm8001_ha,
3028                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
3029                 ts->resp = SAS_TASK_COMPLETE;
3030                 ts->stat = SAS_OPEN_REJECT;
3031                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3032                 pm8001_handle_event(pm8001_ha,
3033                                 pm8001_dev,
3034                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
3035                 break;
3036         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
3037                 PM8001_IO_DBG(pm8001_ha,
3038                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
3039                 ts->resp = SAS_TASK_COMPLETE;
3040                 ts->stat = SAS_OPEN_REJECT;
3041                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
3042                 break;
3043         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
3044                 PM8001_IO_DBG(pm8001_ha,
3045                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
3046                         "NOT_SUPPORTED\n"));
3047                 ts->resp = SAS_TASK_COMPLETE;
3048                 ts->stat = SAS_OPEN_REJECT;
3049                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
3050                 break;
3051         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3052                 PM8001_IO_DBG(pm8001_ha,
3053                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
3054                 ts->resp = SAS_TASK_COMPLETE;
3055                 ts->stat = SAS_OPEN_REJECT;
3056                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3057                 break;
3058         case IO_XFER_ERROR_RX_FRAME:
3059                 PM8001_IO_DBG(pm8001_ha,
3060                         pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
3061                 ts->resp = SAS_TASK_COMPLETE;
3062                 ts->stat = SAS_DEV_NO_RESPONSE;
3063                 break;
3064         case IO_XFER_OPEN_RETRY_TIMEOUT:
3065                 PM8001_IO_DBG(pm8001_ha,
3066                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
3067                 ts->resp = SAS_TASK_COMPLETE;
3068                 ts->stat = SAS_OPEN_REJECT;
3069                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3070                 break;
3071         case IO_ERROR_INTERNAL_SMP_RESOURCE:
3072                 PM8001_IO_DBG(pm8001_ha,
3073                         pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
3074                 ts->resp = SAS_TASK_COMPLETE;
3075                 ts->stat = SAS_QUEUE_FULL;
3076                 break;
3077         case IO_PORT_IN_RESET:
3078                 PM8001_IO_DBG(pm8001_ha,
3079                         pm8001_printk("IO_PORT_IN_RESET\n"));
3080                 ts->resp = SAS_TASK_COMPLETE;
3081                 ts->stat = SAS_OPEN_REJECT;
3082                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3083                 break;
3084         case IO_DS_NON_OPERATIONAL:
3085                 PM8001_IO_DBG(pm8001_ha,
3086                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
3087                 ts->resp = SAS_TASK_COMPLETE;
3088                 ts->stat = SAS_DEV_NO_RESPONSE;
3089                 break;
3090         case IO_DS_IN_RECOVERY:
3091                 PM8001_IO_DBG(pm8001_ha,
3092                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
3093                 ts->resp = SAS_TASK_COMPLETE;
3094                 ts->stat = SAS_OPEN_REJECT;
3095                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3096                 break;
3097         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3098                 PM8001_IO_DBG(pm8001_ha,
3099                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
3100                 ts->resp = SAS_TASK_COMPLETE;
3101                 ts->stat = SAS_OPEN_REJECT;
3102                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3103                 break;
3104         default:
3105                 PM8001_IO_DBG(pm8001_ha,
3106                         pm8001_printk("Unknown status 0x%x\n", status));
3107                 ts->resp = SAS_TASK_COMPLETE;
3108                 ts->stat = SAS_DEV_NO_RESPONSE;
3109                 /* not allowed case. Therefore, return failed status */
3110                 break;
3111         }
3112         spin_lock_irqsave(&t->task_state_lock, flags);
3113         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3114         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3115         t->task_state_flags |= SAS_TASK_STATE_DONE;
3116         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3117                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3118                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
3119                         " io_status 0x%x resp 0x%x "
3120                         "stat 0x%x but aborted by upper layer!\n",
3121                         t, status, ts->resp, ts->stat));
3122                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3123         } else {
3124                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3125                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3126                 mb();/* in order to force CPU ordering */
3127                 t->task_done(t);
3128         }
3129 }
3130
3131 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
3132                 void *piomb)
3133 {
3134         struct set_dev_state_resp *pPayload =
3135                 (struct set_dev_state_resp *)(piomb + 4);
3136         u32 tag = le32_to_cpu(pPayload->tag);
3137         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3138         struct pm8001_device *pm8001_dev = ccb->device;
3139         u32 status = le32_to_cpu(pPayload->status);
3140         u32 device_id = le32_to_cpu(pPayload->device_id);
3141         u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS;
3142         u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS;
3143         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
3144                 "from 0x%x to 0x%x status = 0x%x!\n",
3145                 device_id, pds, nds, status));
3146         complete(pm8001_dev->setds_completion);
3147         ccb->task = NULL;
3148         ccb->ccb_tag = 0xFFFFFFFF;
3149         pm8001_ccb_free(pm8001_ha, tag);
3150 }
3151
3152 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3153 {
3154         struct get_nvm_data_resp *pPayload =
3155                 (struct get_nvm_data_resp *)(piomb + 4);
3156         u32 tag = le32_to_cpu(pPayload->tag);
3157         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3158         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3159         complete(pm8001_ha->nvmd_completion);
3160         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
3161         if ((dlen_status & NVMD_STAT) != 0) {
3162                 PM8001_FAIL_DBG(pm8001_ha,
3163                         pm8001_printk("Set nvm data error!\n"));
3164                 return;
3165         }
3166         ccb->task = NULL;
3167         ccb->ccb_tag = 0xFFFFFFFF;
3168         pm8001_ccb_free(pm8001_ha, tag);
3169 }
3170
3171 void
3172 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3173 {
3174         struct fw_control_ex    *fw_control_context;
3175         struct get_nvm_data_resp *pPayload =
3176                 (struct get_nvm_data_resp *)(piomb + 4);
3177         u32 tag = le32_to_cpu(pPayload->tag);
3178         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3179         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3180         u32 ir_tds_bn_dps_das_nvm =
3181                 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
3182         void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
3183         fw_control_context = ccb->fw_control_context;
3184
3185         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
3186         if ((dlen_status & NVMD_STAT) != 0) {
3187                 PM8001_FAIL_DBG(pm8001_ha,
3188                         pm8001_printk("Get nvm data error!\n"));
3189                 complete(pm8001_ha->nvmd_completion);
3190                 return;
3191         }
3192
3193         if (ir_tds_bn_dps_das_nvm & IPMode) {
3194                 /* indirect mode - IR bit set */
3195                 PM8001_MSG_DBG(pm8001_ha,
3196                         pm8001_printk("Get NVMD success, IR=1\n"));
3197                 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
3198                         if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
3199                                 memcpy(pm8001_ha->sas_addr,
3200                                       ((u8 *)virt_addr + 4),
3201                                        SAS_ADDR_SIZE);
3202                                 PM8001_MSG_DBG(pm8001_ha,
3203                                         pm8001_printk("Get SAS address"
3204                                         " from VPD successfully!\n"));
3205                         }
3206                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
3207                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
3208                         ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
3209                                 ;
3210                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
3211                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
3212                         ;
3213                 } else {
3214                         /* Should not be happened*/
3215                         PM8001_MSG_DBG(pm8001_ha,
3216                                 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
3217                                 ir_tds_bn_dps_das_nvm));
3218                 }
3219         } else /* direct mode */{
3220                 PM8001_MSG_DBG(pm8001_ha,
3221                         pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
3222                         (dlen_status & NVMD_LEN) >> 24));
3223         }
3224         memcpy(fw_control_context->usrAddr,
3225                 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
3226                 fw_control_context->len);
3227         complete(pm8001_ha->nvmd_completion);
3228         ccb->task = NULL;
3229         ccb->ccb_tag = 0xFFFFFFFF;
3230         pm8001_ccb_free(pm8001_ha, tag);
3231 }
3232
3233 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
3234 {
3235         struct local_phy_ctl_resp *pPayload =
3236                 (struct local_phy_ctl_resp *)(piomb + 4);
3237         u32 status = le32_to_cpu(pPayload->status);
3238         u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
3239         u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
3240         if (status != 0) {
3241                 PM8001_MSG_DBG(pm8001_ha,
3242                         pm8001_printk("%x phy execute %x phy op failed!\n",
3243                         phy_id, phy_op));
3244         } else
3245                 PM8001_MSG_DBG(pm8001_ha,
3246                         pm8001_printk("%x phy execute %x phy op success!\n",
3247                         phy_id, phy_op));
3248         return 0;
3249 }
3250
3251 /**
3252  * pm8001_bytes_dmaed - one of the interface function communication with libsas
3253  * @pm8001_ha: our hba card information
3254  * @i: which phy that received the event.
3255  *
3256  * when HBA driver received the identify done event or initiate FIS received
3257  * event(for SATA), it will invoke this function to notify the sas layer that
3258  * the sas toplogy has formed, please discover the the whole sas domain,
3259  * while receive a broadcast(change) primitive just tell the sas
3260  * layer to discover the changed domain rather than the whole domain.
3261  */
3262 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
3263 {
3264         struct pm8001_phy *phy = &pm8001_ha->phy[i];
3265         struct asd_sas_phy *sas_phy = &phy->sas_phy;
3266         struct sas_ha_struct *sas_ha;
3267         if (!phy->phy_attached)
3268                 return;
3269
3270         sas_ha = pm8001_ha->sas;
3271         if (sas_phy->phy) {
3272                 struct sas_phy *sphy = sas_phy->phy;
3273                 sphy->negotiated_linkrate = sas_phy->linkrate;
3274                 sphy->minimum_linkrate = phy->minimum_linkrate;
3275                 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3276                 sphy->maximum_linkrate = phy->maximum_linkrate;
3277                 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
3278         }
3279
3280         if (phy->phy_type & PORT_TYPE_SAS) {
3281                 struct sas_identify_frame *id;
3282                 id = (struct sas_identify_frame *)phy->frame_rcvd;
3283                 id->dev_type = phy->identify.device_type;
3284                 id->initiator_bits = SAS_PROTOCOL_ALL;
3285                 id->target_bits = phy->identify.target_port_protocols;
3286         } else if (phy->phy_type & PORT_TYPE_SATA) {
3287                 /*Nothing*/
3288         }
3289         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
3290
3291         sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
3292         pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
3293 }
3294
3295 /* Get the link rate speed  */
3296 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
3297 {
3298         struct sas_phy *sas_phy = phy->sas_phy.phy;
3299
3300         switch (link_rate) {
3301         case PHY_SPEED_60:
3302                 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
3303                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
3304                 break;
3305         case PHY_SPEED_30:
3306                 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3307                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3308                 break;
3309         case PHY_SPEED_15:
3310                 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3311                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3312                 break;
3313         }
3314         sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3315         sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3316         sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3317         sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3318         sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3319 }
3320
3321 /**
3322  * asd_get_attached_sas_addr -- extract/generate attached SAS address
3323  * @phy: pointer to asd_phy
3324  * @sas_addr: pointer to buffer where the SAS address is to be written
3325  *
3326  * This function extracts the SAS address from an IDENTIFY frame
3327  * received.  If OOB is SATA, then a SAS address is generated from the
3328  * HA tables.
3329  *
3330  * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3331  * buffer.
3332  */
3333 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3334         u8 *sas_addr)
3335 {
3336         if (phy->sas_phy.frame_rcvd[0] == 0x34
3337                 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3338                 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3339                 /* FIS device-to-host */
3340                 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3341                 addr += phy->sas_phy.id;
3342                 *(__be64 *)sas_addr = cpu_to_be64(addr);
3343         } else {
3344                 struct sas_identify_frame *idframe =
3345                         (void *) phy->sas_phy.frame_rcvd;
3346                 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3347         }
3348 }
3349
3350 /**
3351  * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3352  * @pm8001_ha: our hba card information
3353  * @Qnum: the outbound queue message number.
3354  * @SEA: source of event to ack
3355  * @port_id: port id.
3356  * @phyId: phy id.
3357  * @param0: parameter 0.
3358  * @param1: parameter 1.
3359  */
3360 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3361         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3362 {
3363         struct hw_event_ack_req  payload;
3364         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3365
3366         struct inbound_queue_table *circularQ;
3367
3368         memset((u8 *)&payload, 0, sizeof(payload));
3369         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3370         payload.tag = cpu_to_le32(1);
3371         payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3372                 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3373         payload.param0 = cpu_to_le32(param0);
3374         payload.param1 = cpu_to_le32(param1);
3375         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
3376 }
3377
3378 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3379         u32 phyId, u32 phy_op);
3380
3381 /**
3382  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3383  * @pm8001_ha: our hba card information
3384  * @piomb: IO message buffer
3385  */
3386 static void
3387 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3388 {
3389         struct hw_event_resp *pPayload =
3390                 (struct hw_event_resp *)(piomb + 4);
3391         u32 lr_evt_status_phyid_portid =
3392                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3393         u8 link_rate =
3394                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3395         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3396         u8 phy_id =
3397                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3398         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3399         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3400         struct pm8001_port *port = &pm8001_ha->port[port_id];
3401         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3402         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3403         unsigned long flags;
3404         u8 deviceType = pPayload->sas_identify.dev_type;
3405         port->port_state =  portstate;
3406         phy->phy_state = PHY_STATE_LINK_UP_SPC;
3407         PM8001_MSG_DBG(pm8001_ha,
3408                 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3409                 port_id, phy_id));
3410
3411         switch (deviceType) {
3412         case SAS_PHY_UNUSED:
3413                 PM8001_MSG_DBG(pm8001_ha,
3414                         pm8001_printk("device type no device.\n"));
3415                 break;
3416         case SAS_END_DEVICE:
3417                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3418                 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3419                         PHY_NOTIFY_ENABLE_SPINUP);
3420                 port->port_attached = 1;
3421                 pm8001_get_lrate_mode(phy, link_rate);
3422                 break;
3423         case SAS_EDGE_EXPANDER_DEVICE:
3424                 PM8001_MSG_DBG(pm8001_ha,
3425                         pm8001_printk("expander device.\n"));
3426                 port->port_attached = 1;
3427                 pm8001_get_lrate_mode(phy, link_rate);
3428                 break;
3429         case SAS_FANOUT_EXPANDER_DEVICE:
3430                 PM8001_MSG_DBG(pm8001_ha,
3431                         pm8001_printk("fanout expander device.\n"));
3432                 port->port_attached = 1;
3433                 pm8001_get_lrate_mode(phy, link_rate);
3434                 break;
3435         default:
3436                 PM8001_MSG_DBG(pm8001_ha,
3437                         pm8001_printk("unknown device type(%x)\n", deviceType));
3438                 break;
3439         }
3440         phy->phy_type |= PORT_TYPE_SAS;
3441         phy->identify.device_type = deviceType;
3442         phy->phy_attached = 1;
3443         if (phy->identify.device_type == SAS_END_DEVICE)
3444                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3445         else if (phy->identify.device_type != SAS_PHY_UNUSED)
3446                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3447         phy->sas_phy.oob_mode = SAS_OOB_MODE;
3448         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3449         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3450         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3451                 sizeof(struct sas_identify_frame)-4);
3452         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3453         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3454         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3455         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3456                 mdelay(200);/*delay a moment to wait disk to spinup*/
3457         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3458 }
3459
3460 /**
3461  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3462  * @pm8001_ha: our hba card information
3463  * @piomb: IO message buffer
3464  */
3465 static void
3466 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3467 {
3468         struct hw_event_resp *pPayload =
3469                 (struct hw_event_resp *)(piomb + 4);
3470         u32 lr_evt_status_phyid_portid =
3471                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3472         u8 link_rate =
3473                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3474         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3475         u8 phy_id =
3476                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3477         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3478         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3479         struct pm8001_port *port = &pm8001_ha->port[port_id];
3480         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3481         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3482         unsigned long flags;
3483         PM8001_MSG_DBG(pm8001_ha,
3484                 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
3485                 " phy id = %d\n", port_id, phy_id));
3486         port->port_state =  portstate;
3487         phy->phy_state = PHY_STATE_LINK_UP_SPC;
3488         port->port_attached = 1;
3489         pm8001_get_lrate_mode(phy, link_rate);
3490         phy->phy_type |= PORT_TYPE_SATA;
3491         phy->phy_attached = 1;
3492         phy->sas_phy.oob_mode = SATA_OOB_MODE;
3493         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3494         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3495         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3496                 sizeof(struct dev_to_host_fis));
3497         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3498         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3499         phy->identify.device_type = SAS_SATA_DEV;
3500         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3501         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3502         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3503 }
3504
3505 /**
3506  * hw_event_phy_down -we should notify the libsas the phy is down.
3507  * @pm8001_ha: our hba card information
3508  * @piomb: IO message buffer
3509  */
3510 static void
3511 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3512 {
3513         struct hw_event_resp *pPayload =
3514                 (struct hw_event_resp *)(piomb + 4);
3515         u32 lr_evt_status_phyid_portid =
3516                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3517         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3518         u8 phy_id =
3519                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3520         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3521         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3522         struct pm8001_port *port = &pm8001_ha->port[port_id];
3523         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3524         port->port_state =  portstate;
3525         phy->phy_type = 0;
3526         phy->identify.device_type = 0;
3527         phy->phy_attached = 0;
3528         memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3529         switch (portstate) {
3530         case PORT_VALID:
3531                 break;
3532         case PORT_INVALID:
3533                 PM8001_MSG_DBG(pm8001_ha,
3534                         pm8001_printk(" PortInvalid portID %d\n", port_id));
3535                 PM8001_MSG_DBG(pm8001_ha,
3536                         pm8001_printk(" Last phy Down and port invalid\n"));
3537                 port->port_attached = 0;
3538                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3539                         port_id, phy_id, 0, 0);
3540                 break;
3541         case PORT_IN_RESET:
3542                 PM8001_MSG_DBG(pm8001_ha,
3543                         pm8001_printk(" Port In Reset portID %d\n", port_id));
3544                 break;
3545         case PORT_NOT_ESTABLISHED:
3546                 PM8001_MSG_DBG(pm8001_ha,
3547                         pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3548                 port->port_attached = 0;
3549                 break;
3550         case PORT_LOSTCOMM:
3551                 PM8001_MSG_DBG(pm8001_ha,
3552                         pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3553                 PM8001_MSG_DBG(pm8001_ha,
3554                         pm8001_printk(" Last phy Down and port invalid\n"));
3555                 port->port_attached = 0;
3556                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3557                         port_id, phy_id, 0, 0);
3558                 break;
3559         default:
3560                 port->port_attached = 0;
3561                 PM8001_MSG_DBG(pm8001_ha,
3562                         pm8001_printk(" phy Down and(default) = %x\n",
3563                         portstate));
3564                 break;
3565
3566         }
3567 }
3568
3569 /**
3570  * pm8001_mpi_reg_resp -process register device ID response.
3571  * @pm8001_ha: our hba card information
3572  * @piomb: IO message buffer
3573  *
3574  * when sas layer find a device it will notify LLDD, then the driver register
3575  * the domain device to FW, this event is the return device ID which the FW
3576  * has assigned, from now,inter-communication with FW is no longer using the
3577  * SAS address, use device ID which FW assigned.
3578  */
3579 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3580 {
3581         u32 status;
3582         u32 device_id;
3583         u32 htag;
3584         struct pm8001_ccb_info *ccb;
3585         struct pm8001_device *pm8001_dev;
3586         struct dev_reg_resp *registerRespPayload =
3587                 (struct dev_reg_resp *)(piomb + 4);
3588
3589         htag = le32_to_cpu(registerRespPayload->tag);
3590         ccb = &pm8001_ha->ccb_info[htag];
3591         pm8001_dev = ccb->device;
3592         status = le32_to_cpu(registerRespPayload->status);
3593         device_id = le32_to_cpu(registerRespPayload->device_id);
3594         PM8001_MSG_DBG(pm8001_ha,
3595                 pm8001_printk(" register device is status = %d\n", status));
3596         switch (status) {
3597         case DEVREG_SUCCESS:
3598                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3599                 pm8001_dev->device_id = device_id;
3600                 break;
3601         case DEVREG_FAILURE_OUT_OF_RESOURCE:
3602                 PM8001_MSG_DBG(pm8001_ha,
3603                         pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3604                 break;
3605         case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3606                 PM8001_MSG_DBG(pm8001_ha,
3607                    pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3608                 break;
3609         case DEVREG_FAILURE_INVALID_PHY_ID:
3610                 PM8001_MSG_DBG(pm8001_ha,
3611                         pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3612                 break;
3613         case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3614                 PM8001_MSG_DBG(pm8001_ha,
3615                    pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3616                 break;
3617         case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3618                 PM8001_MSG_DBG(pm8001_ha,
3619                         pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3620                 break;
3621         case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3622                 PM8001_MSG_DBG(pm8001_ha,
3623                         pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3624                 break;
3625         case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3626                 PM8001_MSG_DBG(pm8001_ha,
3627                        pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3628                 break;
3629         default:
3630                 PM8001_MSG_DBG(pm8001_ha,
3631                  pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n"));
3632                 break;
3633         }
3634         complete(pm8001_dev->dcompletion);
3635         ccb->task = NULL;
3636         ccb->ccb_tag = 0xFFFFFFFF;
3637         pm8001_ccb_free(pm8001_ha, htag);
3638         return 0;
3639 }
3640
3641 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3642 {
3643         u32 status;
3644         u32 device_id;
3645         struct dev_reg_resp *registerRespPayload =
3646                 (struct dev_reg_resp *)(piomb + 4);
3647
3648         status = le32_to_cpu(registerRespPayload->status);
3649         device_id = le32_to_cpu(registerRespPayload->device_id);
3650         if (status != 0)
3651                 PM8001_MSG_DBG(pm8001_ha,
3652                         pm8001_printk(" deregister device failed ,status = %x"
3653                         ", device_id = %x\n", status, device_id));
3654         return 0;
3655 }
3656
3657 /**
3658  * fw_flash_update_resp - Response from FW for flash update command.
3659  * @pm8001_ha: our hba card information
3660  * @piomb: IO message buffer
3661  */
3662 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
3663                 void *piomb)
3664 {
3665         u32 status;
3666         struct fw_control_ex    fw_control_context;
3667         struct fw_flash_Update_resp *ppayload =
3668                 (struct fw_flash_Update_resp *)(piomb + 4);
3669         u32 tag = le32_to_cpu(ppayload->tag);
3670         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3671         status = le32_to_cpu(ppayload->status);
3672         memcpy(&fw_control_context,
3673                 ccb->fw_control_context,
3674                 sizeof(fw_control_context));
3675         switch (status) {
3676         case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3677                 PM8001_MSG_DBG(pm8001_ha,
3678                 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3679                 break;
3680         case FLASH_UPDATE_IN_PROGRESS:
3681                 PM8001_MSG_DBG(pm8001_ha,
3682                         pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3683                 break;
3684         case FLASH_UPDATE_HDR_ERR:
3685                 PM8001_MSG_DBG(pm8001_ha,
3686                         pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3687                 break;
3688         case FLASH_UPDATE_OFFSET_ERR:
3689                 PM8001_MSG_DBG(pm8001_ha,
3690                         pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3691                 break;
3692         case FLASH_UPDATE_CRC_ERR:
3693                 PM8001_MSG_DBG(pm8001_ha,
3694                         pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3695                 break;
3696         case FLASH_UPDATE_LENGTH_ERR:
3697                 PM8001_MSG_DBG(pm8001_ha,
3698                         pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3699                 break;
3700         case FLASH_UPDATE_HW_ERR:
3701                 PM8001_MSG_DBG(pm8001_ha,
3702                         pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3703                 break;
3704         case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3705                 PM8001_MSG_DBG(pm8001_ha,
3706                         pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3707                 break;
3708         case FLASH_UPDATE_DISABLED:
3709                 PM8001_MSG_DBG(pm8001_ha,
3710                         pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3711                 break;
3712         default:
3713                 PM8001_MSG_DBG(pm8001_ha,
3714                         pm8001_printk("No matched status = %d\n", status));
3715                 break;
3716         }
3717         ccb->fw_control_context->fw_control->retcode = status;
3718         complete(pm8001_ha->nvmd_completion);
3719         ccb->task = NULL;
3720         ccb->ccb_tag = 0xFFFFFFFF;
3721         pm8001_ccb_free(pm8001_ha, tag);
3722         return 0;
3723 }
3724
3725 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3726 {
3727         u32 status;
3728         int i;
3729         struct general_event_resp *pPayload =
3730                 (struct general_event_resp *)(piomb + 4);
3731         status = le32_to_cpu(pPayload->status);
3732         PM8001_MSG_DBG(pm8001_ha,
3733                 pm8001_printk(" status = 0x%x\n", status));
3734         for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3735                 PM8001_MSG_DBG(pm8001_ha,
3736                         pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i,
3737                         pPayload->inb_IOMB_payload[i]));
3738         return 0;
3739 }
3740
3741 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3742 {
3743         struct sas_task *t;
3744         struct pm8001_ccb_info *ccb;
3745         unsigned long flags;
3746         u32 status ;
3747         u32 tag, scp;
3748         struct task_status_struct *ts;
3749         struct pm8001_device *pm8001_dev;
3750
3751         struct task_abort_resp *pPayload =
3752                 (struct task_abort_resp *)(piomb + 4);
3753
3754         status = le32_to_cpu(pPayload->status);
3755         tag = le32_to_cpu(pPayload->tag);
3756         if (!tag) {
3757                 PM8001_FAIL_DBG(pm8001_ha,
3758                         pm8001_printk(" TAG NULL. RETURNING !!!"));
3759                 return -1;
3760         }
3761
3762         scp = le32_to_cpu(pPayload->scp);
3763         ccb = &pm8001_ha->ccb_info[tag];
3764         t = ccb->task;
3765         pm8001_dev = ccb->device; /* retrieve device */
3766
3767         if (!t) {
3768                 PM8001_FAIL_DBG(pm8001_ha,
3769                         pm8001_printk(" TASK NULL. RETURNING !!!"));
3770                 return -1;
3771         }
3772         ts = &t->task_status;
3773         if (status != 0)
3774                 PM8001_FAIL_DBG(pm8001_ha,
3775                         pm8001_printk("task abort failed status 0x%x ,"
3776                         "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
3777         switch (status) {
3778         case IO_SUCCESS:
3779                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3780                 ts->resp = SAS_TASK_COMPLETE;
3781                 ts->stat = SAM_STAT_GOOD;
3782                 break;
3783         case IO_NOT_VALID:
3784                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
3785                 ts->resp = TMF_RESP_FUNC_FAILED;
3786                 break;
3787         }
3788         spin_lock_irqsave(&t->task_state_lock, flags);
3789         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3790         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3791         t->task_state_flags |= SAS_TASK_STATE_DONE;
3792         spin_unlock_irqrestore(&t->task_state_lock, flags);
3793         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3794         mb();
3795
3796         if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) {
3797                 pm8001_tag_free(pm8001_ha, tag);
3798                 sas_free_task(t);
3799                 /* clear the flag */
3800                 pm8001_dev->id &= 0xBFFFFFFF;
3801         } else
3802                 t->task_done(t);
3803
3804         return 0;
3805 }
3806
3807 /**
3808  * mpi_hw_event -The hw event has come.
3809  * @pm8001_ha: our hba card information
3810  * @piomb: IO message buffer
3811  */
3812 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3813 {
3814         unsigned long flags;
3815         struct hw_event_resp *pPayload =
3816                 (struct hw_event_resp *)(piomb + 4);
3817         u32 lr_evt_status_phyid_portid =
3818                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3819         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3820         u8 phy_id =
3821                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3822         u16 eventType =
3823                 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3824         u8 status =
3825                 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3826         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3827         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3828         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3829         PM8001_MSG_DBG(pm8001_ha,
3830                 pm8001_printk("outbound queue HW event & event type : "));
3831         switch (eventType) {
3832         case HW_EVENT_PHY_START_STATUS:
3833                 PM8001_MSG_DBG(pm8001_ha,
3834                 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3835                         " status = %x\n", status));
3836                 if (status == 0) {
3837                         phy->phy_state = 1;
3838                         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3839                                 complete(phy->enable_completion);
3840                 }
3841                 break;
3842         case HW_EVENT_SAS_PHY_UP:
3843                 PM8001_MSG_DBG(pm8001_ha,
3844                         pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3845                 hw_event_sas_phy_up(pm8001_ha, piomb);
3846                 break;
3847         case HW_EVENT_SATA_PHY_UP:
3848                 PM8001_MSG_DBG(pm8001_ha,
3849                         pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3850                 hw_event_sata_phy_up(pm8001_ha, piomb);
3851                 break;
3852         case HW_EVENT_PHY_STOP_STATUS:
3853                 PM8001_MSG_DBG(pm8001_ha,
3854                         pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3855                         "status = %x\n", status));
3856                 if (status == 0)
3857                         phy->phy_state = 0;
3858                 break;
3859         case HW_EVENT_SATA_SPINUP_HOLD:
3860                 PM8001_MSG_DBG(pm8001_ha,
3861                         pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3862                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3863                 break;
3864         case HW_EVENT_PHY_DOWN:
3865                 PM8001_MSG_DBG(pm8001_ha,
3866                         pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3867                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3868                 phy->phy_attached = 0;
3869                 phy->phy_state = 0;
3870                 hw_event_phy_down(pm8001_ha, piomb);
3871                 break;
3872         case HW_EVENT_PORT_INVALID:
3873                 PM8001_MSG_DBG(pm8001_ha,
3874                         pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3875                 sas_phy_disconnected(sas_phy);
3876                 phy->phy_attached = 0;
3877                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3878                 break;
3879         /* the broadcast change primitive received, tell the LIBSAS this event
3880         to revalidate the sas domain*/
3881         case HW_EVENT_BROADCAST_CHANGE:
3882                 PM8001_MSG_DBG(pm8001_ha,
3883                         pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3884                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3885                         port_id, phy_id, 1, 0);
3886                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3887                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3888                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3889                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3890                 break;
3891         case HW_EVENT_PHY_ERROR:
3892                 PM8001_MSG_DBG(pm8001_ha,
3893                         pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3894                 sas_phy_disconnected(&phy->sas_phy);
3895                 phy->phy_attached = 0;
3896                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3897                 break;
3898         case HW_EVENT_BROADCAST_EXP:
3899                 PM8001_MSG_DBG(pm8001_ha,
3900                         pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3901                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3902                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3903                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3904                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3905                 break;
3906         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3907                 PM8001_MSG_DBG(pm8001_ha,
3908                         pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3909                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3910                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3911                 sas_phy_disconnected(sas_phy);
3912                 phy->phy_attached = 0;
3913                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3914                 break;
3915         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3916                 PM8001_MSG_DBG(pm8001_ha,
3917                         pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3918                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3919                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3920                         port_id, phy_id, 0, 0);
3921                 sas_phy_disconnected(sas_phy);
3922                 phy->phy_attached = 0;
3923                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3924                 break;
3925         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3926                 PM8001_MSG_DBG(pm8001_ha,
3927                         pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3928                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3929                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3930                         port_id, phy_id, 0, 0);
3931                 sas_phy_disconnected(sas_phy);
3932                 phy->phy_attached = 0;
3933                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3934                 break;
3935         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3936                 PM8001_MSG_DBG(pm8001_ha,
3937                       pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3938                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3939                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3940                         port_id, phy_id, 0, 0);
3941                 sas_phy_disconnected(sas_phy);
3942                 phy->phy_attached = 0;
3943                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3944                 break;
3945         case HW_EVENT_MALFUNCTION:
3946                 PM8001_MSG_DBG(pm8001_ha,
3947                         pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3948                 break;
3949         case HW_EVENT_BROADCAST_SES:
3950                 PM8001_MSG_DBG(pm8001_ha,
3951                         pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3952                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3953                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3954                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3955                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3956                 break;
3957         case HW_EVENT_INBOUND_CRC_ERROR:
3958                 PM8001_MSG_DBG(pm8001_ha,
3959                         pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3960                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3961                         HW_EVENT_INBOUND_CRC_ERROR,
3962                         port_id, phy_id, 0, 0);
3963                 break;
3964         case HW_EVENT_HARD_RESET_RECEIVED:
3965                 PM8001_MSG_DBG(pm8001_ha,
3966                         pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3967                 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3968                 break;
3969         case HW_EVENT_ID_FRAME_TIMEOUT:
3970                 PM8001_MSG_DBG(pm8001_ha,
3971                         pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3972                 sas_phy_disconnected(sas_phy);
3973                 phy->phy_attached = 0;
3974                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3975                 break;
3976         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3977                 PM8001_MSG_DBG(pm8001_ha,
3978                         pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3979                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3980                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3981                         port_id, phy_id, 0, 0);
3982                 sas_phy_disconnected(sas_phy);
3983                 phy->phy_attached = 0;
3984                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3985                 break;
3986         case HW_EVENT_PORT_RESET_TIMER_TMO:
3987                 PM8001_MSG_DBG(pm8001_ha,
3988                         pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3989                 sas_phy_disconnected(sas_phy);
3990                 phy->phy_attached = 0;
3991                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3992                 break;
3993         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3994                 PM8001_MSG_DBG(pm8001_ha,
3995                         pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3996                 sas_phy_disconnected(sas_phy);
3997                 phy->phy_attached = 0;
3998                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3999                 break;
4000         case HW_EVENT_PORT_RECOVER:
4001                 PM8001_MSG_DBG(pm8001_ha,
4002                         pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
4003                 break;
4004         case HW_EVENT_PORT_RESET_COMPLETE:
4005                 PM8001_MSG_DBG(pm8001_ha,
4006                         pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
4007                 break;
4008         case EVENT_BROADCAST_ASYNCH_EVENT:
4009                 PM8001_MSG_DBG(pm8001_ha,
4010                         pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
4011                 break;
4012         default:
4013                 PM8001_MSG_DBG(pm8001_ha,
4014                         pm8001_printk("Unknown event type = %x\n", eventType));
4015                 break;
4016         }
4017         return 0;
4018 }
4019
4020 /**
4021  * process_one_iomb - process one outbound Queue memory block
4022  * @pm8001_ha: our hba card information
4023  * @piomb: IO message buffer
4024  */
4025 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
4026 {
4027         __le32 pHeader = *(__le32 *)piomb;
4028         u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
4029
4030         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
4031
4032         switch (opc) {
4033         case OPC_OUB_ECHO:
4034                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
4035                 break;
4036         case OPC_OUB_HW_EVENT:
4037                 PM8001_MSG_DBG(pm8001_ha,
4038                         pm8001_printk("OPC_OUB_HW_EVENT\n"));
4039                 mpi_hw_event(pm8001_ha, piomb);
4040                 break;
4041         case OPC_OUB_SSP_COMP:
4042                 PM8001_MSG_DBG(pm8001_ha,
4043                         pm8001_printk("OPC_OUB_SSP_COMP\n"));
4044                 mpi_ssp_completion(pm8001_ha, piomb);
4045                 break;
4046         case OPC_OUB_SMP_COMP:
4047                 PM8001_MSG_DBG(pm8001_ha,
4048                         pm8001_printk("OPC_OUB_SMP_COMP\n"));
4049                 mpi_smp_completion(pm8001_ha, piomb);
4050                 break;
4051         case OPC_OUB_LOCAL_PHY_CNTRL:
4052                 PM8001_MSG_DBG(pm8001_ha,
4053                         pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
4054                 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
4055                 break;
4056         case OPC_OUB_DEV_REGIST:
4057                 PM8001_MSG_DBG(pm8001_ha,
4058                         pm8001_printk("OPC_OUB_DEV_REGIST\n"));
4059                 pm8001_mpi_reg_resp(pm8001_ha, piomb);
4060                 break;
4061         case OPC_OUB_DEREG_DEV:
4062                 PM8001_MSG_DBG(pm8001_ha,
4063                         pm8001_printk("unregister the device\n"));
4064                 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
4065                 break;
4066         case OPC_OUB_GET_DEV_HANDLE:
4067                 PM8001_MSG_DBG(pm8001_ha,
4068                         pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
4069                 break;
4070         case OPC_OUB_SATA_COMP:
4071                 PM8001_MSG_DBG(pm8001_ha,
4072                         pm8001_printk("OPC_OUB_SATA_COMP\n"));
4073                 mpi_sata_completion(pm8001_ha, piomb);
4074                 break;
4075         case OPC_OUB_SATA_EVENT:
4076                 PM8001_MSG_DBG(pm8001_ha,
4077                         pm8001_printk("OPC_OUB_SATA_EVENT\n"));
4078                 mpi_sata_event(pm8001_ha, piomb);
4079                 break;
4080         case OPC_OUB_SSP_EVENT:
4081                 PM8001_MSG_DBG(pm8001_ha,
4082                         pm8001_printk("OPC_OUB_SSP_EVENT\n"));
4083                 mpi_ssp_event(pm8001_ha, piomb);
4084                 break;
4085         case OPC_OUB_DEV_HANDLE_ARRIV:
4086                 PM8001_MSG_DBG(pm8001_ha,
4087                         pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
4088                 /*This is for target*/
4089                 break;
4090         case OPC_OUB_SSP_RECV_EVENT:
4091                 PM8001_MSG_DBG(pm8001_ha,
4092                         pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
4093                 /*This is for target*/
4094                 break;
4095         case OPC_OUB_DEV_INFO:
4096                 PM8001_MSG_DBG(pm8001_ha,
4097                         pm8001_printk("OPC_OUB_DEV_INFO\n"));
4098                 break;
4099         case OPC_OUB_FW_FLASH_UPDATE:
4100                 PM8001_MSG_DBG(pm8001_ha,
4101                         pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
4102                 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
4103                 break;
4104         case OPC_OUB_GPIO_RESPONSE:
4105                 PM8001_MSG_DBG(pm8001_ha,
4106                         pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
4107                 break;
4108         case OPC_OUB_GPIO_EVENT:
4109                 PM8001_MSG_DBG(pm8001_ha,
4110                         pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
4111                 break;
4112         case OPC_OUB_GENERAL_EVENT:
4113                 PM8001_MSG_DBG(pm8001_ha,
4114                         pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
4115                 pm8001_mpi_general_event(pm8001_ha, piomb);
4116                 break;
4117         case OPC_OUB_SSP_ABORT_RSP:
4118                 PM8001_MSG_DBG(pm8001_ha,
4119                         pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
4120                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4121                 break;
4122         case OPC_OUB_SATA_ABORT_RSP:
4123                 PM8001_MSG_DBG(pm8001_ha,
4124                         pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
4125                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4126                 break;
4127         case OPC_OUB_SAS_DIAG_MODE_START_END:
4128                 PM8001_MSG_DBG(pm8001_ha,
4129                         pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
4130                 break;
4131         case OPC_OUB_SAS_DIAG_EXECUTE:
4132                 PM8001_MSG_DBG(pm8001_ha,
4133                         pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
4134                 break;
4135         case OPC_OUB_GET_TIME_STAMP:
4136                 PM8001_MSG_DBG(pm8001_ha,
4137                         pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
4138                 break;
4139         case OPC_OUB_SAS_HW_EVENT_ACK:
4140                 PM8001_MSG_DBG(pm8001_ha,
4141                         pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
4142                 break;
4143         case OPC_OUB_PORT_CONTROL:
4144                 PM8001_MSG_DBG(pm8001_ha,
4145                         pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
4146                 break;
4147         case OPC_OUB_SMP_ABORT_RSP:
4148                 PM8001_MSG_DBG(pm8001_ha,
4149                         pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
4150                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4151                 break;
4152         case OPC_OUB_GET_NVMD_DATA:
4153                 PM8001_MSG_DBG(pm8001_ha,
4154                         pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
4155                 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
4156                 break;
4157         case OPC_OUB_SET_NVMD_DATA:
4158                 PM8001_MSG_DBG(pm8001_ha,
4159                         pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
4160                 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
4161                 break;
4162         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
4163                 PM8001_MSG_DBG(pm8001_ha,
4164                         pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
4165                 break;
4166         case OPC_OUB_SET_DEVICE_STATE:
4167                 PM8001_MSG_DBG(pm8001_ha,
4168                         pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
4169                 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
4170                 break;
4171         case OPC_OUB_GET_DEVICE_STATE:
4172                 PM8001_MSG_DBG(pm8001_ha,
4173                         pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
4174                 break;
4175         case OPC_OUB_SET_DEV_INFO:
4176                 PM8001_MSG_DBG(pm8001_ha,
4177                         pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
4178                 break;
4179         case OPC_OUB_SAS_RE_INITIALIZE:
4180                 PM8001_MSG_DBG(pm8001_ha,
4181                         pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
4182                 break;
4183         default:
4184                 PM8001_MSG_DBG(pm8001_ha,
4185                         pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
4186                         opc));
4187                 break;
4188         }
4189 }
4190
4191 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4192 {
4193         struct outbound_queue_table *circularQ;
4194         void *pMsg1 = NULL;
4195         u8 uninitialized_var(bc);
4196         u32 ret = MPI_IO_STATUS_FAIL;
4197         unsigned long flags;
4198
4199         spin_lock_irqsave(&pm8001_ha->lock, flags);
4200         circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4201         do {
4202                 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4203                 if (MPI_IO_STATUS_SUCCESS == ret) {
4204                         /* process the outbound message */
4205                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4206                         /* free the message from the outbound circular buffer */
4207                         pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4208                                                         circularQ, bc);
4209                 }
4210                 if (MPI_IO_STATUS_BUSY == ret) {
4211                         /* Update the producer index from SPC */
4212                         circularQ->producer_index =
4213                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4214                         if (le32_to_cpu(circularQ->producer_index) ==
4215                                 circularQ->consumer_idx)
4216                                 /* OQ is empty */
4217                                 break;
4218                 }
4219         } while (1);
4220         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4221         return ret;
4222 }
4223
4224 /* PCI_DMA_... to our direction translation. */
4225 static const u8 data_dir_flags[] = {
4226         [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
4227         [PCI_DMA_TODEVICE]      = DATA_DIR_OUT,/* OUTBOUND */
4228         [PCI_DMA_FROMDEVICE]    = DATA_DIR_IN,/* INBOUND */
4229         [PCI_DMA_NONE]          = DATA_DIR_NONE,/* NO TRANSFER */
4230 };
4231 void
4232 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
4233 {
4234         int i;
4235         struct scatterlist *sg;
4236         struct pm8001_prd *buf_prd = prd;
4237
4238         for_each_sg(scatter, sg, nr, i) {
4239                 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
4240                 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
4241                 buf_prd->im_len.e = 0;
4242                 buf_prd++;
4243         }
4244 }
4245
4246 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
4247 {
4248         psmp_cmd->tag = hTag;
4249         psmp_cmd->device_id = cpu_to_le32(deviceID);
4250         psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4251 }
4252
4253 /**
4254  * pm8001_chip_smp_req - send a SMP task to FW
4255  * @pm8001_ha: our hba card information.
4256  * @ccb: the ccb information this request used.
4257  */
4258 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4259         struct pm8001_ccb_info *ccb)
4260 {
4261         int elem, rc;
4262         struct sas_task *task = ccb->task;
4263         struct domain_device *dev = task->dev;
4264         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4265         struct scatterlist *sg_req, *sg_resp;
4266         u32 req_len, resp_len;
4267         struct smp_req smp_cmd;
4268         u32 opc;
4269         struct inbound_queue_table *circularQ;
4270
4271         memset(&smp_cmd, 0, sizeof(smp_cmd));
4272         /*
4273          * DMA-map SMP request, response buffers
4274          */
4275         sg_req = &task->smp_task.smp_req;
4276         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
4277         if (!elem)
4278                 return -ENOMEM;
4279         req_len = sg_dma_len(sg_req);
4280
4281         sg_resp = &task->smp_task.smp_resp;
4282         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
4283         if (!elem) {
4284                 rc = -ENOMEM;
4285                 goto err_out;
4286         }
4287         resp_len = sg_dma_len(sg_resp);
4288         /* must be in dwords */
4289         if ((req_len & 0x3) || (resp_len & 0x3)) {
4290                 rc = -EINVAL;
4291                 goto err_out_2;
4292         }
4293
4294         opc = OPC_INB_SMP_REQUEST;
4295         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4296         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4297         smp_cmd.long_smp_req.long_req_addr =
4298                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4299         smp_cmd.long_smp_req.long_req_size =
4300                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4301         smp_cmd.long_smp_req.long_resp_addr =
4302                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
4303         smp_cmd.long_smp_req.long_resp_size =
4304                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4305         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
4306         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd, 0);
4307         return 0;
4308
4309 err_out_2:
4310         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4311                         PCI_DMA_FROMDEVICE);
4312 err_out:
4313         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4314                         PCI_DMA_TODEVICE);
4315         return rc;
4316 }
4317
4318 /**
4319  * pm8001_chip_ssp_io_req - send a SSP task to FW
4320  * @pm8001_ha: our hba card information.
4321  * @ccb: the ccb information this request used.
4322  */
4323 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4324         struct pm8001_ccb_info *ccb)
4325 {
4326         struct sas_task *task = ccb->task;
4327         struct domain_device *dev = task->dev;
4328         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4329         struct ssp_ini_io_start_req ssp_cmd;
4330         u32 tag = ccb->ccb_tag;
4331         int ret;
4332         u64 phys_addr;
4333         struct inbound_queue_table *circularQ;
4334         u32 opc = OPC_INB_SSPINIIOSTART;
4335         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4336         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4337         ssp_cmd.dir_m_tlr =
4338                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4339         SAS 1.1 compatible TLR*/
4340         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4341         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4342         ssp_cmd.tag = cpu_to_le32(tag);
4343         if (task->ssp_task.enable_first_burst)
4344                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4345         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4346         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4347         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4348                task->ssp_task.cmd->cmd_len);
4349         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4350
4351         /* fill in PRD (scatter/gather) table, if any */
4352         if (task->num_scatter > 1) {
4353                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4354                 phys_addr = ccb->ccb_dma_handle +
4355                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4356                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4357                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
4358                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4359         } else if (task->num_scatter == 1) {
4360                 u64 dma_addr = sg_dma_address(task->scatter);
4361                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4362                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
4363                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4364                 ssp_cmd.esgl = 0;
4365         } else if (task->num_scatter == 0) {
4366                 ssp_cmd.addr_low = 0;
4367                 ssp_cmd.addr_high = 0;
4368                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4369                 ssp_cmd.esgl = 0;
4370         }
4371         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd, 0);
4372         return ret;
4373 }
4374
4375 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4376         struct pm8001_ccb_info *ccb)
4377 {
4378         struct sas_task *task = ccb->task;
4379         struct domain_device *dev = task->dev;
4380         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4381         u32 tag = ccb->ccb_tag;
4382         int ret;
4383         struct sata_start_req sata_cmd;
4384         u32 hdr_tag, ncg_tag = 0;
4385         u64 phys_addr;
4386         u32 ATAP = 0x0;
4387         u32 dir;
4388         struct inbound_queue_table *circularQ;
4389         unsigned long flags;
4390         u32  opc = OPC_INB_SATA_HOST_OPSTART;
4391         memset(&sata_cmd, 0, sizeof(sata_cmd));
4392         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4393         if (task->data_dir == PCI_DMA_NONE) {
4394                 ATAP = 0x04;  /* no data*/
4395                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4396         } else if (likely(!task->ata_task.device_control_reg_update)) {
4397                 if (task->ata_task.dma_xfer) {
4398                         ATAP = 0x06; /* DMA */
4399                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4400                 } else {
4401                         ATAP = 0x05; /* PIO*/
4402                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4403                 }
4404                 if (task->ata_task.use_ncq &&
4405                         dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
4406                         ATAP = 0x07; /* FPDMA */
4407                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4408                 }
4409         }
4410         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4411                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4412                 ncg_tag = hdr_tag;
4413         }
4414         dir = data_dir_flags[task->data_dir] << 8;
4415         sata_cmd.tag = cpu_to_le32(tag);
4416         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4417         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4418         sata_cmd.ncqtag_atap_dir_m =
4419                 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4420         sata_cmd.sata_fis = task->ata_task.fis;
4421         if (likely(!task->ata_task.device_control_reg_update))
4422                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4423         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4424         /* fill in PRD (scatter/gather) table, if any */
4425         if (task->num_scatter > 1) {
4426                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4427                 phys_addr = ccb->ccb_dma_handle +
4428                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4429                 sata_cmd.addr_low = lower_32_bits(phys_addr);
4430                 sata_cmd.addr_high = upper_32_bits(phys_addr);
4431                 sata_cmd.esgl = cpu_to_le32(1 << 31);
4432         } else if (task->num_scatter == 1) {
4433                 u64 dma_addr = sg_dma_address(task->scatter);
4434                 sata_cmd.addr_low = lower_32_bits(dma_addr);
4435                 sata_cmd.addr_high = upper_32_bits(dma_addr);
4436                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4437                 sata_cmd.esgl = 0;
4438         } else if (task->num_scatter == 0) {
4439                 sata_cmd.addr_low = 0;
4440                 sata_cmd.addr_high = 0;
4441                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4442                 sata_cmd.esgl = 0;
4443         }
4444
4445         /* Check for read log for failed drive and return */
4446         if (sata_cmd.sata_fis.command == 0x2f) {
4447                 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4448                         (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4449                         (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4450                         struct task_status_struct *ts;
4451
4452                         pm8001_ha_dev->id &= 0xDFFFFFFF;
4453                         ts = &task->task_status;
4454
4455                         spin_lock_irqsave(&task->task_state_lock, flags);
4456                         ts->resp = SAS_TASK_COMPLETE;
4457                         ts->stat = SAM_STAT_GOOD;
4458                         task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4459                         task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4460                         task->task_state_flags |= SAS_TASK_STATE_DONE;
4461                         if (unlikely((task->task_state_flags &
4462                                         SAS_TASK_STATE_ABORTED))) {
4463                                 spin_unlock_irqrestore(&task->task_state_lock,
4464                                                         flags);
4465                                 PM8001_FAIL_DBG(pm8001_ha,
4466                                         pm8001_printk("task 0x%p resp 0x%x "
4467                                         " stat 0x%x but aborted by upper layer "
4468                                         "\n", task, ts->resp, ts->stat));
4469                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4470                         } else if (task->uldd_task) {
4471                                 spin_unlock_irqrestore(&task->task_state_lock,
4472                                                         flags);
4473                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4474                                 mb();/* ditto */
4475                                 spin_unlock_irq(&pm8001_ha->lock);
4476                                 task->task_done(task);
4477                                 spin_lock_irq(&pm8001_ha->lock);
4478                                 return 0;
4479                         } else if (!task->uldd_task) {
4480                                 spin_unlock_irqrestore(&task->task_state_lock,
4481                                                         flags);
4482                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4483                                 mb();/*ditto*/
4484                                 spin_unlock_irq(&pm8001_ha->lock);
4485                                 task->task_done(task);
4486                                 spin_lock_irq(&pm8001_ha->lock);
4487                                 return 0;
4488                         }
4489                 }
4490         }
4491
4492         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
4493         return ret;
4494 }
4495
4496 /**
4497  * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4498  * @pm8001_ha: our hba card information.
4499  * @num: the inbound queue number
4500  * @phy_id: the phy id which we wanted to start up.
4501  */
4502 static int
4503 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4504 {
4505         struct phy_start_req payload;
4506         struct inbound_queue_table *circularQ;
4507         int ret;
4508         u32 tag = 0x01;
4509         u32 opcode = OPC_INB_PHYSTART;
4510         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4511         memset(&payload, 0, sizeof(payload));
4512         payload.tag = cpu_to_le32(tag);
4513         /*
4514          ** [0:7]   PHY Identifier
4515          ** [8:11]  link rate 1.5G, 3G, 6G
4516          ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4517          ** [14]    0b disable spin up hold; 1b enable spin up hold
4518          */
4519         payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4520                 LINKMODE_AUTO | LINKRATE_15 |
4521                 LINKRATE_30 | LINKRATE_60 | phy_id);
4522         payload.sas_identify.dev_type = SAS_END_DEVICE;
4523         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4524         memcpy(payload.sas_identify.sas_addr,
4525                 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4526         payload.sas_identify.phy_id = phy_id;
4527         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4528         return ret;
4529 }
4530
4531 /**
4532  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4533  * @pm8001_ha: our hba card information.
4534  * @num: the inbound queue number
4535  * @phy_id: the phy id which we wanted to start up.
4536  */
4537 int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4538         u8 phy_id)
4539 {
4540         struct phy_stop_req payload;
4541         struct inbound_queue_table *circularQ;
4542         int ret;
4543         u32 tag = 0x01;
4544         u32 opcode = OPC_INB_PHYSTOP;
4545         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4546         memset(&payload, 0, sizeof(payload));
4547         payload.tag = cpu_to_le32(tag);
4548         payload.phy_id = cpu_to_le32(phy_id);
4549         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4550         return ret;
4551 }
4552
4553 /**
4554  * see comments on pm8001_mpi_reg_resp.
4555  */
4556 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4557         struct pm8001_device *pm8001_dev, u32 flag)
4558 {
4559         struct reg_dev_req payload;
4560         u32     opc;
4561         u32 stp_sspsmp_sata = 0x4;
4562         struct inbound_queue_table *circularQ;
4563         u32 linkrate, phy_id;
4564         int rc, tag = 0xdeadbeef;
4565         struct pm8001_ccb_info *ccb;
4566         u8 retryFlag = 0x1;
4567         u16 firstBurstSize = 0;
4568         u16 ITNT = 2000;
4569         struct domain_device *dev = pm8001_dev->sas_device;
4570         struct domain_device *parent_dev = dev->parent;
4571         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4572
4573         memset(&payload, 0, sizeof(payload));
4574         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4575         if (rc)
4576                 return rc;
4577         ccb = &pm8001_ha->ccb_info[tag];
4578         ccb->device = pm8001_dev;
4579         ccb->ccb_tag = tag;
4580         payload.tag = cpu_to_le32(tag);
4581         if (flag == 1)
4582                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4583         else {
4584                 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4585                         stp_sspsmp_sata = 0x00; /* stp*/
4586                 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4587                         pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4588                         pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4589                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4590         }
4591         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4592                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4593         else
4594                 phy_id = pm8001_dev->attached_phy;
4595         opc = OPC_INB_REG_DEV;
4596         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4597                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4598         payload.phyid_portid =
4599                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4600                 ((phy_id & 0x0F) << 4));
4601         payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4602                 ((linkrate & 0x0F) * 0x1000000) |
4603                 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4604         payload.firstburstsize_ITNexustimeout =
4605                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4606         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4607                 SAS_ADDR_SIZE);
4608         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4609         return rc;
4610 }
4611
4612 /**
4613  * see comments on pm8001_mpi_reg_resp.
4614  */
4615 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4616         u32 device_id)
4617 {
4618         struct dereg_dev_req payload;
4619         u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4620         int ret;
4621         struct inbound_queue_table *circularQ;
4622
4623         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4624         memset(&payload, 0, sizeof(payload));
4625         payload.tag = cpu_to_le32(1);
4626         payload.device_id = cpu_to_le32(device_id);
4627         PM8001_MSG_DBG(pm8001_ha,
4628                 pm8001_printk("unregister device device_id = %d\n", device_id));
4629         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4630         return ret;
4631 }
4632
4633 /**
4634  * pm8001_chip_phy_ctl_req - support the local phy operation
4635  * @pm8001_ha: our hba card information.
4636  * @num: the inbound queue number
4637  * @phy_id: the phy id which we wanted to operate
4638  * @phy_op:
4639  */
4640 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4641         u32 phyId, u32 phy_op)
4642 {
4643         struct local_phy_ctl_req payload;
4644         struct inbound_queue_table *circularQ;
4645         int ret;
4646         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4647         memset(&payload, 0, sizeof(payload));
4648         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4649         payload.tag = cpu_to_le32(1);
4650         payload.phyop_phyid =
4651                 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4652         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4653         return ret;
4654 }
4655
4656 static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4657 {
4658         u32 value;
4659 #ifdef PM8001_USE_MSIX
4660         return 1;
4661 #endif
4662         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4663         if (value)
4664                 return 1;
4665         return 0;
4666
4667 }
4668
4669 /**
4670  * pm8001_chip_isr - PM8001 isr handler.
4671  * @pm8001_ha: our hba card information.
4672  * @irq: irq number.
4673  * @stat: stat.
4674  */
4675 static irqreturn_t
4676 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4677 {
4678         pm8001_chip_interrupt_disable(pm8001_ha, vec);
4679         process_oq(pm8001_ha, vec);
4680         pm8001_chip_interrupt_enable(pm8001_ha, vec);
4681         return IRQ_HANDLED;
4682 }
4683
4684 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4685         u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4686 {
4687         struct task_abort_req task_abort;
4688         struct inbound_queue_table *circularQ;
4689         int ret;
4690         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4691         memset(&task_abort, 0, sizeof(task_abort));
4692         if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4693                 task_abort.abort_all = 0;
4694                 task_abort.device_id = cpu_to_le32(dev_id);
4695                 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4696                 task_abort.tag = cpu_to_le32(cmd_tag);
4697         } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4698                 task_abort.abort_all = cpu_to_le32(1);
4699                 task_abort.device_id = cpu_to_le32(dev_id);
4700                 task_abort.tag = cpu_to_le32(cmd_tag);
4701         }
4702         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
4703         return ret;
4704 }
4705
4706 /**
4707  * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4708  * @task: the task we wanted to aborted.
4709  * @flag: the abort flag.
4710  */
4711 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4712         struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4713 {
4714         u32 opc, device_id;
4715         int rc = TMF_RESP_FUNC_FAILED;
4716         PM8001_EH_DBG(pm8001_ha,
4717                 pm8001_printk("cmd_tag = %x, abort task tag = 0x%x",
4718                         cmd_tag, task_tag));
4719         if (pm8001_dev->dev_type == SAS_END_DEVICE)
4720                 opc = OPC_INB_SSP_ABORT;
4721         else if (pm8001_dev->dev_type == SAS_SATA_DEV)
4722                 opc = OPC_INB_SATA_ABORT;
4723         else
4724                 opc = OPC_INB_SMP_ABORT;/* SMP */
4725         device_id = pm8001_dev->device_id;
4726         rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4727                 task_tag, cmd_tag);
4728         if (rc != TMF_RESP_FUNC_COMPLETE)
4729                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
4730         return rc;
4731 }
4732
4733 /**
4734  * pm8001_chip_ssp_tm_req - built the task management command.
4735  * @pm8001_ha: our hba card information.
4736  * @ccb: the ccb information.
4737  * @tmf: task management function.
4738  */
4739 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4740         struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4741 {
4742         struct sas_task *task = ccb->task;
4743         struct domain_device *dev = task->dev;
4744         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4745         u32 opc = OPC_INB_SSPINITMSTART;
4746         struct inbound_queue_table *circularQ;
4747         struct ssp_ini_tm_start_req sspTMCmd;
4748         int ret;
4749
4750         memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4751         sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4752         sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4753         sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4754         memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4755         sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4756         if (pm8001_ha->chip_id != chip_8001)
4757                 sspTMCmd.ds_ads_m = 0x08;
4758         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4759         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd, 0);
4760         return ret;
4761 }
4762
4763 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4764         void *payload)
4765 {
4766         u32 opc = OPC_INB_GET_NVMD_DATA;
4767         u32 nvmd_type;
4768         int rc;
4769         u32 tag;
4770         struct pm8001_ccb_info *ccb;
4771         struct inbound_queue_table *circularQ;
4772         struct get_nvm_data_req nvmd_req;
4773         struct fw_control_ex *fw_control_context;
4774         struct pm8001_ioctl_payload *ioctl_payload = payload;
4775
4776         nvmd_type = ioctl_payload->minor_function;
4777         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4778         if (!fw_control_context)
4779                 return -ENOMEM;
4780         fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific;
4781         fw_control_context->len = ioctl_payload->length;
4782         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4783         memset(&nvmd_req, 0, sizeof(nvmd_req));
4784         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4785         if (rc) {
4786                 kfree(fw_control_context);
4787                 return rc;
4788         }
4789         ccb = &pm8001_ha->ccb_info[tag];
4790         ccb->ccb_tag = tag;
4791         ccb->fw_control_context = fw_control_context;
4792         nvmd_req.tag = cpu_to_le32(tag);
4793
4794         switch (nvmd_type) {
4795         case TWI_DEVICE: {
4796                 u32 twi_addr, twi_page_size;
4797                 twi_addr = 0xa8;
4798                 twi_page_size = 2;
4799
4800                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4801                         twi_page_size << 8 | TWI_DEVICE);
4802                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4803                 nvmd_req.resp_addr_hi =
4804                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4805                 nvmd_req.resp_addr_lo =
4806                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4807                 break;
4808         }
4809         case C_SEEPROM: {
4810                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4811                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4812                 nvmd_req.resp_addr_hi =
4813                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4814                 nvmd_req.resp_addr_lo =
4815                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4816                 break;
4817         }
4818         case VPD_FLASH: {
4819                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4820                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4821                 nvmd_req.resp_addr_hi =
4822                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4823                 nvmd_req.resp_addr_lo =
4824                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4825                 break;
4826         }
4827         case EXPAN_ROM: {
4828                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4829                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4830                 nvmd_req.resp_addr_hi =
4831                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4832                 nvmd_req.resp_addr_lo =
4833                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4834                 break;
4835         }
4836         case IOP_RDUMP: {
4837                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP);
4838                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4839                 nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset);
4840                 nvmd_req.resp_addr_hi =
4841                 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4842                 nvmd_req.resp_addr_lo =
4843                 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4844                 break;
4845         }
4846         default:
4847                 break;
4848         }
4849         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0);
4850         return rc;
4851 }
4852
4853 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4854         void *payload)
4855 {
4856         u32 opc = OPC_INB_SET_NVMD_DATA;
4857         u32 nvmd_type;
4858         int rc;
4859         u32 tag;
4860         struct pm8001_ccb_info *ccb;
4861         struct inbound_queue_table *circularQ;
4862         struct set_nvm_data_req nvmd_req;
4863         struct fw_control_ex *fw_control_context;
4864         struct pm8001_ioctl_payload *ioctl_payload = payload;
4865
4866         nvmd_type = ioctl_payload->minor_function;
4867         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4868         if (!fw_control_context)
4869                 return -ENOMEM;
4870         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4871         memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4872                 &ioctl_payload->func_specific,
4873                 ioctl_payload->length);
4874         memset(&nvmd_req, 0, sizeof(nvmd_req));
4875         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4876         if (rc) {
4877                 kfree(fw_control_context);
4878                 return rc;
4879         }
4880         ccb = &pm8001_ha->ccb_info[tag];
4881         ccb->fw_control_context = fw_control_context;
4882         ccb->ccb_tag = tag;
4883         nvmd_req.tag = cpu_to_le32(tag);
4884         switch (nvmd_type) {
4885         case TWI_DEVICE: {
4886                 u32 twi_addr, twi_page_size;
4887                 twi_addr = 0xa8;
4888                 twi_page_size = 2;
4889                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4890                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4891                         twi_page_size << 8 | TWI_DEVICE);
4892                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4893                 nvmd_req.resp_addr_hi =
4894                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4895                 nvmd_req.resp_addr_lo =
4896                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4897                 break;
4898         }
4899         case C_SEEPROM:
4900                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4901                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4902                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4903                 nvmd_req.resp_addr_hi =
4904                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4905                 nvmd_req.resp_addr_lo =
4906                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4907                 break;
4908         case VPD_FLASH:
4909                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4910                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4911                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4912                 nvmd_req.resp_addr_hi =
4913                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4914                 nvmd_req.resp_addr_lo =
4915                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4916                 break;
4917         case EXPAN_ROM:
4918                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4919                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4920                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4921                 nvmd_req.resp_addr_hi =
4922                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4923                 nvmd_req.resp_addr_lo =
4924                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4925                 break;
4926         default:
4927                 break;
4928         }
4929         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0);
4930         return rc;
4931 }
4932
4933 /**
4934  * pm8001_chip_fw_flash_update_build - support the firmware update operation
4935  * @pm8001_ha: our hba card information.
4936  * @fw_flash_updata_info: firmware flash update param
4937  */
4938 int
4939 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4940         void *fw_flash_updata_info, u32 tag)
4941 {
4942         struct fw_flash_Update_req payload;
4943         struct fw_flash_updata_info *info;
4944         struct inbound_queue_table *circularQ;
4945         int ret;
4946         u32 opc = OPC_INB_FW_FLASH_UPDATE;
4947
4948         memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4949         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4950         info = fw_flash_updata_info;
4951         payload.tag = cpu_to_le32(tag);
4952         payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4953         payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4954         payload.total_image_len = cpu_to_le32(info->total_image_len);
4955         payload.len = info->sgl.im_len.len ;
4956         payload.sgl_addr_lo =
4957                 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4958         payload.sgl_addr_hi =
4959                 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
4960         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4961         return ret;
4962 }
4963
4964 int
4965 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4966         void *payload)
4967 {
4968         struct fw_flash_updata_info flash_update_info;
4969         struct fw_control_info *fw_control;
4970         struct fw_control_ex *fw_control_context;
4971         int rc;
4972         u32 tag;
4973         struct pm8001_ccb_info *ccb;
4974         void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr;
4975         dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr;
4976         struct pm8001_ioctl_payload *ioctl_payload = payload;
4977
4978         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4979         if (!fw_control_context)
4980                 return -ENOMEM;
4981         fw_control = (struct fw_control_info *)&ioctl_payload->func_specific;
4982         memcpy(buffer, fw_control->buffer, fw_control->len);
4983         flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4984         flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4985         flash_update_info.sgl.im_len.e = 0;
4986         flash_update_info.cur_image_offset = fw_control->offset;
4987         flash_update_info.cur_image_len = fw_control->len;
4988         flash_update_info.total_image_len = fw_control->size;
4989         fw_control_context->fw_control = fw_control;
4990         fw_control_context->virtAddr = buffer;
4991         fw_control_context->phys_addr = phys_addr;
4992         fw_control_context->len = fw_control->len;
4993         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4994         if (rc) {
4995                 kfree(fw_control_context);
4996                 return rc;
4997         }
4998         ccb = &pm8001_ha->ccb_info[tag];
4999         ccb->fw_control_context = fw_control_context;
5000         ccb->ccb_tag = tag;
5001         rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
5002                 tag);
5003         return rc;
5004 }
5005
5006 ssize_t
5007 pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf)
5008 {
5009         u32 value, rem, offset = 0, bar = 0;
5010         u32 index, work_offset, dw_length;
5011         u32 shift_value, gsm_base, gsm_dump_offset;
5012         char *direct_data;
5013         struct Scsi_Host *shost = class_to_shost(cdev);
5014         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
5015         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
5016
5017         direct_data = buf;
5018         gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset;
5019
5020         /* check max is 1 Mbytes */
5021         if ((length > 0x100000) || (gsm_dump_offset & 3) ||
5022                 ((gsm_dump_offset + length) > 0x1000000))
5023                         return 1;
5024
5025         if (pm8001_ha->chip_id == chip_8001)
5026                 bar = 2;
5027         else
5028                 bar = 1;
5029
5030         work_offset = gsm_dump_offset & 0xFFFF0000;
5031         offset = gsm_dump_offset & 0x0000FFFF;
5032         gsm_dump_offset = work_offset;
5033         /* adjust length to dword boundary */
5034         rem = length & 3;
5035         dw_length = length >> 2;
5036
5037         for (index = 0; index < dw_length; index++) {
5038                 if ((work_offset + offset) & 0xFFFF0000) {
5039                         if (pm8001_ha->chip_id == chip_8001)
5040                                 shift_value = ((gsm_dump_offset + offset) &
5041                                                 SHIFT_REG_64K_MASK);
5042                         else
5043                                 shift_value = (((gsm_dump_offset + offset) &
5044                                                 SHIFT_REG_64K_MASK) >>
5045                                                 SHIFT_REG_BIT_SHIFT);
5046
5047                         if (pm8001_ha->chip_id == chip_8001) {
5048                                 gsm_base = GSM_BASE;
5049                                 if (-1 == pm8001_bar4_shift(pm8001_ha,
5050                                                 (gsm_base + shift_value)))
5051                                         return 1;
5052                         } else {
5053                                 gsm_base = 0;
5054                                 if (-1 == pm80xx_bar4_shift(pm8001_ha,
5055                                                 (gsm_base + shift_value)))
5056                                         return 1;
5057                         }
5058                         gsm_dump_offset = (gsm_dump_offset + offset) &
5059                                                 0xFFFF0000;
5060                         work_offset = 0;
5061                         offset = offset & 0x0000FFFF;
5062                 }
5063                 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
5064                                                 0x0000FFFF);
5065                 direct_data += sprintf(direct_data, "%08x ", value);
5066                 offset += 4;
5067         }
5068         if (rem != 0) {
5069                 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
5070                                                 0x0000FFFF);
5071                 /* xfr for non_dw */
5072                 direct_data += sprintf(direct_data, "%08x ", value);
5073         }
5074         /* Shift back to BAR4 original address */
5075         if (pm8001_ha->chip_id == chip_8001) {
5076                 if (-1 == pm8001_bar4_shift(pm8001_ha, 0))
5077                         return 1;
5078         } else {
5079                 if (-1 == pm80xx_bar4_shift(pm8001_ha, 0))
5080                         return 1;
5081         }
5082         pm8001_ha->fatal_forensic_shift_offset += 1024;
5083
5084         if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000)
5085                 pm8001_ha->fatal_forensic_shift_offset = 0;
5086         return direct_data - buf;
5087 }
5088
5089 int
5090 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
5091         struct pm8001_device *pm8001_dev, u32 state)
5092 {
5093         struct set_dev_state_req payload;
5094         struct inbound_queue_table *circularQ;
5095         struct pm8001_ccb_info *ccb;
5096         int rc;
5097         u32 tag;
5098         u32 opc = OPC_INB_SET_DEVICE_STATE;
5099         memset(&payload, 0, sizeof(payload));
5100         rc = pm8001_tag_alloc(pm8001_ha, &tag);
5101         if (rc)
5102                 return -1;
5103         ccb = &pm8001_ha->ccb_info[tag];
5104         ccb->ccb_tag = tag;
5105         ccb->device = pm8001_dev;
5106         circularQ = &pm8001_ha->inbnd_q_tbl[0];
5107         payload.tag = cpu_to_le32(tag);
5108         payload.device_id = cpu_to_le32(pm8001_dev->device_id);
5109         payload.nds = cpu_to_le32(state);
5110         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
5111         return rc;
5112
5113 }
5114
5115 static int
5116 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
5117 {
5118         struct sas_re_initialization_req payload;
5119         struct inbound_queue_table *circularQ;
5120         struct pm8001_ccb_info *ccb;
5121         int rc;
5122         u32 tag;
5123         u32 opc = OPC_INB_SAS_RE_INITIALIZE;
5124         memset(&payload, 0, sizeof(payload));
5125         rc = pm8001_tag_alloc(pm8001_ha, &tag);
5126         if (rc)
5127                 return -1;
5128         ccb = &pm8001_ha->ccb_info[tag];
5129         ccb->ccb_tag = tag;
5130         circularQ = &pm8001_ha->inbnd_q_tbl[0];
5131         payload.tag = cpu_to_le32(tag);
5132         payload.SSAHOLT = cpu_to_le32(0xd << 25);
5133         payload.sata_hol_tmo = cpu_to_le32(80);
5134         payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
5135         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
5136         return rc;
5137
5138 }
5139
5140 const struct pm8001_dispatch pm8001_8001_dispatch = {
5141         .name                   = "pmc8001",
5142         .chip_init              = pm8001_chip_init,
5143         .chip_soft_rst          = pm8001_chip_soft_rst,
5144         .chip_rst               = pm8001_hw_chip_rst,
5145         .chip_iounmap           = pm8001_chip_iounmap,
5146         .isr                    = pm8001_chip_isr,
5147         .is_our_interupt        = pm8001_chip_is_our_interupt,
5148         .isr_process_oq         = process_oq,
5149         .interrupt_enable       = pm8001_chip_interrupt_enable,
5150         .interrupt_disable      = pm8001_chip_interrupt_disable,
5151         .make_prd               = pm8001_chip_make_sg,
5152         .smp_req                = pm8001_chip_smp_req,
5153         .ssp_io_req             = pm8001_chip_ssp_io_req,
5154         .sata_req               = pm8001_chip_sata_req,
5155         .phy_start_req          = pm8001_chip_phy_start_req,
5156         .phy_stop_req           = pm8001_chip_phy_stop_req,
5157         .reg_dev_req            = pm8001_chip_reg_dev_req,
5158         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
5159         .phy_ctl_req            = pm8001_chip_phy_ctl_req,
5160         .task_abort             = pm8001_chip_abort_task,
5161         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
5162         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
5163         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
5164         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
5165         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
5166         .sas_re_init_req        = pm8001_chip_sas_re_initialization,
5167 };