drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <dt-bindings/pinctrl/rockchip.h>
  41
  42 #include "core.h"
  43 #include "pinconf.h"
  44
  45 /* GPIO control registers */
  46 #define GPIO_SWPORT_DR          0x00
  47 #define GPIO_SWPORT_DDR         0x04
  48 #define GPIO_INTEN              0x30
  49 #define GPIO_INTMASK            0x34
  50 #define GPIO_INTTYPE_LEVEL      0x38
  51 #define GPIO_INT_POLARITY       0x3c
  52 #define GPIO_INT_STATUS         0x40
  53 #define GPIO_INT_RAWSTATUS      0x44
  54 #define GPIO_DEBOUNCE           0x48
  55 #define GPIO_PORTS_EOI          0x4c
  56 #define GPIO_EXT_PORT           0x50
  57 #define GPIO_LS_SYNC            0x60
  58
  59 enum rockchip_pinctrl_type {
  60         RK2928,
  61         RK3066B,
  62         RK3188,
  63 };
  64
  65 enum rockchip_pin_bank_type {
  66         COMMON_BANK,
  67         RK3188_BANK0,
  68 };
  69
  70 /**
  71  * @reg_base: register base of the gpio bank
  72  * @reg_pull: optional separate register for additional pull settings
  73  * @clk: clock of the gpio bank
  74  * @irq: interrupt of the gpio bank
  75  * @pin_base: first pin number
  76  * @nr_pins: number of pins in this bank
  77  * @name: name of the bank
  78  * @bank_num: number of the bank, to account for holes
  79  * @valid: are all necessary informations present
  80  * @of_node: dt node of this bank
  81  * @drvdata: common pinctrl basedata
  82  * @domain: irqdomain of the gpio bank
  83  * @gpio_chip: gpiolib chip
  84  * @grange: gpio range
  85  * @slock: spinlock for the gpio bank
  86  */
  87 struct rockchip_pin_bank {
  88         void __iomem                    *reg_base;
  89         void __iomem                    *reg_pull;
  90         struct clk                      *clk;
  91         int                             irq;
  92         u32                             pin_base;
  93         u8                              nr_pins;
  94         char                            *name;
  95         u8                              bank_num;
  96         enum rockchip_pin_bank_type     bank_type;
  97         bool                            valid;
  98         struct device_node              *of_node;
  99         struct rockchip_pinctrl         *drvdata;
 100         struct irq_domain               *domain;
 101         struct gpio_chip                gpio_chip;
 102         struct pinctrl_gpio_range       grange;
 103         spinlock_t                      slock;
 104         u32                             toggle_edge_mode;
 105 };
 106
 107 #define PIN_BANK(id, pins, label)                       \
 108         {                                               \
 109                 .bank_num       = id,                   \
 110                 .nr_pins        = pins,                 \
 111                 .name           = label,                \
 112         }
 113
 114 /**
 115  */
 116 struct rockchip_pin_ctrl {
 117         struct rockchip_pin_bank        *pin_banks;
 118         u32                             nr_banks;
 119         u32                             nr_pins;
 120         char                            *label;
 121         enum rockchip_pinctrl_type      type;
 122         int                             mux_offset;
 123         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
 124                                  void __iomem **reg, u8 *bit);
 125 };
 126
 127 struct rockchip_pin_config {
 128         unsigned int            func;
 129         unsigned long           *configs;
 130         unsigned int            nconfigs;
 131 };
 132
 133 /**
 134  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 135  * @name: name of the pin group, used to lookup the group.
 136  * @pins: the pins included in this group.
 137  * @npins: number of pins included in this group.
 138  * @func: the mux function number to be programmed when selected.
 139  * @configs: the config values to be set for each pin
 140  * @nconfigs: number of configs for each pin
 141  */
 142 struct rockchip_pin_group {
 143         const char                      *name;
 144         unsigned int                    npins;
 145         unsigned int                    *pins;
 146         struct rockchip_pin_config      *data;
 147 };
 148
 149 /**
 150  * struct rockchip_pmx_func: represent a pin function.
 151  * @name: name of the pin function, used to lookup the function.
 152  * @groups: one or more names of pin groups that provide this function.
 153  * @num_groups: number of groups included in @groups.
 154  */
 155 struct rockchip_pmx_func {
 156         const char              *name;
 157         const char              **groups;
 158         u8                      ngroups;
 159 };
 160
 161 struct rockchip_pinctrl {
 162         void __iomem                    *reg_base;
 163         void __iomem                    *reg_pull;
 164         struct device                   *dev;
 165         struct rockchip_pin_ctrl        *ctrl;
 166         struct pinctrl_desc             pctl;
 167         struct pinctrl_dev              *pctl_dev;
 168         struct rockchip_pin_group       *groups;
 169         unsigned int                    ngroups;
 170         struct rockchip_pmx_func        *functions;
 171         unsigned int                    nfunctions;
 172 };
 173
 174 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 175 {
 176         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 177 }
 178
 179 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 180                                         const struct rockchip_pinctrl *info,
 181                                         const char *name)
 182 {
 183         int i;
 184
 185         for (i = 0; i < info->ngroups; i++) {
 186                 if (!strcmp(info->groups[i].name, name))
 187                         return &info->groups[i];
 188         }
 189
 190         return NULL;
 191 }
 192
 193 /*
 194  * given a pin number that is local to a pin controller, find out the pin bank
 195  * and the register base of the pin bank.
 196  */
 197 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 198                                                                 unsigned pin)
 199 {
 200         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 201
 202         while (pin >= (b->pin_base + b->nr_pins))
 203                 b++;
 204
 205         return b;
 206 }
 207
 208 static struct rockchip_pin_bank *bank_num_to_bank(
 209                                         struct rockchip_pinctrl *info,
 210                                         unsigned num)
 211 {
 212         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 213         int i;
 214
 215         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 216                 if (b->bank_num == num)
 217                         return b;
 218         }
 219
 220         return ERR_PTR(-EINVAL);
 221 }
 222
 223 /*
 224  * Pinctrl_ops handling
 225  */
 226
 227 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 228 {
 229         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 230
 231         return info->ngroups;
 232 }
 233
 234 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 235                                                         unsigned selector)
 236 {
 237         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 238
 239         return info->groups[selector].name;
 240 }
 241
 242 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 243                                       unsigned selector, const unsigned **pins,
 244                                       unsigned *npins)
 245 {
 246         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 247
 248         if (selector >= info->ngroups)
 249                 return -EINVAL;
 250
 251         *pins = info->groups[selector].pins;
 252         *npins = info->groups[selector].npins;
 253
 254         return 0;
 255 }
 256
 257 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 258                                  struct device_node *np,
 259                                  struct pinctrl_map **map, unsigned *num_maps)
 260 {
 261         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 262         const struct rockchip_pin_group *grp;
 263         struct pinctrl_map *new_map;
 264         struct device_node *parent;
 265         int map_num = 1;
 266         int i;
 267
 268         /*
 269          * first find the group of this node and check if we need to create
 270          * config maps for pins
 271          */
 272         grp = pinctrl_name_to_group(info, np->name);
 273         if (!grp) {
 274                 dev_err(info->dev, "unable to find group for node %s\n",
 275                         np->name);
 276                 return -EINVAL;
 277         }
 278
 279         map_num += grp->npins;
 280         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 281                                                                 GFP_KERNEL);
 282         if (!new_map)
 283                 return -ENOMEM;
 284
 285         *map = new_map;
 286         *num_maps = map_num;
 287
 288         /* create mux map */
 289         parent = of_get_parent(np);
 290         if (!parent) {
 291                 devm_kfree(pctldev->dev, new_map);
 292                 return -EINVAL;
 293         }
 294         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 295         new_map[0].data.mux.function = parent->name;
 296         new_map[0].data.mux.group = np->name;
 297         of_node_put(parent);
 298
 299         /* create config map */
 300         new_map++;
 301         for (i = 0; i < grp->npins; i++) {
 302                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 303                 new_map[i].data.configs.group_or_pin =
 304                                 pin_get_name(pctldev, grp->pins[i]);
 305                 new_map[i].data.configs.configs = grp->data[i].configs;
 306                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 307         }
 308
 309         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 310                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 311
 312         return 0;
 313 }
 314
 315 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 316                                     struct pinctrl_map *map, unsigned num_maps)
 317 {
 318 }
 319
 320 static const struct pinctrl_ops rockchip_pctrl_ops = {
 321         .get_groups_count       = rockchip_get_groups_count,
 322         .get_group_name         = rockchip_get_group_name,
 323         .get_group_pins         = rockchip_get_group_pins,
 324         .dt_node_to_map         = rockchip_dt_node_to_map,
 325         .dt_free_map            = rockchip_dt_free_map,
 326 };
 327
 328 /*
 329  * Hardware access
 330  */
 331
 332 /*
 333  * Set a new mux function for a pin.
 334  *
 335  * The register is divided into the upper and lower 16 bit. When changing
 336  * a value, the previous register value is not read and changed. Instead
 337  * it seems the changed bits are marked in the upper 16 bit, while the
 338  * changed value gets set in the same offset in the lower 16 bit.
 339  * All pin settings seem to be 2 bit wide in both the upper and lower
 340  * parts.
 341  * @bank: pin bank to change
 342  * @pin: pin to change
 343  * @mux: new mux function to set
 344  */
 345 static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 346 {
 347         struct rockchip_pinctrl *info = bank->drvdata;
 348         void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
 349         unsigned long flags;
 350         u8 bit;
 351         u32 data;
 352
 353         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 354                                                 bank->bank_num, pin, mux);
 355
 356         /* get basic quadrupel of mux registers and the correct reg inside */
 357         reg += bank->bank_num * 0x10;
 358         reg += (pin / 8) * 4;
 359         bit = (pin % 8) * 2;
 360
 361         spin_lock_irqsave(&bank->slock, flags);
 362
 363         data = (3 << (bit + 16));
 364         data |= (mux & 3) << bit;
 365         writel(data, reg);
 366
 367         spin_unlock_irqrestore(&bank->slock, flags);
 368 }
 369
 370 #define RK2928_PULL_OFFSET              0x118
 371 #define RK2928_PULL_PINS_PER_REG        16
 372 #define RK2928_PULL_BANK_STRIDE         8
 373
 374 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 375                                     int pin_num, void __iomem **reg, u8 *bit)
 376 {
 377         struct rockchip_pinctrl *info = bank->drvdata;
 378
 379         *reg = info->reg_base + RK2928_PULL_OFFSET;
 380         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
 381         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
 382
 383         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
 384 };
 385
 386 #define RK3188_PULL_BITS_PER_PIN        2
 387 #define RK3188_PULL_PINS_PER_REG        8
 388 #define RK3188_PULL_BANK_STRIDE         16
 389
 390 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 391                                     int pin_num, void __iomem **reg, u8 *bit)
 392 {
 393         struct rockchip_pinctrl *info = bank->drvdata;
 394
 395         /* The first 12 pins of the first bank are located elsewhere */
 396         if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
 397                 *reg = bank->reg_pull +
 398                                 ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 399                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 400                 *bit *= RK3188_PULL_BITS_PER_PIN;
 401         } else {
 402                 *reg = info->reg_pull - 4;
 403                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 404                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 405
 406                 /*
 407                  * The bits in these registers have an inverse ordering
 408                  * with the lowest pin being in bits 15:14 and the highest
 409                  * pin in bits 1:0
 410                  */
 411                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
 412                 *bit *= RK3188_PULL_BITS_PER_PIN;
 413         }
 414 }
 415
 416 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 417 {
 418         struct rockchip_pinctrl *info = bank->drvdata;
 419         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 420         void __iomem *reg;
 421         u8 bit;
 422         u32 data;
 423
 424         /* rk3066b does support any pulls */
 425         if (ctrl->type == RK3066B)
 426                 return PIN_CONFIG_BIAS_DISABLE;
 427
 428         ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
 429
 430         switch (ctrl->type) {
 431         case RK2928:
 432                 return !(readl_relaxed(reg) & BIT(bit))
 433                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 434                                 : PIN_CONFIG_BIAS_DISABLE;
 435         case RK3188:
 436                 data = readl_relaxed(reg) >> bit;
 437                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
 438
 439                 switch (data) {
 440                 case 0:
 441                         return PIN_CONFIG_BIAS_DISABLE;
 442                 case 1:
 443                         return PIN_CONFIG_BIAS_PULL_UP;
 444                 case 2:
 445                         return PIN_CONFIG_BIAS_PULL_DOWN;
 446                 case 3:
 447                         return PIN_CONFIG_BIAS_BUS_HOLD;
 448                 }
 449
 450                 dev_err(info->dev, "unknown pull setting\n");
 451                 return -EIO;
 452         default:
 453                 dev_err(info->dev, "unsupported pinctrl type\n");
 454                 return -EINVAL;
 455         };
 456 }
 457
 458 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 459                                         int pin_num, int pull)
 460 {
 461         struct rockchip_pinctrl *info = bank->drvdata;
 462         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 463         void __iomem *reg;
 464         unsigned long flags;
 465         u8 bit;
 466         u32 data;
 467
 468         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
 469                  bank->bank_num, pin_num, pull);
 470
 471         /* rk3066b does support any pulls */
 472         if (ctrl->type == RK3066B)
 473                 return pull ? -EINVAL : 0;
 474
 475         ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
 476
 477         switch (ctrl->type) {
 478         case RK2928:
 479                 spin_lock_irqsave(&bank->slock, flags);
 480
 481                 data = BIT(bit + 16);
 482                 if (pull == PIN_CONFIG_BIAS_DISABLE)
 483                         data |= BIT(bit);
 484                 writel(data, reg);
 485
 486                 spin_unlock_irqrestore(&bank->slock, flags);
 487                 break;
 488         case RK3188:
 489                 spin_lock_irqsave(&bank->slock, flags);
 490
 491                 /* enable the write to the equivalent lower bits */
 492                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 493
 494                 switch (pull) {
 495                 case PIN_CONFIG_BIAS_DISABLE:
 496                         break;
 497                 case PIN_CONFIG_BIAS_PULL_UP:
 498                         data |= (1 << bit);
 499                         break;
 500                 case PIN_CONFIG_BIAS_PULL_DOWN:
 501                         data |= (2 << bit);
 502                         break;
 503                 case PIN_CONFIG_BIAS_BUS_HOLD:
 504                         data |= (3 << bit);
 505                         break;
 506                 default:
 507                         spin_unlock_irqrestore(&bank->slock, flags);
 508                         dev_err(info->dev, "unsupported pull setting %d\n",
 509                                 pull);
 510                         return -EINVAL;
 511                 }
 512
 513                 writel(data, reg);
 514
 515                 spin_unlock_irqrestore(&bank->slock, flags);
 516                 break;
 517         default:
 518                 dev_err(info->dev, "unsupported pinctrl type\n");
 519                 return -EINVAL;
 520         }
 521
 522         return 0;
 523 }
 524
 525 /*
 526  * Pinmux_ops handling
 527  */
 528
 529 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 530 {
 531         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 532
 533         return info->nfunctions;
 534 }
 535
 536 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 537                                           unsigned selector)
 538 {
 539         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 540
 541         return info->functions[selector].name;
 542 }
 543
 544 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 545                                 unsigned selector, const char * const **groups,
 546                                 unsigned * const num_groups)
 547 {
 548         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 549
 550         *groups = info->functions[selector].groups;
 551         *num_groups = info->functions[selector].ngroups;
 552
 553         return 0;
 554 }
 555
 556 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 557                                                             unsigned group)
 558 {
 559         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 560         const unsigned int *pins = info->groups[group].pins;
 561         const struct rockchip_pin_config *data = info->groups[group].data;
 562         struct rockchip_pin_bank *bank;
 563         int cnt;
 564
 565         dev_dbg(info->dev, "enable function %s group %s\n",
 566                 info->functions[selector].name, info->groups[group].name);
 567
 568         /*
 569          * for each pin in the pin group selected, program the correspoding pin
 570          * pin function number in the config register.
 571          */
 572         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 573                 bank = pin_to_bank(info, pins[cnt]);
 574                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 575                                  data[cnt].func);
 576         }
 577
 578         return 0;
 579 }
 580
 581 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
 582                                         unsigned selector, unsigned group)
 583 {
 584         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 585         const unsigned int *pins = info->groups[group].pins;
 586         struct rockchip_pin_bank *bank;
 587         int cnt;
 588
 589         dev_dbg(info->dev, "disable function %s group %s\n",
 590                 info->functions[selector].name, info->groups[group].name);
 591
 592         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 593                 bank = pin_to_bank(info, pins[cnt]);
 594                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 595         }
 596 }
 597
 598 /*
 599  * The calls to gpio_direction_output() and gpio_direction_input()
 600  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
 601  * function called from the gpiolib interface).
 602  */
 603 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 604                                               struct pinctrl_gpio_range *range,
 605                                               unsigned offset, bool input)
 606 {
 607         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 608         struct rockchip_pin_bank *bank;
 609         struct gpio_chip *chip;
 610         int pin;
 611         u32 data;
 612
 613         chip = range->gc;
 614         bank = gc_to_pin_bank(chip);
 615         pin = offset - chip->base;
 616
 617         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
 618                  offset, range->name, pin, input ? "input" : "output");
 619
 620         rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
 621
 622         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 623         /* set bit to 1 for output, 0 for input */
 624         if (!input)
 625                 data |= BIT(pin);
 626         else
 627                 data &= ~BIT(pin);
 628         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 629
 630         return 0;
 631 }
 632
 633 static const struct pinmux_ops rockchip_pmx_ops = {
 634         .get_functions_count    = rockchip_pmx_get_funcs_count,
 635         .get_function_name      = rockchip_pmx_get_func_name,
 636         .get_function_groups    = rockchip_pmx_get_groups,
 637         .enable                 = rockchip_pmx_enable,
 638         .disable                = rockchip_pmx_disable,
 639         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
 640 };
 641
 642 /*
 643  * Pinconf_ops handling
 644  */
 645
 646 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 647                                         enum pin_config_param pull)
 648 {
 649         switch (ctrl->type) {
 650         case RK2928:
 651                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
 652                                         pull == PIN_CONFIG_BIAS_DISABLE);
 653         case RK3066B:
 654                 return pull ? false : true;
 655         case RK3188:
 656                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
 657         }
 658
 659         return false;
 660 }
 661
 662 /* set the pin config settings for a specified pin */
 663 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 664                                 unsigned long *configs, unsigned num_configs)
 665 {
 666         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 667         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 668         enum pin_config_param param;
 669         u16 arg;
 670         int i;
 671         int rc;
 672
 673         for (i = 0; i < num_configs; i++) {
 674                 param = pinconf_to_config_param(configs[i]);
 675                 arg = pinconf_to_config_argument(configs[i]);
 676
 677                 switch (param) {
 678                 case PIN_CONFIG_BIAS_DISABLE:
 679                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
 680                                 param);
 681                         if (rc)
 682                                 return rc;
 683                         break;
 684                 case PIN_CONFIG_BIAS_PULL_UP:
 685                 case PIN_CONFIG_BIAS_PULL_DOWN:
 686                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 687                 case PIN_CONFIG_BIAS_BUS_HOLD:
 688                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 689                                 return -ENOTSUPP;
 690
 691                         if (!arg)
 692                                 return -EINVAL;
 693
 694                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
 695                                 param);
 696                         if (rc)
 697                                 return rc;
 698                         break;
 699                 default:
 700                         return -ENOTSUPP;
 701                         break;
 702                 }
 703         } /* for each config */
 704
 705         return 0;
 706 }
 707
 708 /* get the pin config settings for a specified pin */
 709 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 710                                                         unsigned long *config)
 711 {
 712         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 713         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 714         enum pin_config_param param = pinconf_to_config_param(*config);
 715
 716         switch (param) {
 717         case PIN_CONFIG_BIAS_DISABLE:
 718                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
 719                         return -EINVAL;
 720
 721                 *config = 0;
 722                 break;
 723         case PIN_CONFIG_BIAS_PULL_UP:
 724         case PIN_CONFIG_BIAS_PULL_DOWN:
 725         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 726         case PIN_CONFIG_BIAS_BUS_HOLD:
 727                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 728                         return -ENOTSUPP;
 729
 730                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
 731                         return -EINVAL;
 732
 733                 *config = 1;
 734                 break;
 735         default:
 736                 return -ENOTSUPP;
 737                 break;
 738         }
 739
 740         return 0;
 741 }
 742
 743 static const struct pinconf_ops rockchip_pinconf_ops = {
 744         .pin_config_get                 = rockchip_pinconf_get,
 745         .pin_config_set                 = rockchip_pinconf_set,
 746 };
 747
 748 static const struct of_device_id rockchip_bank_match[] = {
 749         { .compatible = "rockchip,gpio-bank" },
 750         { .compatible = "rockchip,rk3188-gpio-bank0" },
 751         {},
 752 };
 753
 754 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
 755                                                 struct device_node *np)
 756 {
 757         struct device_node *child;
 758
 759         for_each_child_of_node(np, child) {
 760                 if (of_match_node(rockchip_bank_match, child))
 761                         continue;
 762
 763                 info->nfunctions++;
 764                 info->ngroups += of_get_child_count(child);
 765         }
 766 }
 767
 768 static int rockchip_pinctrl_parse_groups(struct device_node *np,
 769                                               struct rockchip_pin_group *grp,
 770                                               struct rockchip_pinctrl *info,
 771                                               u32 index)
 772 {
 773         struct rockchip_pin_bank *bank;
 774         int size;
 775         const __be32 *list;
 776         int num;
 777         int i, j;
 778         int ret;
 779
 780         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
 781
 782         /* Initialise group */
 783         grp->name = np->name;
 784
 785         /*
 786          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
 787          * do sanity check and calculate pins number
 788          */
 789         list = of_get_property(np, "rockchip,pins", &size);
 790         /* we do not check return since it's safe node passed down */
 791         size /= sizeof(*list);
 792         if (!size || size % 4) {
 793                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
 794                 return -EINVAL;
 795         }
 796
 797         grp->npins = size / 4;
 798
 799         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
 800                                                 GFP_KERNEL);
 801         grp->data = devm_kzalloc(info->dev, grp->npins *
 802                                           sizeof(struct rockchip_pin_config),
 803                                         GFP_KERNEL);
 804         if (!grp->pins || !grp->data)
 805                 return -ENOMEM;
 806
 807         for (i = 0, j = 0; i < size; i += 4, j++) {
 808                 const __be32 *phandle;
 809                 struct device_node *np_config;
 810
 811                 num = be32_to_cpu(*list++);
 812                 bank = bank_num_to_bank(info, num);
 813                 if (IS_ERR(bank))
 814                         return PTR_ERR(bank);
 815
 816                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
 817                 grp->data[j].func = be32_to_cpu(*list++);
 818
 819                 phandle = list++;
 820                 if (!phandle)
 821                         return -EINVAL;
 822
 823                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
 824                 ret = pinconf_generic_parse_dt_config(np_config,
 825                                 &grp->data[j].configs, &grp->data[j].nconfigs);
 826                 if (ret)
 827                         return ret;
 828         }
 829
 830         return 0;
 831 }
 832
 833 static int rockchip_pinctrl_parse_functions(struct device_node *np,
 834                                                 struct rockchip_pinctrl *info,
 835                                                 u32 index)
 836 {
 837         struct device_node *child;
 838         struct rockchip_pmx_func *func;
 839         struct rockchip_pin_group *grp;
 840         int ret;
 841         static u32 grp_index;
 842         u32 i = 0;
 843
 844         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
 845
 846         func = &info->functions[index];
 847
 848         /* Initialise function */
 849         func->name = np->name;
 850         func->ngroups = of_get_child_count(np);
 851         if (func->ngroups <= 0)
 852                 return 0;
 853
 854         func->groups = devm_kzalloc(info->dev,
 855                         func->ngroups * sizeof(char *), GFP_KERNEL);
 856         if (!func->groups)
 857                 return -ENOMEM;
 858
 859         for_each_child_of_node(np, child) {
 860                 func->groups[i] = child->name;
 861                 grp = &info->groups[grp_index++];
 862                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
 863                 if (ret)
 864                         return ret;
 865         }
 866
 867         return 0;
 868 }
 869
 870 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
 871                                               struct rockchip_pinctrl *info)
 872 {
 873         struct device *dev = &pdev->dev;
 874         struct device_node *np = dev->of_node;
 875         struct device_node *child;
 876         int ret;
 877         int i;
 878
 879         rockchip_pinctrl_child_count(info, np);
 880
 881         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
 882         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
 883
 884         info->functions = devm_kzalloc(dev, info->nfunctions *
 885                                               sizeof(struct rockchip_pmx_func),
 886                                               GFP_KERNEL);
 887         if (!info->functions) {
 888                 dev_err(dev, "failed to allocate memory for function list\n");
 889                 return -EINVAL;
 890         }
 891
 892         info->groups = devm_kzalloc(dev, info->ngroups *
 893                                             sizeof(struct rockchip_pin_group),
 894                                             GFP_KERNEL);
 895         if (!info->groups) {
 896                 dev_err(dev, "failed allocate memory for ping group list\n");
 897                 return -EINVAL;
 898         }
 899
 900         i = 0;
 901
 902         for_each_child_of_node(np, child) {
 903                 if (of_match_node(rockchip_bank_match, child))
 904                         continue;
 905
 906                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
 907                 if (ret) {
 908                         dev_err(&pdev->dev, "failed to parse function\n");
 909                         return ret;
 910                 }
 911         }
 912
 913         return 0;
 914 }
 915
 916 static int rockchip_pinctrl_register(struct platform_device *pdev,
 917                                         struct rockchip_pinctrl *info)
 918 {
 919         struct pinctrl_desc *ctrldesc = &info->pctl;
 920         struct pinctrl_pin_desc *pindesc, *pdesc;
 921         struct rockchip_pin_bank *pin_bank;
 922         int pin, bank, ret;
 923         int k;
 924
 925         ctrldesc->name = "rockchip-pinctrl";
 926         ctrldesc->owner = THIS_MODULE;
 927         ctrldesc->pctlops = &rockchip_pctrl_ops;
 928         ctrldesc->pmxops = &rockchip_pmx_ops;
 929         ctrldesc->confops = &rockchip_pinconf_ops;
 930
 931         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
 932                         info->ctrl->nr_pins, GFP_KERNEL);
 933         if (!pindesc) {
 934                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
 935                 return -ENOMEM;
 936         }
 937         ctrldesc->pins = pindesc;
 938         ctrldesc->npins = info->ctrl->nr_pins;
 939
 940         pdesc = pindesc;
 941         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
 942                 pin_bank = &info->ctrl->pin_banks[bank];
 943                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
 944                         pdesc->number = k;
 945                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
 946                                                 pin_bank->name, pin);
 947                         pdesc++;
 948                 }
 949         }
 950
 951         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
 952         if (!info->pctl_dev) {
 953                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
 954                 return -EINVAL;
 955         }
 956
 957         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
 958                 pin_bank = &info->ctrl->pin_banks[bank];
 959                 pin_bank->grange.name = pin_bank->name;
 960                 pin_bank->grange.id = bank;
 961                 pin_bank->grange.pin_base = pin_bank->pin_base;
 962                 pin_bank->grange.base = pin_bank->gpio_chip.base;
 963                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
 964                 pin_bank->grange.gc = &pin_bank->gpio_chip;
 965                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
 966         }
 967
 968         ret = rockchip_pinctrl_parse_dt(pdev, info);
 969         if (ret) {
 970                 pinctrl_unregister(info->pctl_dev);
 971                 return ret;
 972         }
 973
 974         return 0;
 975 }
 976
 977 /*
 978  * GPIO handling
 979  */
 980
 981 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
 982 {
 983         return pinctrl_request_gpio(chip->base + offset);
 984 }
 985
 986 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
 987 {
 988         pinctrl_free_gpio(chip->base + offset);
 989 }
 990
 991 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
 992 {
 993         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
 994         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
 995         unsigned long flags;
 996         u32 data;
 997
 998         spin_lock_irqsave(&bank->slock, flags);
 999
1000         data = readl(reg);
1001         data &= ~BIT(offset);
1002         if (value)
1003                 data |= BIT(offset);
1004         writel(data, reg);
1005
1006         spin_unlock_irqrestore(&bank->slock, flags);
1007 }
1008
1009 /*
1010  * Returns the level of the pin for input direction and setting of the DR
1011  * register for output gpios.
1012  */
1013 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1014 {
1015         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1016         u32 data;
1017
1018         data = readl(bank->reg_base + GPIO_EXT_PORT);
1019         data >>= offset;
1020         data &= 1;
1021         return data;
1022 }
1023
1024 /*
1025  * gpiolib gpio_direction_input callback function. The setting of the pin
1026  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1027  * interface.
1028  */
1029 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1030 {
1031         return pinctrl_gpio_direction_input(gc->base + offset);
1032 }
1033
1034 /*
1035  * gpiolib gpio_direction_output callback function. The setting of the pin
1036  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1037  * interface.
1038  */
1039 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1040                                           unsigned offset, int value)
1041 {
1042         rockchip_gpio_set(gc, offset, value);
1043         return pinctrl_gpio_direction_output(gc->base + offset);
1044 }
1045
1046 /*
1047  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1048  * and a virtual IRQ, if not already present.
1049  */
1050 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1051 {
1052         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1053         unsigned int virq;
1054
1055         if (!bank->domain)
1056                 return -ENXIO;
1057
1058         virq = irq_create_mapping(bank->domain, offset);
1059
1060         return (virq) ? : -ENXIO;
1061 }
1062
1063 static const struct gpio_chip rockchip_gpiolib_chip = {
1064         .request = rockchip_gpio_request,
1065         .free = rockchip_gpio_free,
1066         .set = rockchip_gpio_set,
1067         .get = rockchip_gpio_get,
1068         .direction_input = rockchip_gpio_direction_input,
1069         .direction_output = rockchip_gpio_direction_output,
1070         .to_irq = rockchip_gpio_to_irq,
1071         .owner = THIS_MODULE,
1072 };
1073
1074 /*
1075  * Interrupt handling
1076  */
1077
1078 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1079 {
1080         struct irq_chip *chip = irq_get_chip(irq);
1081         struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1082         u32 polarity = 0, data = 0;
1083         u32 pend;
1084         bool edge_changed = false;
1085
1086         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1087
1088         chained_irq_enter(chip, desc);
1089
1090         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1091
1092         if (bank->toggle_edge_mode) {
1093                 polarity = readl_relaxed(bank->reg_base +
1094                                          GPIO_INT_POLARITY);
1095                 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1096         }
1097
1098         while (pend) {
1099                 unsigned int virq;
1100
1101                 irq = __ffs(pend);
1102                 pend &= ~BIT(irq);
1103                 virq = irq_linear_revmap(bank->domain, irq);
1104
1105                 if (!virq) {
1106                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1107                         continue;
1108                 }
1109
1110                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1111
1112                 /*
1113                  * Triggering IRQ on both rising and falling edge
1114                  * needs manual intervention.
1115                  */
1116                 if (bank->toggle_edge_mode & BIT(irq)) {
1117                         if (data & BIT(irq))
1118                                 polarity &= ~BIT(irq);
1119                         else
1120                                 polarity |= BIT(irq);
1121
1122                         edge_changed = true;
1123                 }
1124
1125                 generic_handle_irq(virq);
1126         }
1127
1128         if (bank->toggle_edge_mode && edge_changed) {
1129                 /* Interrupt params should only be set with ints disabled */
1130                 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1131                 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1132                 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1133                 writel(data, bank->reg_base + GPIO_INTEN);
1134         }
1135
1136         chained_irq_exit(chip, desc);
1137 }
1138
1139 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1140 {
1141         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1142         struct rockchip_pin_bank *bank = gc->private;
1143         u32 mask = BIT(d->hwirq);
1144         u32 polarity;
1145         u32 level;
1146         u32 data;
1147
1148         /* make sure the pin is configured as gpio input */
1149         rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1150         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1151         data &= ~mask;
1152         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1153
1154         if (type & IRQ_TYPE_EDGE_BOTH)
1155                 __irq_set_handler_locked(d->irq, handle_edge_irq);
1156         else
1157                 __irq_set_handler_locked(d->irq, handle_level_irq);
1158
1159         irq_gc_lock(gc);
1160
1161         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1162         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1163
1164         switch (type) {
1165         case IRQ_TYPE_EDGE_BOTH:
1166                 bank->toggle_edge_mode |= mask;
1167                 level |= mask;
1168
1169                 /*
1170                  * Determine gpio state. If 1 next interrupt should be falling
1171                  * otherwise rising.
1172                  */
1173                 data = readl(bank->reg_base + GPIO_EXT_PORT);
1174                 if (data & mask)
1175                         polarity &= ~mask;
1176                 else
1177                         polarity |= mask;
1178                 break;
1179         case IRQ_TYPE_EDGE_RISING:
1180                 bank->toggle_edge_mode &= ~mask;
1181                 level |= mask;
1182                 polarity |= mask;
1183                 break;
1184         case IRQ_TYPE_EDGE_FALLING:
1185                 bank->toggle_edge_mode &= ~mask;
1186                 level |= mask;
1187                 polarity &= ~mask;
1188                 break;
1189         case IRQ_TYPE_LEVEL_HIGH:
1190                 bank->toggle_edge_mode &= ~mask;
1191                 level &= ~mask;
1192                 polarity |= mask;
1193                 break;
1194         case IRQ_TYPE_LEVEL_LOW:
1195                 bank->toggle_edge_mode &= ~mask;
1196                 level &= ~mask;
1197                 polarity &= ~mask;
1198                 break;
1199         default:
1200                 irq_gc_unlock(gc);
1201                 return -EINVAL;
1202         }
1203
1204         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1205         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1206
1207         irq_gc_unlock(gc);
1208
1209         return 0;
1210 }
1211
1212 static int rockchip_interrupts_register(struct platform_device *pdev,
1213                                                 struct rockchip_pinctrl *info)
1214 {
1215         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1216         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1217         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1218         struct irq_chip_generic *gc;
1219         int ret;
1220         int i;
1221
1222         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1223                 if (!bank->valid) {
1224                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1225                                  bank->name);
1226                         continue;
1227                 }
1228
1229                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1230                                                 &irq_generic_chip_ops, NULL);
1231                 if (!bank->domain) {
1232                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1233                                  bank->name);
1234                         continue;
1235                 }
1236
1237                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1238                                          "rockchip_gpio_irq", handle_level_irq,
1239                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
1240                 if (ret) {
1241                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1242                                 bank->name);
1243                         irq_domain_remove(bank->domain);
1244                         continue;
1245                 }
1246
1247                 gc = irq_get_domain_generic_chip(bank->domain, 0);
1248                 gc->reg_base = bank->reg_base;
1249                 gc->private = bank;
1250                 gc->chip_types[0].regs.mask = GPIO_INTEN;
1251                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1252                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1253                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1254                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1255                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1256                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1257
1258                 irq_set_handler_data(bank->irq, bank);
1259                 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1260         }
1261
1262         return 0;
1263 }
1264
1265 static int rockchip_gpiolib_register(struct platform_device *pdev,
1266                                                 struct rockchip_pinctrl *info)
1267 {
1268         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1269         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1270         struct gpio_chip *gc;
1271         int ret;
1272         int i;
1273
1274         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1275                 if (!bank->valid) {
1276                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1277                                  bank->name);
1278                         continue;
1279                 }
1280
1281                 bank->gpio_chip = rockchip_gpiolib_chip;
1282
1283                 gc = &bank->gpio_chip;
1284                 gc->base = bank->pin_base;
1285                 gc->ngpio = bank->nr_pins;
1286                 gc->dev = &pdev->dev;
1287                 gc->of_node = bank->of_node;
1288                 gc->label = bank->name;
1289
1290                 ret = gpiochip_add(gc);
1291                 if (ret) {
1292                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1293                                                         gc->label, ret);
1294                         goto fail;
1295                 }
1296         }
1297
1298         rockchip_interrupts_register(pdev, info);
1299
1300         return 0;
1301
1302 fail:
1303         for (--i, --bank; i >= 0; --i, --bank) {
1304                 if (!bank->valid)
1305                         continue;
1306
1307                 if (gpiochip_remove(&bank->gpio_chip))
1308                         dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1309                                                         bank->gpio_chip.label);
1310         }
1311         return ret;
1312 }
1313
1314 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1315                                                 struct rockchip_pinctrl *info)
1316 {
1317         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1318         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1319         int ret = 0;
1320         int i;
1321
1322         for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1323                 if (!bank->valid)
1324                         continue;
1325
1326                 ret = gpiochip_remove(&bank->gpio_chip);
1327         }
1328
1329         if (ret)
1330                 dev_err(&pdev->dev, "gpio chip remove failed\n");
1331
1332         return ret;
1333 }
1334
1335 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1336                                   struct device *dev)
1337 {
1338         struct resource res;
1339
1340         if (of_address_to_resource(bank->of_node, 0, &res)) {
1341                 dev_err(dev, "cannot find IO resource for bank\n");
1342                 return -ENOENT;
1343         }
1344
1345         bank->reg_base = devm_ioremap_resource(dev, &res);
1346         if (IS_ERR(bank->reg_base))
1347                 return PTR_ERR(bank->reg_base);
1348
1349         /*
1350          * special case, where parts of the pull setting-registers are
1351          * part of the PMU register space
1352          */
1353         if (of_device_is_compatible(bank->of_node,
1354                                     "rockchip,rk3188-gpio-bank0")) {
1355                 bank->bank_type = RK3188_BANK0;
1356
1357                 if (of_address_to_resource(bank->of_node, 1, &res)) {
1358                         dev_err(dev, "cannot find IO resource for bank\n");
1359                         return -ENOENT;
1360                 }
1361
1362                 bank->reg_pull = devm_ioremap_resource(dev, &res);
1363                 if (IS_ERR(bank->reg_pull))
1364                         return PTR_ERR(bank->reg_pull);
1365         } else {
1366                 bank->bank_type = COMMON_BANK;
1367         }
1368
1369         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1370
1371         bank->clk = of_clk_get(bank->of_node, 0);
1372         if (IS_ERR(bank->clk))
1373                 return PTR_ERR(bank->clk);
1374
1375         return clk_prepare_enable(bank->clk);
1376 }
1377
1378 static const struct of_device_id rockchip_pinctrl_dt_match[];
1379
1380 /* retrieve the soc specific data */
1381 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1382                                                 struct rockchip_pinctrl *d,
1383                                                 struct platform_device *pdev)
1384 {
1385         const struct of_device_id *match;
1386         struct device_node *node = pdev->dev.of_node;
1387         struct device_node *np;
1388         struct rockchip_pin_ctrl *ctrl;
1389         struct rockchip_pin_bank *bank;
1390         int i;
1391
1392         match = of_match_node(rockchip_pinctrl_dt_match, node);
1393         ctrl = (struct rockchip_pin_ctrl *)match->data;
1394
1395         for_each_child_of_node(node, np) {
1396                 if (!of_find_property(np, "gpio-controller", NULL))
1397                         continue;
1398
1399                 bank = ctrl->pin_banks;
1400                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1401                         if (!strcmp(bank->name, np->name)) {
1402                                 bank->of_node = np;
1403
1404                                 if (!rockchip_get_bank_data(bank, &pdev->dev))
1405                                         bank->valid = true;
1406
1407                                 break;
1408                         }
1409                 }
1410         }
1411
1412         bank = ctrl->pin_banks;
1413         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1414                 spin_lock_init(&bank->slock);
1415                 bank->drvdata = d;
1416                 bank->pin_base = ctrl->nr_pins;
1417                 ctrl->nr_pins += bank->nr_pins;
1418         }
1419
1420         return ctrl;
1421 }
1422
1423 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1424 {
1425         struct rockchip_pinctrl *info;
1426         struct device *dev = &pdev->dev;
1427         struct rockchip_pin_ctrl *ctrl;
1428         struct resource *res;
1429         int ret;
1430
1431         if (!dev->of_node) {
1432                 dev_err(dev, "device tree node not found\n");
1433                 return -ENODEV;
1434         }
1435
1436         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1437         if (!info)
1438                 return -ENOMEM;
1439
1440         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1441         if (!ctrl) {
1442                 dev_err(dev, "driver data not available\n");
1443                 return -EINVAL;
1444         }
1445         info->ctrl = ctrl;
1446         info->dev = dev;
1447
1448         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1449         info->reg_base = devm_ioremap_resource(&pdev->dev, res);
1450         if (IS_ERR(info->reg_base))
1451                 return PTR_ERR(info->reg_base);
1452
1453         /* The RK3188 has its pull registers in a separate place */
1454         if (ctrl->type == RK3188) {
1455                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1456                 info->reg_pull = devm_ioremap_resource(&pdev->dev, res);
1457                 if (IS_ERR(info->reg_pull))
1458                         return PTR_ERR(info->reg_pull);
1459         }
1460
1461         ret = rockchip_gpiolib_register(pdev, info);
1462         if (ret)
1463                 return ret;
1464
1465         ret = rockchip_pinctrl_register(pdev, info);
1466         if (ret) {
1467                 rockchip_gpiolib_unregister(pdev, info);
1468                 return ret;
1469         }
1470
1471         platform_set_drvdata(pdev, info);
1472
1473         return 0;
1474 }
1475
1476 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1477         PIN_BANK(0, 32, "gpio0"),
1478         PIN_BANK(1, 32, "gpio1"),
1479         PIN_BANK(2, 32, "gpio2"),
1480         PIN_BANK(3, 32, "gpio3"),
1481 };
1482
1483 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1484                 .pin_banks              = rk2928_pin_banks,
1485                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
1486                 .label                  = "RK2928-GPIO",
1487                 .type                   = RK2928,
1488                 .mux_offset             = 0xa8,
1489                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
1490 };
1491
1492 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1493         PIN_BANK(0, 32, "gpio0"),
1494         PIN_BANK(1, 32, "gpio1"),
1495         PIN_BANK(2, 32, "gpio2"),
1496         PIN_BANK(3, 32, "gpio3"),
1497         PIN_BANK(4, 32, "gpio4"),
1498         PIN_BANK(6, 16, "gpio6"),
1499 };
1500
1501 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1502                 .pin_banks              = rk3066a_pin_banks,
1503                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
1504                 .label                  = "RK3066a-GPIO",
1505                 .type                   = RK2928,
1506                 .mux_offset             = 0xa8,
1507                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
1508 };
1509
1510 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1511         PIN_BANK(0, 32, "gpio0"),
1512         PIN_BANK(1, 32, "gpio1"),
1513         PIN_BANK(2, 32, "gpio2"),
1514         PIN_BANK(3, 32, "gpio3"),
1515 };
1516
1517 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1518                 .pin_banks      = rk3066b_pin_banks,
1519                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
1520                 .label          = "RK3066b-GPIO",
1521                 .type           = RK3066B,
1522                 .mux_offset     = 0x60,
1523 };
1524
1525 static struct rockchip_pin_bank rk3188_pin_banks[] = {
1526         PIN_BANK(0, 32, "gpio0"),
1527         PIN_BANK(1, 32, "gpio1"),
1528         PIN_BANK(2, 32, "gpio2"),
1529         PIN_BANK(3, 32, "gpio3"),
1530 };
1531
1532 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1533                 .pin_banks              = rk3188_pin_banks,
1534                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
1535                 .label                  = "RK3188-GPIO",
1536                 .type                   = RK3188,
1537                 .mux_offset             = 0x68,
1538                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
1539 };
1540
1541 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1542         { .compatible = "rockchip,rk2928-pinctrl",
1543                 .data = (void *)&rk2928_pin_ctrl },
1544         { .compatible = "rockchip,rk3066a-pinctrl",
1545                 .data = (void *)&rk3066a_pin_ctrl },
1546         { .compatible = "rockchip,rk3066b-pinctrl",
1547                 .data = (void *)&rk3066b_pin_ctrl },
1548         { .compatible = "rockchip,rk3188-pinctrl",
1549                 .data = (void *)&rk3188_pin_ctrl },
1550         {},
1551 };
1552 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1553
1554 static struct platform_driver rockchip_pinctrl_driver = {
1555         .probe          = rockchip_pinctrl_probe,
1556         .driver = {
1557                 .name   = "rockchip-pinctrl",
1558                 .owner  = THIS_MODULE,
1559                 .of_match_table = rockchip_pinctrl_dt_match,
1560         },
1561 };
1562
1563 static int __init rockchip_pinctrl_drv_register(void)
1564 {
1565         return platform_driver_register(&rockchip_pinctrl_driver);
1566 }
1567 postcore_initcall(rockchip_pinctrl_drv_register);
1568
1569 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1570 MODULE_DESCRIPTION("Rockchip pinctrl driver");
1571 MODULE_LICENSE("GPL v2");