2 * PCIe host controller driver for Tegra SoCs
4 * Copyright (c) 2010, CompuLab, Ltd.
5 * Author: Mike Rapoport <mike@compulab.co.il>
7 * Based on NVIDIA PCIe driver
8 * Copyright (c) 2008-2009, NVIDIA Corporation.
10 * Bits taken from arch/arm/mach-dove/pcie.c
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
27 #include <linux/clk.h>
28 #include <linux/clk/tegra.h>
29 #include <linux/delay.h>
30 #include <linux/export.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/irqdomain.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/msi.h>
37 #include <linux/of_address.h>
38 #include <linux/of_pci.h>
39 #include <linux/of_platform.h>
40 #include <linux/pci.h>
41 #include <linux/platform_device.h>
42 #include <linux/sizes.h>
43 #include <linux/slab.h>
44 #include <linux/tegra-cpuidle.h>
45 #include <linux/tegra-powergate.h>
46 #include <linux/vmalloc.h>
47 #include <linux/regulator/consumer.h>
49 #include <asm/mach/irq.h>
50 #include <asm/mach/map.h>
51 #include <asm/mach/pci.h>
53 #define INT_PCI_MSI_NR (8 * 32)
55 /* register definitions */
57 #define AFI_AXI_BAR0_SZ 0x00
58 #define AFI_AXI_BAR1_SZ 0x04
59 #define AFI_AXI_BAR2_SZ 0x08
60 #define AFI_AXI_BAR3_SZ 0x0c
61 #define AFI_AXI_BAR4_SZ 0x10
62 #define AFI_AXI_BAR5_SZ 0x14
64 #define AFI_AXI_BAR0_START 0x18
65 #define AFI_AXI_BAR1_START 0x1c
66 #define AFI_AXI_BAR2_START 0x20
67 #define AFI_AXI_BAR3_START 0x24
68 #define AFI_AXI_BAR4_START 0x28
69 #define AFI_AXI_BAR5_START 0x2c
71 #define AFI_FPCI_BAR0 0x30
72 #define AFI_FPCI_BAR1 0x34
73 #define AFI_FPCI_BAR2 0x38
74 #define AFI_FPCI_BAR3 0x3c
75 #define AFI_FPCI_BAR4 0x40
76 #define AFI_FPCI_BAR5 0x44
78 #define AFI_CACHE_BAR0_SZ 0x48
79 #define AFI_CACHE_BAR0_ST 0x4c
80 #define AFI_CACHE_BAR1_SZ 0x50
81 #define AFI_CACHE_BAR1_ST 0x54
83 #define AFI_MSI_BAR_SZ 0x60
84 #define AFI_MSI_FPCI_BAR_ST 0x64
85 #define AFI_MSI_AXI_BAR_ST 0x68
87 #define AFI_MSI_VEC0 0x6c
88 #define AFI_MSI_VEC1 0x70
89 #define AFI_MSI_VEC2 0x74
90 #define AFI_MSI_VEC3 0x78
91 #define AFI_MSI_VEC4 0x7c
92 #define AFI_MSI_VEC5 0x80
93 #define AFI_MSI_VEC6 0x84
94 #define AFI_MSI_VEC7 0x88
96 #define AFI_MSI_EN_VEC0 0x8c
97 #define AFI_MSI_EN_VEC1 0x90
98 #define AFI_MSI_EN_VEC2 0x94
99 #define AFI_MSI_EN_VEC3 0x98
100 #define AFI_MSI_EN_VEC4 0x9c
101 #define AFI_MSI_EN_VEC5 0xa0
102 #define AFI_MSI_EN_VEC6 0xa4
103 #define AFI_MSI_EN_VEC7 0xa8
105 #define AFI_CONFIGURATION 0xac
106 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
108 #define AFI_FPCI_ERROR_MASKS 0xb0
110 #define AFI_INTR_MASK 0xb4
111 #define AFI_INTR_MASK_INT_MASK (1 << 0)
112 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
114 #define AFI_INTR_CODE 0xb8
115 #define AFI_INTR_CODE_MASK 0xf
116 #define AFI_INTR_AXI_SLAVE_ERROR 1
117 #define AFI_INTR_AXI_DECODE_ERROR 2
118 #define AFI_INTR_TARGET_ABORT 3
119 #define AFI_INTR_MASTER_ABORT 4
120 #define AFI_INTR_INVALID_WRITE 5
121 #define AFI_INTR_LEGACY 6
122 #define AFI_INTR_FPCI_DECODE_ERROR 7
124 #define AFI_INTR_SIGNATURE 0xbc
125 #define AFI_UPPER_FPCI_ADDRESS 0xc0
126 #define AFI_SM_INTR_ENABLE 0xc4
127 #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
128 #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
129 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
130 #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
131 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
132 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
133 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
134 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
136 #define AFI_AFI_INTR_ENABLE 0xc8
137 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
138 #define AFI_INTR_EN_INI_DECERR (1 << 1)
139 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
140 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
141 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
142 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
143 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
144 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
145 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
147 #define AFI_PCIE_CONFIG 0x0f8
148 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
149 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
150 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
151 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
152 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
153 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
154 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
155 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
157 #define AFI_FUSE 0x104
158 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
160 #define AFI_PEX0_CTRL 0x110
161 #define AFI_PEX1_CTRL 0x118
162 #define AFI_PEX2_CTRL 0x128
163 #define AFI_PEX_CTRL_RST (1 << 0)
164 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
165 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
167 #define AFI_PEXBIAS_CTRL_0 0x168
169 #define RP_VEND_XP 0x00000F00
170 #define RP_VEND_XP_DL_UP (1 << 30)
172 #define RP_LINK_CONTROL_STATUS 0x00000090
173 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
174 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
176 #define PADS_CTL_SEL 0x0000009C
178 #define PADS_CTL 0x000000A0
179 #define PADS_CTL_IDDQ_1L (1 << 0)
180 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
181 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
183 #define PADS_PLL_CTL_TEGRA20 0x000000B8
184 #define PADS_PLL_CTL_TEGRA30 0x000000B4
185 #define PADS_PLL_CTL_RST_B4SM (1 << 1)
186 #define PADS_PLL_CTL_LOCKDET (1 << 8)
187 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
188 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16)
189 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16)
190 #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16)
191 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
192 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20)
193 #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
194 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (1 << 22)
196 #define PADS_REFCLK_CFG0 0x000000C8
197 #define PADS_REFCLK_CFG1 0x000000CC
200 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
201 * entries, one entry per PCIe port. These field definitions and desired
202 * values aren't in the TRM, but do come from NVIDIA.
204 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
205 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7
206 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
207 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
209 /* Default value provided by HW engineering is 0xfa5c */
210 #define PADS_REFCLK_CFG_VALUE \
212 (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \
213 (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \
214 (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \
215 (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \
219 struct msi_chip chip;
220 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
221 struct irq_domain *domain;
227 /* used to differentiate between Tegra SoC generations */
228 struct tegra_pcie_soc_data {
229 unsigned int num_ports;
230 unsigned int msi_base_shift;
233 bool has_pex_clkreq_en;
234 bool has_pex_bias_ctrl;
235 bool has_intr_prsnt_sense;
236 bool has_avdd_supply;
240 static inline struct tegra_msi *to_tegra_msi(struct msi_chip *chip)
242 return container_of(chip, struct tegra_msi, chip);
252 struct list_head buses;
257 struct resource prefetch;
258 struct resource busn;
262 struct clk *pcie_xclk;
266 struct tegra_msi msi;
268 struct list_head ports;
269 unsigned int num_ports;
272 struct regulator *pex_clk_supply;
273 struct regulator *vdd_supply;
274 struct regulator *avdd_supply;
276 const struct tegra_pcie_soc_data *soc_data;
279 struct tegra_pcie_port {
280 struct tegra_pcie *pcie;
281 struct list_head list;
282 struct resource regs;
288 struct tegra_pcie_bus {
289 struct vm_struct *area;
290 struct list_head list;
294 static inline struct tegra_pcie *sys_to_pcie(struct pci_sys_data *sys)
296 return sys->private_data;
299 static inline void afi_writel(struct tegra_pcie *pcie, u32 value,
300 unsigned long offset)
302 writel(value, pcie->afi + offset);
305 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset)
307 return readl(pcie->afi + offset);
310 static inline void pads_writel(struct tegra_pcie *pcie, u32 value,
311 unsigned long offset)
313 writel(value, pcie->pads + offset);
316 static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
318 return readl(pcie->pads + offset);
322 * The configuration space mapping on Tegra is somewhat similar to the ECAM
323 * defined by PCIe. However it deviates a bit in how the 4 bits for extended
324 * register accesses are mapped:
326 * [27:24] extended register number
328 * [15:11] device number
329 * [10: 8] function number
330 * [ 7: 0] register number
332 * Mapping the whole extended configuration space would require 256 MiB of
333 * virtual address space, only a small part of which will actually be used.
334 * To work around this, a 1 MiB of virtual addresses are allocated per bus
335 * when the bus is first accessed. When the physical range is mapped, the
336 * the bus number bits are hidden so that the extended register number bits
337 * appear as bits [19:16]. Therefore the virtual mapping looks like this:
339 * [19:16] extended register number
340 * [15:11] device number
341 * [10: 8] function number
342 * [ 7: 0] register number
344 * This is achieved by stitching together 16 chunks of 64 KiB of physical
345 * address space via the MMU.
347 static unsigned long tegra_pcie_conf_offset(unsigned int devfn, int where)
349 return ((where & 0xf00) << 8) | (PCI_SLOT(devfn) << 11) |
350 (PCI_FUNC(devfn) << 8) | (where & 0xfc);
353 static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie,
356 pgprot_t prot = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | L_PTE_XN |
357 L_PTE_MT_DEV_SHARED | L_PTE_SHARED;
358 phys_addr_t cs = pcie->cs->start;
359 struct tegra_pcie_bus *bus;
363 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
365 return ERR_PTR(-ENOMEM);
367 INIT_LIST_HEAD(&bus->list);
370 /* allocate 1 MiB of virtual addresses */
371 bus->area = get_vm_area(SZ_1M, VM_IOREMAP);
377 /* map each of the 16 chunks of 64 KiB each */
378 for (i = 0; i < 16; i++) {
379 unsigned long virt = (unsigned long)bus->area->addr +
381 phys_addr_t phys = cs + i * SZ_1M + busnr * SZ_64K;
383 err = ioremap_page_range(virt, virt + SZ_64K, phys, prot);
385 dev_err(pcie->dev, "ioremap_page_range() failed: %d\n",
394 vunmap(bus->area->addr);
401 * Look up a virtual address mapping for the specified bus number. If no such
402 * mapping exists, try to create one.
404 static void __iomem *tegra_pcie_bus_map(struct tegra_pcie *pcie,
407 struct tegra_pcie_bus *bus;
409 list_for_each_entry(bus, &pcie->buses, list)
410 if (bus->nr == busnr)
411 return (void __iomem *)bus->area->addr;
413 bus = tegra_pcie_bus_alloc(pcie, busnr);
417 list_add_tail(&bus->list, &pcie->buses);
419 return (void __iomem *)bus->area->addr;
422 static void __iomem *tegra_pcie_conf_address(struct pci_bus *bus,
426 struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata);
427 void __iomem *addr = NULL;
429 if (bus->number == 0) {
430 unsigned int slot = PCI_SLOT(devfn);
431 struct tegra_pcie_port *port;
433 list_for_each_entry(port, &pcie->ports, list) {
434 if (port->index + 1 == slot) {
435 addr = port->base + (where & ~3);
440 addr = tegra_pcie_bus_map(pcie, bus->number);
443 "failed to map cfg. space for bus %u\n",
448 addr += tegra_pcie_conf_offset(devfn, where);
454 static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
455 int where, int size, u32 *value)
459 addr = tegra_pcie_conf_address(bus, devfn, where);
462 return PCIBIOS_DEVICE_NOT_FOUND;
465 *value = readl(addr);
468 *value = (*value >> (8 * (where & 3))) & 0xff;
470 *value = (*value >> (8 * (where & 3))) & 0xffff;
472 return PCIBIOS_SUCCESSFUL;
475 static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
476 int where, int size, u32 value)
481 addr = tegra_pcie_conf_address(bus, devfn, where);
483 return PCIBIOS_DEVICE_NOT_FOUND;
487 return PCIBIOS_SUCCESSFUL;
491 mask = ~(0xffff << ((where & 0x3) * 8));
493 mask = ~(0xff << ((where & 0x3) * 8));
495 return PCIBIOS_BAD_REGISTER_NUMBER;
497 tmp = readl(addr) & mask;
498 tmp |= value << ((where & 0x3) * 8);
501 return PCIBIOS_SUCCESSFUL;
504 static struct pci_ops tegra_pcie_ops = {
505 .read = tegra_pcie_read_conf,
506 .write = tegra_pcie_write_conf,
509 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
511 unsigned long ret = 0;
513 switch (port->index) {
530 static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
532 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
535 /* pulse reset signal */
536 value = afi_readl(port->pcie, ctrl);
537 value &= ~AFI_PEX_CTRL_RST;
538 afi_writel(port->pcie, value, ctrl);
540 usleep_range(1000, 2000);
542 value = afi_readl(port->pcie, ctrl);
543 value |= AFI_PEX_CTRL_RST;
544 afi_writel(port->pcie, value, ctrl);
547 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
549 const struct tegra_pcie_soc_data *soc = port->pcie->soc_data;
550 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
553 /* enable reference clock */
554 value = afi_readl(port->pcie, ctrl);
555 value |= AFI_PEX_CTRL_REFCLK_EN;
557 if (soc->has_pex_clkreq_en)
558 value |= AFI_PEX_CTRL_CLKREQ_EN;
560 afi_writel(port->pcie, value, ctrl);
562 tegra_pcie_port_reset(port);
565 static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
567 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
570 /* assert port reset */
571 value = afi_readl(port->pcie, ctrl);
572 value &= ~AFI_PEX_CTRL_RST;
573 afi_writel(port->pcie, value, ctrl);
575 /* disable reference clock */
576 value = afi_readl(port->pcie, ctrl);
577 value &= ~AFI_PEX_CTRL_REFCLK_EN;
578 afi_writel(port->pcie, value, ctrl);
581 static void tegra_pcie_port_free(struct tegra_pcie_port *port)
583 struct tegra_pcie *pcie = port->pcie;
585 devm_iounmap(pcie->dev, port->base);
586 devm_release_mem_region(pcie->dev, port->regs.start,
587 resource_size(&port->regs));
588 list_del(&port->list);
589 devm_kfree(pcie->dev, port);
592 static void tegra_pcie_fixup_bridge(struct pci_dev *dev)
596 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) {
597 pci_read_config_word(dev, PCI_COMMAND, ®);
598 reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
599 PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
600 pci_write_config_word(dev, PCI_COMMAND, reg);
603 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge);
605 /* Tegra PCIE root complex wrongly reports device class */
606 static void tegra_pcie_fixup_class(struct pci_dev *dev)
608 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
610 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
611 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
612 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, tegra_pcie_fixup_class);
613 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, tegra_pcie_fixup_class);
615 /* Tegra PCIE requires relaxed ordering */
616 static void tegra_pcie_relax_enable(struct pci_dev *dev)
618 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
620 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
622 static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
624 struct tegra_pcie *pcie = sys_to_pcie(sys);
626 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
627 pci_add_resource_offset(&sys->resources, &pcie->prefetch,
629 pci_add_resource(&sys->resources, &pcie->busn);
631 pci_ioremap_io(nr * SZ_64K, pcie->io.start);
636 static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
638 struct tegra_pcie *pcie = sys_to_pcie(pdev->bus->sysdata);
640 tegra_cpuidle_pcie_irqs_in_use();
645 static void tegra_pcie_add_bus(struct pci_bus *bus)
647 if (IS_ENABLED(CONFIG_PCI_MSI)) {
648 struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata);
650 bus->msi = &pcie->msi.chip;
654 static struct pci_bus *tegra_pcie_scan_bus(int nr, struct pci_sys_data *sys)
656 struct tegra_pcie *pcie = sys_to_pcie(sys);
659 bus = pci_create_root_bus(pcie->dev, sys->busnr, &tegra_pcie_ops, sys,
664 pci_scan_child_bus(bus);
669 static irqreturn_t tegra_pcie_isr(int irq, void *arg)
671 const char *err_msg[] = {
678 "Response decoding error",
679 "AXI response decoding error",
680 "Transaction timeout",
682 struct tegra_pcie *pcie = arg;
685 code = afi_readl(pcie, AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
686 signature = afi_readl(pcie, AFI_INTR_SIGNATURE);
687 afi_writel(pcie, 0, AFI_INTR_CODE);
689 if (code == AFI_INTR_LEGACY)
692 if (code >= ARRAY_SIZE(err_msg))
696 * do not pollute kernel log with master abort reports since they
697 * happen a lot during enumeration
699 if (code == AFI_INTR_MASTER_ABORT)
700 dev_dbg(pcie->dev, "%s, signature: %08x\n", err_msg[code],
703 dev_err(pcie->dev, "%s, signature: %08x\n", err_msg[code],
706 if (code == AFI_INTR_TARGET_ABORT || code == AFI_INTR_MASTER_ABORT ||
707 code == AFI_INTR_FPCI_DECODE_ERROR) {
708 u32 fpci = afi_readl(pcie, AFI_UPPER_FPCI_ADDRESS) & 0xff;
709 u64 address = (u64)fpci << 32 | (signature & 0xfffffffc);
711 if (code == AFI_INTR_MASTER_ABORT)
712 dev_dbg(pcie->dev, " FPCI address: %10llx\n", address);
714 dev_err(pcie->dev, " FPCI address: %10llx\n", address);
721 * FPCI map is as follows:
722 * - 0xfdfc000000: I/O space
723 * - 0xfdfe000000: type 0 configuration space
724 * - 0xfdff000000: type 1 configuration space
725 * - 0xfe00000000: type 0 extended configuration space
726 * - 0xfe10000000: type 1 extended configuration space
728 static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
730 u32 fpci_bar, size, axi_address;
732 /* Bar 0: type 1 extended configuration space */
733 fpci_bar = 0xfe100000;
734 size = resource_size(pcie->cs);
735 axi_address = pcie->cs->start;
736 afi_writel(pcie, axi_address, AFI_AXI_BAR0_START);
737 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
738 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR0);
740 /* Bar 1: downstream IO bar */
741 fpci_bar = 0xfdfc0000;
742 size = resource_size(&pcie->io);
743 axi_address = pcie->io.start;
744 afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
745 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
746 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
748 /* Bar 2: prefetchable memory BAR */
749 fpci_bar = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1;
750 size = resource_size(&pcie->prefetch);
751 axi_address = pcie->prefetch.start;
752 afi_writel(pcie, axi_address, AFI_AXI_BAR2_START);
753 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
754 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2);
756 /* Bar 3: non prefetchable memory BAR */
757 fpci_bar = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1;
758 size = resource_size(&pcie->mem);
759 axi_address = pcie->mem.start;
760 afi_writel(pcie, axi_address, AFI_AXI_BAR3_START);
761 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
762 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3);
764 /* NULL out the remaining BARs as they are not used */
765 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
766 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
767 afi_writel(pcie, 0, AFI_FPCI_BAR4);
769 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
770 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
771 afi_writel(pcie, 0, AFI_FPCI_BAR5);
773 /* map all upstream transactions as uncached */
774 afi_writel(pcie, PHYS_OFFSET, AFI_CACHE_BAR0_ST);
775 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
776 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
777 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
779 /* MSI translations are setup only when needed */
780 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
781 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
782 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
783 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
786 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
788 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
789 struct tegra_pcie_port *port;
790 unsigned int timeout;
793 /* power down PCIe slot clock bias pad */
794 if (soc->has_pex_bias_ctrl)
795 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
797 /* configure mode and disable all ports */
798 value = afi_readl(pcie, AFI_PCIE_CONFIG);
799 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
800 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config;
802 list_for_each_entry(port, &pcie->ports, list)
803 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
805 afi_writel(pcie, value, AFI_PCIE_CONFIG);
807 value = afi_readl(pcie, AFI_FUSE);
808 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
809 afi_writel(pcie, value, AFI_FUSE);
811 /* initialize internal PHY, enable up to 16 PCIE lanes */
812 pads_writel(pcie, 0x0, PADS_CTL_SEL);
814 /* override IDDQ to 1 on all 4 lanes */
815 value = pads_readl(pcie, PADS_CTL);
816 value |= PADS_CTL_IDDQ_1L;
817 pads_writel(pcie, value, PADS_CTL);
820 * Set up PHY PLL inputs select PLLE output as refclock,
821 * set TX ref sel to div10 (not div5).
823 value = pads_readl(pcie, soc->pads_pll_ctl);
824 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
825 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
826 pads_writel(pcie, value, soc->pads_pll_ctl);
828 /* take PLL out of reset */
829 value = pads_readl(pcie, soc->pads_pll_ctl);
830 value |= PADS_PLL_CTL_RST_B4SM;
831 pads_writel(pcie, value, soc->pads_pll_ctl);
833 /* Configure the reference clock driver */
834 value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);
835 pads_writel(pcie, value, PADS_REFCLK_CFG0);
836 if (soc->num_ports > 2)
837 pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);
839 /* wait for the PLL to lock */
842 value = pads_readl(pcie, soc->pads_pll_ctl);
843 usleep_range(1000, 2000);
844 if (--timeout == 0) {
845 pr_err("Tegra PCIe error: timeout waiting for PLL\n");
848 } while (!(value & PADS_PLL_CTL_LOCKDET));
850 /* turn off IDDQ override */
851 value = pads_readl(pcie, PADS_CTL);
852 value &= ~PADS_CTL_IDDQ_1L;
853 pads_writel(pcie, value, PADS_CTL);
855 /* enable TX/RX data */
856 value = pads_readl(pcie, PADS_CTL);
857 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
858 pads_writel(pcie, value, PADS_CTL);
860 /* take the PCIe interface module out of reset */
861 tegra_periph_reset_deassert(pcie->pcie_xclk);
863 /* finally enable PCIe */
864 value = afi_readl(pcie, AFI_CONFIGURATION);
865 value |= AFI_CONFIGURATION_EN_FPCI;
866 afi_writel(pcie, value, AFI_CONFIGURATION);
868 value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
869 AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
870 AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR;
872 if (soc->has_intr_prsnt_sense)
873 value |= AFI_INTR_EN_PRSNT_SENSE;
875 afi_writel(pcie, value, AFI_AFI_INTR_ENABLE);
876 afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE);
878 /* don't enable MSI for now, only when needed */
879 afi_writel(pcie, AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
881 /* disable all exceptions */
882 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
887 static void tegra_pcie_power_off(struct tegra_pcie *pcie)
889 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
892 /* TODO: disable and unprepare clocks? */
894 tegra_periph_reset_assert(pcie->pcie_xclk);
895 tegra_periph_reset_assert(pcie->afi_clk);
896 tegra_periph_reset_assert(pcie->pex_clk);
898 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
900 if (soc->has_avdd_supply) {
901 err = regulator_disable(pcie->avdd_supply);
904 "failed to disable AVDD regulator: %d\n",
908 err = regulator_disable(pcie->pex_clk_supply);
910 dev_warn(pcie->dev, "failed to disable pex-clk regulator: %d\n",
913 err = regulator_disable(pcie->vdd_supply);
915 dev_warn(pcie->dev, "failed to disable VDD regulator: %d\n",
919 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
921 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
924 tegra_periph_reset_assert(pcie->pcie_xclk);
925 tegra_periph_reset_assert(pcie->afi_clk);
926 tegra_periph_reset_assert(pcie->pex_clk);
928 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
930 /* enable regulators */
931 err = regulator_enable(pcie->vdd_supply);
933 dev_err(pcie->dev, "failed to enable VDD regulator: %d\n", err);
937 err = regulator_enable(pcie->pex_clk_supply);
939 dev_err(pcie->dev, "failed to enable pex-clk regulator: %d\n",
944 if (soc->has_avdd_supply) {
945 err = regulator_enable(pcie->avdd_supply);
948 "failed to enable AVDD regulator: %d\n",
954 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
957 dev_err(pcie->dev, "powerup sequence failed: %d\n", err);
961 tegra_periph_reset_deassert(pcie->afi_clk);
963 err = clk_prepare_enable(pcie->afi_clk);
965 dev_err(pcie->dev, "failed to enable AFI clock: %d\n", err);
969 if (soc->has_cml_clk) {
970 err = clk_prepare_enable(pcie->cml_clk);
972 dev_err(pcie->dev, "failed to enable CML clock: %d\n",
978 err = clk_prepare_enable(pcie->pll_e);
980 dev_err(pcie->dev, "failed to enable PLLE clock: %d\n", err);
987 static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
989 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
991 pcie->pex_clk = devm_clk_get(pcie->dev, "pex");
992 if (IS_ERR(pcie->pex_clk))
993 return PTR_ERR(pcie->pex_clk);
995 pcie->afi_clk = devm_clk_get(pcie->dev, "afi");
996 if (IS_ERR(pcie->afi_clk))
997 return PTR_ERR(pcie->afi_clk);
999 pcie->pcie_xclk = devm_clk_get(pcie->dev, "pcie_xclk");
1000 if (IS_ERR(pcie->pcie_xclk))
1001 return PTR_ERR(pcie->pcie_xclk);
1003 pcie->pll_e = devm_clk_get(pcie->dev, "pll_e");
1004 if (IS_ERR(pcie->pll_e))
1005 return PTR_ERR(pcie->pll_e);
1007 if (soc->has_cml_clk) {
1008 pcie->cml_clk = devm_clk_get(pcie->dev, "cml");
1009 if (IS_ERR(pcie->cml_clk))
1010 return PTR_ERR(pcie->cml_clk);
1016 static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
1018 struct platform_device *pdev = to_platform_device(pcie->dev);
1019 struct resource *pads, *afi, *res;
1022 err = tegra_pcie_clocks_get(pcie);
1024 dev_err(&pdev->dev, "failed to get clocks: %d\n", err);
1028 err = tegra_pcie_power_on(pcie);
1030 dev_err(&pdev->dev, "failed to power up: %d\n", err);
1034 pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
1035 pcie->pads = devm_ioremap_resource(&pdev->dev, pads);
1036 if (IS_ERR(pcie->pads)) {
1037 err = PTR_ERR(pcie->pads);
1041 afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
1042 pcie->afi = devm_ioremap_resource(&pdev->dev, afi);
1043 if (IS_ERR(pcie->afi)) {
1044 err = PTR_ERR(pcie->afi);
1048 /* request configuration space, but remap later, on demand */
1049 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs");
1051 err = -EADDRNOTAVAIL;
1055 pcie->cs = devm_request_mem_region(pcie->dev, res->start,
1056 resource_size(res), res->name);
1058 err = -EADDRNOTAVAIL;
1062 /* request interrupt */
1063 err = platform_get_irq_byname(pdev, "intr");
1065 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
1071 err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie);
1073 dev_err(&pdev->dev, "failed to register IRQ: %d\n", err);
1080 tegra_pcie_power_off(pcie);
1084 static int tegra_pcie_put_resources(struct tegra_pcie *pcie)
1087 free_irq(pcie->irq, pcie);
1089 tegra_pcie_power_off(pcie);
1093 static int tegra_msi_alloc(struct tegra_msi *chip)
1097 mutex_lock(&chip->lock);
1099 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
1100 if (msi < INT_PCI_MSI_NR)
1101 set_bit(msi, chip->used);
1105 mutex_unlock(&chip->lock);
1110 static void tegra_msi_free(struct tegra_msi *chip, unsigned long irq)
1112 struct device *dev = chip->chip.dev;
1114 mutex_lock(&chip->lock);
1116 if (!test_bit(irq, chip->used))
1117 dev_err(dev, "trying to free unused MSI#%lu\n", irq);
1119 clear_bit(irq, chip->used);
1121 mutex_unlock(&chip->lock);
1124 static irqreturn_t tegra_pcie_msi_irq(int irq, void *data)
1126 struct tegra_pcie *pcie = data;
1127 struct tegra_msi *msi = &pcie->msi;
1128 unsigned int i, processed = 0;
1130 for (i = 0; i < 8; i++) {
1131 unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
1134 unsigned int offset = find_first_bit(®, 32);
1135 unsigned int index = i * 32 + offset;
1138 /* clear the interrupt */
1139 afi_writel(pcie, 1 << offset, AFI_MSI_VEC0 + i * 4);
1141 irq = irq_find_mapping(msi->domain, index);
1143 if (test_bit(index, msi->used))
1144 generic_handle_irq(irq);
1146 dev_info(pcie->dev, "unhandled MSI\n");
1149 * that's weird who triggered this?
1152 dev_info(pcie->dev, "unexpected MSI\n");
1155 /* see if there's any more pending in this vector */
1156 reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
1162 return processed > 0 ? IRQ_HANDLED : IRQ_NONE;
1165 static int tegra_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
1166 struct msi_desc *desc)
1168 struct tegra_msi *msi = to_tegra_msi(chip);
1173 hwirq = tegra_msi_alloc(msi);
1177 irq = irq_create_mapping(msi->domain, hwirq);
1181 irq_set_msi_desc(irq, desc);
1183 msg.address_lo = virt_to_phys((void *)msi->pages);
1184 /* 32 bit address only */
1188 write_msi_msg(irq, &msg);
1193 static void tegra_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
1195 struct tegra_msi *msi = to_tegra_msi(chip);
1196 struct irq_data *d = irq_get_irq_data(irq);
1198 tegra_msi_free(msi, d->hwirq);
1201 static struct irq_chip tegra_msi_irq_chip = {
1202 .name = "Tegra PCIe MSI",
1203 .irq_enable = unmask_msi_irq,
1204 .irq_disable = mask_msi_irq,
1205 .irq_mask = mask_msi_irq,
1206 .irq_unmask = unmask_msi_irq,
1209 static int tegra_msi_map(struct irq_domain *domain, unsigned int irq,
1210 irq_hw_number_t hwirq)
1212 irq_set_chip_and_handler(irq, &tegra_msi_irq_chip, handle_simple_irq);
1213 irq_set_chip_data(irq, domain->host_data);
1214 set_irq_flags(irq, IRQF_VALID);
1216 tegra_cpuidle_pcie_irqs_in_use();
1221 static const struct irq_domain_ops msi_domain_ops = {
1222 .map = tegra_msi_map,
1225 static int tegra_pcie_enable_msi(struct tegra_pcie *pcie)
1227 struct platform_device *pdev = to_platform_device(pcie->dev);
1228 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
1229 struct tegra_msi *msi = &pcie->msi;
1234 mutex_init(&msi->lock);
1236 msi->chip.dev = pcie->dev;
1237 msi->chip.setup_irq = tegra_msi_setup_irq;
1238 msi->chip.teardown_irq = tegra_msi_teardown_irq;
1240 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
1241 &msi_domain_ops, &msi->chip);
1243 dev_err(&pdev->dev, "failed to create IRQ domain\n");
1247 err = platform_get_irq_byname(pdev, "msi");
1249 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
1255 err = request_irq(msi->irq, tegra_pcie_msi_irq, 0,
1256 tegra_msi_irq_chip.name, pcie);
1258 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1262 /* setup AFI/FPCI range */
1263 msi->pages = __get_free_pages(GFP_KERNEL, 0);
1264 base = virt_to_phys((void *)msi->pages);
1266 afi_writel(pcie, base >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);
1267 afi_writel(pcie, base, AFI_MSI_AXI_BAR_ST);
1268 /* this register is in 4K increments */
1269 afi_writel(pcie, 1, AFI_MSI_BAR_SZ);
1271 /* enable all MSI vectors */
1272 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC0);
1273 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC1);
1274 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC2);
1275 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC3);
1276 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC4);
1277 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC5);
1278 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC6);
1279 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC7);
1281 /* and unmask the MSI interrupt */
1282 reg = afi_readl(pcie, AFI_INTR_MASK);
1283 reg |= AFI_INTR_MASK_MSI_MASK;
1284 afi_writel(pcie, reg, AFI_INTR_MASK);
1289 irq_domain_remove(msi->domain);
1293 static int tegra_pcie_disable_msi(struct tegra_pcie *pcie)
1295 struct tegra_msi *msi = &pcie->msi;
1296 unsigned int i, irq;
1299 /* mask the MSI interrupt */
1300 value = afi_readl(pcie, AFI_INTR_MASK);
1301 value &= ~AFI_INTR_MASK_MSI_MASK;
1302 afi_writel(pcie, value, AFI_INTR_MASK);
1304 /* disable all MSI vectors */
1305 afi_writel(pcie, 0, AFI_MSI_EN_VEC0);
1306 afi_writel(pcie, 0, AFI_MSI_EN_VEC1);
1307 afi_writel(pcie, 0, AFI_MSI_EN_VEC2);
1308 afi_writel(pcie, 0, AFI_MSI_EN_VEC3);
1309 afi_writel(pcie, 0, AFI_MSI_EN_VEC4);
1310 afi_writel(pcie, 0, AFI_MSI_EN_VEC5);
1311 afi_writel(pcie, 0, AFI_MSI_EN_VEC6);
1312 afi_writel(pcie, 0, AFI_MSI_EN_VEC7);
1314 free_pages(msi->pages, 0);
1317 free_irq(msi->irq, pcie);
1319 for (i = 0; i < INT_PCI_MSI_NR; i++) {
1320 irq = irq_find_mapping(msi->domain, i);
1322 irq_dispose_mapping(irq);
1325 irq_domain_remove(msi->domain);
1330 static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
1333 struct device_node *np = pcie->dev->of_node;
1335 if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
1338 dev_info(pcie->dev, "4x1, 2x1 configuration\n");
1339 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
1343 dev_info(pcie->dev, "2x3 configuration\n");
1344 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
1348 dev_info(pcie->dev, "4x1, 1x2 configuration\n");
1349 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
1352 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
1355 dev_info(pcie->dev, "single-mode configuration\n");
1356 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
1360 dev_info(pcie->dev, "dual-mode configuration\n");
1361 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
1369 static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
1371 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
1372 struct device_node *np = pcie->dev->of_node, *port;
1373 struct of_pci_range_parser parser;
1374 struct of_pci_range range;
1375 struct resource res;
1379 if (of_pci_range_parser_init(&parser, np)) {
1380 dev_err(pcie->dev, "missing \"ranges\" property\n");
1384 pcie->vdd_supply = devm_regulator_get(pcie->dev, "vdd");
1385 if (IS_ERR(pcie->vdd_supply))
1386 return PTR_ERR(pcie->vdd_supply);
1388 pcie->pex_clk_supply = devm_regulator_get(pcie->dev, "pex-clk");
1389 if (IS_ERR(pcie->pex_clk_supply))
1390 return PTR_ERR(pcie->pex_clk_supply);
1392 if (soc->has_avdd_supply) {
1393 pcie->avdd_supply = devm_regulator_get(pcie->dev, "avdd");
1394 if (IS_ERR(pcie->avdd_supply))
1395 return PTR_ERR(pcie->avdd_supply);
1398 for_each_of_pci_range(&parser, &range) {
1399 of_pci_range_to_resource(&range, np, &res);
1401 switch (res.flags & IORESOURCE_TYPE_BITS) {
1403 memcpy(&pcie->io, &res, sizeof(res));
1404 pcie->io.name = "I/O";
1407 case IORESOURCE_MEM:
1408 if (res.flags & IORESOURCE_PREFETCH) {
1409 memcpy(&pcie->prefetch, &res, sizeof(res));
1410 pcie->prefetch.name = "PREFETCH";
1412 memcpy(&pcie->mem, &res, sizeof(res));
1413 pcie->mem.name = "MEM";
1419 err = of_pci_parse_bus_range(np, &pcie->busn);
1421 dev_err(pcie->dev, "failed to parse ranges property: %d\n",
1423 pcie->busn.name = np->name;
1424 pcie->busn.start = 0;
1425 pcie->busn.end = 0xff;
1426 pcie->busn.flags = IORESOURCE_BUS;
1429 /* parse root ports */
1430 for_each_child_of_node(np, port) {
1431 struct tegra_pcie_port *rp;
1435 err = of_pci_get_devfn(port);
1437 dev_err(pcie->dev, "failed to parse address: %d\n",
1442 index = PCI_SLOT(err);
1444 if (index < 1 || index > soc->num_ports) {
1445 dev_err(pcie->dev, "invalid port number: %d\n", index);
1451 err = of_property_read_u32(port, "nvidia,num-lanes", &value);
1453 dev_err(pcie->dev, "failed to parse # of lanes: %d\n",
1459 dev_err(pcie->dev, "invalid # of lanes: %u\n", value);
1463 lanes |= value << (index << 3);
1465 if (!of_device_is_available(port))
1468 rp = devm_kzalloc(pcie->dev, sizeof(*rp), GFP_KERNEL);
1472 err = of_address_to_resource(port, 0, &rp->regs);
1474 dev_err(pcie->dev, "failed to parse address: %d\n",
1479 INIT_LIST_HEAD(&rp->list);
1484 rp->base = devm_ioremap_resource(pcie->dev, &rp->regs);
1485 if (IS_ERR(rp->base))
1486 return PTR_ERR(rp->base);
1488 list_add_tail(&rp->list, &pcie->ports);
1491 err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config);
1493 dev_err(pcie->dev, "invalid lane configuration\n");
1501 * FIXME: If there are no PCIe cards attached, then calling this function
1502 * can result in the increase of the bootup time as there are big timeout
1505 #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */
1506 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
1508 unsigned int retries = 3;
1509 unsigned long value;
1512 unsigned int timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
1515 value = readl(port->base + RP_VEND_XP);
1517 if (value & RP_VEND_XP_DL_UP)
1520 usleep_range(1000, 2000);
1521 } while (--timeout);
1524 dev_err(port->pcie->dev, "link %u down, retrying\n",
1529 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
1532 value = readl(port->base + RP_LINK_CONTROL_STATUS);
1534 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
1537 usleep_range(1000, 2000);
1538 } while (--timeout);
1541 tegra_pcie_port_reset(port);
1542 } while (--retries);
1547 static int tegra_pcie_enable(struct tegra_pcie *pcie)
1549 struct tegra_pcie_port *port, *tmp;
1552 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
1553 dev_info(pcie->dev, "probing port %u, using %u lanes\n",
1554 port->index, port->lanes);
1556 tegra_pcie_port_enable(port);
1558 if (tegra_pcie_port_check_link(port))
1561 dev_info(pcie->dev, "link %u down, ignoring\n", port->index);
1563 tegra_pcie_port_disable(port);
1564 tegra_pcie_port_free(port);
1567 memset(&hw, 0, sizeof(hw));
1569 hw.nr_controllers = 1;
1570 hw.private_data = (void **)&pcie;
1571 hw.setup = tegra_pcie_setup;
1572 hw.map_irq = tegra_pcie_map_irq;
1573 hw.add_bus = tegra_pcie_add_bus;
1574 hw.scan = tegra_pcie_scan_bus;
1575 hw.ops = &tegra_pcie_ops;
1577 pci_common_init_dev(pcie->dev, &hw);
1582 static const struct tegra_pcie_soc_data tegra20_pcie_data = {
1584 .msi_base_shift = 0,
1585 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
1586 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
1587 .has_pex_clkreq_en = false,
1588 .has_pex_bias_ctrl = false,
1589 .has_intr_prsnt_sense = false,
1590 .has_avdd_supply = false,
1591 .has_cml_clk = false,
1594 static const struct tegra_pcie_soc_data tegra30_pcie_data = {
1596 .msi_base_shift = 8,
1597 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1598 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1599 .has_pex_clkreq_en = true,
1600 .has_pex_bias_ctrl = true,
1601 .has_intr_prsnt_sense = true,
1602 .has_avdd_supply = true,
1603 .has_cml_clk = true,
1606 static const struct of_device_id tegra_pcie_of_match[] = {
1607 { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie_data },
1608 { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie_data },
1611 MODULE_DEVICE_TABLE(of, tegra_pcie_of_match);
1613 static int tegra_pcie_probe(struct platform_device *pdev)
1615 const struct of_device_id *match;
1616 struct tegra_pcie *pcie;
1619 match = of_match_device(tegra_pcie_of_match, &pdev->dev);
1623 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
1627 INIT_LIST_HEAD(&pcie->buses);
1628 INIT_LIST_HEAD(&pcie->ports);
1629 pcie->soc_data = match->data;
1630 pcie->dev = &pdev->dev;
1632 err = tegra_pcie_parse_dt(pcie);
1636 pcibios_min_mem = 0;
1638 err = tegra_pcie_get_resources(pcie);
1640 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
1644 err = tegra_pcie_enable_controller(pcie);
1648 /* setup the AFI address translations */
1649 tegra_pcie_setup_translations(pcie);
1651 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1652 err = tegra_pcie_enable_msi(pcie);
1655 "failed to enable MSI support: %d\n",
1661 err = tegra_pcie_enable(pcie);
1663 dev_err(&pdev->dev, "failed to enable PCIe ports: %d\n", err);
1667 platform_set_drvdata(pdev, pcie);
1671 if (IS_ENABLED(CONFIG_PCI_MSI))
1672 tegra_pcie_disable_msi(pcie);
1674 tegra_pcie_put_resources(pcie);
1678 static struct platform_driver tegra_pcie_driver = {
1680 .name = "tegra-pcie",
1681 .owner = THIS_MODULE,
1682 .of_match_table = tegra_pcie_of_match,
1683 .suppress_bind_attrs = true,
1685 .probe = tegra_pcie_probe,
1687 module_platform_driver(tegra_pcie_driver);
1689 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1690 MODULE_DESCRIPTION("NVIDIA Tegra PCIe driver");
1691 MODULE_LICENSE("GPLv2");