drivers/ntb/ntb_hw.c

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  *   redistributing this file, you may do so under either license.
   4  *
   5  *   GPL LICENSE SUMMARY
   6  *
   7  *   Copyright(c) 2012 Intel Corporation. All rights reserved.
   8  *
   9  *   This program is free software; you can redistribute it and/or modify
  10  *   it under the terms of version 2 of the GNU General Public License as
  11  *   published by the Free Software Foundation.
  12  *
  13  *   BSD LICENSE
  14  *
  15  *   Copyright(c) 2012 Intel Corporation. All rights reserved.
  16  *
  17  *   Redistribution and use in source and binary forms, with or without
  18  *   modification, are permitted provided that the following conditions
  19  *   are met:
  20  *
  21  *     * Redistributions of source code must retain the above copyright
  22  *       notice, this list of conditions and the following disclaimer.
  23  *     * Redistributions in binary form must reproduce the above copy
  24  *       notice, this list of conditions and the following disclaimer in
  25  *       the documentation and/or other materials provided with the
  26  *       distribution.
  27  *     * Neither the name of Intel Corporation nor the names of its
  28  *       contributors may be used to endorse or promote products derived
  29  *       from this software without specific prior written permission.
  30  *
  31  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  32  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  33  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  34  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  35  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  36  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  37  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  38  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  39  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  41  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42  *
  43  * Intel PCIe NTB Linux driver
  44  *
  45  * Contact Information:
  46  * Jon Mason <jon.mason@intel.com>
  47  */
  48 #include <linux/debugfs.h>
  49 #include <linux/delay.h>
  50 #include <linux/init.h>
  51 #include <linux/interrupt.h>
  52 #include <linux/module.h>
  53 #include <linux/pci.h>
  54 #include <linux/random.h>
  55 #include <linux/slab.h>
  56 #include "ntb_hw.h"
  57 #include "ntb_regs.h"
  58
  59 #define NTB_NAME        "Intel(R) PCI-E Non-Transparent Bridge Driver"
  60 #define NTB_VER         "1.0"
  61
  62 MODULE_DESCRIPTION(NTB_NAME);
  63 MODULE_VERSION(NTB_VER);
  64 MODULE_LICENSE("Dual BSD/GPL");
  65 MODULE_AUTHOR("Intel Corporation");
  66
  67 static bool xeon_errata_workaround = true;
  68 module_param(xeon_errata_workaround, bool, 0644);
  69 MODULE_PARM_DESC(xeon_errata_workaround, "Workaround for the Xeon Errata");
  70
  71 enum {
  72         NTB_CONN_TRANSPARENT = 0,
  73         NTB_CONN_B2B,
  74         NTB_CONN_RP,
  75 };
  76
  77 enum {
  78         NTB_DEV_USD = 0,
  79         NTB_DEV_DSD,
  80 };
  81
  82 enum {
  83         SNB_HW = 0,
  84         BWD_HW,
  85 };
  86
  87 static struct dentry *debugfs_dir;
  88
  89 #define BWD_LINK_RECOVERY_TIME  500
  90
  91 /* Translate memory window 0,1 to BAR 2,4 */
  92 #define MW_TO_BAR(mw)   (mw * NTB_MAX_NUM_MW + 2)
  93
  94 static DEFINE_PCI_DEVICE_TABLE(ntb_pci_tbl) = {
  95         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_BWD)},
  96         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_JSF)},
  97         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SNB)},
  98         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_IVT)},
  99         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_HSX)},
 100         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_JSF)},
 101         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_SNB)},
 102         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_IVT)},
 103         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_HSX)},
 104         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_JSF)},
 105         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_SNB)},
 106         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_IVT)},
 107         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_HSX)},
 108         {0}
 109 };
 110 MODULE_DEVICE_TABLE(pci, ntb_pci_tbl);
 111
 112 /**
 113  * ntb_register_event_callback() - register event callback
 114  * @ndev: pointer to ntb_device instance
 115  * @func: callback function to register
 116  *
 117  * This function registers a callback for any HW driver events such as link
 118  * up/down, power management notices and etc.
 119  *
 120  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 121  */
 122 int ntb_register_event_callback(struct ntb_device *ndev,
 123                             void (*func)(void *handle, enum ntb_hw_event event))
 124 {
 125         if (ndev->event_cb)
 126                 return -EINVAL;
 127
 128         ndev->event_cb = func;
 129
 130         return 0;
 131 }
 132
 133 /**
 134  * ntb_unregister_event_callback() - unregisters the event callback
 135  * @ndev: pointer to ntb_device instance
 136  *
 137  * This function unregisters the existing callback from transport
 138  */
 139 void ntb_unregister_event_callback(struct ntb_device *ndev)
 140 {
 141         ndev->event_cb = NULL;
 142 }
 143
 144 /**
 145  * ntb_register_db_callback() - register a callback for doorbell interrupt
 146  * @ndev: pointer to ntb_device instance
 147  * @idx: doorbell index to register callback, zero based
 148  * @data: pointer to be returned to caller with every callback
 149  * @func: callback function to register
 150  *
 151  * This function registers a callback function for the doorbell interrupt
 152  * on the primary side. The function will unmask the doorbell as well to
 153  * allow interrupt.
 154  *
 155  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 156  */
 157 int ntb_register_db_callback(struct ntb_device *ndev, unsigned int idx,
 158                              void *data, void (*func)(void *data, int db_num))
 159 {
 160         unsigned long mask;
 161
 162         if (idx >= ndev->max_cbs || ndev->db_cb[idx].callback) {
 163                 dev_warn(&ndev->pdev->dev, "Invalid Index.\n");
 164                 return -EINVAL;
 165         }
 166
 167         ndev->db_cb[idx].callback = func;
 168         ndev->db_cb[idx].data = data;
 169
 170         /* unmask interrupt */
 171         mask = readw(ndev->reg_ofs.ldb_mask);
 172         clear_bit(idx * ndev->bits_per_vector, &mask);
 173         writew(mask, ndev->reg_ofs.ldb_mask);
 174
 175         return 0;
 176 }
 177
 178 /**
 179  * ntb_unregister_db_callback() - unregister a callback for doorbell interrupt
 180  * @ndev: pointer to ntb_device instance
 181  * @idx: doorbell index to register callback, zero based
 182  *
 183  * This function unregisters a callback function for the doorbell interrupt
 184  * on the primary side. The function will also mask the said doorbell.
 185  */
 186 void ntb_unregister_db_callback(struct ntb_device *ndev, unsigned int idx)
 187 {
 188         unsigned long mask;
 189
 190         if (idx >= ndev->max_cbs || !ndev->db_cb[idx].callback)
 191                 return;
 192
 193         mask = readw(ndev->reg_ofs.ldb_mask);
 194         set_bit(idx * ndev->bits_per_vector, &mask);
 195         writew(mask, ndev->reg_ofs.ldb_mask);
 196
 197         ndev->db_cb[idx].callback = NULL;
 198 }
 199
 200 /**
 201  * ntb_find_transport() - find the transport pointer
 202  * @transport: pointer to pci device
 203  *
 204  * Given the pci device pointer, return the transport pointer passed in when
 205  * the transport attached when it was inited.
 206  *
 207  * RETURNS: pointer to transport.
 208  */
 209 void *ntb_find_transport(struct pci_dev *pdev)
 210 {
 211         struct ntb_device *ndev = pci_get_drvdata(pdev);
 212         return ndev->ntb_transport;
 213 }
 214
 215 /**
 216  * ntb_register_transport() - Register NTB transport with NTB HW driver
 217  * @transport: transport identifier
 218  *
 219  * This function allows a transport to reserve the hardware driver for
 220  * NTB usage.
 221  *
 222  * RETURNS: pointer to ntb_device, NULL on error.
 223  */
 224 struct ntb_device *ntb_register_transport(struct pci_dev *pdev, void *transport)
 225 {
 226         struct ntb_device *ndev = pci_get_drvdata(pdev);
 227
 228         if (ndev->ntb_transport)
 229                 return NULL;
 230
 231         ndev->ntb_transport = transport;
 232         return ndev;
 233 }
 234
 235 /**
 236  * ntb_unregister_transport() - Unregister the transport with the NTB HW driver
 237  * @ndev - ntb_device of the transport to be freed
 238  *
 239  * This function unregisters the transport from the HW driver and performs any
 240  * necessary cleanups.
 241  */
 242 void ntb_unregister_transport(struct ntb_device *ndev)
 243 {
 244         int i;
 245
 246         if (!ndev->ntb_transport)
 247                 return;
 248
 249         for (i = 0; i < ndev->max_cbs; i++)
 250                 ntb_unregister_db_callback(ndev, i);
 251
 252         ntb_unregister_event_callback(ndev);
 253         ndev->ntb_transport = NULL;
 254 }
 255
 256 /**
 257  * ntb_write_local_spad() - write to the secondary scratchpad register
 258  * @ndev: pointer to ntb_device instance
 259  * @idx: index to the scratchpad register, 0 based
 260  * @val: the data value to put into the register
 261  *
 262  * This function allows writing of a 32bit value to the indexed scratchpad
 263  * register. This writes over the data mirrored to the local scratchpad register
 264  * by the remote system.
 265  *
 266  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 267  */
 268 int ntb_write_local_spad(struct ntb_device *ndev, unsigned int idx, u32 val)
 269 {
 270         if (idx >= ndev->limits.max_spads)
 271                 return -EINVAL;
 272
 273         dev_dbg(&ndev->pdev->dev, "Writing %x to local scratch pad index %d\n",
 274                 val, idx);
 275         writel(val, ndev->reg_ofs.spad_read + idx * 4);
 276
 277         return 0;
 278 }
 279
 280 /**
 281  * ntb_read_local_spad() - read from the primary scratchpad register
 282  * @ndev: pointer to ntb_device instance
 283  * @idx: index to scratchpad register, 0 based
 284  * @val: pointer to 32bit integer for storing the register value
 285  *
 286  * This function allows reading of the 32bit scratchpad register on
 287  * the primary (internal) side.  This allows the local system to read data
 288  * written and mirrored to the scratchpad register by the remote system.
 289  *
 290  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 291  */
 292 int ntb_read_local_spad(struct ntb_device *ndev, unsigned int idx, u32 *val)
 293 {
 294         if (idx >= ndev->limits.max_spads)
 295                 return -EINVAL;
 296
 297         *val = readl(ndev->reg_ofs.spad_write + idx * 4);
 298         dev_dbg(&ndev->pdev->dev,
 299                 "Reading %x from local scratch pad index %d\n", *val, idx);
 300
 301         return 0;
 302 }
 303
 304 /**
 305  * ntb_write_remote_spad() - write to the secondary scratchpad register
 306  * @ndev: pointer to ntb_device instance
 307  * @idx: index to the scratchpad register, 0 based
 308  * @val: the data value to put into the register
 309  *
 310  * This function allows writing of a 32bit value to the indexed scratchpad
 311  * register. The register resides on the secondary (external) side.  This allows
 312  * the local system to write data to be mirrored to the remote systems
 313  * scratchpad register.
 314  *
 315  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 316  */
 317 int ntb_write_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 val)
 318 {
 319         if (idx >= ndev->limits.max_spads)
 320                 return -EINVAL;
 321
 322         dev_dbg(&ndev->pdev->dev, "Writing %x to remote scratch pad index %d\n",
 323                 val, idx);
 324         writel(val, ndev->reg_ofs.spad_write + idx * 4);
 325
 326         return 0;
 327 }
 328
 329 /**
 330  * ntb_read_remote_spad() - read from the primary scratchpad register
 331  * @ndev: pointer to ntb_device instance
 332  * @idx: index to scratchpad register, 0 based
 333  * @val: pointer to 32bit integer for storing the register value
 334  *
 335  * This function allows reading of the 32bit scratchpad register on
 336  * the primary (internal) side.  This alloows the local system to read the data
 337  * it wrote to be mirrored on the remote system.
 338  *
 339  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 340  */
 341 int ntb_read_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 *val)
 342 {
 343         if (idx >= ndev->limits.max_spads)
 344                 return -EINVAL;
 345
 346         *val = readl(ndev->reg_ofs.spad_read + idx * 4);
 347         dev_dbg(&ndev->pdev->dev,
 348                 "Reading %x from remote scratch pad index %d\n", *val, idx);
 349
 350         return 0;
 351 }
 352
 353 /**
 354  * ntb_get_mw_base() - get addr for the NTB memory window
 355  * @ndev: pointer to ntb_device instance
 356  * @mw: memory window number
 357  *
 358  * This function provides the base address of the memory window specified.
 359  *
 360  * RETURNS: address, or NULL on error.
 361  */
 362 resource_size_t ntb_get_mw_base(struct ntb_device *ndev, unsigned int mw)
 363 {
 364         if (mw >= ntb_max_mw(ndev))
 365                 return 0;
 366
 367         return pci_resource_start(ndev->pdev, MW_TO_BAR(mw));
 368 }
 369
 370 /**
 371  * ntb_get_mw_vbase() - get virtual addr for the NTB memory window
 372  * @ndev: pointer to ntb_device instance
 373  * @mw: memory window number
 374  *
 375  * This function provides the base virtual address of the memory window
 376  * specified.
 377  *
 378  * RETURNS: pointer to virtual address, or NULL on error.
 379  */
 380 void __iomem *ntb_get_mw_vbase(struct ntb_device *ndev, unsigned int mw)
 381 {
 382         if (mw >= ntb_max_mw(ndev))
 383                 return NULL;
 384
 385         return ndev->mw[mw].vbase;
 386 }
 387
 388 /**
 389  * ntb_get_mw_size() - return size of NTB memory window
 390  * @ndev: pointer to ntb_device instance
 391  * @mw: memory window number
 392  *
 393  * This function provides the physical size of the memory window specified
 394  *
 395  * RETURNS: the size of the memory window or zero on error
 396  */
 397 u64 ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw)
 398 {
 399         if (mw >= ntb_max_mw(ndev))
 400                 return 0;
 401
 402         return ndev->mw[mw].bar_sz;
 403 }
 404
 405 /**
 406  * ntb_set_mw_addr - set the memory window address
 407  * @ndev: pointer to ntb_device instance
 408  * @mw: memory window number
 409  * @addr: base address for data
 410  *
 411  * This function sets the base physical address of the memory window.  This
 412  * memory address is where data from the remote system will be transfered into
 413  * or out of depending on how the transport is configured.
 414  */
 415 void ntb_set_mw_addr(struct ntb_device *ndev, unsigned int mw, u64 addr)
 416 {
 417         if (mw >= ntb_max_mw(ndev))
 418                 return;
 419
 420         dev_dbg(&ndev->pdev->dev, "Writing addr %Lx to BAR %d\n", addr,
 421                 MW_TO_BAR(mw));
 422
 423         ndev->mw[mw].phys_addr = addr;
 424
 425         switch (MW_TO_BAR(mw)) {
 426         case NTB_BAR_23:
 427                 writeq(addr, ndev->reg_ofs.bar2_xlat);
 428                 break;
 429         case NTB_BAR_45:
 430                 writeq(addr, ndev->reg_ofs.bar4_xlat);
 431                 break;
 432         }
 433 }
 434
 435 /**
 436  * ntb_ring_doorbell() - Set the doorbell on the secondary/external side
 437  * @ndev: pointer to ntb_device instance
 438  * @db: doorbell to ring
 439  *
 440  * This function allows triggering of a doorbell on the secondary/external
 441  * side that will initiate an interrupt on the remote host
 442  *
 443  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 444  */
 445 void ntb_ring_doorbell(struct ntb_device *ndev, unsigned int db)
 446 {
 447         dev_dbg(&ndev->pdev->dev, "%s: ringing doorbell %d\n", __func__, db);
 448
 449         if (ndev->hw_type == BWD_HW)
 450                 writeq((u64) 1 << db, ndev->reg_ofs.rdb);
 451         else
 452                 writew(((1 << ndev->bits_per_vector) - 1) <<
 453                        (db * ndev->bits_per_vector), ndev->reg_ofs.rdb);
 454 }
 455
 456 static void bwd_recover_link(struct ntb_device *ndev)
 457 {
 458         u32 status;
 459
 460         /* Driver resets the NTB ModPhy lanes - magic! */
 461         writeb(0xe0, ndev->reg_base + BWD_MODPHY_PCSREG6);
 462         writeb(0x40, ndev->reg_base + BWD_MODPHY_PCSREG4);
 463         writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG4);
 464         writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG6);
 465
 466         /* Driver waits 100ms to allow the NTB ModPhy to settle */
 467         msleep(100);
 468
 469         /* Clear AER Errors, write to clear */
 470         status = readl(ndev->reg_base + BWD_ERRCORSTS_OFFSET);
 471         dev_dbg(&ndev->pdev->dev, "ERRCORSTS = %x\n", status);
 472         status &= PCI_ERR_COR_REP_ROLL;
 473         writel(status, ndev->reg_base + BWD_ERRCORSTS_OFFSET);
 474
 475         /* Clear unexpected electrical idle event in LTSSM, write to clear */
 476         status = readl(ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET);
 477         dev_dbg(&ndev->pdev->dev, "LTSSMERRSTS0 = %x\n", status);
 478         status |= BWD_LTSSMERRSTS0_UNEXPECTEDEI;
 479         writel(status, ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET);
 480
 481         /* Clear DeSkew Buffer error, write to clear */
 482         status = readl(ndev->reg_base + BWD_DESKEWSTS_OFFSET);
 483         dev_dbg(&ndev->pdev->dev, "DESKEWSTS = %x\n", status);
 484         status |= BWD_DESKEWSTS_DBERR;
 485         writel(status, ndev->reg_base + BWD_DESKEWSTS_OFFSET);
 486
 487         status = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
 488         dev_dbg(&ndev->pdev->dev, "IBSTERRRCRVSTS0 = %x\n", status);
 489         status &= BWD_IBIST_ERR_OFLOW;
 490         writel(status, ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
 491
 492         /* Releases the NTB state machine to allow the link to retrain */
 493         status = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
 494         dev_dbg(&ndev->pdev->dev, "LTSSMSTATEJMP = %x\n", status);
 495         status &= ~BWD_LTSSMSTATEJMP_FORCEDETECT;
 496         writel(status, ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
 497 }
 498
 499 static void ntb_link_event(struct ntb_device *ndev, int link_state)
 500 {
 501         unsigned int event;
 502
 503         if (ndev->link_status == link_state)
 504                 return;
 505
 506         if (link_state == NTB_LINK_UP) {
 507                 u16 status;
 508
 509                 dev_info(&ndev->pdev->dev, "Link Up\n");
 510                 ndev->link_status = NTB_LINK_UP;
 511                 event = NTB_EVENT_HW_LINK_UP;
 512
 513                 if (ndev->hw_type == BWD_HW ||
 514                     ndev->conn_type == NTB_CONN_TRANSPARENT)
 515                         status = readw(ndev->reg_ofs.lnk_stat);
 516                 else {
 517                         int rc = pci_read_config_word(ndev->pdev,
 518                                                       SNB_LINK_STATUS_OFFSET,
 519                                                       &status);
 520                         if (rc)
 521                                 return;
 522                 }
 523
 524                 ndev->link_width = (status & NTB_LINK_WIDTH_MASK) >> 4;
 525                 ndev->link_speed = (status & NTB_LINK_SPEED_MASK);
 526                 dev_info(&ndev->pdev->dev, "Link Width %d, Link Speed %d\n",
 527                          ndev->link_width, ndev->link_speed);
 528         } else {
 529                 dev_info(&ndev->pdev->dev, "Link Down\n");
 530                 ndev->link_status = NTB_LINK_DOWN;
 531                 event = NTB_EVENT_HW_LINK_DOWN;
 532                 /* Don't modify link width/speed, we need it in link recovery */
 533         }
 534
 535         /* notify the upper layer if we have an event change */
 536         if (ndev->event_cb)
 537                 ndev->event_cb(ndev->ntb_transport, event);
 538 }
 539
 540 static int ntb_link_status(struct ntb_device *ndev)
 541 {
 542         int link_state;
 543
 544         if (ndev->hw_type == BWD_HW) {
 545                 u32 ntb_cntl;
 546
 547                 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
 548                 if (ntb_cntl & BWD_CNTL_LINK_DOWN)
 549                         link_state = NTB_LINK_DOWN;
 550                 else
 551                         link_state = NTB_LINK_UP;
 552         } else {
 553                 u16 status;
 554                 int rc;
 555
 556                 rc = pci_read_config_word(ndev->pdev, SNB_LINK_STATUS_OFFSET,
 557                                           &status);
 558                 if (rc)
 559                         return rc;
 560
 561                 if (status & NTB_LINK_STATUS_ACTIVE)
 562                         link_state = NTB_LINK_UP;
 563                 else
 564                         link_state = NTB_LINK_DOWN;
 565         }
 566
 567         ntb_link_event(ndev, link_state);
 568
 569         return 0;
 570 }
 571
 572 static void bwd_link_recovery(struct work_struct *work)
 573 {
 574         struct ntb_device *ndev = container_of(work, struct ntb_device,
 575                                                lr_timer.work);
 576         u32 status32;
 577
 578         bwd_recover_link(ndev);
 579         /* There is a potential race between the 2 NTB devices recovering at the
 580          * same time.  If the times are the same, the link will not recover and
 581          * the driver will be stuck in this loop forever.  Add a random interval
 582          * to the recovery time to prevent this race.
 583          */
 584         msleep(BWD_LINK_RECOVERY_TIME + prandom_u32() % BWD_LINK_RECOVERY_TIME);
 585
 586         status32 = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
 587         if (status32 & BWD_LTSSMSTATEJMP_FORCEDETECT)
 588                 goto retry;
 589
 590         status32 = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
 591         if (status32 & BWD_IBIST_ERR_OFLOW)
 592                 goto retry;
 593
 594         status32 = readl(ndev->reg_ofs.lnk_cntl);
 595         if (!(status32 & BWD_CNTL_LINK_DOWN)) {
 596                 unsigned char speed, width;
 597                 u16 status16;
 598
 599                 status16 = readw(ndev->reg_ofs.lnk_stat);
 600                 width = (status16 & NTB_LINK_WIDTH_MASK) >> 4;
 601                 speed = (status16 & NTB_LINK_SPEED_MASK);
 602                 if (ndev->link_width != width || ndev->link_speed != speed)
 603                         goto retry;
 604         }
 605
 606         schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
 607         return;
 608
 609 retry:
 610         schedule_delayed_work(&ndev->lr_timer, NTB_HB_TIMEOUT);
 611 }
 612
 613 /* BWD doesn't have link status interrupt, poll on that platform */
 614 static void bwd_link_poll(struct work_struct *work)
 615 {
 616         struct ntb_device *ndev = container_of(work, struct ntb_device,
 617                                                hb_timer.work);
 618         unsigned long ts = jiffies;
 619
 620         /* If we haven't gotten an interrupt in a while, check the BWD link
 621          * status bit
 622          */
 623         if (ts > ndev->last_ts + NTB_HB_TIMEOUT) {
 624                 int rc = ntb_link_status(ndev);
 625                 if (rc)
 626                         dev_err(&ndev->pdev->dev,
 627                                 "Error determining link status\n");
 628
 629                 /* Check to see if a link error is the cause of the link down */
 630                 if (ndev->link_status == NTB_LINK_DOWN) {
 631                         u32 status32 = readl(ndev->reg_base +
 632                                              BWD_LTSSMSTATEJMP_OFFSET);
 633                         if (status32 & BWD_LTSSMSTATEJMP_FORCEDETECT) {
 634                                 schedule_delayed_work(&ndev->lr_timer, 0);
 635                                 return;
 636                         }
 637                 }
 638         }
 639
 640         schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
 641 }
 642
 643 static int ntb_xeon_setup(struct ntb_device *ndev)
 644 {
 645         int rc;
 646         u8 val;
 647
 648         ndev->hw_type = SNB_HW;
 649
 650         rc = pci_read_config_byte(ndev->pdev, NTB_PPD_OFFSET, &val);
 651         if (rc)
 652                 return rc;
 653
 654         if (val & SNB_PPD_DEV_TYPE)
 655                 ndev->dev_type = NTB_DEV_USD;
 656         else
 657                 ndev->dev_type = NTB_DEV_DSD;
 658
 659         switch (val & SNB_PPD_CONN_TYPE) {
 660         case NTB_CONN_B2B:
 661                 dev_info(&ndev->pdev->dev, "Conn Type = B2B\n");
 662                 ndev->conn_type = NTB_CONN_B2B;
 663                 ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
 664                 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
 665                 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
 666                 ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
 667                 ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
 668                 ndev->limits.max_spads = SNB_MAX_B2B_SPADS;
 669
 670                 /* There is a Xeon hardware errata related to writes to
 671                  * SDOORBELL or B2BDOORBELL in conjunction with inbound access
 672                  * to NTB MMIO Space, which may hang the system.  To workaround
 673                  * this use the second memory window to access the interrupt and
 674                  * scratch pad registers on the remote system.
 675                  */
 676                 if (xeon_errata_workaround) {
 677                         if (!ndev->mw[1].bar_sz)
 678                                 return -EINVAL;
 679
 680                         ndev->limits.max_mw = SNB_ERRATA_MAX_MW;
 681                         ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
 682                         ndev->reg_ofs.spad_write = ndev->mw[1].vbase +
 683                                                    SNB_SPAD_OFFSET;
 684                         ndev->reg_ofs.rdb = ndev->mw[1].vbase +
 685                                             SNB_PDOORBELL_OFFSET;
 686
 687                         /* Set the Limit register to 4k, the minimum size, to
 688                          * prevent an illegal access
 689                          */
 690                         writeq(ndev->mw[1].bar_sz + 0x1000, ndev->reg_base +
 691                                SNB_PBAR4LMT_OFFSET);
 692                 } else {
 693                         ndev->limits.max_mw = SNB_MAX_MW;
 694
 695                         /* HW Errata on bit 14 of b2bdoorbell register.  Writes
 696                          * will not be mirrored to the remote system.  Shrink
 697                          * the number of bits by one, since bit 14 is the last
 698                          * bit.
 699                          */
 700                         ndev->limits.max_db_bits = SNB_MAX_DB_BITS - 1;
 701                         ndev->reg_ofs.spad_write = ndev->reg_base +
 702                                                    SNB_B2B_SPAD_OFFSET;
 703                         ndev->reg_ofs.rdb = ndev->reg_base +
 704                                             SNB_B2B_DOORBELL_OFFSET;
 705
 706                         /* Disable the Limit register, just incase it is set to
 707                          * something silly
 708                          */
 709                         writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET);
 710                 }
 711
 712                 /* The Xeon errata workaround requires setting SBAR Base
 713                  * addresses to known values, so that the PBAR XLAT can be
 714                  * pointed at SBAR0 of the remote system.
 715                  */
 716                 if (ndev->dev_type == NTB_DEV_USD) {
 717                         writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
 718                                SNB_PBAR2XLAT_OFFSET);
 719                         if (xeon_errata_workaround)
 720                                 writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
 721                                        SNB_PBAR4XLAT_OFFSET);
 722                         else {
 723                                 writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
 724                                        SNB_PBAR4XLAT_OFFSET);
 725                                 /* B2B_XLAT_OFFSET is a 64bit register, but can
 726                                  * only take 32bit writes
 727                                  */
 728                                 writel(SNB_MBAR01_DSD_ADDR & 0xffffffff,
 729                                        ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
 730                                 writel(SNB_MBAR01_DSD_ADDR >> 32,
 731                                        ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
 732                         }
 733
 734                         writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
 735                                SNB_SBAR0BASE_OFFSET);
 736                         writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
 737                                SNB_SBAR2BASE_OFFSET);
 738                         writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
 739                                SNB_SBAR4BASE_OFFSET);
 740                 } else {
 741                         writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
 742                                SNB_PBAR2XLAT_OFFSET);
 743                         if (xeon_errata_workaround)
 744                                 writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
 745                                        SNB_PBAR4XLAT_OFFSET);
 746                         else {
 747                                 writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
 748                                        SNB_PBAR4XLAT_OFFSET);
 749                                 /* B2B_XLAT_OFFSET is a 64bit register, but can
 750                                  * only take 32bit writes
 751                                  */
 752                                 writel(SNB_MBAR01_DSD_ADDR & 0xffffffff,
 753                                        ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
 754                                 writel(SNB_MBAR01_USD_ADDR >> 32,
 755                                        ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
 756                         }
 757                         writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
 758                                SNB_SBAR0BASE_OFFSET);
 759                         writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
 760                                SNB_SBAR2BASE_OFFSET);
 761                         writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
 762                                SNB_SBAR4BASE_OFFSET);
 763                 }
 764                 break;
 765         case NTB_CONN_RP:
 766                 dev_info(&ndev->pdev->dev, "Conn Type = RP\n");
 767                 ndev->conn_type = NTB_CONN_RP;
 768
 769                 if (xeon_errata_workaround) {
 770                         dev_err(&ndev->pdev->dev,
 771                                 "NTB-RP disabled due to hardware errata.  To disregard this warning and potentially lock-up the system, add the parameter 'xeon_errata_workaround=0'.\n");
 772                         return -EINVAL;
 773                 }
 774
 775                 /* Scratch pads need to have exclusive access from the primary
 776                  * or secondary side.  Halve the num spads so that each side can
 777                  * have an equal amount.
 778                  */
 779                 ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2;
 780                 ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
 781                 /* Note: The SDOORBELL is the cause of the errata.  You REALLY
 782                  * don't want to touch it.
 783                  */
 784                 ndev->reg_ofs.rdb = ndev->reg_base + SNB_SDOORBELL_OFFSET;
 785                 ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
 786                 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
 787                 /* Offset the start of the spads to correspond to whether it is
 788                  * primary or secondary
 789                  */
 790                 ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET +
 791                                            ndev->limits.max_spads * 4;
 792                 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
 793                 ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
 794                 ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
 795                 ndev->limits.max_mw = SNB_MAX_MW;
 796                 break;
 797         case NTB_CONN_TRANSPARENT:
 798                 dev_info(&ndev->pdev->dev, "Conn Type = TRANSPARENT\n");
 799                 ndev->conn_type = NTB_CONN_TRANSPARENT;
 800                 /* Scratch pads need to have exclusive access from the primary
 801                  * or secondary side.  Halve the num spads so that each side can
 802                  * have an equal amount.
 803                  */
 804                 ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2;
 805                 ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
 806                 ndev->reg_ofs.rdb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
 807                 ndev->reg_ofs.ldb = ndev->reg_base + SNB_SDOORBELL_OFFSET;
 808                 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_SDBMSK_OFFSET;
 809                 ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET;
 810                 /* Offset the start of the spads to correspond to whether it is
 811                  * primary or secondary
 812                  */
 813                 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET +
 814                                           ndev->limits.max_spads * 4;
 815                 ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_PBAR2XLAT_OFFSET;
 816                 ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_PBAR4XLAT_OFFSET;
 817
 818                 ndev->limits.max_mw = SNB_MAX_MW;
 819                 break;
 820         default:
 821                 /* Most likely caused by the remote NTB-RP device not being
 822                  * configured
 823                  */
 824                 dev_err(&ndev->pdev->dev, "Unknown PPD %x\n", val);
 825                 return -EINVAL;
 826         }
 827
 828         ndev->reg_ofs.lnk_cntl = ndev->reg_base + SNB_NTBCNTL_OFFSET;
 829         ndev->reg_ofs.lnk_stat = ndev->reg_base + SNB_SLINK_STATUS_OFFSET;
 830         ndev->reg_ofs.spci_cmd = ndev->reg_base + SNB_PCICMD_OFFSET;
 831
 832         ndev->limits.msix_cnt = SNB_MSIX_CNT;
 833         ndev->bits_per_vector = SNB_DB_BITS_PER_VEC;
 834
 835         return 0;
 836 }
 837
 838 static int ntb_bwd_setup(struct ntb_device *ndev)
 839 {
 840         int rc;
 841         u32 val;
 842
 843         ndev->hw_type = BWD_HW;
 844
 845         rc = pci_read_config_dword(ndev->pdev, NTB_PPD_OFFSET, &val);
 846         if (rc)
 847                 return rc;
 848
 849         switch ((val & BWD_PPD_CONN_TYPE) >> 8) {
 850         case NTB_CONN_B2B:
 851                 ndev->conn_type = NTB_CONN_B2B;
 852                 break;
 853         case NTB_CONN_RP:
 854         default:
 855                 dev_err(&ndev->pdev->dev, "Unsupported NTB configuration\n");
 856                 return -EINVAL;
 857         }
 858
 859         if (val & BWD_PPD_DEV_TYPE)
 860                 ndev->dev_type = NTB_DEV_DSD;
 861         else
 862                 ndev->dev_type = NTB_DEV_USD;
 863
 864         /* Initiate PCI-E link training */
 865         rc = pci_write_config_dword(ndev->pdev, NTB_PPD_OFFSET,
 866                                     val | BWD_PPD_INIT_LINK);
 867         if (rc)
 868                 return rc;
 869
 870         ndev->reg_ofs.ldb = ndev->reg_base + BWD_PDOORBELL_OFFSET;
 871         ndev->reg_ofs.ldb_mask = ndev->reg_base + BWD_PDBMSK_OFFSET;
 872         ndev->reg_ofs.rdb = ndev->reg_base + BWD_B2B_DOORBELL_OFFSET;
 873         ndev->reg_ofs.bar2_xlat = ndev->reg_base + BWD_SBAR2XLAT_OFFSET;
 874         ndev->reg_ofs.bar4_xlat = ndev->reg_base + BWD_SBAR4XLAT_OFFSET;
 875         ndev->reg_ofs.lnk_cntl = ndev->reg_base + BWD_NTBCNTL_OFFSET;
 876         ndev->reg_ofs.lnk_stat = ndev->reg_base + BWD_LINK_STATUS_OFFSET;
 877         ndev->reg_ofs.spad_read = ndev->reg_base + BWD_SPAD_OFFSET;
 878         ndev->reg_ofs.spad_write = ndev->reg_base + BWD_B2B_SPAD_OFFSET;
 879         ndev->reg_ofs.spci_cmd = ndev->reg_base + BWD_PCICMD_OFFSET;
 880         ndev->limits.max_mw = BWD_MAX_MW;
 881         ndev->limits.max_spads = BWD_MAX_SPADS;
 882         ndev->limits.max_db_bits = BWD_MAX_DB_BITS;
 883         ndev->limits.msix_cnt = BWD_MSIX_CNT;
 884         ndev->bits_per_vector = BWD_DB_BITS_PER_VEC;
 885
 886         /* Since bwd doesn't have a link interrupt, setup a poll timer */
 887         INIT_DELAYED_WORK(&ndev->hb_timer, bwd_link_poll);
 888         INIT_DELAYED_WORK(&ndev->lr_timer, bwd_link_recovery);
 889         schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
 890
 891         return 0;
 892 }
 893
 894 static int ntb_device_setup(struct ntb_device *ndev)
 895 {
 896         int rc;
 897
 898         switch (ndev->pdev->device) {
 899         case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
 900         case PCI_DEVICE_ID_INTEL_NTB_SS_SNB:
 901         case PCI_DEVICE_ID_INTEL_NTB_SS_IVT:
 902         case PCI_DEVICE_ID_INTEL_NTB_SS_HSX:
 903         case PCI_DEVICE_ID_INTEL_NTB_PS_JSF:
 904         case PCI_DEVICE_ID_INTEL_NTB_PS_SNB:
 905         case PCI_DEVICE_ID_INTEL_NTB_PS_IVT:
 906         case PCI_DEVICE_ID_INTEL_NTB_PS_HSX:
 907         case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:
 908         case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:
 909         case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT:
 910         case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX:
 911                 rc = ntb_xeon_setup(ndev);
 912                 break;
 913         case PCI_DEVICE_ID_INTEL_NTB_B2B_BWD:
 914                 rc = ntb_bwd_setup(ndev);
 915                 break;
 916         default:
 917                 rc = -ENODEV;
 918         }
 919
 920         if (rc)
 921                 return rc;
 922
 923         dev_info(&ndev->pdev->dev, "Device Type = %s\n",
 924                  ndev->dev_type == NTB_DEV_USD ? "USD/DSP" : "DSD/USP");
 925
 926         if (ndev->conn_type == NTB_CONN_B2B)
 927                 /* Enable Bus Master and Memory Space on the secondary side */
 928                 writew(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
 929                        ndev->reg_ofs.spci_cmd);
 930
 931         return 0;
 932 }
 933
 934 static void ntb_device_free(struct ntb_device *ndev)
 935 {
 936         if (ndev->hw_type == BWD_HW) {
 937                 cancel_delayed_work_sync(&ndev->hb_timer);
 938                 cancel_delayed_work_sync(&ndev->lr_timer);
 939         }
 940 }
 941
 942 static irqreturn_t bwd_callback_msix_irq(int irq, void *data)
 943 {
 944         struct ntb_db_cb *db_cb = data;
 945         struct ntb_device *ndev = db_cb->ndev;
 946
 947         dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
 948                 db_cb->db_num);
 949
 950         if (db_cb->callback)
 951                 db_cb->callback(db_cb->data, db_cb->db_num);
 952
 953         /* No need to check for the specific HB irq, any interrupt means
 954          * we're connected.
 955          */
 956         ndev->last_ts = jiffies;
 957
 958         writeq((u64) 1 << db_cb->db_num, ndev->reg_ofs.ldb);
 959
 960         return IRQ_HANDLED;
 961 }
 962
 963 static irqreturn_t xeon_callback_msix_irq(int irq, void *data)
 964 {
 965         struct ntb_db_cb *db_cb = data;
 966         struct ntb_device *ndev = db_cb->ndev;
 967
 968         dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
 969                 db_cb->db_num);
 970
 971         if (db_cb->callback)
 972                 db_cb->callback(db_cb->data, db_cb->db_num);
 973
 974         /* On Sandybridge, there are 16 bits in the interrupt register
 975          * but only 4 vectors.  So, 5 bits are assigned to the first 3
 976          * vectors, with the 4th having a single bit for link
 977          * interrupts.
 978          */
 979         writew(((1 << ndev->bits_per_vector) - 1) <<
 980                (db_cb->db_num * ndev->bits_per_vector), ndev->reg_ofs.ldb);
 981
 982         return IRQ_HANDLED;
 983 }
 984
 985 /* Since we do not have a HW doorbell in BWD, this is only used in JF/JT */
 986 static irqreturn_t xeon_event_msix_irq(int irq, void *dev)
 987 {
 988         struct ntb_device *ndev = dev;
 989         int rc;
 990
 991         dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for Events\n", irq);
 992
 993         rc = ntb_link_status(ndev);
 994         if (rc)
 995                 dev_err(&ndev->pdev->dev, "Error determining link status\n");
 996
 997         /* bit 15 is always the link bit */
 998         writew(1 << SNB_LINK_DB, ndev->reg_ofs.ldb);
 999
1000         return IRQ_HANDLED;
1001 }
1002
1003 static irqreturn_t ntb_interrupt(int irq, void *dev)
1004 {
1005         struct ntb_device *ndev = dev;
1006         unsigned int i = 0;
1007
1008         if (ndev->hw_type == BWD_HW) {
1009                 u64 ldb = readq(ndev->reg_ofs.ldb);
1010
1011                 dev_dbg(&ndev->pdev->dev, "irq %d - ldb = %Lx\n", irq, ldb);
1012
1013                 while (ldb) {
1014                         i = __ffs(ldb);
1015                         ldb &= ldb - 1;
1016                         bwd_callback_msix_irq(irq, &ndev->db_cb[i]);
1017                 }
1018         } else {
1019                 u16 ldb = readw(ndev->reg_ofs.ldb);
1020
1021                 dev_dbg(&ndev->pdev->dev, "irq %d - ldb = %x\n", irq, ldb);
1022
1023                 if (ldb & SNB_DB_HW_LINK) {
1024                         xeon_event_msix_irq(irq, dev);
1025                         ldb &= ~SNB_DB_HW_LINK;
1026                 }
1027
1028                 while (ldb) {
1029                         i = __ffs(ldb);
1030                         ldb &= ldb - 1;
1031                         xeon_callback_msix_irq(irq, &ndev->db_cb[i]);
1032                 }
1033         }
1034
1035         return IRQ_HANDLED;
1036 }
1037
1038 static int ntb_setup_msix(struct ntb_device *ndev)
1039 {
1040         struct pci_dev *pdev = ndev->pdev;
1041         struct msix_entry *msix;
1042         int msix_entries;
1043         int rc, i;
1044         u16 val;
1045
1046         if (!pdev->msix_cap) {
1047                 rc = -EIO;
1048                 goto err;
1049         }
1050
1051         rc = pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &val);
1052         if (rc)
1053                 goto err;
1054
1055         msix_entries = msix_table_size(val);
1056         if (msix_entries > ndev->limits.msix_cnt) {
1057                 rc = -EINVAL;
1058                 goto err;
1059         }
1060
1061         ndev->msix_entries = kmalloc(sizeof(struct msix_entry) * msix_entries,
1062                                      GFP_KERNEL);
1063         if (!ndev->msix_entries) {
1064                 rc = -ENOMEM;
1065                 goto err;
1066         }
1067
1068         for (i = 0; i < msix_entries; i++)
1069                 ndev->msix_entries[i].entry = i;
1070
1071         rc = pci_enable_msix(pdev, ndev->msix_entries, msix_entries);
1072         if (rc < 0)
1073                 goto err1;
1074         if (rc > 0) {
1075                 /* On SNB, the link interrupt is always tied to 4th vector.  If
1076                  * we can't get all 4, then we can't use MSI-X.
1077                  */
1078                 if (ndev->hw_type != BWD_HW) {
1079                         rc = -EIO;
1080                         goto err1;
1081                 }
1082
1083                 dev_warn(&pdev->dev,
1084                          "Only %d MSI-X vectors.  Limiting the number of queues to that number.\n",
1085                          rc);
1086                 msix_entries = rc;
1087
1088                 rc = pci_enable_msix(pdev, ndev->msix_entries, msix_entries);
1089                 if (rc)
1090                         goto err1;
1091         }
1092
1093         for (i = 0; i < msix_entries; i++) {
1094                 msix = &ndev->msix_entries[i];
1095                 WARN_ON(!msix->vector);
1096
1097                 /* Use the last MSI-X vector for Link status */
1098                 if (ndev->hw_type == BWD_HW) {
1099                         rc = request_irq(msix->vector, bwd_callback_msix_irq, 0,
1100                                          "ntb-callback-msix", &ndev->db_cb[i]);
1101                         if (rc)
1102                                 goto err2;
1103                 } else {
1104                         if (i == msix_entries - 1) {
1105                                 rc = request_irq(msix->vector,
1106                                                  xeon_event_msix_irq, 0,
1107                                                  "ntb-event-msix", ndev);
1108                                 if (rc)
1109                                         goto err2;
1110                         } else {
1111                                 rc = request_irq(msix->vector,
1112                                                  xeon_callback_msix_irq, 0,
1113                                                  "ntb-callback-msix",
1114                                                  &ndev->db_cb[i]);
1115                                 if (rc)
1116                                         goto err2;
1117                         }
1118                 }
1119         }
1120
1121         ndev->num_msix = msix_entries;
1122         if (ndev->hw_type == BWD_HW)
1123                 ndev->max_cbs = msix_entries;
1124         else
1125                 ndev->max_cbs = msix_entries - 1;
1126
1127         return 0;
1128
1129 err2:
1130         while (--i >= 0) {
1131                 msix = &ndev->msix_entries[i];
1132                 if (ndev->hw_type != BWD_HW && i == ndev->num_msix - 1)
1133                         free_irq(msix->vector, ndev);
1134                 else
1135                         free_irq(msix->vector, &ndev->db_cb[i]);
1136         }
1137         pci_disable_msix(pdev);
1138 err1:
1139         kfree(ndev->msix_entries);
1140         dev_err(&pdev->dev, "Error allocating MSI-X interrupt\n");
1141 err:
1142         ndev->num_msix = 0;
1143         return rc;
1144 }
1145
1146 static int ntb_setup_msi(struct ntb_device *ndev)
1147 {
1148         struct pci_dev *pdev = ndev->pdev;
1149         int rc;
1150
1151         rc = pci_enable_msi(pdev);
1152         if (rc)
1153                 return rc;
1154
1155         rc = request_irq(pdev->irq, ntb_interrupt, 0, "ntb-msi", ndev);
1156         if (rc) {
1157                 pci_disable_msi(pdev);
1158                 dev_err(&pdev->dev, "Error allocating MSI interrupt\n");
1159                 return rc;
1160         }
1161
1162         return 0;
1163 }
1164
1165 static int ntb_setup_intx(struct ntb_device *ndev)
1166 {
1167         struct pci_dev *pdev = ndev->pdev;
1168         int rc;
1169
1170         pci_msi_off(pdev);
1171
1172         /* Verify intx is enabled */
1173         pci_intx(pdev, 1);
1174
1175         rc = request_irq(pdev->irq, ntb_interrupt, IRQF_SHARED, "ntb-intx",
1176                          ndev);
1177         if (rc)
1178                 return rc;
1179
1180         return 0;
1181 }
1182
1183 static int ntb_setup_interrupts(struct ntb_device *ndev)
1184 {
1185         int rc;
1186
1187         /* On BWD, disable all interrupts.  On SNB, disable all but Link
1188          * Interrupt.  The rest will be unmasked as callbacks are registered.
1189          */
1190         if (ndev->hw_type == BWD_HW)
1191                 writeq(~0, ndev->reg_ofs.ldb_mask);
1192         else {
1193                 u16 var = 1 << SNB_LINK_DB;
1194                 writew(~var, ndev->reg_ofs.ldb_mask);
1195         }
1196
1197         rc = ntb_setup_msix(ndev);
1198         if (!rc)
1199                 goto done;
1200
1201         ndev->bits_per_vector = 1;
1202         ndev->max_cbs = ndev->limits.max_db_bits;
1203
1204         rc = ntb_setup_msi(ndev);
1205         if (!rc)
1206                 goto done;
1207
1208         rc = ntb_setup_intx(ndev);
1209         if (rc) {
1210                 dev_err(&ndev->pdev->dev, "no usable interrupts\n");
1211                 return rc;
1212         }
1213
1214 done:
1215         return 0;
1216 }
1217
1218 static void ntb_free_interrupts(struct ntb_device *ndev)
1219 {
1220         struct pci_dev *pdev = ndev->pdev;
1221
1222         /* mask interrupts */
1223         if (ndev->hw_type == BWD_HW)
1224                 writeq(~0, ndev->reg_ofs.ldb_mask);
1225         else
1226                 writew(~0, ndev->reg_ofs.ldb_mask);
1227
1228         if (ndev->num_msix) {
1229                 struct msix_entry *msix;
1230                 u32 i;
1231
1232                 for (i = 0; i < ndev->num_msix; i++) {
1233                         msix = &ndev->msix_entries[i];
1234                         if (ndev->hw_type != BWD_HW && i == ndev->num_msix - 1)
1235                                 free_irq(msix->vector, ndev);
1236                         else
1237                                 free_irq(msix->vector, &ndev->db_cb[i]);
1238                 }
1239                 pci_disable_msix(pdev);
1240         } else {
1241                 free_irq(pdev->irq, ndev);
1242
1243                 if (pci_dev_msi_enabled(pdev))
1244                         pci_disable_msi(pdev);
1245         }
1246 }
1247
1248 static int ntb_create_callbacks(struct ntb_device *ndev)
1249 {
1250         int i;
1251
1252         /* Chicken-egg issue.  We won't know how many callbacks are necessary
1253          * until we see how many MSI-X vectors we get, but these pointers need
1254          * to be passed into the MSI-X register function.  So, we allocate the
1255          * max, knowing that they might not all be used, to work around this.
1256          */
1257         ndev->db_cb = kcalloc(ndev->limits.max_db_bits,
1258                               sizeof(struct ntb_db_cb),
1259                               GFP_KERNEL);
1260         if (!ndev->db_cb)
1261                 return -ENOMEM;
1262
1263         for (i = 0; i < ndev->limits.max_db_bits; i++) {
1264                 ndev->db_cb[i].db_num = i;
1265                 ndev->db_cb[i].ndev = ndev;
1266         }
1267
1268         return 0;
1269 }
1270
1271 static void ntb_free_callbacks(struct ntb_device *ndev)
1272 {
1273         int i;
1274
1275         for (i = 0; i < ndev->limits.max_db_bits; i++)
1276                 ntb_unregister_db_callback(ndev, i);
1277
1278         kfree(ndev->db_cb);
1279 }
1280
1281 static void ntb_setup_debugfs(struct ntb_device *ndev)
1282 {
1283         if (!debugfs_initialized())
1284                 return;
1285
1286         if (!debugfs_dir)
1287                 debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL);
1288
1289         ndev->debugfs_dir = debugfs_create_dir(pci_name(ndev->pdev),
1290                                                debugfs_dir);
1291 }
1292
1293 static void ntb_free_debugfs(struct ntb_device *ndev)
1294 {
1295         debugfs_remove_recursive(ndev->debugfs_dir);
1296
1297         if (debugfs_dir && simple_empty(debugfs_dir)) {
1298                 debugfs_remove_recursive(debugfs_dir);
1299                 debugfs_dir = NULL;
1300         }
1301 }
1302
1303 static void ntb_hw_link_up(struct ntb_device *ndev)
1304 {
1305         if (ndev->conn_type == NTB_CONN_TRANSPARENT)
1306                 ntb_link_event(ndev, NTB_LINK_UP);
1307         else
1308                 /* Let's bring the NTB link up */
1309                 writel(NTB_CNTL_BAR23_SNOOP | NTB_CNTL_BAR45_SNOOP,
1310                        ndev->reg_ofs.lnk_cntl);
1311 }
1312
1313 static void ntb_hw_link_down(struct ntb_device *ndev)
1314 {
1315         u32 ntb_cntl;
1316
1317         if (ndev->conn_type == NTB_CONN_TRANSPARENT) {
1318                 ntb_link_event(ndev, NTB_LINK_DOWN);
1319                 return;
1320         }
1321
1322         /* Bring NTB link down */
1323         ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
1324         ntb_cntl &= ~(NTB_CNTL_BAR23_SNOOP | NTB_CNTL_BAR45_SNOOP);
1325         ntb_cntl |= NTB_CNTL_LINK_DISABLE;
1326         writel(ntb_cntl, ndev->reg_ofs.lnk_cntl);
1327 }
1328
1329 static int ntb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1330 {
1331         struct ntb_device *ndev;
1332         int rc, i;
1333
1334         ndev = kzalloc(sizeof(struct ntb_device), GFP_KERNEL);
1335         if (!ndev)
1336                 return -ENOMEM;
1337
1338         ndev->pdev = pdev;
1339         ndev->link_status = NTB_LINK_DOWN;
1340         pci_set_drvdata(pdev, ndev);
1341         ntb_setup_debugfs(ndev);
1342
1343         rc = pci_enable_device(pdev);
1344         if (rc)
1345                 goto err;
1346
1347         pci_set_master(ndev->pdev);
1348
1349         rc = pci_request_selected_regions(pdev, NTB_BAR_MASK, KBUILD_MODNAME);
1350         if (rc)
1351                 goto err1;
1352
1353         ndev->reg_base = pci_ioremap_bar(pdev, NTB_BAR_MMIO);
1354         if (!ndev->reg_base) {
1355                 dev_warn(&pdev->dev, "Cannot remap BAR 0\n");
1356                 rc = -EIO;
1357                 goto err2;
1358         }
1359
1360         for (i = 0; i < NTB_MAX_NUM_MW; i++) {
1361                 ndev->mw[i].bar_sz = pci_resource_len(pdev, MW_TO_BAR(i));
1362                 ndev->mw[i].vbase =
1363                     ioremap_wc(pci_resource_start(pdev, MW_TO_BAR(i)),
1364                                ndev->mw[i].bar_sz);
1365                 dev_info(&pdev->dev, "MW %d size %llu\n", i,
1366                          (unsigned long long) ndev->mw[i].bar_sz);
1367                 if (!ndev->mw[i].vbase) {
1368                         dev_warn(&pdev->dev, "Cannot remap BAR %d\n",
1369                                  MW_TO_BAR(i));
1370                         rc = -EIO;
1371                         goto err3;
1372                 }
1373         }
1374
1375         rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1376         if (rc) {
1377                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1378                 if (rc)
1379                         goto err3;
1380
1381                 dev_warn(&pdev->dev, "Cannot DMA highmem\n");
1382         }
1383
1384         rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1385         if (rc) {
1386                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1387                 if (rc)
1388                         goto err3;
1389
1390                 dev_warn(&pdev->dev, "Cannot DMA consistent highmem\n");
1391         }
1392
1393         rc = ntb_device_setup(ndev);
1394         if (rc)
1395                 goto err3;
1396
1397         rc = ntb_create_callbacks(ndev);
1398         if (rc)
1399                 goto err4;
1400
1401         rc = ntb_setup_interrupts(ndev);
1402         if (rc)
1403                 goto err5;
1404
1405         /* The scratchpad registers keep the values between rmmod/insmod,
1406          * blast them now
1407          */
1408         for (i = 0; i < ndev->limits.max_spads; i++) {
1409                 ntb_write_local_spad(ndev, i, 0);
1410                 ntb_write_remote_spad(ndev, i, 0);
1411         }
1412
1413         rc = ntb_transport_init(pdev);
1414         if (rc)
1415                 goto err6;
1416
1417         ntb_hw_link_up(ndev);
1418
1419         return 0;
1420
1421 err6:
1422         ntb_free_interrupts(ndev);
1423 err5:
1424         ntb_free_callbacks(ndev);
1425 err4:
1426         ntb_device_free(ndev);
1427 err3:
1428         for (i--; i >= 0; i--)
1429                 iounmap(ndev->mw[i].vbase);
1430         iounmap(ndev->reg_base);
1431 err2:
1432         pci_release_selected_regions(pdev, NTB_BAR_MASK);
1433 err1:
1434         pci_disable_device(pdev);
1435 err:
1436         ntb_free_debugfs(ndev);
1437         kfree(ndev);
1438
1439         dev_err(&pdev->dev, "Error loading %s module\n", KBUILD_MODNAME);
1440         return rc;
1441 }
1442
1443 static void ntb_pci_remove(struct pci_dev *pdev)
1444 {
1445         struct ntb_device *ndev = pci_get_drvdata(pdev);
1446         int i;
1447
1448         ntb_hw_link_down(ndev);
1449
1450         ntb_transport_free(ndev->ntb_transport);
1451
1452         ntb_free_interrupts(ndev);
1453         ntb_free_callbacks(ndev);
1454         ntb_device_free(ndev);
1455
1456         for (i = 0; i < NTB_MAX_NUM_MW; i++)
1457                 iounmap(ndev->mw[i].vbase);
1458
1459         iounmap(ndev->reg_base);
1460         pci_release_selected_regions(pdev, NTB_BAR_MASK);
1461         pci_disable_device(pdev);
1462         ntb_free_debugfs(ndev);
1463         kfree(ndev);
1464 }
1465
1466 static struct pci_driver ntb_pci_driver = {
1467         .name = KBUILD_MODNAME,
1468         .id_table = ntb_pci_tbl,
1469         .probe = ntb_pci_probe,
1470         .remove = ntb_pci_remove,
1471 };
1472 module_pci_driver(ntb_pci_driver);