2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
23 #include <linux/firmware.h>
35 #define ATHEROS_VENDOR_ID 0x168c
37 #define AR5416_DEVID_PCI 0x0023
38 #define AR5416_DEVID_PCIE 0x0024
39 #define AR9160_DEVID_PCI 0x0027
40 #define AR9280_DEVID_PCI 0x0029
41 #define AR9280_DEVID_PCIE 0x002a
42 #define AR9285_DEVID_PCIE 0x002b
43 #define AR2427_DEVID_PCIE 0x002c
44 #define AR9287_DEVID_PCI 0x002d
45 #define AR9287_DEVID_PCIE 0x002e
46 #define AR9300_DEVID_PCIE 0x0030
47 #define AR9300_DEVID_AR9340 0x0031
48 #define AR9300_DEVID_AR9485_PCIE 0x0032
49 #define AR9300_DEVID_AR9580 0x0033
50 #define AR9300_DEVID_AR9462 0x0034
51 #define AR9300_DEVID_AR9330 0x0035
52 #define AR9300_DEVID_QCA955X 0x0038
53 #define AR9485_DEVID_AR1111 0x0037
54 #define AR9300_DEVID_AR9565 0x0036
56 #define AR5416_AR9100_DEVID 0x000b
58 #define AR_SUBVENDOR_ID_NOG 0x0e11
59 #define AR_SUBVENDOR_ID_NEW_A 0x7065
60 #define AR5416_MAGIC 0x19641014
62 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
63 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
64 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
66 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
68 #define ATH_DEFAULT_NOISE_FLOOR -95
70 #define ATH9K_RSSI_BAD -128
72 #define ATH9K_NUM_CHANNELS 38
74 /* Register read/write primitives */
75 #define REG_WRITE(_ah, _reg, _val) \
76 (_ah)->reg_ops.write((_ah), (_val), (_reg))
78 #define REG_READ(_ah, _reg) \
79 (_ah)->reg_ops.read((_ah), (_reg))
81 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
82 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
84 #define REG_RMW(_ah, _reg, _set, _clr) \
85 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
87 #define ENABLE_REGWRITE_BUFFER(_ah) \
89 if ((_ah)->reg_ops.enable_write_buffer) \
90 (_ah)->reg_ops.enable_write_buffer((_ah)); \
93 #define REGWRITE_BUFFER_FLUSH(_ah) \
95 if ((_ah)->reg_ops.write_flush) \
96 (_ah)->reg_ops.write_flush((_ah)); \
99 #define PR_EEP(_s, _val) \
101 len += scnprintf(buf + len, size - len, "%20s : %10d\n",\
105 #define SM(_v, _f) (((_v) << _f##_S) & _f)
106 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
107 #define REG_RMW_FIELD(_a, _r, _f, _v) \
108 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
109 #define REG_READ_FIELD(_a, _r, _f) \
110 (((REG_READ(_a, _r) & _f) >> _f##_S))
111 #define REG_SET_BIT(_a, _r, _f) \
112 REG_RMW(_a, _r, (_f), 0)
113 #define REG_CLR_BIT(_a, _r, _f) \
114 REG_RMW(_a, _r, 0, (_f))
116 #define DO_DELAY(x) do { \
117 if (((++(x) % 64) == 0) && \
118 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
123 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
124 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
126 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
127 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
128 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
129 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
130 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
131 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
132 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
133 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
134 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
135 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
136 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
137 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
138 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
139 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9
140 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8
141 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
142 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
144 #define AR_GPIOD_MASK 0x00001FFF
145 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
147 #define BASE_ACTIVATE_DELAY 100
148 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
149 #define COEF_SCALE_S 24
150 #define HT40_CHANNEL_CENTER_SHIFT 10
152 #define ATH9K_ANTENNA0_CHAINMASK 0x1
153 #define ATH9K_ANTENNA1_CHAINMASK 0x2
155 #define ATH9K_NUM_DMA_DEBUG_REGS 8
156 #define ATH9K_NUM_QUEUES 10
158 #define MAX_RATE_POWER 63
159 #define AH_WAIT_TIMEOUT 100000 /* (us) */
160 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
161 #define AH_TIME_QUANTUM 10
162 #define AR_KEYTABLE_SIZE 128
163 #define POWER_UP_TIME 10000
164 #define SPUR_RSSI_THRESH 40
165 #define UPPER_5G_SUB_BAND_START 5700
166 #define MID_5G_SUB_BAND_START 5400
168 #define CAB_TIMEOUT_VAL 10
169 #define BEACON_TIMEOUT_VAL 10
170 #define MIN_BEACON_TIMEOUT_VAL 1
173 #define INIT_CONFIG_STATUS 0x00000000
174 #define INIT_RSSI_THR 0x00000700
175 #define INIT_BCON_CNTRL_REG 0x00000000
177 #define TU_TO_USEC(_tu) ((_tu) << 10)
179 #define ATH9K_HW_RX_HP_QDEPTH 16
180 #define ATH9K_HW_RX_LP_QDEPTH 128
182 #define PAPRD_GAIN_TABLE_ENTRIES 32
183 #define PAPRD_TABLE_SZ 24
184 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
190 /* Keep Alive Frame */
191 #define KAL_FRAME_LEN 28
192 #define KAL_FRAME_TYPE 0x2 /* data frame */
193 #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */
194 #define KAL_DURATION_ID 0x3d
195 #define KAL_NUM_DATA_WORDS 6
196 #define KAL_NUM_DESC_WORDS 12
197 #define KAL_ANTENNA_MODE 1
199 #define KAL_DELAY 4 /*delay of 4ms between 2 KAL frames */
200 #define KAL_TIMEOUT 900
202 #define MAX_PATTERN_SIZE 256
203 #define MAX_PATTERN_MASK_SIZE 32
204 #define MAX_NUM_PATTERN 8
205 #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and
206 deauthenticate packets */
209 * WoW trigger mapping to hardware code
212 #define AH_WOW_USER_PATTERN_EN BIT(0)
213 #define AH_WOW_MAGIC_PATTERN_EN BIT(1)
214 #define AH_WOW_LINK_CHANGE BIT(2)
215 #define AH_WOW_BEACON_MISS BIT(3)
217 enum ath_hw_txq_subtype {
224 enum ath_ini_subsys {
232 ATH9K_HW_CAP_HT = BIT(0),
233 ATH9K_HW_CAP_RFSILENT = BIT(1),
234 ATH9K_HW_CAP_AUTOSLEEP = BIT(2),
235 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3),
236 ATH9K_HW_CAP_EDMA = BIT(4),
237 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5),
238 ATH9K_HW_CAP_LDPC = BIT(6),
239 ATH9K_HW_CAP_FASTCLOCK = BIT(7),
240 ATH9K_HW_CAP_SGI_20 = BIT(8),
241 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
242 ATH9K_HW_CAP_2GHZ = BIT(11),
243 ATH9K_HW_CAP_5GHZ = BIT(12),
244 ATH9K_HW_CAP_APM = BIT(13),
245 ATH9K_HW_CAP_RTT = BIT(14),
246 ATH9K_HW_CAP_MCI = BIT(15),
247 ATH9K_HW_CAP_DFS = BIT(16),
248 ATH9K_HW_WOW_DEVICE_CAPABLE = BIT(17),
249 ATH9K_HW_CAP_PAPRD = BIT(18),
250 ATH9K_HW_CAP_FCC_BAND_SWITCH = BIT(19),
251 ATH9K_HW_CAP_BT_ANT_DIV = BIT(20),
255 * WoW device capabilities
256 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW.
257 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching
258 * an exact user defined pattern or de-authentication/disassoc pattern.
259 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four
260 * bytes of the pattern for user defined pattern, de-authentication and
261 * disassociation patterns for all types of possible frames recieved
265 struct ath9k_hw_capabilities {
266 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
280 struct ath9k_ops_config {
281 int dma_beacon_response_time;
282 int sw_beacon_response_time;
283 int additional_swba_backoff;
285 u32 cwm_ignore_extcca;
286 bool pcieSerDesWrite;
295 int serialize_regmode;
296 bool rx_intr_mitigation;
297 bool tx_intr_mitigation;
298 #define SPUR_DISABLE 0
299 #define SPUR_ENABLE_IOCTL 1
300 #define SPUR_ENABLE_EEPROM 2
301 #define AR_SPUR_5413_1 1640
302 #define AR_SPUR_5413_2 1200
303 #define AR_NO_SPUR 0x8000
304 #define AR_BASE_FREQ_2GHZ 2300
305 #define AR_BASE_FREQ_5GHZ 4900
306 #define AR_SPUR_FEEQ_BOUND_HT40 19
307 #define AR_SPUR_FEEQ_BOUND_HT20 10
309 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
311 u16 ani_poll_interval; /* ANI poll interval in ms */
313 /* Platform specific config */
316 u32 ant_ctrl_comm2g_switch_enable;
317 bool xatten_margin_cfg;
323 ATH9K_INT_RX = 0x00000001,
324 ATH9K_INT_RXDESC = 0x00000002,
325 ATH9K_INT_RXHP = 0x00000001,
326 ATH9K_INT_RXLP = 0x00000002,
327 ATH9K_INT_RXNOFRM = 0x00000008,
328 ATH9K_INT_RXEOL = 0x00000010,
329 ATH9K_INT_RXORN = 0x00000020,
330 ATH9K_INT_TX = 0x00000040,
331 ATH9K_INT_TXDESC = 0x00000080,
332 ATH9K_INT_TIM_TIMER = 0x00000100,
333 ATH9K_INT_MCI = 0x00000200,
334 ATH9K_INT_BB_WATCHDOG = 0x00000400,
335 ATH9K_INT_TXURN = 0x00000800,
336 ATH9K_INT_MIB = 0x00001000,
337 ATH9K_INT_RXPHY = 0x00004000,
338 ATH9K_INT_RXKCM = 0x00008000,
339 ATH9K_INT_SWBA = 0x00010000,
340 ATH9K_INT_BMISS = 0x00040000,
341 ATH9K_INT_BNR = 0x00100000,
342 ATH9K_INT_TIM = 0x00200000,
343 ATH9K_INT_DTIM = 0x00400000,
344 ATH9K_INT_DTIMSYNC = 0x00800000,
345 ATH9K_INT_GPIO = 0x01000000,
346 ATH9K_INT_CABEND = 0x02000000,
347 ATH9K_INT_TSFOOR = 0x04000000,
348 ATH9K_INT_GENTIMER = 0x08000000,
349 ATH9K_INT_CST = 0x10000000,
350 ATH9K_INT_GTT = 0x20000000,
351 ATH9K_INT_FATAL = 0x40000000,
352 ATH9K_INT_GLOBAL = 0x80000000,
353 ATH9K_INT_BMISC = ATH9K_INT_TIM |
358 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
370 ATH9K_INT_NOCARD = 0xffffffff
373 #define MAX_RTT_TABLE_ENTRY 6
374 #define MAX_IQCAL_MEASUREMENT 8
375 #define MAX_CL_TAB_ENTRY 16
376 #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
378 enum ath9k_cal_flags {
389 struct ath9k_hw_cal_data {
392 unsigned long cal_flags;
397 u16 small_signal_gain[AR9300_MAX_CHAINS];
398 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
399 u32 num_measures[AR9300_MAX_CHAINS];
400 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
401 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
402 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY];
403 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
406 struct ath9k_channel {
407 struct ieee80211_channel *chan;
413 #define CHANNEL_5GHZ BIT(0)
414 #define CHANNEL_HALF BIT(1)
415 #define CHANNEL_QUARTER BIT(2)
416 #define CHANNEL_HT BIT(3)
417 #define CHANNEL_HT40PLUS BIT(4)
418 #define CHANNEL_HT40MINUS BIT(5)
420 #define IS_CHAN_5GHZ(_c) (!!((_c)->channelFlags & CHANNEL_5GHZ))
421 #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c))
423 #define IS_CHAN_HALF_RATE(_c) (!!((_c)->channelFlags & CHANNEL_HALF))
424 #define IS_CHAN_QUARTER_RATE(_c) (!!((_c)->channelFlags & CHANNEL_QUARTER))
425 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
426 (IS_CHAN_5GHZ(_c) && ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
428 #define IS_CHAN_HT(_c) ((_c)->channelFlags & CHANNEL_HT)
430 #define IS_CHAN_HT20(_c) (IS_CHAN_HT(_c) && !IS_CHAN_HT40(_c))
432 #define IS_CHAN_HT40(_c) \
433 (!!((_c)->channelFlags & (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)))
435 #define IS_CHAN_HT40PLUS(_c) ((_c)->channelFlags & CHANNEL_HT40PLUS)
436 #define IS_CHAN_HT40MINUS(_c) ((_c)->channelFlags & CHANNEL_HT40MINUS)
438 enum ath9k_power_mode {
441 ATH9K_PM_NETWORK_SLEEP,
446 SER_REG_MODE_OFF = 0,
448 SER_REG_MODE_AUTO = 2,
451 enum ath9k_rx_qtype {
457 struct ath9k_beacon_state {
461 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
464 u16 bs_cfpmaxduration;
467 u16 bs_bmissthreshold;
468 u32 bs_sleepduration;
469 u32 bs_tsfoor_threshold;
472 struct chan_centers {
479 ATH9K_RESET_POWER_ON,
484 struct ath9k_hw_version {
493 enum ath_usb_dev usbdev;
496 /* Generic TSF timer definitions */
498 #define ATH_MAX_GEN_TIMER 16
500 #define AR_GENTMR_BIT(_index) (1 << (_index))
503 * Using de Bruijin sequence to look up 1's index in a 32 bit number
504 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
506 #define debruijn32 0x077CB531U
508 struct ath_gen_timer_configuration {
515 struct ath_gen_timer {
516 void (*trigger)(void *arg);
517 void (*overflow)(void *arg);
522 struct ath_gen_timer_table {
523 u32 gen_timer_index[32];
524 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
526 unsigned long timer_bits;
531 struct ath_hw_antcomb_conf {
538 int lna1_lna2_switch_delta;
543 * struct ath_hw_radar_conf - radar detection initialization parameters
545 * @pulse_inband: threshold for checking the ratio of in-band power
546 * to total power for short radar pulses (half dB steps)
547 * @pulse_inband_step: threshold for checking an in-band power to total
548 * power ratio increase for short radar pulses (half dB steps)
549 * @pulse_height: threshold for detecting the beginning of a short
550 * radar pulse (dB step)
551 * @pulse_rssi: threshold for detecting if a short radar pulse is
553 * @pulse_maxlen: maximum pulse length (0.8 us steps)
555 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
556 * @radar_inband: threshold for checking the ratio of in-band power
557 * to total power for long radar pulses (half dB steps)
558 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
560 * @ext_channel: enable extension channel radar detection
562 struct ath_hw_radar_conf {
563 unsigned int pulse_inband;
564 unsigned int pulse_inband_step;
565 unsigned int pulse_height;
566 unsigned int pulse_rssi;
567 unsigned int pulse_maxlen;
569 unsigned int radar_rssi;
570 unsigned int radar_inband;
577 * struct ath_hw_private_ops - callbacks used internally by hardware code
579 * This structure contains private callbacks designed to only be used internally
580 * by the hardware core.
582 * @init_cal_settings: setup types of calibrations supported
583 * @init_cal: starts actual calibration
585 * @init_mode_gain_regs: Initialize TX/RX gain registers
587 * @rf_set_freq: change frequency
588 * @spur_mitigate_freq: spur mitigation
590 * @compute_pll_control: compute the PLL control value to use for
591 * AR_RTC_PLL_CONTROL for a given channel
592 * @setup_calibration: set up calibration
593 * @iscal_supported: used to query if a type of calibration is supported
595 * @ani_cache_ini_regs: cache the values for ANI from the initial
596 * register settings through the register initialization.
598 struct ath_hw_private_ops {
599 /* Calibration ops */
600 void (*init_cal_settings)(struct ath_hw *ah);
601 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
603 void (*init_mode_gain_regs)(struct ath_hw *ah);
604 void (*setup_calibration)(struct ath_hw *ah,
605 struct ath9k_cal_list *currCal);
608 int (*rf_set_freq)(struct ath_hw *ah,
609 struct ath9k_channel *chan);
610 void (*spur_mitigate_freq)(struct ath_hw *ah,
611 struct ath9k_channel *chan);
612 bool (*set_rf_regs)(struct ath_hw *ah,
613 struct ath9k_channel *chan,
615 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
616 void (*init_bb)(struct ath_hw *ah,
617 struct ath9k_channel *chan);
618 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
619 void (*olc_init)(struct ath_hw *ah);
620 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
621 void (*mark_phy_inactive)(struct ath_hw *ah);
622 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
623 bool (*rfbus_req)(struct ath_hw *ah);
624 void (*rfbus_done)(struct ath_hw *ah);
625 void (*restore_chainmask)(struct ath_hw *ah);
626 u32 (*compute_pll_control)(struct ath_hw *ah,
627 struct ath9k_channel *chan);
628 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
630 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
631 void (*set_radar_params)(struct ath_hw *ah,
632 struct ath_hw_radar_conf *conf);
633 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
637 void (*ani_cache_ini_regs)(struct ath_hw *ah);
641 * struct ath_spec_scan - parameters for Atheros spectral scan
643 * @enabled: enable/disable spectral scan
644 * @short_repeat: controls whether the chip is in spectral scan mode
645 * for 4 usec (enabled) or 204 usec (disabled)
646 * @count: number of scan results requested. There are special meanings
647 * in some chip revisions:
648 * AR92xx: highest bit set (>=128) for endless mode
649 * (spectral scan won't stopped until explicitly disabled)
650 * AR9300 and newer: 0 for endless mode
651 * @endless: true if endless mode is intended. Otherwise, count value is
652 * corrected to the next possible value.
653 * @period: time duration between successive spectral scan entry points
654 * (period*256*Tclk). Tclk = ath_common->clockrate
655 * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS
657 * Note: Tclk = 40MHz or 44MHz depending upon operating mode.
658 * Typically it's 44MHz in 2/5GHz on later chips, but there's
659 * a "fast clock" check for this in 5GHz.
662 struct ath_spec_scan {
672 * struct ath_hw_ops - callbacks used by hardware code and driver code
674 * This structure contains callbacks designed to to be used internally by
675 * hardware code and also by the lower level driver.
677 * @config_pci_powersave:
678 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
680 * @spectral_scan_config: set parameters for spectral scan and enable/disable it
681 * @spectral_scan_trigger: trigger a spectral scan run
682 * @spectral_scan_wait: wait for a spectral scan run to finish
685 void (*config_pci_powersave)(struct ath_hw *ah,
687 void (*rx_enable)(struct ath_hw *ah);
688 void (*set_desc_link)(void *ds, u32 link);
689 bool (*calibrate)(struct ath_hw *ah,
690 struct ath9k_channel *chan,
693 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
694 void (*set_txdesc)(struct ath_hw *ah, void *ds,
695 struct ath_tx_info *i);
696 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
697 struct ath_tx_status *ts);
698 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
699 struct ath_hw_antcomb_conf *antconf);
700 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
701 struct ath_hw_antcomb_conf *antconf);
702 void (*spectral_scan_config)(struct ath_hw *ah,
703 struct ath_spec_scan *param);
704 void (*spectral_scan_trigger)(struct ath_hw *ah);
705 void (*spectral_scan_wait)(struct ath_hw *ah);
707 void (*tx99_start)(struct ath_hw *ah, u32 qnum);
708 void (*tx99_stop)(struct ath_hw *ah);
709 void (*tx99_set_txpower)(struct ath_hw *ah, u8 power);
711 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
712 void (*set_bt_ant_diversity)(struct ath_hw *hw, bool enable);
716 struct ath_nf_limits {
724 TX_IQ_ON_AGC_CAL = BIT(1),
729 #define AH_USE_EEPROM 0x1
730 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
731 #define AH_FASTCC 0x4
734 struct ath_ops reg_ops;
737 struct ieee80211_hw *hw;
738 struct ath_common common;
739 struct ath9k_hw_version hw_version;
740 struct ath9k_ops_config config;
741 struct ath9k_hw_capabilities caps;
742 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
743 struct ath9k_channel *curchan;
746 struct ar5416_eeprom_def def;
747 struct ar5416_eeprom_4k map4k;
748 struct ar9287_eeprom map9287;
749 struct ar9300_eeprom ar9300_eep;
751 const struct eeprom_ops *eep_ops;
757 bool need_an_top2_fixup;
761 struct ath_nf_limits nf_2g;
762 struct ath_nf_limits nf_5g;
771 enum nl80211_iftype opmode;
772 enum ath9k_power_mode power_mode;
775 struct ath9k_hw_cal_data *caldata;
776 struct ath9k_pacal_info pacal_info;
777 struct ar5416Stats stats;
778 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
780 enum ath9k_int imask;
782 u32 txok_interrupt_mask;
783 u32 txerr_interrupt_mask;
784 u32 txdesc_interrupt_mask;
785 u32 txeol_interrupt_mask;
786 u32 txurn_interrupt_mask;
787 atomic_t intr_ref_cnt;
794 struct ath9k_cal_list iq_caldata;
795 struct ath9k_cal_list adcgain_caldata;
796 struct ath9k_cal_list adcdc_caldata;
797 struct ath9k_cal_list *cal_list;
798 struct ath9k_cal_list *cal_list_last;
799 struct ath9k_cal_list *cal_list_curr;
800 #define totalPowerMeasI meas0.unsign
801 #define totalPowerMeasQ meas1.unsign
802 #define totalIqCorrMeas meas2.sign
803 #define totalAdcIOddPhase meas0.unsign
804 #define totalAdcIEvenPhase meas1.unsign
805 #define totalAdcQOddPhase meas2.unsign
806 #define totalAdcQEvenPhase meas3.unsign
807 #define totalAdcDcOffsetIOddPhase meas0.sign
808 #define totalAdcDcOffsetIEvenPhase meas1.sign
809 #define totalAdcDcOffsetQOddPhase meas2.sign
810 #define totalAdcDcOffsetQEvenPhase meas3.sign
812 u32 unsign[AR5416_MAX_CHAINS];
813 int32_t sign[AR5416_MAX_CHAINS];
816 u32 unsign[AR5416_MAX_CHAINS];
817 int32_t sign[AR5416_MAX_CHAINS];
820 u32 unsign[AR5416_MAX_CHAINS];
821 int32_t sign[AR5416_MAX_CHAINS];
824 u32 unsign[AR5416_MAX_CHAINS];
825 int32_t sign[AR5416_MAX_CHAINS];
830 u32 sta_id1_defaults;
833 /* Private to hardware code */
834 struct ath_hw_private_ops private_ops;
835 /* Accessed by the lower level driver */
836 struct ath_hw_ops ops;
838 /* Used to program the radio on non single-chip devices */
839 u32 *analogBank6Data;
847 enum ath9k_ani_cmd ani_function;
849 struct ar5416AniState ani;
851 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
852 struct ath_btcoex_hw btcoex_hw;
859 struct ath_hw_radar_conf radar_conf;
861 u32 originalGain[22];
868 struct ar5416IniArray iniModes;
869 struct ar5416IniArray iniCommon;
870 struct ar5416IniArray iniBB_RfGain;
871 struct ar5416IniArray iniBank6;
872 struct ar5416IniArray iniAddac;
873 struct ar5416IniArray iniPcieSerdes;
874 struct ar5416IniArray iniPcieSerdesLowPower;
875 struct ar5416IniArray iniModesFastClock;
876 struct ar5416IniArray iniAdditional;
877 struct ar5416IniArray iniModesRxGain;
878 struct ar5416IniArray ini_modes_rx_gain_bounds;
879 struct ar5416IniArray iniModesTxGain;
880 struct ar5416IniArray iniCckfirNormal;
881 struct ar5416IniArray iniCckfirJapan2484;
882 struct ar5416IniArray iniModes_9271_ANI_reg;
883 struct ar5416IniArray ini_radio_post_sys2ant;
884 struct ar5416IniArray ini_modes_rxgain_5g_xlna;
885 struct ar5416IniArray ini_modes_rxgain_bb_core;
886 struct ar5416IniArray ini_modes_rxgain_bb_postamble;
888 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
889 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
890 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
891 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
893 u32 intr_gen_timer_trigger;
894 u32 intr_gen_timer_thresh;
895 struct ath_gen_timer_table hw_gen_timers;
897 struct ar9003_txs *ts_ring;
903 u32 bb_watchdog_last_status;
904 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
905 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
907 unsigned int paprd_target_power;
908 unsigned int paprd_training_power;
909 unsigned int paprd_ratemask;
910 unsigned int paprd_ratemask_ht40;
911 bool paprd_table_write_done;
912 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
913 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
915 * Store the permanent value of Reg 0x4004in WARegVal
916 * so we dont have to R/M/W. We should not be reading
917 * this register when in sleep states.
921 /* Enterprise mode cap */
924 #ifdef CONFIG_PM_SLEEP
928 int (*get_mac_revision)(void);
929 int (*external_reset)(void);
931 const struct firmware *eeprom_blob;
935 enum ath_bus_type ath_bus_type;
936 void (*read_cachesize)(struct ath_common *common, int *csz);
937 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
938 void (*bt_coex_prep)(struct ath_common *common);
939 void (*aspm_init)(struct ath_common *common);
942 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
947 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
949 return &(ath9k_hw_common(ah)->regulatory);
952 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
954 return &ah->private_ops;
957 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
962 static inline u8 get_streams(int mask)
964 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
967 /* Initialization, Detach, Reset */
968 void ath9k_hw_deinit(struct ath_hw *ah);
969 int ath9k_hw_init(struct ath_hw *ah);
970 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
971 struct ath9k_hw_cal_data *caldata, bool fastcc);
972 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
973 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
975 /* GPIO / RFKILL / Antennae */
976 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
977 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
978 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
980 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
981 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
983 /* General Operation */
984 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
986 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
987 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
988 int column, unsigned int *writecnt);
989 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
990 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
992 u32 frameLen, u16 rateix, bool shortPreamble);
993 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
994 struct ath9k_channel *chan,
995 struct chan_centers *centers);
996 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
997 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
998 bool ath9k_hw_phy_disable(struct ath_hw *ah);
999 bool ath9k_hw_disable(struct ath_hw *ah);
1000 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
1001 void ath9k_hw_setopmode(struct ath_hw *ah);
1002 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
1003 void ath9k_hw_write_associd(struct ath_hw *ah);
1004 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
1005 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
1006 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
1007 void ath9k_hw_reset_tsf(struct ath_hw *ah);
1008 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set);
1009 void ath9k_hw_init_global_settings(struct ath_hw *ah);
1010 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
1011 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan);
1012 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
1013 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1014 const struct ath9k_beacon_state *bs);
1015 void ath9k_hw_check_nav(struct ath_hw *ah);
1016 bool ath9k_hw_check_alive(struct ath_hw *ah);
1018 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
1020 #ifdef CONFIG_ATH9K_DEBUGFS
1021 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause);
1023 static inline void ath9k_debug_sync_cause(struct ath_common *common,
1027 /* Generic hw timer primitives */
1028 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
1029 void (*trigger)(void *),
1030 void (*overflow)(void *),
1033 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
1034 struct ath_gen_timer *timer,
1037 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
1039 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
1040 void ath_gen_timer_isr(struct ath_hw *hw);
1042 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
1045 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1046 u32 *coef_mantissa, u32 *coef_exponent);
1047 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
1051 * Code Specific to AR5008, AR9001 or AR9002,
1052 * we stuff these here to avoid callbacks for AR9003.
1054 int ar9002_hw_rf_claim(struct ath_hw *ah);
1055 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
1058 * Code specific to AR9003, we stuff these here to avoid callbacks
1059 * for older families
1061 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1062 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1063 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
1064 void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
1065 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1066 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1067 struct ath9k_hw_cal_data *caldata,
1069 int ar9003_paprd_create_curve(struct ath_hw *ah,
1070 struct ath9k_hw_cal_data *caldata, int chain);
1071 void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1072 int ar9003_paprd_init_table(struct ath_hw *ah);
1073 bool ar9003_paprd_is_done(struct ath_hw *ah);
1074 bool ar9003_is_paprd_enabled(struct ath_hw *ah);
1075 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
1077 /* Hardware family op attach helpers */
1078 int ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1079 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1080 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1082 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1083 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1085 int ar9002_hw_attach_ops(struct ath_hw *ah);
1086 void ar9003_hw_attach_ops(struct ath_hw *ah);
1088 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1090 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1091 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1093 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1094 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1096 return ah->btcoex_hw.enabled;
1098 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1100 return ah->common.btcoex_enabled &&
1101 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1104 void ath9k_hw_btcoex_enable(struct ath_hw *ah);
1105 static inline enum ath_btcoex_scheme
1106 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1108 return ah->btcoex_hw.scheme;
1111 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1115 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1119 static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah)
1122 static inline enum ath_btcoex_scheme
1123 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1125 return ATH_BTCOEX_CFG_NONE;
1127 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
1130 #ifdef CONFIG_PM_SLEEP
1131 const char *ath9k_hw_wow_event_to_string(u32 wow_event);
1132 void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
1133 u8 *user_mask, int pattern_count,
1135 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah);
1136 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable);
1138 static inline const char *ath9k_hw_wow_event_to_string(u32 wow_event)
1142 static inline void ath9k_hw_wow_apply_pattern(struct ath_hw *ah,
1149 static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
1153 static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
1158 #define ATH9K_CLOCK_RATE_CCK 22
1159 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1160 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1161 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44