drivers/net/wireless/ath/ath9k/ar9003_phy.c

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/export.h>
  18 #include "hw.h"
  19 #include "ar9003_phy.h"
  20
  21 static const int firstep_table[] =
  22 /* level:  0   1   2   3   4   5   6   7   8  */
  23         { -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
  24
  25 static const int cycpwrThr1_table[] =
  26 /* level:  0   1   2   3   4   5   6   7   8  */
  27         { -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
  28
  29 /*
  30  * register values to turn OFDM weak signal detection OFF
  31  */
  32 static const int m1ThreshLow_off = 127;
  33 static const int m2ThreshLow_off = 127;
  34 static const int m1Thresh_off = 127;
  35 static const int m2Thresh_off = 127;
  36 static const int m2CountThr_off =  31;
  37 static const int m2CountThrLow_off =  63;
  38 static const int m1ThreshLowExt_off = 127;
  39 static const int m2ThreshLowExt_off = 127;
  40 static const int m1ThreshExt_off = 127;
  41 static const int m2ThreshExt_off = 127;
  42
  43 /**
  44  * ar9003_hw_set_channel - set channel on single-chip device
  45  * @ah: atheros hardware structure
  46  * @chan:
  47  *
  48  * This is the function to change channel on single-chip devices, that is
  49  * for AR9300 family of chipsets.
  50  *
  51  * This function takes the channel value in MHz and sets
  52  * hardware channel value. Assumes writes have been enabled to analog bus.
  53  *
  54  * Actual Expression,
  55  *
  56  * For 2GHz channel,
  57  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  58  * (freq_ref = 40MHz)
  59  *
  60  * For 5GHz channel,
  61  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
  62  * (freq_ref = 40MHz/(24>>amodeRefSel))
  63  *
  64  * For 5GHz channels which are 5MHz spaced,
  65  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  66  * (freq_ref = 40MHz)
  67  */
  68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  69 {
  70         u16 bMode, fracMode = 0, aModeRefSel = 0;
  71         u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
  72         struct chan_centers centers;
  73         int loadSynthChannel;
  74
  75         ath9k_hw_get_channel_centers(ah, chan, &centers);
  76         freq = centers.synth_center;
  77
  78         if (freq < 4800) {     /* 2 GHz, fractional mode */
  79                 if (AR_SREV_9330(ah)) {
  80                         if (ah->is_clk_25mhz)
  81                                 div = 75;
  82                         else
  83                                 div = 120;
  84
  85                         channelSel = (freq * 4) / div;
  86                         chan_frac = (((freq * 4) % div) * 0x20000) / div;
  87                         channelSel = (channelSel << 17) | chan_frac;
  88                 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
  89                         /*
  90                          * freq_ref = 40 / (refdiva >> amoderefsel);
  91                          * where refdiva=1 and amoderefsel=0
  92                          * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
  93                          * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
  94                          */
  95                         channelSel = (freq * 4) / 120;
  96                         chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
  97                         channelSel = (channelSel << 17) | chan_frac;
  98                 } else if (AR_SREV_9340(ah)) {
  99                         if (ah->is_clk_25mhz) {
 100                                 channelSel = (freq * 2) / 75;
 101                                 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
 102                                 channelSel = (channelSel << 17) | chan_frac;
 103                         } else {
 104                                 channelSel = CHANSEL_2G(freq) >> 1;
 105                         }
 106                 } else if (AR_SREV_9550(ah)) {
 107                         if (ah->is_clk_25mhz)
 108                                 div = 75;
 109                         else
 110                                 div = 120;
 111
 112                         channelSel = (freq * 4) / div;
 113                         chan_frac = (((freq * 4) % div) * 0x20000) / div;
 114                         channelSel = (channelSel << 17) | chan_frac;
 115                 } else {
 116                         channelSel = CHANSEL_2G(freq);
 117                 }
 118                 /* Set to 2G mode */
 119                 bMode = 1;
 120         } else {
 121                 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
 122                     ah->is_clk_25mhz) {
 123                         channelSel = freq / 75;
 124                         chan_frac = ((freq % 75) * 0x20000) / 75;
 125                         channelSel = (channelSel << 17) | chan_frac;
 126                 } else {
 127                         channelSel = CHANSEL_5G(freq);
 128                         /* Doubler is ON, so, divide channelSel by 2. */
 129                         channelSel >>= 1;
 130                 }
 131                 /* Set to 5G mode */
 132                 bMode = 0;
 133         }
 134
 135         /* Enable fractional mode for all channels */
 136         fracMode = 1;
 137         aModeRefSel = 0;
 138         loadSynthChannel = 0;
 139
 140         reg32 = (bMode << 29);
 141         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
 142
 143         /* Enable Long shift Select for Synthesizer */
 144         REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
 145                       AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
 146
 147         /* Program Synth. setting */
 148         reg32 = (channelSel << 2) | (fracMode << 30) |
 149                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 150         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 151
 152         /* Toggle Load Synth channel bit */
 153         loadSynthChannel = 1;
 154         reg32 = (channelSel << 2) | (fracMode << 30) |
 155                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 156         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 157
 158         ah->curchan = chan;
 159
 160         return 0;
 161 }
 162
 163 /**
 164  * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
 165  * @ah: atheros hardware structure
 166  * @chan:
 167  *
 168  * For single-chip solutions. Converts to baseband spur frequency given the
 169  * input channel frequency and compute register settings below.
 170  *
 171  * Spur mitigation for MRC CCK
 172  */
 173 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
 174                                             struct ath9k_channel *chan)
 175 {
 176         static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
 177         int cur_bb_spur, negative = 0, cck_spur_freq;
 178         int i;
 179         int range, max_spur_cnts, synth_freq;
 180         u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
 181
 182         /*
 183          * Need to verify range +/- 10 MHz in control channel, otherwise spur
 184          * is out-of-band and can be ignored.
 185          */
 186
 187         if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
 188             AR_SREV_9550(ah)) {
 189                 if (spur_fbin_ptr[0] == 0) /* No spur */
 190                         return;
 191                 max_spur_cnts = 5;
 192                 if (IS_CHAN_HT40(chan)) {
 193                         range = 19;
 194                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 195                                            AR_PHY_GC_DYN2040_PRI_CH) == 0)
 196                                 synth_freq = chan->channel + 10;
 197                         else
 198                                 synth_freq = chan->channel - 10;
 199                 } else {
 200                         range = 10;
 201                         synth_freq = chan->channel;
 202                 }
 203         } else {
 204                 range = AR_SREV_9462(ah) ? 5 : 10;
 205                 max_spur_cnts = 4;
 206                 synth_freq = chan->channel;
 207         }
 208
 209         for (i = 0; i < max_spur_cnts; i++) {
 210                 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
 211                         continue;
 212
 213                 negative = 0;
 214                 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
 215                     AR_SREV_9550(ah))
 216                         cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
 217                                                          IS_CHAN_2GHZ(chan));
 218                 else
 219                         cur_bb_spur = spur_freq[i];
 220
 221                 cur_bb_spur -= synth_freq;
 222                 if (cur_bb_spur < 0) {
 223                         negative = 1;
 224                         cur_bb_spur = -cur_bb_spur;
 225                 }
 226                 if (cur_bb_spur < range) {
 227                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
 228
 229                         if (negative == 1)
 230                                 cck_spur_freq = -cck_spur_freq;
 231
 232                         cck_spur_freq = cck_spur_freq & 0xfffff;
 233
 234                         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 235                                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
 236                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 237                                       AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
 238                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 239                                       AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
 240                                       0x2);
 241                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 242                                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
 243                                       0x1);
 244                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 245                                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
 246                                       cck_spur_freq);
 247
 248                         return;
 249                 }
 250         }
 251
 252         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 253                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
 254         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 255                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
 256         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 257                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
 258 }
 259
 260 /* Clean all spur register fields */
 261 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
 262 {
 263         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 264                       AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
 265         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 266                       AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
 267         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 268                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
 269         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 270                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
 271         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 272                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
 273         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 274                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
 275         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 276                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
 277         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 278                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
 279         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 280                       AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
 281
 282         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 283                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
 284         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 285                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
 286         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 287                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
 288         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 289                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
 290         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 291                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
 292         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 293                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
 294         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 295                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
 296         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 297                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
 298         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 299                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
 300         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 301                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
 302 }
 303
 304 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
 305                                 int freq_offset,
 306                                 int spur_freq_sd,
 307                                 int spur_delta_phase,
 308                                 int spur_subchannel_sd,
 309                                 int range,
 310                                 int synth_freq)
 311 {
 312         int mask_index = 0;
 313
 314         /* OFDM Spur mitigation */
 315         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 316                  AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
 317         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 318                       AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
 319         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 320                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
 321         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 322                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
 323         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 324                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
 325
 326         if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
 327                 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 328                               AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
 329
 330         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 331                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
 332         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 333                       AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
 334         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 335                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
 336
 337         if (!AR_SREV_9340(ah) &&
 338             REG_READ_FIELD(ah, AR_PHY_MODE,
 339                            AR_PHY_MODE_DYNAMIC) == 0x1)
 340                 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 341                               AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
 342
 343         mask_index = (freq_offset << 4) / 5;
 344         if (mask_index < 0)
 345                 mask_index = mask_index - 1;
 346
 347         mask_index = mask_index & 0x7f;
 348
 349         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 350                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
 351         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 352                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
 353         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 354                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
 355         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 356                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
 357         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 358                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
 359         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 360                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
 361         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 362                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
 363         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 364                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
 365         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 366                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 367         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 368                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
 369 }
 370
 371 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
 372                                      int freq_offset)
 373 {
 374         int mask_index = 0;
 375
 376         mask_index = (freq_offset << 4) / 5;
 377         if (mask_index < 0)
 378                 mask_index = mask_index - 1;
 379
 380         mask_index = mask_index & 0x7f;
 381
 382         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 383                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
 384                       mask_index);
 385
 386         /* A == B */
 387         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
 388                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
 389                       mask_index);
 390
 391         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 392                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
 393                       mask_index);
 394         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 395                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
 396         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 397                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
 398
 399         /* A == B */
 400         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
 401                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 402 }
 403
 404 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
 405                                      struct ath9k_channel *chan,
 406                                      int freq_offset,
 407                                      int range,
 408                                      int synth_freq)
 409 {
 410         int spur_freq_sd = 0;
 411         int spur_subchannel_sd = 0;
 412         int spur_delta_phase = 0;
 413
 414         if (IS_CHAN_HT40(chan)) {
 415                 if (freq_offset < 0) {
 416                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 417                                            AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 418                                 spur_subchannel_sd = 1;
 419                         else
 420                                 spur_subchannel_sd = 0;
 421
 422                         spur_freq_sd = ((freq_offset + 10) << 9) / 11;
 423
 424                 } else {
 425                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 426                             AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 427                                 spur_subchannel_sd = 0;
 428                         else
 429                                 spur_subchannel_sd = 1;
 430
 431                         spur_freq_sd = ((freq_offset - 10) << 9) / 11;
 432
 433                 }
 434
 435                 spur_delta_phase = (freq_offset << 17) / 5;
 436
 437         } else {
 438                 spur_subchannel_sd = 0;
 439                 spur_freq_sd = (freq_offset << 9) /11;
 440                 spur_delta_phase = (freq_offset << 18) / 5;
 441         }
 442
 443         spur_freq_sd = spur_freq_sd & 0x3ff;
 444         spur_delta_phase = spur_delta_phase & 0xfffff;
 445
 446         ar9003_hw_spur_ofdm(ah,
 447                             freq_offset,
 448                             spur_freq_sd,
 449                             spur_delta_phase,
 450                             spur_subchannel_sd,
 451                             range, synth_freq);
 452 }
 453
 454 /* Spur mitigation for OFDM */
 455 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
 456                                          struct ath9k_channel *chan)
 457 {
 458         int synth_freq;
 459         int range = 10;
 460         int freq_offset = 0;
 461         int mode;
 462         u8* spurChansPtr;
 463         unsigned int i;
 464         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 465
 466         if (IS_CHAN_5GHZ(chan)) {
 467                 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
 468                 mode = 0;
 469         }
 470         else {
 471                 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
 472                 mode = 1;
 473         }
 474
 475         if (spurChansPtr[0] == 0)
 476                 return; /* No spur in the mode */
 477
 478         if (IS_CHAN_HT40(chan)) {
 479                 range = 19;
 480                 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 481                                    AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 482                         synth_freq = chan->channel - 10;
 483                 else
 484                         synth_freq = chan->channel + 10;
 485         } else {
 486                 range = 10;
 487                 synth_freq = chan->channel;
 488         }
 489
 490         ar9003_hw_spur_ofdm_clear(ah);
 491
 492         for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
 493                 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
 494                 freq_offset -= synth_freq;
 495                 if (abs(freq_offset) < range) {
 496                         ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
 497                                                  range, synth_freq);
 498
 499                         if (AR_SREV_9565(ah) && (i < 4)) {
 500                                 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
 501                                                                  mode);
 502                                 freq_offset -= synth_freq;
 503                                 if (abs(freq_offset) < range)
 504                                         ar9003_hw_spur_ofdm_9565(ah, freq_offset);
 505                         }
 506
 507                         break;
 508                 }
 509         }
 510 }
 511
 512 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
 513                                     struct ath9k_channel *chan)
 514 {
 515         if (!AR_SREV_9565(ah))
 516                 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
 517         ar9003_hw_spur_mitigate_ofdm(ah, chan);
 518 }
 519
 520 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
 521                                          struct ath9k_channel *chan)
 522 {
 523         u32 pll;
 524
 525         pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
 526
 527         if (chan && IS_CHAN_HALF_RATE(chan))
 528                 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
 529         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 530                 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
 531
 532         pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
 533
 534         return pll;
 535 }
 536
 537 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
 538                                        struct ath9k_channel *chan)
 539 {
 540         u32 phymode;
 541         u32 enableDacFifo = 0;
 542
 543         enableDacFifo =
 544                 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
 545
 546         /* Enable 11n HT, 20 MHz */
 547         phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
 548                   AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
 549
 550         /* Configure baseband for dynamic 20/40 operation */
 551         if (IS_CHAN_HT40(chan)) {
 552                 phymode |= AR_PHY_GC_DYN2040_EN;
 553                 /* Configure control (primary) channel at +-10MHz */
 554                 if (IS_CHAN_HT40PLUS(chan))
 555                         phymode |= AR_PHY_GC_DYN2040_PRI_CH;
 556
 557         }
 558
 559         /* make sure we preserve INI settings */
 560         phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
 561         /* turn off Green Field detection for STA for now */
 562         phymode &= ~AR_PHY_GC_GF_DETECT_EN;
 563
 564         REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
 565
 566         /* Configure MAC for 20/40 operation */
 567         ath9k_hw_set11nmac2040(ah, chan);
 568
 569         /* global transmit timeout (25 TUs default)*/
 570         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
 571         /* carrier sense timeout */
 572         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
 573 }
 574
 575 static void ar9003_hw_init_bb(struct ath_hw *ah,
 576                               struct ath9k_channel *chan)
 577 {
 578         u32 synthDelay;
 579
 580         /*
 581          * Wait for the frequency synth to settle (synth goes on
 582          * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
 583          * Value is in 100ns increments.
 584          */
 585         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 586
 587         /* Activate the PHY (includes baseband activate + synthesizer on) */
 588         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 589         ath9k_hw_synth_delay(ah, chan, synthDelay);
 590 }
 591
 592 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
 593 {
 594         if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
 595                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 596                             AR_PHY_SWAP_ALT_CHAIN);
 597
 598         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
 599         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
 600
 601         if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
 602                 tx = 3;
 603
 604         REG_WRITE(ah, AR_SELFGEN_MASK, tx);
 605 }
 606
 607 /*
 608  * Override INI values with chip specific configuration.
 609  */
 610 static void ar9003_hw_override_ini(struct ath_hw *ah)
 611 {
 612         u32 val;
 613
 614         /*
 615          * Set the RX_ABORT and RX_DIS and clear it only after
 616          * RXE is set for MAC. This prevents frames with
 617          * corrupted descriptor status.
 618          */
 619         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 620
 621         /*
 622          * For AR9280 and above, there is a new feature that allows
 623          * Multicast search based on both MAC Address and Key ID. By default,
 624          * this feature is enabled. But since the driver is not using this
 625          * feature, we switch it off; otherwise multicast search based on
 626          * MAC addr only will fail.
 627          */
 628         val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
 629         val |= AR_AGG_WEP_ENABLE_FIX |
 630                AR_AGG_WEP_ENABLE |
 631                AR_PCU_MISC_MODE2_CFP_IGNORE;
 632         REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
 633
 634         if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
 635                 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
 636                           AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
 637
 638                 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
 639                                    AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
 640                         ah->enabled_cals |= TX_IQ_CAL;
 641                 else
 642                         ah->enabled_cals &= ~TX_IQ_CAL;
 643
 644                 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
 645                         ah->enabled_cals |= TX_CL_CAL;
 646                 else
 647                         ah->enabled_cals &= ~TX_CL_CAL;
 648         }
 649 }
 650
 651 static void ar9003_hw_prog_ini(struct ath_hw *ah,
 652                                struct ar5416IniArray *iniArr,
 653                                int column)
 654 {
 655         unsigned int i, regWrites = 0;
 656
 657         /* New INI format: Array may be undefined (pre, core, post arrays) */
 658         if (!iniArr->ia_array)
 659                 return;
 660
 661         /*
 662          * New INI format: Pre, core, and post arrays for a given subsystem
 663          * may be modal (> 2 columns) or non-modal (2 columns). Determine if
 664          * the array is non-modal and force the column to 1.
 665          */
 666         if (column >= iniArr->ia_columns)
 667                 column = 1;
 668
 669         for (i = 0; i < iniArr->ia_rows; i++) {
 670                 u32 reg = INI_RA(iniArr, i, 0);
 671                 u32 val = INI_RA(iniArr, i, column);
 672
 673                 REG_WRITE(ah, reg, val);
 674
 675                 DO_DELAY(regWrites);
 676         }
 677 }
 678
 679 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
 680                                             struct ath9k_channel *chan)
 681 {
 682         int ret;
 683
 684         if (IS_CHAN_2GHZ(chan)) {
 685                 if (IS_CHAN_HT40(chan))
 686                         return 7;
 687                 else
 688                         return 8;
 689         }
 690
 691         if (chan->channel <= 5350)
 692                 ret = 1;
 693         else if ((chan->channel > 5350) && (chan->channel <= 5600))
 694                 ret = 3;
 695         else
 696                 ret = 5;
 697
 698         if (IS_CHAN_HT40(chan))
 699                 ret++;
 700
 701         return ret;
 702 }
 703
 704 static void ar9003_doubler_fix(struct ath_hw *ah)
 705 {
 706         if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
 707                 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2,
 708                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
 709                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
 710                 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2,
 711                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
 712                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
 713                 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2,
 714                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
 715                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
 716
 717                 udelay(200);
 718
 719                 REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
 720                             AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
 721                 REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
 722                             AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
 723                 REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
 724                             AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
 725
 726                 udelay(1);
 727
 728                 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2,
 729                               AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
 730                 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2,
 731                               AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
 732                 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2,
 733                               AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
 734
 735                 udelay(200);
 736
 737                 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12,
 738                               AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf);
 739
 740                 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0,
 741                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
 742                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
 743                 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0,
 744                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
 745                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
 746                 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0,
 747                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
 748                         1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
 749         }
 750 }
 751
 752 static int ar9003_hw_process_ini(struct ath_hw *ah,
 753                                  struct ath9k_channel *chan)
 754 {
 755         unsigned int regWrites = 0, i;
 756         u32 modesIndex;
 757
 758         if (IS_CHAN_5GHZ(chan))
 759                 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
 760         else
 761                 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
 762
 763         /*
 764          * SOC, MAC, BB, RADIO initvals.
 765          */
 766         for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
 767                 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
 768                 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
 769                 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
 770                 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
 771                 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
 772                         ar9003_hw_prog_ini(ah,
 773                                            &ah->ini_radio_post_sys2ant,
 774                                            modesIndex);
 775         }
 776
 777         ar9003_doubler_fix(ah);
 778
 779         /*
 780          * RXGAIN initvals.
 781          */
 782         REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
 783
 784         if (AR_SREV_9462_20_OR_LATER(ah)) {
 785                 /*
 786                  * CUS217 mix LNA mode.
 787                  */
 788                 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
 789                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
 790                                         1, regWrites);
 791                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
 792                                         modesIndex, regWrites);
 793                 }
 794
 795                 /*
 796                  * 5G-XLNA
 797                  */
 798                 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
 799                     (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
 800                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 801                                         modesIndex, regWrites);
 802                 }
 803         }
 804
 805         if (AR_SREV_9550(ah))
 806                 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
 807                                 regWrites);
 808
 809         /*
 810          * TXGAIN initvals.
 811          */
 812         if (AR_SREV_9550(ah)) {
 813                 int modes_txgain_index;
 814
 815                 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
 816                 if (modes_txgain_index < 0)
 817                         return -EINVAL;
 818
 819                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
 820                                 regWrites);
 821         } else {
 822                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
 823         }
 824
 825         /*
 826          * For 5GHz channels requiring Fast Clock, apply
 827          * different modal values.
 828          */
 829         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 830                 REG_WRITE_ARRAY(&ah->iniModesFastClock,
 831                                 modesIndex, regWrites);
 832
 833         /*
 834          * Clock frequency initvals.
 835          */
 836         REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
 837
 838         /*
 839          * JAPAN regulatory.
 840          */
 841         if (chan->channel == 2484)
 842                 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
 843
 844         ah->modes_index = modesIndex;
 845         ar9003_hw_override_ini(ah);
 846         ar9003_hw_set_channel_regs(ah, chan);
 847         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
 848         ath9k_hw_apply_txpower(ah, chan, false);
 849
 850         return 0;
 851 }
 852
 853 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
 854                                  struct ath9k_channel *chan)
 855 {
 856         u32 rfMode = 0;
 857
 858         if (chan == NULL)
 859                 return;
 860
 861         if (IS_CHAN_2GHZ(chan))
 862                 rfMode |= AR_PHY_MODE_DYNAMIC;
 863         else
 864                 rfMode |= AR_PHY_MODE_OFDM;
 865
 866         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 867                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
 868         if (IS_CHAN_QUARTER_RATE(chan))
 869                 rfMode |= AR_PHY_MODE_QUARTER;
 870         if (IS_CHAN_HALF_RATE(chan))
 871                 rfMode |= AR_PHY_MODE_HALF;
 872
 873         if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
 874                 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
 875                               AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
 876
 877         REG_WRITE(ah, AR_PHY_MODE, rfMode);
 878 }
 879
 880 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
 881 {
 882         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
 883 }
 884
 885 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
 886                                       struct ath9k_channel *chan)
 887 {
 888         u32 coef_scaled, ds_coef_exp, ds_coef_man;
 889         u32 clockMhzScaled = 0x64000000;
 890         struct chan_centers centers;
 891
 892         /*
 893          * half and quarter rate can divide the scaled clock by 2 or 4
 894          * scale for selected channel bandwidth
 895          */
 896         if (IS_CHAN_HALF_RATE(chan))
 897                 clockMhzScaled = clockMhzScaled >> 1;
 898         else if (IS_CHAN_QUARTER_RATE(chan))
 899                 clockMhzScaled = clockMhzScaled >> 2;
 900
 901         /*
 902          * ALGO -> coef = 1e8/fcarrier*fclock/40;
 903          * scaled coef to provide precision for this floating calculation
 904          */
 905         ath9k_hw_get_channel_centers(ah, chan, &centers);
 906         coef_scaled = clockMhzScaled / centers.synth_center;
 907
 908         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 909                                       &ds_coef_exp);
 910
 911         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 912                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
 913         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 914                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
 915
 916         /*
 917          * For Short GI,
 918          * scaled coeff is 9/10 that of normal coeff
 919          */
 920         coef_scaled = (9 * coef_scaled) / 10;
 921
 922         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 923                                       &ds_coef_exp);
 924
 925         /* for short gi */
 926         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 927                       AR_PHY_SGI_DSC_MAN, ds_coef_man);
 928         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 929                       AR_PHY_SGI_DSC_EXP, ds_coef_exp);
 930 }
 931
 932 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
 933 {
 934         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
 935         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
 936                              AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
 937 }
 938
 939 /*
 940  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
 941  * Read the phy active delay register. Value is in 100ns increments.
 942  */
 943 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
 944 {
 945         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 946
 947         ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
 948
 949         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 950 }
 951
 952 static bool ar9003_hw_ani_control(struct ath_hw *ah,
 953                                   enum ath9k_ani_cmd cmd, int param)
 954 {
 955         struct ath_common *common = ath9k_hw_common(ah);
 956         struct ath9k_channel *chan = ah->curchan;
 957         struct ar5416AniState *aniState = &ah->ani;
 958         int m1ThreshLow, m2ThreshLow;
 959         int m1Thresh, m2Thresh;
 960         int m2CountThr, m2CountThrLow;
 961         int m1ThreshLowExt, m2ThreshLowExt;
 962         int m1ThreshExt, m2ThreshExt;
 963         s32 value, value2;
 964
 965         switch (cmd & ah->ani_function) {
 966         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
 967                 /*
 968                  * on == 1 means ofdm weak signal detection is ON
 969                  * on == 1 is the default, for less noise immunity
 970                  *
 971                  * on == 0 means ofdm weak signal detection is OFF
 972                  * on == 0 means more noise imm
 973                  */
 974                 u32 on = param ? 1 : 0;
 975
 976                 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
 977                         goto skip_ws_det;
 978
 979                 m1ThreshLow = on ?
 980                         aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
 981                 m2ThreshLow = on ?
 982                         aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
 983                 m1Thresh = on ?
 984                         aniState->iniDef.m1Thresh : m1Thresh_off;
 985                 m2Thresh = on ?
 986                         aniState->iniDef.m2Thresh : m2Thresh_off;
 987                 m2CountThr = on ?
 988                         aniState->iniDef.m2CountThr : m2CountThr_off;
 989                 m2CountThrLow = on ?
 990                         aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
 991                 m1ThreshLowExt = on ?
 992                         aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
 993                 m2ThreshLowExt = on ?
 994                         aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
 995                 m1ThreshExt = on ?
 996                         aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
 997                 m2ThreshExt = on ?
 998                         aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
 999
1000                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1001                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1002                               m1ThreshLow);
1003                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1004                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1005                               m2ThreshLow);
1006                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1007                               AR_PHY_SFCORR_M1_THRESH,
1008                               m1Thresh);
1009                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1010                               AR_PHY_SFCORR_M2_THRESH,
1011                               m2Thresh);
1012                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1013                               AR_PHY_SFCORR_M2COUNT_THR,
1014                               m2CountThr);
1015                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1016                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1017                               m2CountThrLow);
1018                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1019                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1020                               m1ThreshLowExt);
1021                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1022                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1023                               m2ThreshLowExt);
1024                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1025                               AR_PHY_SFCORR_EXT_M1_THRESH,
1026                               m1ThreshExt);
1027                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1028                               AR_PHY_SFCORR_EXT_M2_THRESH,
1029                               m2ThreshExt);
1030 skip_ws_det:
1031                 if (on)
1032                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1033                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1034                 else
1035                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1036                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1037
1038                 if (on != aniState->ofdmWeakSigDetect) {
1039                         ath_dbg(common, ANI,
1040                                 "** ch %d: ofdm weak signal: %s=>%s\n",
1041                                 chan->channel,
1042                                 aniState->ofdmWeakSigDetect ?
1043                                 "on" : "off",
1044                                 on ? "on" : "off");
1045                         if (on)
1046                                 ah->stats.ast_ani_ofdmon++;
1047                         else
1048                                 ah->stats.ast_ani_ofdmoff++;
1049                         aniState->ofdmWeakSigDetect = on;
1050                 }
1051                 break;
1052         }
1053         case ATH9K_ANI_FIRSTEP_LEVEL:{
1054                 u32 level = param;
1055
1056                 if (level >= ARRAY_SIZE(firstep_table)) {
1057                         ath_dbg(common, ANI,
1058                                 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1059                                 level, ARRAY_SIZE(firstep_table));
1060                         return false;
1061                 }
1062
1063                 /*
1064                  * make register setting relative to default
1065                  * from INI file & cap value
1066                  */
1067                 value = firstep_table[level] -
1068                         firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1069                         aniState->iniDef.firstep;
1070                 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1071                         value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1072                 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1073                         value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1074                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1075                               AR_PHY_FIND_SIG_FIRSTEP,
1076                               value);
1077                 /*
1078                  * we need to set first step low register too
1079                  * make register setting relative to default
1080                  * from INI file & cap value
1081                  */
1082                 value2 = firstep_table[level] -
1083                          firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1084                          aniState->iniDef.firstepLow;
1085                 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1086                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1087                 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1088                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1089
1090                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1091                               AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1092
1093                 if (level != aniState->firstepLevel) {
1094                         ath_dbg(common, ANI,
1095                                 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1096                                 chan->channel,
1097                                 aniState->firstepLevel,
1098                                 level,
1099                                 ATH9K_ANI_FIRSTEP_LVL,
1100                                 value,
1101                                 aniState->iniDef.firstep);
1102                         ath_dbg(common, ANI,
1103                                 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1104                                 chan->channel,
1105                                 aniState->firstepLevel,
1106                                 level,
1107                                 ATH9K_ANI_FIRSTEP_LVL,
1108                                 value2,
1109                                 aniState->iniDef.firstepLow);
1110                         if (level > aniState->firstepLevel)
1111                                 ah->stats.ast_ani_stepup++;
1112                         else if (level < aniState->firstepLevel)
1113                                 ah->stats.ast_ani_stepdown++;
1114                         aniState->firstepLevel = level;
1115                 }
1116                 break;
1117         }
1118         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1119                 u32 level = param;
1120
1121                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1122                         ath_dbg(common, ANI,
1123                                 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1124                                 level, ARRAY_SIZE(cycpwrThr1_table));
1125                         return false;
1126                 }
1127                 /*
1128                  * make register setting relative to default
1129                  * from INI file & cap value
1130                  */
1131                 value = cycpwrThr1_table[level] -
1132                         cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1133                         aniState->iniDef.cycpwrThr1;
1134                 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1135                         value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1136                 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1137                         value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1138                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1139                               AR_PHY_TIMING5_CYCPWR_THR1,
1140                               value);
1141
1142                 /*
1143                  * set AR_PHY_EXT_CCA for extension channel
1144                  * make register setting relative to default
1145                  * from INI file & cap value
1146                  */
1147                 value2 = cycpwrThr1_table[level] -
1148                          cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1149                          aniState->iniDef.cycpwrThr1Ext;
1150                 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1151                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1152                 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1153                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1154                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1155                               AR_PHY_EXT_CYCPWR_THR1, value2);
1156
1157                 if (level != aniState->spurImmunityLevel) {
1158                         ath_dbg(common, ANI,
1159                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1160                                 chan->channel,
1161                                 aniState->spurImmunityLevel,
1162                                 level,
1163                                 ATH9K_ANI_SPUR_IMMUNE_LVL,
1164                                 value,
1165                                 aniState->iniDef.cycpwrThr1);
1166                         ath_dbg(common, ANI,
1167                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1168                                 chan->channel,
1169                                 aniState->spurImmunityLevel,
1170                                 level,
1171                                 ATH9K_ANI_SPUR_IMMUNE_LVL,
1172                                 value2,
1173                                 aniState->iniDef.cycpwrThr1Ext);
1174                         if (level > aniState->spurImmunityLevel)
1175                                 ah->stats.ast_ani_spurup++;
1176                         else if (level < aniState->spurImmunityLevel)
1177                                 ah->stats.ast_ani_spurdown++;
1178                         aniState->spurImmunityLevel = level;
1179                 }
1180                 break;
1181         }
1182         case ATH9K_ANI_MRC_CCK:{
1183                 /*
1184                  * is_on == 1 means MRC CCK ON (default, less noise imm)
1185                  * is_on == 0 means MRC CCK is OFF (more noise imm)
1186                  */
1187                 bool is_on = param ? 1 : 0;
1188
1189                 if (ah->caps.rx_chainmask == 1)
1190                         break;
1191
1192                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1193                               AR_PHY_MRC_CCK_ENABLE, is_on);
1194                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1195                               AR_PHY_MRC_CCK_MUX_REG, is_on);
1196                 if (is_on != aniState->mrcCCK) {
1197                         ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1198                                 chan->channel,
1199                                 aniState->mrcCCK ? "on" : "off",
1200                                 is_on ? "on" : "off");
1201                 if (is_on)
1202                         ah->stats.ast_ani_ccklow++;
1203                 else
1204                         ah->stats.ast_ani_cckhigh++;
1205                 aniState->mrcCCK = is_on;
1206                 }
1207         break;
1208         }
1209         default:
1210                 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1211                 return false;
1212         }
1213
1214         ath_dbg(common, ANI,
1215                 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1216                 aniState->spurImmunityLevel,
1217                 aniState->ofdmWeakSigDetect ? "on" : "off",
1218                 aniState->firstepLevel,
1219                 aniState->mrcCCK ? "on" : "off",
1220                 aniState->listenTime,
1221                 aniState->ofdmPhyErrCount,
1222                 aniState->cckPhyErrCount);
1223         return true;
1224 }
1225
1226 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1227                               int16_t nfarray[NUM_NF_READINGS])
1228 {
1229 #define AR_PHY_CH_MINCCA_PWR    0x1FF00000
1230 #define AR_PHY_CH_MINCCA_PWR_S  20
1231 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1232 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1233
1234         int16_t nf;
1235         int i;
1236
1237         for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1238                 if (ah->rxchainmask & BIT(i)) {
1239                         nf = MS(REG_READ(ah, ah->nf_regs[i]),
1240                                          AR_PHY_CH_MINCCA_PWR);
1241                         nfarray[i] = sign_extend32(nf, 8);
1242
1243                         if (IS_CHAN_HT40(ah->curchan)) {
1244                                 u8 ext_idx = AR9300_MAX_CHAINS + i;
1245
1246                                 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1247                                                  AR_PHY_CH_EXT_MINCCA_PWR);
1248                                 nfarray[ext_idx] = sign_extend32(nf, 8);
1249                         }
1250                 }
1251         }
1252 }
1253
1254 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1255 {
1256         ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1257         ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1258         ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1259         ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1260         ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1261         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1262
1263         if (AR_SREV_9330(ah))
1264                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1265
1266         if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1267                 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1268                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1269                 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1270                 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1271         }
1272 }
1273
1274 /*
1275  * Initialize the ANI register values with default (ini) values.
1276  * This routine is called during a (full) hardware reset after
1277  * all the registers are initialised from the INI.
1278  */
1279 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1280 {
1281         struct ar5416AniState *aniState;
1282         struct ath_common *common = ath9k_hw_common(ah);
1283         struct ath9k_channel *chan = ah->curchan;
1284         struct ath9k_ani_default *iniDef;
1285         u32 val;
1286
1287         aniState = &ah->ani;
1288         iniDef = &aniState->iniDef;
1289
1290         ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
1291                 ah->hw_version.macVersion,
1292                 ah->hw_version.macRev,
1293                 ah->opmode,
1294                 chan->channel);
1295
1296         val = REG_READ(ah, AR_PHY_SFCORR);
1297         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1298         iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1299         iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1300
1301         val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1302         iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1303         iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1304         iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1305
1306         val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1307         iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1308         iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1309         iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1310         iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1311         iniDef->firstep = REG_READ_FIELD(ah,
1312                                          AR_PHY_FIND_SIG,
1313                                          AR_PHY_FIND_SIG_FIRSTEP);
1314         iniDef->firstepLow = REG_READ_FIELD(ah,
1315                                             AR_PHY_FIND_SIG_LOW,
1316                                             AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1317         iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1318                                             AR_PHY_TIMING5,
1319                                             AR_PHY_TIMING5_CYCPWR_THR1);
1320         iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1321                                                AR_PHY_EXT_CCA,
1322                                                AR_PHY_EXT_CYCPWR_THR1);
1323
1324         /* these levels just got reset to defaults by the INI */
1325         aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1326         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1327         aniState->ofdmWeakSigDetect = true;
1328         aniState->mrcCCK = true;
1329 }
1330
1331 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1332                                        struct ath_hw_radar_conf *conf)
1333 {
1334         u32 radar_0 = 0, radar_1 = 0;
1335
1336         if (!conf) {
1337                 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1338                 return;
1339         }
1340
1341         radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1342         radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1343         radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1344         radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1345         radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1346         radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1347
1348         radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1349         radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1350         radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1351         radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1352         radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1353
1354         REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1355         REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1356         if (conf->ext_channel)
1357                 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1358         else
1359                 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1360 }
1361
1362 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1363 {
1364         struct ath_hw_radar_conf *conf = &ah->radar_conf;
1365
1366         conf->fir_power = -28;
1367         conf->radar_rssi = 0;
1368         conf->pulse_height = 10;
1369         conf->pulse_rssi = 24;
1370         conf->pulse_inband = 8;
1371         conf->pulse_maxlen = 255;
1372         conf->pulse_inband_step = 12;
1373         conf->radar_inband = 8;
1374 }
1375
1376 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1377                                            struct ath_hw_antcomb_conf *antconf)
1378 {
1379         u32 regval;
1380
1381         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1382         antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1383                                   AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1384         antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1385                                  AR_PHY_ANT_DIV_ALT_LNACONF_S;
1386         antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1387                                   AR_PHY_ANT_FAST_DIV_BIAS_S;
1388
1389         if (AR_SREV_9330_11(ah)) {
1390                 antconf->lna1_lna2_switch_delta = -1;
1391                 antconf->lna1_lna2_delta = -9;
1392                 antconf->div_group = 1;
1393         } else if (AR_SREV_9485(ah)) {
1394                 antconf->lna1_lna2_switch_delta = -1;
1395                 antconf->lna1_lna2_delta = -9;
1396                 antconf->div_group = 2;
1397         } else if (AR_SREV_9565(ah)) {
1398                 antconf->lna1_lna2_switch_delta = 3;
1399                 antconf->lna1_lna2_delta = -9;
1400                 antconf->div_group = 3;
1401         } else {
1402                 antconf->lna1_lna2_switch_delta = -1;
1403                 antconf->lna1_lna2_delta = -3;
1404                 antconf->div_group = 0;
1405         }
1406 }
1407
1408 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1409                                    struct ath_hw_antcomb_conf *antconf)
1410 {
1411         u32 regval;
1412
1413         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1414         regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1415                     AR_PHY_ANT_DIV_ALT_LNACONF |
1416                     AR_PHY_ANT_FAST_DIV_BIAS |
1417                     AR_PHY_ANT_DIV_MAIN_GAINTB |
1418                     AR_PHY_ANT_DIV_ALT_GAINTB);
1419         regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1420                    & AR_PHY_ANT_DIV_MAIN_LNACONF);
1421         regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1422                    & AR_PHY_ANT_DIV_ALT_LNACONF);
1423         regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1424                    & AR_PHY_ANT_FAST_DIV_BIAS);
1425         regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1426                    & AR_PHY_ANT_DIV_MAIN_GAINTB);
1427         regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1428                    & AR_PHY_ANT_DIV_ALT_GAINTB);
1429
1430         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1431 }
1432
1433 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1434
1435 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
1436 {
1437         struct ath9k_hw_capabilities *pCap = &ah->caps;
1438         u8 ant_div_ctl1;
1439         u32 regval;
1440
1441         if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah))
1442                 return;
1443
1444         if (AR_SREV_9485(ah)) {
1445                 regval = ar9003_hw_ant_ctrl_common_2_get(ah,
1446                                                  IS_CHAN_2GHZ(ah->curchan));
1447                 if (enable) {
1448                         regval &= ~AR_SWITCH_TABLE_COM2_ALL;
1449                         regval |= ah->config.ant_ctrl_comm2g_switch_enable;
1450                 }
1451                 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2,
1452                               AR_SWITCH_TABLE_COM2_ALL, regval);
1453         }
1454
1455         ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1456
1457         /*
1458          * Set MAIN/ALT LNA conf.
1459          * Set MAIN/ALT gain_tb.
1460          */
1461         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1462         regval &= (~AR_ANT_DIV_CTRL_ALL);
1463         regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1464         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1465
1466         if (AR_SREV_9485_11_OR_LATER(ah)) {
1467                 /*
1468                  * Enable LNA diversity.
1469                  */
1470                 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1471                 regval &= ~AR_PHY_ANT_DIV_LNADIV;
1472                 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1473                 if (enable)
1474                         regval |= AR_ANT_DIV_ENABLE;
1475
1476                 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1477
1478                 /*
1479                  * Enable fast antenna diversity.
1480                  */
1481                 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1482                 regval &= ~AR_FAST_DIV_ENABLE;
1483                 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1484                 if (enable)
1485                         regval |= AR_FAST_DIV_ENABLE;
1486
1487                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1488
1489                 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
1490                         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1491                         regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1492                                      AR_PHY_ANT_DIV_ALT_LNACONF |
1493                                      AR_PHY_ANT_DIV_ALT_GAINTB |
1494                                      AR_PHY_ANT_DIV_MAIN_GAINTB));
1495                         /*
1496                          * Set MAIN to LNA1 and ALT to LNA2 at the
1497                          * beginning.
1498                          */
1499                         regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1500                                    AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1501                         regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1502                                    AR_PHY_ANT_DIV_ALT_LNACONF_S);
1503                         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1504                 }
1505         } else if (AR_SREV_9565(ah)) {
1506                 if (enable) {
1507                         REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1508                                     AR_ANT_DIV_ENABLE);
1509                         REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1510                                     (1 << AR_PHY_ANT_SW_RX_PROT_S));
1511                         REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
1512                                     AR_FAST_DIV_ENABLE);
1513                         REG_SET_BIT(ah, AR_PHY_RESTART,
1514                                     AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1515                         REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1516                                     AR_BTCOEX_WL_LNADIV_FORCE_ON);
1517                 } else {
1518                         REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1519                                     AR_ANT_DIV_ENABLE);
1520                         REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1521                                     (1 << AR_PHY_ANT_SW_RX_PROT_S));
1522                         REG_CLR_BIT(ah, AR_PHY_CCK_DETECT,
1523                                     AR_FAST_DIV_ENABLE);
1524                         REG_CLR_BIT(ah, AR_PHY_RESTART,
1525                                     AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1526                         REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1527                                     AR_BTCOEX_WL_LNADIV_FORCE_ON);
1528
1529                         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1530                         regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1531                                     AR_PHY_ANT_DIV_ALT_LNACONF |
1532                                     AR_PHY_ANT_DIV_MAIN_GAINTB |
1533                                     AR_PHY_ANT_DIV_ALT_GAINTB);
1534                         regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1535                                    AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1536                         regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1537                                    AR_PHY_ANT_DIV_ALT_LNACONF_S);
1538                         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1539                 }
1540         }
1541 }
1542
1543 #endif
1544
1545 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1546                                       struct ath9k_channel *chan,
1547                                       u8 *ini_reloaded)
1548 {
1549         unsigned int regWrites = 0;
1550         u32 modesIndex;
1551
1552         if (IS_CHAN_5GHZ(chan))
1553                 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
1554         else
1555                 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
1556
1557         if (modesIndex == ah->modes_index) {
1558                 *ini_reloaded = false;
1559                 goto set_rfmode;
1560         }
1561
1562         ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1563         ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1564         ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1565         ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1566
1567         if (AR_SREV_9462_20_OR_LATER(ah))
1568                 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1569                                    modesIndex);
1570
1571         REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1572
1573         if (AR_SREV_9462_20_OR_LATER(ah)) {
1574                 /*
1575                  * CUS217 mix LNA mode.
1576                  */
1577                 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
1578                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
1579                                         1, regWrites);
1580                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
1581                                         modesIndex, regWrites);
1582                 }
1583         }
1584
1585         /*
1586          * For 5GHz channels requiring Fast Clock, apply
1587          * different modal values.
1588          */
1589         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1590                 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1591
1592         if (AR_SREV_9565(ah))
1593                 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1594
1595         /*
1596          * JAPAN regulatory.
1597          */
1598         if (chan->channel == 2484)
1599                 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
1600
1601         ah->modes_index = modesIndex;
1602         *ini_reloaded = true;
1603
1604 set_rfmode:
1605         ar9003_hw_set_rfmode(ah, chan);
1606         return 0;
1607 }
1608
1609 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1610                                            struct ath_spec_scan *param)
1611 {
1612         u8 count;
1613
1614         if (!param->enabled) {
1615                 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1616                             AR_PHY_SPECTRAL_SCAN_ENABLE);
1617                 return;
1618         }
1619
1620         REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1621         REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1622
1623         /* on AR93xx and newer, count = 0 will make the the chip send
1624          * spectral samples endlessly. Check if this really was intended,
1625          * and fix otherwise.
1626          */
1627         count = param->count;
1628         if (param->endless)
1629                 count = 0;
1630         else if (param->count == 0)
1631                 count = 1;
1632
1633         if (param->short_repeat)
1634                 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1635                             AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1636         else
1637                 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1638                             AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1639
1640         REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1641                       AR_PHY_SPECTRAL_SCAN_COUNT, count);
1642         REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1643                       AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1644         REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1645                       AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1646
1647         return;
1648 }
1649
1650 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1651 {
1652         /* Activate spectral scan */
1653         REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1654                     AR_PHY_SPECTRAL_SCAN_ACTIVE);
1655 }
1656
1657 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1658 {
1659         struct ath_common *common = ath9k_hw_common(ah);
1660
1661         /* Poll for spectral scan complete */
1662         if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1663                            AR_PHY_SPECTRAL_SCAN_ACTIVE,
1664                            0, AH_WAIT_TIMEOUT)) {
1665                 ath_err(common, "spectral scan wait failed\n");
1666                 return;
1667         }
1668 }
1669
1670 static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum)
1671 {
1672         REG_SET_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR);
1673         REG_SET_BIT(ah, 0x9864, 0x7f000);
1674         REG_SET_BIT(ah, 0x9924, 0x7f00fe);
1675         REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1676         REG_WRITE(ah, AR_CR, AR_CR_RXD);
1677         REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
1678         REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */
1679         REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
1680         REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
1681         REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
1682         REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ);
1683 }
1684
1685 static void ar9003_hw_tx99_stop(struct ath_hw *ah)
1686 {
1687         REG_CLR_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR);
1688         REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1689 }
1690
1691 static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower)
1692 {
1693         static s16 p_pwr_array[ar9300RateSize] = { 0 };
1694         unsigned int i;
1695
1696         if (txpower <= MAX_RATE_POWER) {
1697                 for (i = 0; i < ar9300RateSize; i++)
1698                         p_pwr_array[i] = txpower;
1699         } else {
1700                 for (i = 0; i < ar9300RateSize; i++)
1701                         p_pwr_array[i] = MAX_RATE_POWER;
1702         }
1703
1704         REG_WRITE(ah, 0xa458, 0);
1705
1706         REG_WRITE(ah, 0xa3c0,
1707                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) |
1708                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) |
1709                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24],  8) |
1710                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24],  0));
1711         REG_WRITE(ah, 0xa3c4,
1712                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_54],  24) |
1713                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_48],  16) |
1714                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_36],   8) |
1715                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0));
1716         REG_WRITE(ah, 0xa3c8,
1717                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) |
1718                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) |
1719                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L],  0));
1720         REG_WRITE(ah, 0xa3cc,
1721                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11S],   24) |
1722                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11L],   16) |
1723                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_5S],     8) |
1724                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L],  0));
1725         REG_WRITE(ah, 0xa3d0,
1726                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_5],  24) |
1727                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_4],  16) |
1728                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8)|
1729                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0));
1730         REG_WRITE(ah, 0xa3d4,
1731                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_13], 24) |
1732                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_12], 16) |
1733                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_7],   8) |
1734                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_6],   0));
1735         REG_WRITE(ah, 0xa3e4,
1736                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_21], 24) |
1737                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_20], 16) |
1738                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_15],  8) |
1739                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_14],  0));
1740         REG_WRITE(ah, 0xa3e8,
1741                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_23], 24) |
1742                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_22], 16) |
1743                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_23],  8) |
1744                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_22],  0));
1745         REG_WRITE(ah, 0xa3d8,
1746                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_5], 24) |
1747                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_4], 16) |
1748                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
1749                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0));
1750         REG_WRITE(ah, 0xa3dc,
1751                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_13], 24) |
1752                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_12], 16) |
1753                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_7],   8) |
1754                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_6],   0));
1755         REG_WRITE(ah, 0xa3ec,
1756                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_21], 24) |
1757                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_20], 16) |
1758                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_15],  8) |
1759                   ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_14],  0));
1760 }
1761
1762 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1763 {
1764         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1765         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1766         static const u32 ar9300_cca_regs[6] = {
1767                 AR_PHY_CCA_0,
1768                 AR_PHY_CCA_1,
1769                 AR_PHY_CCA_2,
1770                 AR_PHY_EXT_CCA,
1771                 AR_PHY_EXT_CCA_1,
1772                 AR_PHY_EXT_CCA_2,
1773         };
1774
1775         priv_ops->rf_set_freq = ar9003_hw_set_channel;
1776         priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1777         priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1778         priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1779         priv_ops->init_bb = ar9003_hw_init_bb;
1780         priv_ops->process_ini = ar9003_hw_process_ini;
1781         priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1782         priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1783         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1784         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1785         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1786         priv_ops->ani_control = ar9003_hw_ani_control;
1787         priv_ops->do_getnf = ar9003_hw_do_getnf;
1788         priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1789         priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1790         priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1791
1792         ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1793         ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1794         ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
1795         ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
1796         ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
1797
1798 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1799         ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity;
1800 #endif
1801         ops->tx99_start = ar9003_hw_tx99_start;
1802         ops->tx99_stop = ar9003_hw_tx99_stop;
1803         ops->tx99_set_txpower = ar9003_hw_tx99_set_txpower;
1804
1805         ar9003_hw_set_nf_limits(ah);
1806         ar9003_hw_set_radar_conf(ah);
1807         memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1808 }
1809
1810 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1811 {
1812         struct ath_common *common = ath9k_hw_common(ah);
1813         u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1814         u32 val, idle_count;
1815
1816         if (!idle_tmo_ms) {
1817                 /* disable IRQ, disable chip-reset for BB panic */
1818                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1819                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1820                           ~(AR_PHY_WATCHDOG_RST_ENABLE |
1821                             AR_PHY_WATCHDOG_IRQ_ENABLE));
1822
1823                 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1824                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1825                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1826                           ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1827                             AR_PHY_WATCHDOG_IDLE_ENABLE));
1828
1829                 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
1830                 return;
1831         }
1832
1833         /* enable IRQ, disable chip-reset for BB watchdog */
1834         val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1835         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1836                   (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1837                   ~AR_PHY_WATCHDOG_RST_ENABLE);
1838
1839         /* bound limit to 10 secs */
1840         if (idle_tmo_ms > 10000)
1841                 idle_tmo_ms = 10000;
1842
1843         /*
1844          * The time unit for watchdog event is 2^15 44/88MHz cycles.
1845          *
1846          * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1847          * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1848          *
1849          * Given we use fast clock now in 5 GHz, these time units should
1850          * be common for both 2 GHz and 5 GHz.
1851          */
1852         idle_count = (100 * idle_tmo_ms) / 74;
1853         if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1854                 idle_count = (100 * idle_tmo_ms) / 37;
1855
1856         /*
1857          * enable watchdog in non-IDLE mode, disable in IDLE mode,
1858          * set idle time-out.
1859          */
1860         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1861                   AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1862                   AR_PHY_WATCHDOG_IDLE_MASK |
1863                   (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1864
1865         ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
1866                 idle_tmo_ms);
1867 }
1868
1869 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1870 {
1871         /*
1872          * we want to avoid printing in ISR context so we save the
1873          * watchdog status to be printed later in bottom half context.
1874          */
1875         ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1876
1877         /*
1878          * the watchdog timer should reset on status read but to be sure
1879          * sure we write 0 to the watchdog status bit.
1880          */
1881         REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1882                   ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1883 }
1884
1885 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1886 {
1887         struct ath_common *common = ath9k_hw_common(ah);
1888         u32 status;
1889
1890         if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1891                 return;
1892
1893         status = ah->bb_watchdog_last_status;
1894         ath_dbg(common, RESET,
1895                 "\n==== BB update: BB status=0x%08x ====\n", status);
1896         ath_dbg(common, RESET,
1897                 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1898                 MS(status, AR_PHY_WATCHDOG_INFO),
1899                 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1900                 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1901                 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1902                 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1903                 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1904                 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1905                 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1906                 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1907
1908         ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1909                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1910                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1911         ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
1912                 REG_READ(ah, AR_PHY_GEN_CTRL));
1913
1914 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1915         if (common->cc_survey.cycles)
1916                 ath_dbg(common, RESET,
1917                         "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1918                         PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1919
1920         ath_dbg(common, RESET, "==== BB update: done ====\n\n");
1921 }
1922 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
1923
1924 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1925 {
1926         u32 val;
1927
1928         /* While receiving unsupported rate frame rx state machine
1929          * gets into a state 0xb and if phy_restart happens in that
1930          * state, BB would go hang. If RXSM is in 0xb state after
1931          * first bb panic, ensure to disable the phy_restart.
1932          */
1933         if (!((MS(ah->bb_watchdog_last_status,
1934                   AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1935             ah->bb_hang_rx_ofdm))
1936                 return;
1937
1938         ah->bb_hang_rx_ofdm = true;
1939         val = REG_READ(ah, AR_PHY_RESTART);
1940         val &= ~AR_PHY_RESTART_ENA;
1941
1942         REG_WRITE(ah, AR_PHY_RESTART, val);
1943 }
1944 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);