2 * Intel IXP4xx Ethernet driver for Linux
4 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
10 * Ethernet port config (0x00 is not present on IXP42X):
12 * logical port 0x00 0x10 0x20
13 * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
14 * physical PortId 2 0 1
16 * RX-free queue 26 27 28
17 * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
21 * bits 0 -> 1 - NPE ID (RX and TX-done)
22 * bits 0 -> 2 - priority (TX, per 802.1D)
23 * bits 3 -> 4 - port ID (user-set?)
24 * bits 5 -> 31 - physical descriptor address
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/dmapool.h>
30 #include <linux/etherdevice.h>
32 #include <linux/kernel.h>
33 #include <linux/net_tstamp.h>
34 #include <linux/phy.h>
35 #include <linux/platform_device.h>
36 #include <linux/ptp_classify.h>
37 #include <linux/slab.h>
38 #include <linux/module.h>
39 #include <mach/ixp46x_ts.h>
41 #include <mach/qmgr.h>
46 #define DEBUG_PKT_BYTES 0
50 #define DRV_NAME "ixp4xx_eth"
54 #define RX_DESCS 64 /* also length of all RX queues */
55 #define TX_DESCS 16 /* also length of all TX queues */
56 #define TXDONE_QUEUE_LEN 64 /* dwords */
58 #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
59 #define REGS_SIZE 0x1000
60 #define MAX_MRU 1536 /* 0x600 */
61 #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
63 #define NAPI_WEIGHT 16
64 #define MDIO_INTERVAL (3 * HZ)
65 #define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */
66 #define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */
68 #define NPE_ID(port_id) ((port_id) >> 4)
69 #define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3)
70 #define TX_QUEUE(port_id) (NPE_ID(port_id) + 23)
71 #define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
72 #define TXDONE_QUEUE 31
74 #define PTP_SLAVE_MODE 1
75 #define PTP_MASTER_MODE 2
76 #define PORT2CHANNEL(p) NPE_ID(p->id)
78 /* TX Control Registers */
79 #define TX_CNTRL0_TX_EN 0x01
80 #define TX_CNTRL0_HALFDUPLEX 0x02
81 #define TX_CNTRL0_RETRY 0x04
82 #define TX_CNTRL0_PAD_EN 0x08
83 #define TX_CNTRL0_APPEND_FCS 0x10
84 #define TX_CNTRL0_2DEFER 0x20
85 #define TX_CNTRL0_RMII 0x40 /* reduced MII */
86 #define TX_CNTRL1_RETRIES 0x0F /* 4 bits */
88 /* RX Control Registers */
89 #define RX_CNTRL0_RX_EN 0x01
90 #define RX_CNTRL0_PADSTRIP_EN 0x02
91 #define RX_CNTRL0_SEND_FCS 0x04
92 #define RX_CNTRL0_PAUSE_EN 0x08
93 #define RX_CNTRL0_LOOP_EN 0x10
94 #define RX_CNTRL0_ADDR_FLTR_EN 0x20
95 #define RX_CNTRL0_RX_RUNT_EN 0x40
96 #define RX_CNTRL0_BCAST_DIS 0x80
97 #define RX_CNTRL1_DEFER_EN 0x01
99 /* Core Control Register */
100 #define CORE_RESET 0x01
101 #define CORE_RX_FIFO_FLUSH 0x02
102 #define CORE_TX_FIFO_FLUSH 0x04
103 #define CORE_SEND_JAM 0x08
104 #define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */
106 #define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \
107 TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
109 #define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN
110 #define DEFAULT_CORE_CNTRL CORE_MDC_EN
113 /* NPE message codes */
114 #define NPE_GETSTATUS 0x00
115 #define NPE_EDB_SETPORTADDRESS 0x01
116 #define NPE_EDB_GETMACADDRESSDATABASE 0x02
117 #define NPE_EDB_SETMACADDRESSSDATABASE 0x03
118 #define NPE_GETSTATS 0x04
119 #define NPE_RESETSTATS 0x05
120 #define NPE_SETMAXFRAMELENGTHS 0x06
121 #define NPE_VLAN_SETRXTAGMODE 0x07
122 #define NPE_VLAN_SETDEFAULTRXVID 0x08
123 #define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09
124 #define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A
125 #define NPE_VLAN_SETRXQOSENTRY 0x0B
126 #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
127 #define NPE_STP_SETBLOCKINGSTATE 0x0D
128 #define NPE_FW_SETFIREWALLMODE 0x0E
129 #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
130 #define NPE_PC_SETAPMACTABLE 0x11
131 #define NPE_SETLOOPBACK_MODE 0x12
132 #define NPE_PC_SETBSSIDTABLE 0x13
133 #define NPE_ADDRESS_FILTER_CONFIG 0x14
134 #define NPE_APPENDFCSCONFIG 0x15
135 #define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16
136 #define NPE_MAC_RECOVERY_START 0x17
140 typedef struct sk_buff buffer_t;
141 #define free_buffer dev_kfree_skb
142 #define free_buffer_irq dev_kfree_skb_irq
144 typedef void buffer_t;
145 #define free_buffer kfree
146 #define free_buffer_irq kfree
150 u32 tx_control[2], __res1[2]; /* 000 */
151 u32 rx_control[2], __res2[2]; /* 010 */
152 u32 random_seed, __res3[3]; /* 020 */
153 u32 partial_empty_threshold, __res4; /* 030 */
154 u32 partial_full_threshold, __res5; /* 038 */
155 u32 tx_start_bytes, __res6[3]; /* 040 */
156 u32 tx_deferral, rx_deferral, __res7[2];/* 050 */
157 u32 tx_2part_deferral[2], __res8[2]; /* 060 */
158 u32 slot_time, __res9[3]; /* 070 */
159 u32 mdio_command[4]; /* 080 */
160 u32 mdio_status[4]; /* 090 */
161 u32 mcast_mask[6], __res10[2]; /* 0A0 */
162 u32 mcast_addr[6], __res11[2]; /* 0C0 */
163 u32 int_clock_threshold, __res12[3]; /* 0E0 */
164 u32 hw_addr[6], __res13[61]; /* 0F0 */
165 u32 core_control; /* 1FC */
169 struct resource *mem_res;
170 struct eth_regs __iomem *regs;
172 struct net_device *netdev;
173 struct napi_struct napi;
174 struct phy_device *phydev;
175 struct eth_plat_info *plat;
176 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
177 struct desc *desc_tab; /* coherent */
179 int id; /* logical port ID */
186 /* NPE message structure */
189 u8 cmd, eth_id, byte2, byte3;
190 u8 byte4, byte5, byte6, byte7;
192 u8 byte3, byte2, eth_id, cmd;
193 u8 byte7, byte6, byte5, byte4;
197 /* Ethernet packet descriptor */
199 u32 next; /* pointer to next buffer, unused */
202 u16 buf_len; /* buffer length */
203 u16 pkt_len; /* packet length */
204 u32 data; /* pointer to data buffer in RAM */
212 u16 pkt_len; /* packet length */
213 u16 buf_len; /* buffer length */
214 u32 data; /* pointer to data buffer in RAM */
224 u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
225 u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
226 u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
228 u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
229 u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
230 u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
235 #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
236 (n) * sizeof(struct desc))
237 #define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
239 #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
240 ((n) + RX_DESCS) * sizeof(struct desc))
241 #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
244 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
247 for (i = 0; i < cnt; i++)
248 dest[i] = swab32(src[i]);
252 static spinlock_t mdio_lock;
253 static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
254 static struct mii_bus *mdio_bus;
255 static int ports_open;
256 static struct port *npe_port_tab[MAX_NPES];
257 static struct dma_pool *dma_pool;
259 static struct sock_filter ptp_filter[] = {
263 static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
265 u8 *data = skb->data;
270 if (sk_run_filter(skb, ptp_filter) != PTP_CLASS_V1_IPV4)
273 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
275 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
278 hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
279 id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
281 memcpy(&lo, &hi[1], sizeof(lo));
283 return (uid_hi == ntohs(*hi) &&
284 uid_lo == ntohl(lo) &&
285 seqid == ntohs(*id));
288 static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb)
290 struct skb_shared_hwtstamps *shhwtstamps;
291 struct ixp46x_ts_regs *regs;
296 if (!port->hwts_rx_en)
299 ch = PORT2CHANNEL(port);
301 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
303 val = __raw_readl(®s->channel[ch].ch_event);
305 if (!(val & RX_SNAPSHOT_LOCKED))
308 lo = __raw_readl(®s->channel[ch].src_uuid_lo);
309 hi = __raw_readl(®s->channel[ch].src_uuid_hi);
312 seq = (hi >> 16) & 0xffff;
314 if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
317 lo = __raw_readl(®s->channel[ch].rx_snap_lo);
318 hi = __raw_readl(®s->channel[ch].rx_snap_hi);
319 ns = ((u64) hi) << 32;
321 ns <<= TICKS_NS_SHIFT;
323 shhwtstamps = skb_hwtstamps(skb);
324 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
325 shhwtstamps->hwtstamp = ns_to_ktime(ns);
327 __raw_writel(RX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event);
330 static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb)
332 struct skb_shared_hwtstamps shhwtstamps;
333 struct ixp46x_ts_regs *regs;
334 struct skb_shared_info *shtx;
336 u32 ch, cnt, hi, lo, val;
338 shtx = skb_shinfo(skb);
339 if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en))
340 shtx->tx_flags |= SKBTX_IN_PROGRESS;
344 ch = PORT2CHANNEL(port);
346 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
349 * This really stinks, but we have to poll for the Tx time stamp.
350 * Usually, the time stamp is ready after 4 to 6 microseconds.
352 for (cnt = 0; cnt < 100; cnt++) {
353 val = __raw_readl(®s->channel[ch].ch_event);
354 if (val & TX_SNAPSHOT_LOCKED)
358 if (!(val & TX_SNAPSHOT_LOCKED)) {
359 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
363 lo = __raw_readl(®s->channel[ch].tx_snap_lo);
364 hi = __raw_readl(®s->channel[ch].tx_snap_hi);
365 ns = ((u64) hi) << 32;
367 ns <<= TICKS_NS_SHIFT;
369 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
370 shhwtstamps.hwtstamp = ns_to_ktime(ns);
371 skb_tstamp_tx(skb, &shhwtstamps);
373 __raw_writel(TX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event);
376 static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
378 struct hwtstamp_config cfg;
379 struct ixp46x_ts_regs *regs;
380 struct port *port = netdev_priv(netdev);
383 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
386 if (cfg.flags) /* reserved for future extensions */
389 ch = PORT2CHANNEL(port);
390 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
392 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
395 switch (cfg.rx_filter) {
396 case HWTSTAMP_FILTER_NONE:
397 port->hwts_rx_en = 0;
399 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
400 port->hwts_rx_en = PTP_SLAVE_MODE;
401 __raw_writel(0, ®s->channel[ch].ch_control);
403 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
404 port->hwts_rx_en = PTP_MASTER_MODE;
405 __raw_writel(MASTER_MODE, ®s->channel[ch].ch_control);
411 port->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
413 /* Clear out any old time stamps. */
414 __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED,
415 ®s->channel[ch].ch_event);
417 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
420 static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
425 if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
426 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name);
431 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
432 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
434 __raw_writel(((phy_id << 5) | location) & 0xFF,
435 &mdio_regs->mdio_command[2]);
436 __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
437 &mdio_regs->mdio_command[3]);
439 while ((cycles < MAX_MDIO_RETRIES) &&
440 (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
445 if (cycles == MAX_MDIO_RETRIES) {
446 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name,
452 printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name,
453 phy_id, write ? "write" : "read", cycles);
459 if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
461 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name,
464 return 0xFFFF; /* don't return error */
467 return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
468 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8);
471 static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location)
476 spin_lock_irqsave(&mdio_lock, flags);
477 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0);
478 spin_unlock_irqrestore(&mdio_lock, flags);
480 printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name,
481 phy_id, location, ret);
486 static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location,
492 spin_lock_irqsave(&mdio_lock, flags);
493 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val);
494 spin_unlock_irqrestore(&mdio_lock, flags);
496 printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n",
497 bus->name, phy_id, location, val, ret);
502 static int ixp4xx_mdio_register(void)
506 if (!(mdio_bus = mdiobus_alloc()))
509 if (cpu_is_ixp43x()) {
510 /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */
511 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEC_ETH))
513 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
515 /* All MII PHY accesses use NPE-B Ethernet registers */
516 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
518 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
521 __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
522 spin_lock_init(&mdio_lock);
523 mdio_bus->name = "IXP4xx MII Bus";
524 mdio_bus->read = &ixp4xx_mdio_read;
525 mdio_bus->write = &ixp4xx_mdio_write;
526 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0");
528 if ((err = mdiobus_register(mdio_bus)))
529 mdiobus_free(mdio_bus);
533 static void ixp4xx_mdio_remove(void)
535 mdiobus_unregister(mdio_bus);
536 mdiobus_free(mdio_bus);
540 static void ixp4xx_adjust_link(struct net_device *dev)
542 struct port *port = netdev_priv(dev);
543 struct phy_device *phydev = port->phydev;
548 printk(KERN_INFO "%s: link down\n", dev->name);
553 if (port->speed == phydev->speed && port->duplex == phydev->duplex)
556 port->speed = phydev->speed;
557 port->duplex = phydev->duplex;
560 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
561 &port->regs->tx_control[0]);
563 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
564 &port->regs->tx_control[0]);
566 printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
567 dev->name, port->speed, port->duplex ? "full" : "half");
571 static inline void debug_pkt(struct net_device *dev, const char *func,
577 printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
578 for (i = 0; i < len; i++) {
579 if (i >= DEBUG_PKT_BYTES)
582 ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
590 static inline void debug_desc(u32 phys, struct desc *desc)
593 printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
594 " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
595 phys, desc->next, desc->buf_len, desc->pkt_len,
596 desc->data, desc->dest_id, desc->src_id, desc->flags,
597 desc->qos, desc->padlen, desc->vlan_tci,
598 desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
599 desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
600 desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
601 desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
605 static inline int queue_get_desc(unsigned int queue, struct port *port,
608 u32 phys, tab_phys, n_desc;
611 if (!(phys = qmgr_get_entry(queue)))
614 phys &= ~0x1F; /* mask out non-address bits */
615 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
616 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
617 n_desc = (phys - tab_phys) / sizeof(struct desc);
618 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
619 debug_desc(phys, &tab[n_desc]);
620 BUG_ON(tab[n_desc].next);
624 static inline void queue_put_desc(unsigned int queue, u32 phys,
627 debug_desc(phys, desc);
629 qmgr_put_entry(queue, phys);
630 /* Don't check for queue overflow here, we've allocated sufficient
631 length and queues >= 32 don't support this check anyway. */
635 static inline void dma_unmap_tx(struct port *port, struct desc *desc)
638 dma_unmap_single(&port->netdev->dev, desc->data,
639 desc->buf_len, DMA_TO_DEVICE);
641 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
642 ALIGN((desc->data & 3) + desc->buf_len, 4),
648 static void eth_rx_irq(void *pdev)
650 struct net_device *dev = pdev;
651 struct port *port = netdev_priv(dev);
654 printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
656 qmgr_disable_irq(port->plat->rxq);
657 napi_schedule(&port->napi);
660 static int eth_poll(struct napi_struct *napi, int budget)
662 struct port *port = container_of(napi, struct port, napi);
663 struct net_device *dev = port->netdev;
664 unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
668 printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
671 while (received < budget) {
676 struct sk_buff *temp;
680 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
682 printk(KERN_DEBUG "%s: eth_poll napi_complete\n",
686 qmgr_enable_irq(rxq);
687 if (!qmgr_stat_below_low_watermark(rxq) &&
688 napi_reschedule(napi)) { /* not empty again */
690 printk(KERN_DEBUG "%s: eth_poll"
691 " napi_reschedule successed\n",
694 qmgr_disable_irq(rxq);
698 printk(KERN_DEBUG "%s: eth_poll all done\n",
701 return received; /* all work done */
704 desc = rx_desc_ptr(port, n);
707 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {
708 phys = dma_map_single(&dev->dev, skb->data,
709 RX_BUFF_SIZE, DMA_FROM_DEVICE);
710 if (dma_mapping_error(&dev->dev, phys)) {
716 skb = netdev_alloc_skb(dev,
717 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4));
721 dev->stats.rx_dropped++;
722 /* put the desc back on RX-ready queue */
723 desc->buf_len = MAX_MRU;
725 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
729 /* process received frame */
732 skb = port->rx_buff_tab[n];
733 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN,
734 RX_BUFF_SIZE, DMA_FROM_DEVICE);
736 dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN,
737 RX_BUFF_SIZE, DMA_FROM_DEVICE);
738 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
739 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4);
741 skb_reserve(skb, NET_IP_ALIGN);
742 skb_put(skb, desc->pkt_len);
744 debug_pkt(dev, "eth_poll", skb->data, skb->len);
746 ixp_rx_timestamp(port, skb);
747 skb->protocol = eth_type_trans(skb, dev);
748 dev->stats.rx_packets++;
749 dev->stats.rx_bytes += skb->len;
750 netif_receive_skb(skb);
752 /* put the new buffer on RX-free queue */
754 port->rx_buff_tab[n] = temp;
755 desc->data = phys + NET_IP_ALIGN;
757 desc->buf_len = MAX_MRU;
759 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
764 printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
766 return received; /* not all work done */
770 static void eth_txdone_irq(void *unused)
775 printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
777 while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) {
784 BUG_ON(npe_id >= MAX_NPES);
785 port = npe_port_tab[npe_id];
787 phys &= ~0x1F; /* mask out non-address bits */
788 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
789 BUG_ON(n_desc >= TX_DESCS);
790 desc = tx_desc_ptr(port, n_desc);
791 debug_desc(phys, desc);
793 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
794 port->netdev->stats.tx_packets++;
795 port->netdev->stats.tx_bytes += desc->pkt_len;
797 dma_unmap_tx(port, desc);
799 printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
800 port->netdev->name, port->tx_buff_tab[n_desc]);
802 free_buffer_irq(port->tx_buff_tab[n_desc]);
803 port->tx_buff_tab[n_desc] = NULL;
806 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
807 queue_put_desc(port->plat->txreadyq, phys, desc);
808 if (start) { /* TX-ready queue was empty */
810 printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
813 netif_wake_queue(port->netdev);
818 static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
820 struct port *port = netdev_priv(dev);
821 unsigned int txreadyq = port->plat->txreadyq;
822 int len, offset, bytes, n;
828 printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
831 if (unlikely(skb->len > MAX_MRU)) {
833 dev->stats.tx_errors++;
837 debug_pkt(dev, "eth_xmit", skb->data, skb->len);
841 offset = 0; /* no need to keep alignment */
845 offset = (int)skb->data & 3; /* keep 32-bit alignment */
846 bytes = ALIGN(offset + len, 4);
847 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
849 dev->stats.tx_dropped++;
852 memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
855 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
856 if (dma_mapping_error(&dev->dev, phys)) {
861 dev->stats.tx_dropped++;
865 n = queue_get_desc(txreadyq, port, 1);
867 desc = tx_desc_ptr(port, n);
870 port->tx_buff_tab[n] = skb;
872 port->tx_buff_tab[n] = mem;
874 desc->data = phys + offset;
875 desc->buf_len = desc->pkt_len = len;
877 /* NPE firmware pads short frames with zeros internally */
879 queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
881 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
883 printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
885 netif_stop_queue(dev);
886 /* we could miss TX ready interrupt */
887 /* really empty in fact */
888 if (!qmgr_stat_below_low_watermark(txreadyq)) {
890 printk(KERN_DEBUG "%s: eth_xmit ready again\n",
893 netif_wake_queue(dev);
898 printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
901 ixp_tx_timestamp(port, skb);
902 skb_tx_timestamp(skb);
911 static void eth_set_mcast_list(struct net_device *dev)
913 struct port *port = netdev_priv(dev);
914 struct netdev_hw_addr *ha;
915 u8 diffs[ETH_ALEN], *addr;
917 static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
919 if (dev->flags & IFF_ALLMULTI) {
920 for (i = 0; i < ETH_ALEN; i++) {
921 __raw_writel(allmulti[i], &port->regs->mcast_addr[i]);
922 __raw_writel(allmulti[i], &port->regs->mcast_mask[i]);
924 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
925 &port->regs->rx_control[0]);
929 if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) {
930 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
931 &port->regs->rx_control[0]);
935 memset(diffs, 0, ETH_ALEN);
938 netdev_for_each_mc_addr(ha, dev) {
940 addr = ha->addr; /* first MAC address */
941 for (i = 0; i < ETH_ALEN; i++)
942 diffs[i] |= addr[i] ^ ha->addr[i];
945 for (i = 0; i < ETH_ALEN; i++) {
946 __raw_writel(addr[i], &port->regs->mcast_addr[i]);
947 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
950 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
951 &port->regs->rx_control[0]);
955 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
957 struct port *port = netdev_priv(dev);
959 if (!netif_running(dev))
962 if (cpu_is_ixp46x() && cmd == SIOCSHWTSTAMP)
963 return hwtstamp_ioctl(dev, req, cmd);
965 return phy_mii_ioctl(port->phydev, req, cmd);
968 /* ethtool support */
970 static void ixp4xx_get_drvinfo(struct net_device *dev,
971 struct ethtool_drvinfo *info)
973 struct port *port = netdev_priv(dev);
975 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
976 snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u",
977 port->firmware[0], port->firmware[1],
978 port->firmware[2], port->firmware[3]);
979 strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
982 static int ixp4xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
984 struct port *port = netdev_priv(dev);
985 return phy_ethtool_gset(port->phydev, cmd);
988 static int ixp4xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
990 struct port *port = netdev_priv(dev);
991 return phy_ethtool_sset(port->phydev, cmd);
994 static int ixp4xx_nway_reset(struct net_device *dev)
996 struct port *port = netdev_priv(dev);
997 return phy_start_aneg(port->phydev);
1000 int ixp46x_phc_index = -1;
1001 EXPORT_SYMBOL_GPL(ixp46x_phc_index);
1003 static int ixp4xx_get_ts_info(struct net_device *dev,
1004 struct ethtool_ts_info *info)
1006 if (!cpu_is_ixp46x()) {
1007 info->so_timestamping =
1008 SOF_TIMESTAMPING_TX_SOFTWARE |
1009 SOF_TIMESTAMPING_RX_SOFTWARE |
1010 SOF_TIMESTAMPING_SOFTWARE;
1011 info->phc_index = -1;
1014 info->so_timestamping =
1015 SOF_TIMESTAMPING_TX_HARDWARE |
1016 SOF_TIMESTAMPING_RX_HARDWARE |
1017 SOF_TIMESTAMPING_RAW_HARDWARE;
1018 info->phc_index = ixp46x_phc_index;
1020 (1 << HWTSTAMP_TX_OFF) |
1021 (1 << HWTSTAMP_TX_ON);
1023 (1 << HWTSTAMP_FILTER_NONE) |
1024 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1025 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ);
1029 static const struct ethtool_ops ixp4xx_ethtool_ops = {
1030 .get_drvinfo = ixp4xx_get_drvinfo,
1031 .get_settings = ixp4xx_get_settings,
1032 .set_settings = ixp4xx_set_settings,
1033 .nway_reset = ixp4xx_nway_reset,
1034 .get_link = ethtool_op_get_link,
1035 .get_ts_info = ixp4xx_get_ts_info,
1039 static int request_queues(struct port *port)
1043 err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0,
1044 "%s:RX-free", port->netdev->name);
1048 err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0,
1049 "%s:RX", port->netdev->name);
1053 err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0,
1054 "%s:TX", port->netdev->name);
1058 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
1059 "%s:TX-ready", port->netdev->name);
1063 /* TX-done queue handles skbs sent out by the NPEs */
1065 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0,
1066 "%s:TX-done", DRV_NAME);
1073 qmgr_release_queue(port->plat->txreadyq);
1075 qmgr_release_queue(TX_QUEUE(port->id));
1077 qmgr_release_queue(port->plat->rxq);
1079 qmgr_release_queue(RXFREE_QUEUE(port->id));
1080 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
1081 port->netdev->name);
1085 static void release_queues(struct port *port)
1087 qmgr_release_queue(RXFREE_QUEUE(port->id));
1088 qmgr_release_queue(port->plat->rxq);
1089 qmgr_release_queue(TX_QUEUE(port->id));
1090 qmgr_release_queue(port->plat->txreadyq);
1093 qmgr_release_queue(TXDONE_QUEUE);
1096 static int init_queues(struct port *port)
1101 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
1102 POOL_ALLOC_SIZE, 32, 0);
1107 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
1108 &port->desc_tab_phys)))
1110 memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
1111 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
1112 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
1114 /* Setup RX buffers */
1115 for (i = 0; i < RX_DESCS; i++) {
1116 struct desc *desc = rx_desc_ptr(port, i);
1117 buffer_t *buff; /* skb or kmalloc()ated memory */
1120 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE)))
1124 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL)))
1128 desc->buf_len = MAX_MRU;
1129 desc->data = dma_map_single(&port->netdev->dev, data,
1130 RX_BUFF_SIZE, DMA_FROM_DEVICE);
1131 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1135 desc->data += NET_IP_ALIGN;
1136 port->rx_buff_tab[i] = buff;
1142 static void destroy_queues(struct port *port)
1146 if (port->desc_tab) {
1147 for (i = 0; i < RX_DESCS; i++) {
1148 struct desc *desc = rx_desc_ptr(port, i);
1149 buffer_t *buff = port->rx_buff_tab[i];
1151 dma_unmap_single(&port->netdev->dev,
1152 desc->data - NET_IP_ALIGN,
1153 RX_BUFF_SIZE, DMA_FROM_DEVICE);
1157 for (i = 0; i < TX_DESCS; i++) {
1158 struct desc *desc = tx_desc_ptr(port, i);
1159 buffer_t *buff = port->tx_buff_tab[i];
1161 dma_unmap_tx(port, desc);
1165 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1166 port->desc_tab = NULL;
1169 if (!ports_open && dma_pool) {
1170 dma_pool_destroy(dma_pool);
1175 static int eth_open(struct net_device *dev)
1177 struct port *port = netdev_priv(dev);
1178 struct npe *npe = port->npe;
1182 if (!npe_running(npe)) {
1183 err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
1187 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
1188 printk(KERN_ERR "%s: %s not responding\n", dev->name,
1192 port->firmware[0] = msg.byte4;
1193 port->firmware[1] = msg.byte5;
1194 port->firmware[2] = msg.byte6;
1195 port->firmware[3] = msg.byte7;
1198 memset(&msg, 0, sizeof(msg));
1199 msg.cmd = NPE_VLAN_SETRXQOSENTRY;
1200 msg.eth_id = port->id;
1201 msg.byte5 = port->plat->rxq | 0x80;
1202 msg.byte7 = port->plat->rxq << 4;
1203 for (i = 0; i < 8; i++) {
1205 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
1209 msg.cmd = NPE_EDB_SETPORTADDRESS;
1210 msg.eth_id = PHYSICAL_ID(port->id);
1211 msg.byte2 = dev->dev_addr[0];
1212 msg.byte3 = dev->dev_addr[1];
1213 msg.byte4 = dev->dev_addr[2];
1214 msg.byte5 = dev->dev_addr[3];
1215 msg.byte6 = dev->dev_addr[4];
1216 msg.byte7 = dev->dev_addr[5];
1217 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
1220 memset(&msg, 0, sizeof(msg));
1221 msg.cmd = NPE_FW_SETFIREWALLMODE;
1222 msg.eth_id = port->id;
1223 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
1226 if ((err = request_queues(port)) != 0)
1229 if ((err = init_queues(port)) != 0) {
1230 destroy_queues(port);
1231 release_queues(port);
1235 port->speed = 0; /* force "link up" message */
1236 phy_start(port->phydev);
1238 for (i = 0; i < ETH_ALEN; i++)
1239 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
1240 __raw_writel(0x08, &port->regs->random_seed);
1241 __raw_writel(0x12, &port->regs->partial_empty_threshold);
1242 __raw_writel(0x30, &port->regs->partial_full_threshold);
1243 __raw_writel(0x08, &port->regs->tx_start_bytes);
1244 __raw_writel(0x15, &port->regs->tx_deferral);
1245 __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
1246 __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
1247 __raw_writel(0x80, &port->regs->slot_time);
1248 __raw_writel(0x01, &port->regs->int_clock_threshold);
1250 /* Populate queues with buffers, no failure after this point */
1251 for (i = 0; i < TX_DESCS; i++)
1252 queue_put_desc(port->plat->txreadyq,
1253 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1255 for (i = 0; i < RX_DESCS; i++)
1256 queue_put_desc(RXFREE_QUEUE(port->id),
1257 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1259 __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1260 __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1261 __raw_writel(0, &port->regs->rx_control[1]);
1262 __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1264 napi_enable(&port->napi);
1265 eth_set_mcast_list(dev);
1266 netif_start_queue(dev);
1268 qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1271 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1272 eth_txdone_irq, NULL);
1273 qmgr_enable_irq(TXDONE_QUEUE);
1276 /* we may already have RX data, enables IRQ */
1277 napi_schedule(&port->napi);
1281 static int eth_close(struct net_device *dev)
1283 struct port *port = netdev_priv(dev);
1285 int buffs = RX_DESCS; /* allocated RX buffers */
1289 qmgr_disable_irq(port->plat->rxq);
1290 napi_disable(&port->napi);
1291 netif_stop_queue(dev);
1293 while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1296 memset(&msg, 0, sizeof(msg));
1297 msg.cmd = NPE_SETLOOPBACK_MODE;
1298 msg.eth_id = port->id;
1300 if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1301 printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
1304 do { /* drain RX buffers */
1305 while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1309 if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1310 /* we have to inject some packet */
1313 int n = queue_get_desc(port->plat->txreadyq, port, 1);
1315 desc = tx_desc_ptr(port, n);
1316 phys = tx_desc_phys(port, n);
1317 desc->buf_len = desc->pkt_len = 1;
1319 queue_put_desc(TX_QUEUE(port->id), phys, desc);
1322 } while (++i < MAX_CLOSE_WAIT);
1325 printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1326 " left in NPE\n", dev->name, buffs);
1329 printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
1333 while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1334 buffs--; /* cancel TX */
1338 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1342 } while (++i < MAX_CLOSE_WAIT);
1345 printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1346 "left in NPE\n", dev->name, buffs);
1349 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1353 if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1354 printk(KERN_CRIT "%s: unable to disable loopback\n",
1357 phy_stop(port->phydev);
1360 qmgr_disable_irq(TXDONE_QUEUE);
1361 destroy_queues(port);
1362 release_queues(port);
1366 static const struct net_device_ops ixp4xx_netdev_ops = {
1367 .ndo_open = eth_open,
1368 .ndo_stop = eth_close,
1369 .ndo_start_xmit = eth_xmit,
1370 .ndo_set_rx_mode = eth_set_mcast_list,
1371 .ndo_do_ioctl = eth_ioctl,
1372 .ndo_change_mtu = eth_change_mtu,
1373 .ndo_set_mac_address = eth_mac_addr,
1374 .ndo_validate_addr = eth_validate_addr,
1377 static int eth_init_one(struct platform_device *pdev)
1380 struct net_device *dev;
1381 struct eth_plat_info *plat = dev_get_platdata(&pdev->dev);
1383 char phy_id[MII_BUS_ID_SIZE + 3];
1386 if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) {
1387 pr_err("ixp4xx_eth: bad ptp filter\n");
1391 if (!(dev = alloc_etherdev(sizeof(struct port))))
1394 SET_NETDEV_DEV(dev, &pdev->dev);
1395 port = netdev_priv(dev);
1397 port->id = pdev->id;
1400 case IXP4XX_ETH_NPEA:
1401 port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
1402 regs_phys = IXP4XX_EthA_BASE_PHYS;
1404 case IXP4XX_ETH_NPEB:
1405 port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1406 regs_phys = IXP4XX_EthB_BASE_PHYS;
1408 case IXP4XX_ETH_NPEC:
1409 port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
1410 regs_phys = IXP4XX_EthC_BASE_PHYS;
1417 dev->netdev_ops = &ixp4xx_netdev_ops;
1418 dev->ethtool_ops = &ixp4xx_ethtool_ops;
1419 dev->tx_queue_len = 100;
1421 netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT);
1423 if (!(port->npe = npe_request(NPE_ID(port->id)))) {
1428 port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
1429 if (!port->mem_res) {
1435 npe_port_tab[NPE_ID(port->id)] = port;
1436 memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
1438 platform_set_drvdata(pdev, dev);
1440 __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1441 &port->regs->core_control);
1443 __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1446 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
1447 mdio_bus->id, plat->phy);
1448 port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link,
1449 PHY_INTERFACE_MODE_MII);
1450 if (IS_ERR(port->phydev)) {
1451 err = PTR_ERR(port->phydev);
1455 port->phydev->irq = PHY_POLL;
1457 if ((err = register_netdev(dev)))
1460 printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
1461 npe_name(port->npe));
1466 phy_disconnect(port->phydev);
1468 npe_port_tab[NPE_ID(port->id)] = NULL;
1469 release_resource(port->mem_res);
1471 npe_release(port->npe);
1477 static int eth_remove_one(struct platform_device *pdev)
1479 struct net_device *dev = platform_get_drvdata(pdev);
1480 struct port *port = netdev_priv(dev);
1482 unregister_netdev(dev);
1483 phy_disconnect(port->phydev);
1484 npe_port_tab[NPE_ID(port->id)] = NULL;
1485 npe_release(port->npe);
1486 release_resource(port->mem_res);
1491 static struct platform_driver ixp4xx_eth_driver = {
1492 .driver.name = DRV_NAME,
1493 .probe = eth_init_one,
1494 .remove = eth_remove_one,
1497 static int __init eth_init_module(void)
1500 if ((err = ixp4xx_mdio_register()))
1502 return platform_driver_register(&ixp4xx_eth_driver);
1505 static void __exit eth_cleanup_module(void)
1507 platform_driver_unregister(&ixp4xx_eth_driver);
1508 ixp4xx_mdio_remove();
1511 MODULE_AUTHOR("Krzysztof Halasa");
1512 MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1513 MODULE_LICENSE("GPL v2");
1514 MODULE_ALIAS("platform:ixp4xx_eth");
1515 module_init(eth_init_module);
1516 module_exit(eth_cleanup_module);