drivers/net/ethernet/xscale/ixp4xx_eth.c

   1 /*
   2  * Intel IXP4xx Ethernet driver for Linux
   3  *
   4  * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of version 2 of the GNU General Public License
   8  * as published by the Free Software Foundation.
   9  *
  10  * Ethernet port config (0x00 is not present on IXP42X):
  11  *
  12  * logical port         0x00            0x10            0x20
  13  * NPE                  0 (NPE-A)       1 (NPE-B)       2 (NPE-C)
  14  * physical PortId      2               0               1
  15  * TX queue             23              24              25
  16  * RX-free queue        26              27              28
  17  * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
  18  *
  19  *
  20  * Queue entries:
  21  * bits 0 -> 1  - NPE ID (RX and TX-done)
  22  * bits 0 -> 2  - priority (TX, per 802.1D)
  23  * bits 3 -> 4  - port ID (user-set?)
  24  * bits 5 -> 31 - physical descriptor address
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/dmapool.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/io.h>
  32 #include <linux/kernel.h>
  33 #include <linux/net_tstamp.h>
  34 #include <linux/phy.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/ptp_classify.h>
  37 #include <linux/slab.h>
  38 #include <linux/module.h>
  39 #include <mach/ixp46x_ts.h>
  40 #include <mach/npe.h>
  41 #include <mach/qmgr.h>
  42
  43 #define DEBUG_DESC              0
  44 #define DEBUG_RX                0
  45 #define DEBUG_TX                0
  46 #define DEBUG_PKT_BYTES         0
  47 #define DEBUG_MDIO              0
  48 #define DEBUG_CLOSE             0
  49
  50 #define DRV_NAME                "ixp4xx_eth"
  51
  52 #define MAX_NPES                3
  53
  54 #define RX_DESCS                64 /* also length of all RX queues */
  55 #define TX_DESCS                16 /* also length of all TX queues */
  56 #define TXDONE_QUEUE_LEN        64 /* dwords */
  57
  58 #define POOL_ALLOC_SIZE         (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
  59 #define REGS_SIZE               0x1000
  60 #define MAX_MRU                 1536 /* 0x600 */
  61 #define RX_BUFF_SIZE            ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
  62
  63 #define NAPI_WEIGHT             16
  64 #define MDIO_INTERVAL           (3 * HZ)
  65 #define MAX_MDIO_RETRIES        100 /* microseconds, typically 30 cycles */
  66 #define MAX_CLOSE_WAIT          1000 /* microseconds, typically 2-3 cycles */
  67
  68 #define NPE_ID(port_id)         ((port_id) >> 4)
  69 #define PHYSICAL_ID(port_id)    ((NPE_ID(port_id) + 2) % 3)
  70 #define TX_QUEUE(port_id)       (NPE_ID(port_id) + 23)
  71 #define RXFREE_QUEUE(port_id)   (NPE_ID(port_id) + 26)
  72 #define TXDONE_QUEUE            31
  73
  74 #define PTP_SLAVE_MODE          1
  75 #define PTP_MASTER_MODE         2
  76 #define PORT2CHANNEL(p)         NPE_ID(p->id)
  77
  78 /* TX Control Registers */
  79 #define TX_CNTRL0_TX_EN         0x01
  80 #define TX_CNTRL0_HALFDUPLEX    0x02
  81 #define TX_CNTRL0_RETRY         0x04
  82 #define TX_CNTRL0_PAD_EN        0x08
  83 #define TX_CNTRL0_APPEND_FCS    0x10
  84 #define TX_CNTRL0_2DEFER        0x20
  85 #define TX_CNTRL0_RMII          0x40 /* reduced MII */
  86 #define TX_CNTRL1_RETRIES       0x0F /* 4 bits */
  87
  88 /* RX Control Registers */
  89 #define RX_CNTRL0_RX_EN         0x01
  90 #define RX_CNTRL0_PADSTRIP_EN   0x02
  91 #define RX_CNTRL0_SEND_FCS      0x04
  92 #define RX_CNTRL0_PAUSE_EN      0x08
  93 #define RX_CNTRL0_LOOP_EN       0x10
  94 #define RX_CNTRL0_ADDR_FLTR_EN  0x20
  95 #define RX_CNTRL0_RX_RUNT_EN    0x40
  96 #define RX_CNTRL0_BCAST_DIS     0x80
  97 #define RX_CNTRL1_DEFER_EN      0x01
  98
  99 /* Core Control Register */
 100 #define CORE_RESET              0x01
 101 #define CORE_RX_FIFO_FLUSH      0x02
 102 #define CORE_TX_FIFO_FLUSH      0x04
 103 #define CORE_SEND_JAM           0x08
 104 #define CORE_MDC_EN             0x10 /* MDIO using NPE-B ETH-0 only */
 105
 106 #define DEFAULT_TX_CNTRL0       (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY |    \
 107                                  TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
 108                                  TX_CNTRL0_2DEFER)
 109 #define DEFAULT_RX_CNTRL0       RX_CNTRL0_RX_EN
 110 #define DEFAULT_CORE_CNTRL      CORE_MDC_EN
 111
 112
 113 /* NPE message codes */
 114 #define NPE_GETSTATUS                   0x00
 115 #define NPE_EDB_SETPORTADDRESS          0x01
 116 #define NPE_EDB_GETMACADDRESSDATABASE   0x02
 117 #define NPE_EDB_SETMACADDRESSSDATABASE  0x03
 118 #define NPE_GETSTATS                    0x04
 119 #define NPE_RESETSTATS                  0x05
 120 #define NPE_SETMAXFRAMELENGTHS          0x06
 121 #define NPE_VLAN_SETRXTAGMODE           0x07
 122 #define NPE_VLAN_SETDEFAULTRXVID        0x08
 123 #define NPE_VLAN_SETPORTVLANTABLEENTRY  0x09
 124 #define NPE_VLAN_SETPORTVLANTABLERANGE  0x0A
 125 #define NPE_VLAN_SETRXQOSENTRY          0x0B
 126 #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
 127 #define NPE_STP_SETBLOCKINGSTATE        0x0D
 128 #define NPE_FW_SETFIREWALLMODE          0x0E
 129 #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
 130 #define NPE_PC_SETAPMACTABLE            0x11
 131 #define NPE_SETLOOPBACK_MODE            0x12
 132 #define NPE_PC_SETBSSIDTABLE            0x13
 133 #define NPE_ADDRESS_FILTER_CONFIG       0x14
 134 #define NPE_APPENDFCSCONFIG             0x15
 135 #define NPE_NOTIFY_MAC_RECOVERY_DONE    0x16
 136 #define NPE_MAC_RECOVERY_START          0x17
 137
 138
 139 #ifdef __ARMEB__
 140 typedef struct sk_buff buffer_t;
 141 #define free_buffer dev_kfree_skb
 142 #define free_buffer_irq dev_kfree_skb_irq
 143 #else
 144 typedef void buffer_t;
 145 #define free_buffer kfree
 146 #define free_buffer_irq kfree
 147 #endif
 148
 149 struct eth_regs {
 150         u32 tx_control[2], __res1[2];           /* 000 */
 151         u32 rx_control[2], __res2[2];           /* 010 */
 152         u32 random_seed, __res3[3];             /* 020 */
 153         u32 partial_empty_threshold, __res4;    /* 030 */
 154         u32 partial_full_threshold, __res5;     /* 038 */
 155         u32 tx_start_bytes, __res6[3];          /* 040 */
 156         u32 tx_deferral, rx_deferral, __res7[2];/* 050 */
 157         u32 tx_2part_deferral[2], __res8[2];    /* 060 */
 158         u32 slot_time, __res9[3];               /* 070 */
 159         u32 mdio_command[4];                    /* 080 */
 160         u32 mdio_status[4];                     /* 090 */
 161         u32 mcast_mask[6], __res10[2];          /* 0A0 */
 162         u32 mcast_addr[6], __res11[2];          /* 0C0 */
 163         u32 int_clock_threshold, __res12[3];    /* 0E0 */
 164         u32 hw_addr[6], __res13[61];            /* 0F0 */
 165         u32 core_control;                       /* 1FC */
 166 };
 167
 168 struct port {
 169         struct resource *mem_res;
 170         struct eth_regs __iomem *regs;
 171         struct npe *npe;
 172         struct net_device *netdev;
 173         struct napi_struct napi;
 174         struct phy_device *phydev;
 175         struct eth_plat_info *plat;
 176         buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
 177         struct desc *desc_tab;  /* coherent */
 178         u32 desc_tab_phys;
 179         int id;                 /* logical port ID */
 180         int speed, duplex;
 181         u8 firmware[4];
 182         int hwts_tx_en;
 183         int hwts_rx_en;
 184 };
 185
 186 /* NPE message structure */
 187 struct msg {
 188 #ifdef __ARMEB__
 189         u8 cmd, eth_id, byte2, byte3;
 190         u8 byte4, byte5, byte6, byte7;
 191 #else
 192         u8 byte3, byte2, eth_id, cmd;
 193         u8 byte7, byte6, byte5, byte4;
 194 #endif
 195 };
 196
 197 /* Ethernet packet descriptor */
 198 struct desc {
 199         u32 next;               /* pointer to next buffer, unused */
 200
 201 #ifdef __ARMEB__
 202         u16 buf_len;            /* buffer length */
 203         u16 pkt_len;            /* packet length */
 204         u32 data;               /* pointer to data buffer in RAM */
 205         u8 dest_id;
 206         u8 src_id;
 207         u16 flags;
 208         u8 qos;
 209         u8 padlen;
 210         u16 vlan_tci;
 211 #else
 212         u16 pkt_len;            /* packet length */
 213         u16 buf_len;            /* buffer length */
 214         u32 data;               /* pointer to data buffer in RAM */
 215         u16 flags;
 216         u8 src_id;
 217         u8 dest_id;
 218         u16 vlan_tci;
 219         u8 padlen;
 220         u8 qos;
 221 #endif
 222
 223 #ifdef __ARMEB__
 224         u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
 225         u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
 226         u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
 227 #else
 228         u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
 229         u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
 230         u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
 231 #endif
 232 };
 233
 234
 235 #define rx_desc_phys(port, n)   ((port)->desc_tab_phys +                \
 236                                  (n) * sizeof(struct desc))
 237 #define rx_desc_ptr(port, n)    (&(port)->desc_tab[n])
 238
 239 #define tx_desc_phys(port, n)   ((port)->desc_tab_phys +                \
 240                                  ((n) + RX_DESCS) * sizeof(struct desc))
 241 #define tx_desc_ptr(port, n)    (&(port)->desc_tab[(n) + RX_DESCS])
 242
 243 #ifndef __ARMEB__
 244 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
 245 {
 246         int i;
 247         for (i = 0; i < cnt; i++)
 248                 dest[i] = swab32(src[i]);
 249 }
 250 #endif
 251
 252 static spinlock_t mdio_lock;
 253 static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
 254 static struct mii_bus *mdio_bus;
 255 static int ports_open;
 256 static struct port *npe_port_tab[MAX_NPES];
 257 static struct dma_pool *dma_pool;
 258
 259 static struct sock_filter ptp_filter[] = {
 260         PTP_FILTER
 261 };
 262
 263 static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
 264 {
 265         u8 *data = skb->data;
 266         unsigned int offset;
 267         u16 *hi, *id;
 268         u32 lo;
 269
 270         if (sk_run_filter(skb, ptp_filter) != PTP_CLASS_V1_IPV4)
 271                 return 0;
 272
 273         offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
 274
 275         if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
 276                 return 0;
 277
 278         hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
 279         id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
 280
 281         memcpy(&lo, &hi[1], sizeof(lo));
 282
 283         return (uid_hi == ntohs(*hi) &&
 284                 uid_lo == ntohl(lo) &&
 285                 seqid  == ntohs(*id));
 286 }
 287
 288 static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb)
 289 {
 290         struct skb_shared_hwtstamps *shhwtstamps;
 291         struct ixp46x_ts_regs *regs;
 292         u64 ns;
 293         u32 ch, hi, lo, val;
 294         u16 uid, seq;
 295
 296         if (!port->hwts_rx_en)
 297                 return;
 298
 299         ch = PORT2CHANNEL(port);
 300
 301         regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
 302
 303         val = __raw_readl(&regs->channel[ch].ch_event);
 304
 305         if (!(val & RX_SNAPSHOT_LOCKED))
 306                 return;
 307
 308         lo = __raw_readl(&regs->channel[ch].src_uuid_lo);
 309         hi = __raw_readl(&regs->channel[ch].src_uuid_hi);
 310
 311         uid = hi & 0xffff;
 312         seq = (hi >> 16) & 0xffff;
 313
 314         if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
 315                 goto out;
 316
 317         lo = __raw_readl(&regs->channel[ch].rx_snap_lo);
 318         hi = __raw_readl(&regs->channel[ch].rx_snap_hi);
 319         ns = ((u64) hi) << 32;
 320         ns |= lo;
 321         ns <<= TICKS_NS_SHIFT;
 322
 323         shhwtstamps = skb_hwtstamps(skb);
 324         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 325         shhwtstamps->hwtstamp = ns_to_ktime(ns);
 326 out:
 327         __raw_writel(RX_SNAPSHOT_LOCKED, &regs->channel[ch].ch_event);
 328 }
 329
 330 static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb)
 331 {
 332         struct skb_shared_hwtstamps shhwtstamps;
 333         struct ixp46x_ts_regs *regs;
 334         struct skb_shared_info *shtx;
 335         u64 ns;
 336         u32 ch, cnt, hi, lo, val;
 337
 338         shtx = skb_shinfo(skb);
 339         if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en))
 340                 shtx->tx_flags |= SKBTX_IN_PROGRESS;
 341         else
 342                 return;
 343
 344         ch = PORT2CHANNEL(port);
 345
 346         regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
 347
 348         /*
 349          * This really stinks, but we have to poll for the Tx time stamp.
 350          * Usually, the time stamp is ready after 4 to 6 microseconds.
 351          */
 352         for (cnt = 0; cnt < 100; cnt++) {
 353                 val = __raw_readl(&regs->channel[ch].ch_event);
 354                 if (val & TX_SNAPSHOT_LOCKED)
 355                         break;
 356                 udelay(1);
 357         }
 358         if (!(val & TX_SNAPSHOT_LOCKED)) {
 359                 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
 360                 return;
 361         }
 362
 363         lo = __raw_readl(&regs->channel[ch].tx_snap_lo);
 364         hi = __raw_readl(&regs->channel[ch].tx_snap_hi);
 365         ns = ((u64) hi) << 32;
 366         ns |= lo;
 367         ns <<= TICKS_NS_SHIFT;
 368
 369         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 370         shhwtstamps.hwtstamp = ns_to_ktime(ns);
 371         skb_tstamp_tx(skb, &shhwtstamps);
 372
 373         __raw_writel(TX_SNAPSHOT_LOCKED, &regs->channel[ch].ch_event);
 374 }
 375
 376 static int hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
 377 {
 378         struct hwtstamp_config cfg;
 379         struct ixp46x_ts_regs *regs;
 380         struct port *port = netdev_priv(netdev);
 381         int ch;
 382
 383         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
 384                 return -EFAULT;
 385
 386         if (cfg.flags) /* reserved for future extensions */
 387                 return -EINVAL;
 388
 389         ch = PORT2CHANNEL(port);
 390         regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
 391
 392         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
 393                 return -ERANGE;
 394
 395         switch (cfg.rx_filter) {
 396         case HWTSTAMP_FILTER_NONE:
 397                 port->hwts_rx_en = 0;
 398                 break;
 399         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 400                 port->hwts_rx_en = PTP_SLAVE_MODE;
 401                 __raw_writel(0, &regs->channel[ch].ch_control);
 402                 break;
 403         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 404                 port->hwts_rx_en = PTP_MASTER_MODE;
 405                 __raw_writel(MASTER_MODE, &regs->channel[ch].ch_control);
 406                 break;
 407         default:
 408                 return -ERANGE;
 409         }
 410
 411         port->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
 412
 413         /* Clear out any old time stamps. */
 414         __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED,
 415                      &regs->channel[ch].ch_event);
 416
 417         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
 418 }
 419
 420 static int hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
 421 {
 422         struct hwtstamp_config cfg;
 423         struct port *port = netdev_priv(netdev);
 424
 425         cfg.flags = 0;
 426         cfg.tx_type = port->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
 427
 428         switch (port->hwts_rx_en) {
 429         case 0:
 430                 cfg.rx_filter = HWTSTAMP_FILTER_NONE;
 431                 break;
 432         case PTP_SLAVE_MODE:
 433                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 434                 break;
 435         case PTP_MASTER_MODE:
 436                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 437                 break;
 438         default:
 439                 WARN_ON_ONCE(1);
 440                 return -ERANGE;
 441         }
 442
 443         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
 444 }
 445
 446 static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
 447                            int write, u16 cmd)
 448 {
 449         int cycles = 0;
 450
 451         if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
 452                 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name);
 453                 return -1;
 454         }
 455
 456         if (write) {
 457                 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
 458                 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
 459         }
 460         __raw_writel(((phy_id << 5) | location) & 0xFF,
 461                      &mdio_regs->mdio_command[2]);
 462         __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
 463                      &mdio_regs->mdio_command[3]);
 464
 465         while ((cycles < MAX_MDIO_RETRIES) &&
 466                (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
 467                 udelay(1);
 468                 cycles++;
 469         }
 470
 471         if (cycles == MAX_MDIO_RETRIES) {
 472                 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name,
 473                        phy_id);
 474                 return -1;
 475         }
 476
 477 #if DEBUG_MDIO
 478         printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name,
 479                phy_id, write ? "write" : "read", cycles);
 480 #endif
 481
 482         if (write)
 483                 return 0;
 484
 485         if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
 486 #if DEBUG_MDIO
 487                 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name,
 488                        phy_id);
 489 #endif
 490                 return 0xFFFF; /* don't return error */
 491         }
 492
 493         return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
 494                 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8);
 495 }
 496
 497 static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location)
 498 {
 499         unsigned long flags;
 500         int ret;
 501
 502         spin_lock_irqsave(&mdio_lock, flags);
 503         ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0);
 504         spin_unlock_irqrestore(&mdio_lock, flags);
 505 #if DEBUG_MDIO
 506         printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name,
 507                phy_id, location, ret);
 508 #endif
 509         return ret;
 510 }
 511
 512 static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location,
 513                              u16 val)
 514 {
 515         unsigned long flags;
 516         int ret;
 517
 518         spin_lock_irqsave(&mdio_lock, flags);
 519         ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val);
 520         spin_unlock_irqrestore(&mdio_lock, flags);
 521 #if DEBUG_MDIO
 522         printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n",
 523                bus->name, phy_id, location, val, ret);
 524 #endif
 525         return ret;
 526 }
 527
 528 static int ixp4xx_mdio_register(void)
 529 {
 530         int err;
 531
 532         if (!(mdio_bus = mdiobus_alloc()))
 533                 return -ENOMEM;
 534
 535         if (cpu_is_ixp43x()) {
 536                 /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */
 537                 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEC_ETH))
 538                         return -ENODEV;
 539                 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
 540         } else {
 541                 /* All MII PHY accesses use NPE-B Ethernet registers */
 542                 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
 543                         return -ENODEV;
 544                 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
 545         }
 546
 547         __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
 548         spin_lock_init(&mdio_lock);
 549         mdio_bus->name = "IXP4xx MII Bus";
 550         mdio_bus->read = &ixp4xx_mdio_read;
 551         mdio_bus->write = &ixp4xx_mdio_write;
 552         snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0");
 553
 554         if ((err = mdiobus_register(mdio_bus)))
 555                 mdiobus_free(mdio_bus);
 556         return err;
 557 }
 558
 559 static void ixp4xx_mdio_remove(void)
 560 {
 561         mdiobus_unregister(mdio_bus);
 562         mdiobus_free(mdio_bus);
 563 }
 564
 565
 566 static void ixp4xx_adjust_link(struct net_device *dev)
 567 {
 568         struct port *port = netdev_priv(dev);
 569         struct phy_device *phydev = port->phydev;
 570
 571         if (!phydev->link) {
 572                 if (port->speed) {
 573                         port->speed = 0;
 574                         printk(KERN_INFO "%s: link down\n", dev->name);
 575                 }
 576                 return;
 577         }
 578
 579         if (port->speed == phydev->speed && port->duplex == phydev->duplex)
 580                 return;
 581
 582         port->speed = phydev->speed;
 583         port->duplex = phydev->duplex;
 584
 585         if (port->duplex)
 586                 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
 587                              &port->regs->tx_control[0]);
 588         else
 589                 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
 590                              &port->regs->tx_control[0]);
 591
 592         printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
 593                dev->name, port->speed, port->duplex ? "full" : "half");
 594 }
 595
 596
 597 static inline void debug_pkt(struct net_device *dev, const char *func,
 598                              u8 *data, int len)
 599 {
 600 #if DEBUG_PKT_BYTES
 601         int i;
 602
 603         printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
 604         for (i = 0; i < len; i++) {
 605                 if (i >= DEBUG_PKT_BYTES)
 606                         break;
 607                 printk("%s%02X",
 608                        ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
 609                        data[i]);
 610         }
 611         printk("\n");
 612 #endif
 613 }
 614
 615
 616 static inline void debug_desc(u32 phys, struct desc *desc)
 617 {
 618 #if DEBUG_DESC
 619         printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
 620                " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
 621                phys, desc->next, desc->buf_len, desc->pkt_len,
 622                desc->data, desc->dest_id, desc->src_id, desc->flags,
 623                desc->qos, desc->padlen, desc->vlan_tci,
 624                desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
 625                desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
 626                desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
 627                desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
 628 #endif
 629 }
 630
 631 static inline int queue_get_desc(unsigned int queue, struct port *port,
 632                                  int is_tx)
 633 {
 634         u32 phys, tab_phys, n_desc;
 635         struct desc *tab;
 636
 637         if (!(phys = qmgr_get_entry(queue)))
 638                 return -1;
 639
 640         phys &= ~0x1F; /* mask out non-address bits */
 641         tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
 642         tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
 643         n_desc = (phys - tab_phys) / sizeof(struct desc);
 644         BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
 645         debug_desc(phys, &tab[n_desc]);
 646         BUG_ON(tab[n_desc].next);
 647         return n_desc;
 648 }
 649
 650 static inline void queue_put_desc(unsigned int queue, u32 phys,
 651                                   struct desc *desc)
 652 {
 653         debug_desc(phys, desc);
 654         BUG_ON(phys & 0x1F);
 655         qmgr_put_entry(queue, phys);
 656         /* Don't check for queue overflow here, we've allocated sufficient
 657            length and queues >= 32 don't support this check anyway. */
 658 }
 659
 660
 661 static inline void dma_unmap_tx(struct port *port, struct desc *desc)
 662 {
 663 #ifdef __ARMEB__
 664         dma_unmap_single(&port->netdev->dev, desc->data,
 665                          desc->buf_len, DMA_TO_DEVICE);
 666 #else
 667         dma_unmap_single(&port->netdev->dev, desc->data & ~3,
 668                          ALIGN((desc->data & 3) + desc->buf_len, 4),
 669                          DMA_TO_DEVICE);
 670 #endif
 671 }
 672
 673
 674 static void eth_rx_irq(void *pdev)
 675 {
 676         struct net_device *dev = pdev;
 677         struct port *port = netdev_priv(dev);
 678
 679 #if DEBUG_RX
 680         printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
 681 #endif
 682         qmgr_disable_irq(port->plat->rxq);
 683         napi_schedule(&port->napi);
 684 }
 685
 686 static int eth_poll(struct napi_struct *napi, int budget)
 687 {
 688         struct port *port = container_of(napi, struct port, napi);
 689         struct net_device *dev = port->netdev;
 690         unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
 691         int received = 0;
 692
 693 #if DEBUG_RX
 694         printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
 695 #endif
 696
 697         while (received < budget) {
 698                 struct sk_buff *skb;
 699                 struct desc *desc;
 700                 int n;
 701 #ifdef __ARMEB__
 702                 struct sk_buff *temp;
 703                 u32 phys;
 704 #endif
 705
 706                 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
 707 #if DEBUG_RX
 708                         printk(KERN_DEBUG "%s: eth_poll napi_complete\n",
 709                                dev->name);
 710 #endif
 711                         napi_complete(napi);
 712                         qmgr_enable_irq(rxq);
 713                         if (!qmgr_stat_below_low_watermark(rxq) &&
 714                             napi_reschedule(napi)) { /* not empty again */
 715 #if DEBUG_RX
 716                                 printk(KERN_DEBUG "%s: eth_poll"
 717                                        " napi_reschedule successed\n",
 718                                        dev->name);
 719 #endif
 720                                 qmgr_disable_irq(rxq);
 721                                 continue;
 722                         }
 723 #if DEBUG_RX
 724                         printk(KERN_DEBUG "%s: eth_poll all done\n",
 725                                dev->name);
 726 #endif
 727                         return received; /* all work done */
 728                 }
 729
 730                 desc = rx_desc_ptr(port, n);
 731
 732 #ifdef __ARMEB__
 733                 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {
 734                         phys = dma_map_single(&dev->dev, skb->data,
 735                                               RX_BUFF_SIZE, DMA_FROM_DEVICE);
 736                         if (dma_mapping_error(&dev->dev, phys)) {
 737                                 dev_kfree_skb(skb);
 738                                 skb = NULL;
 739                         }
 740                 }
 741 #else
 742                 skb = netdev_alloc_skb(dev,
 743                                        ALIGN(NET_IP_ALIGN + desc->pkt_len, 4));
 744 #endif
 745
 746                 if (!skb) {
 747                         dev->stats.rx_dropped++;
 748                         /* put the desc back on RX-ready queue */
 749                         desc->buf_len = MAX_MRU;
 750                         desc->pkt_len = 0;
 751                         queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
 752                         continue;
 753                 }
 754
 755                 /* process received frame */
 756 #ifdef __ARMEB__
 757                 temp = skb;
 758                 skb = port->rx_buff_tab[n];
 759                 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN,
 760                                  RX_BUFF_SIZE, DMA_FROM_DEVICE);
 761 #else
 762                 dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN,
 763                                         RX_BUFF_SIZE, DMA_FROM_DEVICE);
 764                 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
 765                               ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4);
 766 #endif
 767                 skb_reserve(skb, NET_IP_ALIGN);
 768                 skb_put(skb, desc->pkt_len);
 769
 770                 debug_pkt(dev, "eth_poll", skb->data, skb->len);
 771
 772                 ixp_rx_timestamp(port, skb);
 773                 skb->protocol = eth_type_trans(skb, dev);
 774                 dev->stats.rx_packets++;
 775                 dev->stats.rx_bytes += skb->len;
 776                 netif_receive_skb(skb);
 777
 778                 /* put the new buffer on RX-free queue */
 779 #ifdef __ARMEB__
 780                 port->rx_buff_tab[n] = temp;
 781                 desc->data = phys + NET_IP_ALIGN;
 782 #endif
 783                 desc->buf_len = MAX_MRU;
 784                 desc->pkt_len = 0;
 785                 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
 786                 received++;
 787         }
 788
 789 #if DEBUG_RX
 790         printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
 791 #endif
 792         return received;                /* not all work done */
 793 }
 794
 795
 796 static void eth_txdone_irq(void *unused)
 797 {
 798         u32 phys;
 799
 800 #if DEBUG_TX
 801         printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
 802 #endif
 803         while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) {
 804                 u32 npe_id, n_desc;
 805                 struct port *port;
 806                 struct desc *desc;
 807                 int start;
 808
 809                 npe_id = phys & 3;
 810                 BUG_ON(npe_id >= MAX_NPES);
 811                 port = npe_port_tab[npe_id];
 812                 BUG_ON(!port);
 813                 phys &= ~0x1F; /* mask out non-address bits */
 814                 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
 815                 BUG_ON(n_desc >= TX_DESCS);
 816                 desc = tx_desc_ptr(port, n_desc);
 817                 debug_desc(phys, desc);
 818
 819                 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
 820                         port->netdev->stats.tx_packets++;
 821                         port->netdev->stats.tx_bytes += desc->pkt_len;
 822
 823                         dma_unmap_tx(port, desc);
 824 #if DEBUG_TX
 825                         printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
 826                                port->netdev->name, port->tx_buff_tab[n_desc]);
 827 #endif
 828                         free_buffer_irq(port->tx_buff_tab[n_desc]);
 829                         port->tx_buff_tab[n_desc] = NULL;
 830                 }
 831
 832                 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
 833                 queue_put_desc(port->plat->txreadyq, phys, desc);
 834                 if (start) { /* TX-ready queue was empty */
 835 #if DEBUG_TX
 836                         printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
 837                                port->netdev->name);
 838 #endif
 839                         netif_wake_queue(port->netdev);
 840                 }
 841         }
 842 }
 843
 844 static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
 845 {
 846         struct port *port = netdev_priv(dev);
 847         unsigned int txreadyq = port->plat->txreadyq;
 848         int len, offset, bytes, n;
 849         void *mem;
 850         u32 phys;
 851         struct desc *desc;
 852
 853 #if DEBUG_TX
 854         printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
 855 #endif
 856
 857         if (unlikely(skb->len > MAX_MRU)) {
 858                 dev_kfree_skb(skb);
 859                 dev->stats.tx_errors++;
 860                 return NETDEV_TX_OK;
 861         }
 862
 863         debug_pkt(dev, "eth_xmit", skb->data, skb->len);
 864
 865         len = skb->len;
 866 #ifdef __ARMEB__
 867         offset = 0; /* no need to keep alignment */
 868         bytes = len;
 869         mem = skb->data;
 870 #else
 871         offset = (int)skb->data & 3; /* keep 32-bit alignment */
 872         bytes = ALIGN(offset + len, 4);
 873         if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
 874                 dev_kfree_skb(skb);
 875                 dev->stats.tx_dropped++;
 876                 return NETDEV_TX_OK;
 877         }
 878         memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
 879 #endif
 880
 881         phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
 882         if (dma_mapping_error(&dev->dev, phys)) {
 883                 dev_kfree_skb(skb);
 884 #ifndef __ARMEB__
 885                 kfree(mem);
 886 #endif
 887                 dev->stats.tx_dropped++;
 888                 return NETDEV_TX_OK;
 889         }
 890
 891         n = queue_get_desc(txreadyq, port, 1);
 892         BUG_ON(n < 0);
 893         desc = tx_desc_ptr(port, n);
 894
 895 #ifdef __ARMEB__
 896         port->tx_buff_tab[n] = skb;
 897 #else
 898         port->tx_buff_tab[n] = mem;
 899 #endif
 900         desc->data = phys + offset;
 901         desc->buf_len = desc->pkt_len = len;
 902
 903         /* NPE firmware pads short frames with zeros internally */
 904         wmb();
 905         queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
 906
 907         if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
 908 #if DEBUG_TX
 909                 printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
 910 #endif
 911                 netif_stop_queue(dev);
 912                 /* we could miss TX ready interrupt */
 913                 /* really empty in fact */
 914                 if (!qmgr_stat_below_low_watermark(txreadyq)) {
 915 #if DEBUG_TX
 916                         printk(KERN_DEBUG "%s: eth_xmit ready again\n",
 917                                dev->name);
 918 #endif
 919                         netif_wake_queue(dev);
 920                 }
 921         }
 922
 923 #if DEBUG_TX
 924         printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
 925 #endif
 926
 927         ixp_tx_timestamp(port, skb);
 928         skb_tx_timestamp(skb);
 929
 930 #ifndef __ARMEB__
 931         dev_kfree_skb(skb);
 932 #endif
 933         return NETDEV_TX_OK;
 934 }
 935
 936
 937 static void eth_set_mcast_list(struct net_device *dev)
 938 {
 939         struct port *port = netdev_priv(dev);
 940         struct netdev_hw_addr *ha;
 941         u8 diffs[ETH_ALEN], *addr;
 942         int i;
 943         static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
 944
 945         if (dev->flags & IFF_ALLMULTI) {
 946                 for (i = 0; i < ETH_ALEN; i++) {
 947                         __raw_writel(allmulti[i], &port->regs->mcast_addr[i]);
 948                         __raw_writel(allmulti[i], &port->regs->mcast_mask[i]);
 949                 }
 950                 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
 951                         &port->regs->rx_control[0]);
 952                 return;
 953         }
 954
 955         if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) {
 956                 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
 957                              &port->regs->rx_control[0]);
 958                 return;
 959         }
 960
 961         memset(diffs, 0, ETH_ALEN);
 962
 963         addr = NULL;
 964         netdev_for_each_mc_addr(ha, dev) {
 965                 if (!addr)
 966                         addr = ha->addr; /* first MAC address */
 967                 for (i = 0; i < ETH_ALEN; i++)
 968                         diffs[i] |= addr[i] ^ ha->addr[i];
 969         }
 970
 971         for (i = 0; i < ETH_ALEN; i++) {
 972                 __raw_writel(addr[i], &port->regs->mcast_addr[i]);
 973                 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
 974         }
 975
 976         __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
 977                      &port->regs->rx_control[0]);
 978 }
 979
 980
 981 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
 982 {
 983         struct port *port = netdev_priv(dev);
 984
 985         if (!netif_running(dev))
 986                 return -EINVAL;
 987
 988         if (cpu_is_ixp46x()) {
 989                 if (cmd == SIOCSHWTSTAMP)
 990                         return hwtstamp_set(dev, req);
 991                 if (cmd == SIOCGHWTSTAMP)
 992                         return hwtstamp_get(dev, req);
 993         }
 994
 995         return phy_mii_ioctl(port->phydev, req, cmd);
 996 }
 997
 998 /* ethtool support */
 999
1000 static void ixp4xx_get_drvinfo(struct net_device *dev,
1001                                struct ethtool_drvinfo *info)
1002 {
1003         struct port *port = netdev_priv(dev);
1004
1005         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1006         snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u",
1007                  port->firmware[0], port->firmware[1],
1008                  port->firmware[2], port->firmware[3]);
1009         strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
1010 }
1011
1012 static int ixp4xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1013 {
1014         struct port *port = netdev_priv(dev);
1015         return phy_ethtool_gset(port->phydev, cmd);
1016 }
1017
1018 static int ixp4xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1019 {
1020         struct port *port = netdev_priv(dev);
1021         return phy_ethtool_sset(port->phydev, cmd);
1022 }
1023
1024 static int ixp4xx_nway_reset(struct net_device *dev)
1025 {
1026         struct port *port = netdev_priv(dev);
1027         return phy_start_aneg(port->phydev);
1028 }
1029
1030 int ixp46x_phc_index = -1;
1031 EXPORT_SYMBOL_GPL(ixp46x_phc_index);
1032
1033 static int ixp4xx_get_ts_info(struct net_device *dev,
1034                               struct ethtool_ts_info *info)
1035 {
1036         if (!cpu_is_ixp46x()) {
1037                 info->so_timestamping =
1038                         SOF_TIMESTAMPING_TX_SOFTWARE |
1039                         SOF_TIMESTAMPING_RX_SOFTWARE |
1040                         SOF_TIMESTAMPING_SOFTWARE;
1041                 info->phc_index = -1;
1042                 return 0;
1043         }
1044         info->so_timestamping =
1045                 SOF_TIMESTAMPING_TX_HARDWARE |
1046                 SOF_TIMESTAMPING_RX_HARDWARE |
1047                 SOF_TIMESTAMPING_RAW_HARDWARE;
1048         info->phc_index = ixp46x_phc_index;
1049         info->tx_types =
1050                 (1 << HWTSTAMP_TX_OFF) |
1051                 (1 << HWTSTAMP_TX_ON);
1052         info->rx_filters =
1053                 (1 << HWTSTAMP_FILTER_NONE) |
1054                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1055                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ);
1056         return 0;
1057 }
1058
1059 static const struct ethtool_ops ixp4xx_ethtool_ops = {
1060         .get_drvinfo = ixp4xx_get_drvinfo,
1061         .get_settings = ixp4xx_get_settings,
1062         .set_settings = ixp4xx_set_settings,
1063         .nway_reset = ixp4xx_nway_reset,
1064         .get_link = ethtool_op_get_link,
1065         .get_ts_info = ixp4xx_get_ts_info,
1066 };
1067
1068
1069 static int request_queues(struct port *port)
1070 {
1071         int err;
1072
1073         err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0,
1074                                  "%s:RX-free", port->netdev->name);
1075         if (err)
1076                 return err;
1077
1078         err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0,
1079                                  "%s:RX", port->netdev->name);
1080         if (err)
1081                 goto rel_rxfree;
1082
1083         err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0,
1084                                  "%s:TX", port->netdev->name);
1085         if (err)
1086                 goto rel_rx;
1087
1088         err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
1089                                  "%s:TX-ready", port->netdev->name);
1090         if (err)
1091                 goto rel_tx;
1092
1093         /* TX-done queue handles skbs sent out by the NPEs */
1094         if (!ports_open) {
1095                 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0,
1096                                          "%s:TX-done", DRV_NAME);
1097                 if (err)
1098                         goto rel_txready;
1099         }
1100         return 0;
1101
1102 rel_txready:
1103         qmgr_release_queue(port->plat->txreadyq);
1104 rel_tx:
1105         qmgr_release_queue(TX_QUEUE(port->id));
1106 rel_rx:
1107         qmgr_release_queue(port->plat->rxq);
1108 rel_rxfree:
1109         qmgr_release_queue(RXFREE_QUEUE(port->id));
1110         printk(KERN_DEBUG "%s: unable to request hardware queues\n",
1111                port->netdev->name);
1112         return err;
1113 }
1114
1115 static void release_queues(struct port *port)
1116 {
1117         qmgr_release_queue(RXFREE_QUEUE(port->id));
1118         qmgr_release_queue(port->plat->rxq);
1119         qmgr_release_queue(TX_QUEUE(port->id));
1120         qmgr_release_queue(port->plat->txreadyq);
1121
1122         if (!ports_open)
1123                 qmgr_release_queue(TXDONE_QUEUE);
1124 }
1125
1126 static int init_queues(struct port *port)
1127 {
1128         int i;
1129
1130         if (!ports_open) {
1131                 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
1132                                            POOL_ALLOC_SIZE, 32, 0);
1133                 if (!dma_pool)
1134                         return -ENOMEM;
1135         }
1136
1137         if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
1138                                               &port->desc_tab_phys)))
1139                 return -ENOMEM;
1140         memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
1141         memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
1142         memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
1143
1144         /* Setup RX buffers */
1145         for (i = 0; i < RX_DESCS; i++) {
1146                 struct desc *desc = rx_desc_ptr(port, i);
1147                 buffer_t *buff; /* skb or kmalloc()ated memory */
1148                 void *data;
1149 #ifdef __ARMEB__
1150                 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE)))
1151                         return -ENOMEM;
1152                 data = buff->data;
1153 #else
1154                 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL)))
1155                         return -ENOMEM;
1156                 data = buff;
1157 #endif
1158                 desc->buf_len = MAX_MRU;
1159                 desc->data = dma_map_single(&port->netdev->dev, data,
1160                                             RX_BUFF_SIZE, DMA_FROM_DEVICE);
1161                 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1162                         free_buffer(buff);
1163                         return -EIO;
1164                 }
1165                 desc->data += NET_IP_ALIGN;
1166                 port->rx_buff_tab[i] = buff;
1167         }
1168
1169         return 0;
1170 }
1171
1172 static void destroy_queues(struct port *port)
1173 {
1174         int i;
1175
1176         if (port->desc_tab) {
1177                 for (i = 0; i < RX_DESCS; i++) {
1178                         struct desc *desc = rx_desc_ptr(port, i);
1179                         buffer_t *buff = port->rx_buff_tab[i];
1180                         if (buff) {
1181                                 dma_unmap_single(&port->netdev->dev,
1182                                                  desc->data - NET_IP_ALIGN,
1183                                                  RX_BUFF_SIZE, DMA_FROM_DEVICE);
1184                                 free_buffer(buff);
1185                         }
1186                 }
1187                 for (i = 0; i < TX_DESCS; i++) {
1188                         struct desc *desc = tx_desc_ptr(port, i);
1189                         buffer_t *buff = port->tx_buff_tab[i];
1190                         if (buff) {
1191                                 dma_unmap_tx(port, desc);
1192                                 free_buffer(buff);
1193                         }
1194                 }
1195                 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1196                 port->desc_tab = NULL;
1197         }
1198
1199         if (!ports_open && dma_pool) {
1200                 dma_pool_destroy(dma_pool);
1201                 dma_pool = NULL;
1202         }
1203 }
1204
1205 static int eth_open(struct net_device *dev)
1206 {
1207         struct port *port = netdev_priv(dev);
1208         struct npe *npe = port->npe;
1209         struct msg msg;
1210         int i, err;
1211
1212         if (!npe_running(npe)) {
1213                 err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
1214                 if (err)
1215                         return err;
1216
1217                 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
1218                         printk(KERN_ERR "%s: %s not responding\n", dev->name,
1219                                npe_name(npe));
1220                         return -EIO;
1221                 }
1222                 port->firmware[0] = msg.byte4;
1223                 port->firmware[1] = msg.byte5;
1224                 port->firmware[2] = msg.byte6;
1225                 port->firmware[3] = msg.byte7;
1226         }
1227
1228         memset(&msg, 0, sizeof(msg));
1229         msg.cmd = NPE_VLAN_SETRXQOSENTRY;
1230         msg.eth_id = port->id;
1231         msg.byte5 = port->plat->rxq | 0x80;
1232         msg.byte7 = port->plat->rxq << 4;
1233         for (i = 0; i < 8; i++) {
1234                 msg.byte3 = i;
1235                 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
1236                         return -EIO;
1237         }
1238
1239         msg.cmd = NPE_EDB_SETPORTADDRESS;
1240         msg.eth_id = PHYSICAL_ID(port->id);
1241         msg.byte2 = dev->dev_addr[0];
1242         msg.byte3 = dev->dev_addr[1];
1243         msg.byte4 = dev->dev_addr[2];
1244         msg.byte5 = dev->dev_addr[3];
1245         msg.byte6 = dev->dev_addr[4];
1246         msg.byte7 = dev->dev_addr[5];
1247         if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
1248                 return -EIO;
1249
1250         memset(&msg, 0, sizeof(msg));
1251         msg.cmd = NPE_FW_SETFIREWALLMODE;
1252         msg.eth_id = port->id;
1253         if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
1254                 return -EIO;
1255
1256         if ((err = request_queues(port)) != 0)
1257                 return err;
1258
1259         if ((err = init_queues(port)) != 0) {
1260                 destroy_queues(port);
1261                 release_queues(port);
1262                 return err;
1263         }
1264
1265         port->speed = 0;        /* force "link up" message */
1266         phy_start(port->phydev);
1267
1268         for (i = 0; i < ETH_ALEN; i++)
1269                 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
1270         __raw_writel(0x08, &port->regs->random_seed);
1271         __raw_writel(0x12, &port->regs->partial_empty_threshold);
1272         __raw_writel(0x30, &port->regs->partial_full_threshold);
1273         __raw_writel(0x08, &port->regs->tx_start_bytes);
1274         __raw_writel(0x15, &port->regs->tx_deferral);
1275         __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
1276         __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
1277         __raw_writel(0x80, &port->regs->slot_time);
1278         __raw_writel(0x01, &port->regs->int_clock_threshold);
1279
1280         /* Populate queues with buffers, no failure after this point */
1281         for (i = 0; i < TX_DESCS; i++)
1282                 queue_put_desc(port->plat->txreadyq,
1283                                tx_desc_phys(port, i), tx_desc_ptr(port, i));
1284
1285         for (i = 0; i < RX_DESCS; i++)
1286                 queue_put_desc(RXFREE_QUEUE(port->id),
1287                                rx_desc_phys(port, i), rx_desc_ptr(port, i));
1288
1289         __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1290         __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1291         __raw_writel(0, &port->regs->rx_control[1]);
1292         __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1293
1294         napi_enable(&port->napi);
1295         eth_set_mcast_list(dev);
1296         netif_start_queue(dev);
1297
1298         qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1299                      eth_rx_irq, dev);
1300         if (!ports_open) {
1301                 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1302                              eth_txdone_irq, NULL);
1303                 qmgr_enable_irq(TXDONE_QUEUE);
1304         }
1305         ports_open++;
1306         /* we may already have RX data, enables IRQ */
1307         napi_schedule(&port->napi);
1308         return 0;
1309 }
1310
1311 static int eth_close(struct net_device *dev)
1312 {
1313         struct port *port = netdev_priv(dev);
1314         struct msg msg;
1315         int buffs = RX_DESCS; /* allocated RX buffers */
1316         int i;
1317
1318         ports_open--;
1319         qmgr_disable_irq(port->plat->rxq);
1320         napi_disable(&port->napi);
1321         netif_stop_queue(dev);
1322
1323         while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1324                 buffs--;
1325
1326         memset(&msg, 0, sizeof(msg));
1327         msg.cmd = NPE_SETLOOPBACK_MODE;
1328         msg.eth_id = port->id;
1329         msg.byte3 = 1;
1330         if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1331                 printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
1332
1333         i = 0;
1334         do {                    /* drain RX buffers */
1335                 while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1336                         buffs--;
1337                 if (!buffs)
1338                         break;
1339                 if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1340                         /* we have to inject some packet */
1341                         struct desc *desc;
1342                         u32 phys;
1343                         int n = queue_get_desc(port->plat->txreadyq, port, 1);
1344                         BUG_ON(n < 0);
1345                         desc = tx_desc_ptr(port, n);
1346                         phys = tx_desc_phys(port, n);
1347                         desc->buf_len = desc->pkt_len = 1;
1348                         wmb();
1349                         queue_put_desc(TX_QUEUE(port->id), phys, desc);
1350                 }
1351                 udelay(1);
1352         } while (++i < MAX_CLOSE_WAIT);
1353
1354         if (buffs)
1355                 printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1356                        " left in NPE\n", dev->name, buffs);
1357 #if DEBUG_CLOSE
1358         if (!buffs)
1359                 printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
1360 #endif
1361
1362         buffs = TX_DESCS;
1363         while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1364                 buffs--; /* cancel TX */
1365
1366         i = 0;
1367         do {
1368                 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1369                         buffs--;
1370                 if (!buffs)
1371                         break;
1372         } while (++i < MAX_CLOSE_WAIT);
1373
1374         if (buffs)
1375                 printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1376                        "left in NPE\n", dev->name, buffs);
1377 #if DEBUG_CLOSE
1378         if (!buffs)
1379                 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1380 #endif
1381
1382         msg.byte3 = 0;
1383         if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1384                 printk(KERN_CRIT "%s: unable to disable loopback\n",
1385                        dev->name);
1386
1387         phy_stop(port->phydev);
1388
1389         if (!ports_open)
1390                 qmgr_disable_irq(TXDONE_QUEUE);
1391         destroy_queues(port);
1392         release_queues(port);
1393         return 0;
1394 }
1395
1396 static const struct net_device_ops ixp4xx_netdev_ops = {
1397         .ndo_open = eth_open,
1398         .ndo_stop = eth_close,
1399         .ndo_start_xmit = eth_xmit,
1400         .ndo_set_rx_mode = eth_set_mcast_list,
1401         .ndo_do_ioctl = eth_ioctl,
1402         .ndo_change_mtu = eth_change_mtu,
1403         .ndo_set_mac_address = eth_mac_addr,
1404         .ndo_validate_addr = eth_validate_addr,
1405 };
1406
1407 static int eth_init_one(struct platform_device *pdev)
1408 {
1409         struct port *port;
1410         struct net_device *dev;
1411         struct eth_plat_info *plat = dev_get_platdata(&pdev->dev);
1412         u32 regs_phys;
1413         char phy_id[MII_BUS_ID_SIZE + 3];
1414         int err;
1415
1416         if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) {
1417                 pr_err("ixp4xx_eth: bad ptp filter\n");
1418                 return -EINVAL;
1419         }
1420
1421         if (!(dev = alloc_etherdev(sizeof(struct port))))
1422                 return -ENOMEM;
1423
1424         SET_NETDEV_DEV(dev, &pdev->dev);
1425         port = netdev_priv(dev);
1426         port->netdev = dev;
1427         port->id = pdev->id;
1428
1429         switch (port->id) {
1430         case IXP4XX_ETH_NPEA:
1431                 port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
1432                 regs_phys  = IXP4XX_EthA_BASE_PHYS;
1433                 break;
1434         case IXP4XX_ETH_NPEB:
1435                 port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1436                 regs_phys  = IXP4XX_EthB_BASE_PHYS;
1437                 break;
1438         case IXP4XX_ETH_NPEC:
1439                 port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
1440                 regs_phys  = IXP4XX_EthC_BASE_PHYS;
1441                 break;
1442         default:
1443                 err = -ENODEV;
1444                 goto err_free;
1445         }
1446
1447         dev->netdev_ops = &ixp4xx_netdev_ops;
1448         dev->ethtool_ops = &ixp4xx_ethtool_ops;
1449         dev->tx_queue_len = 100;
1450
1451         netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT);
1452
1453         if (!(port->npe = npe_request(NPE_ID(port->id)))) {
1454                 err = -EIO;
1455                 goto err_free;
1456         }
1457
1458         port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
1459         if (!port->mem_res) {
1460                 err = -EBUSY;
1461                 goto err_npe_rel;
1462         }
1463
1464         port->plat = plat;
1465         npe_port_tab[NPE_ID(port->id)] = port;
1466         memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
1467
1468         platform_set_drvdata(pdev, dev);
1469
1470         __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1471                      &port->regs->core_control);
1472         udelay(50);
1473         __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1474         udelay(50);
1475
1476         snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
1477                 mdio_bus->id, plat->phy);
1478         port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link,
1479                                    PHY_INTERFACE_MODE_MII);
1480         if (IS_ERR(port->phydev)) {
1481                 err = PTR_ERR(port->phydev);
1482                 goto err_free_mem;
1483         }
1484
1485         port->phydev->irq = PHY_POLL;
1486
1487         if ((err = register_netdev(dev)))
1488                 goto err_phy_dis;
1489
1490         printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
1491                npe_name(port->npe));
1492
1493         return 0;
1494
1495 err_phy_dis:
1496         phy_disconnect(port->phydev);
1497 err_free_mem:
1498         npe_port_tab[NPE_ID(port->id)] = NULL;
1499         release_resource(port->mem_res);
1500 err_npe_rel:
1501         npe_release(port->npe);
1502 err_free:
1503         free_netdev(dev);
1504         return err;
1505 }
1506
1507 static int eth_remove_one(struct platform_device *pdev)
1508 {
1509         struct net_device *dev = platform_get_drvdata(pdev);
1510         struct port *port = netdev_priv(dev);
1511
1512         unregister_netdev(dev);
1513         phy_disconnect(port->phydev);
1514         npe_port_tab[NPE_ID(port->id)] = NULL;
1515         npe_release(port->npe);
1516         release_resource(port->mem_res);
1517         free_netdev(dev);
1518         return 0;
1519 }
1520
1521 static struct platform_driver ixp4xx_eth_driver = {
1522         .driver.name    = DRV_NAME,
1523         .probe          = eth_init_one,
1524         .remove         = eth_remove_one,
1525 };
1526
1527 static int __init eth_init_module(void)
1528 {
1529         int err;
1530         if ((err = ixp4xx_mdio_register()))
1531                 return err;
1532         return platform_driver_register(&ixp4xx_eth_driver);
1533 }
1534
1535 static void __exit eth_cleanup_module(void)
1536 {
1537         platform_driver_unregister(&ixp4xx_eth_driver);
1538         ixp4xx_mdio_remove();
1539 }
1540
1541 MODULE_AUTHOR("Krzysztof Halasa");
1542 MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1543 MODULE_LICENSE("GPL v2");
1544 MODULE_ALIAS("platform:ixp4xx_eth");
1545 module_init(eth_init_module);
1546 module_exit(eth_cleanup_module);