2 * DaVinci Ethernet Medium Access Controller
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
6 * Copyright (C) 2009 Texas Instruments.
8 * ---------------------------------------------------------------------------
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/sched.h>
35 #include <linux/string.h>
36 #include <linux/timer.h>
37 #include <linux/errno.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/init.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <linux/skbuff.h>
47 #include <linux/ethtool.h>
48 #include <linux/highmem.h>
49 #include <linux/proc_fs.h>
50 #include <linux/ctype.h>
51 #include <linux/spinlock.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/clk.h>
54 #include <linux/platform_device.h>
55 #include <linux/semaphore.h>
56 #include <linux/phy.h>
57 #include <linux/bitops.h>
59 #include <linux/uaccess.h>
60 #include <linux/pm_runtime.h>
61 #include <linux/davinci_emac.h>
63 #include <linux/of_address.h>
64 #include <linux/of_device.h>
65 #include <linux/of_mdio.h>
66 #include <linux/of_irq.h>
67 #include <linux/of_net.h>
72 #include "davinci_cpdma.h"
74 static int debug_level;
75 module_param(debug_level, int, 0);
76 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
78 /* Netif debug messages possible */
79 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
87 NETIF_MSG_TX_QUEUED | \
90 NETIF_MSG_RX_STATUS | \
96 #define EMAC_MAJOR_VERSION 6
97 #define EMAC_MINOR_VERSION 1
98 #define EMAC_MODULE_VERSION "6.1"
99 MODULE_VERSION(EMAC_MODULE_VERSION);
100 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
102 /* Configuration items */
103 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */
104 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
105 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
106 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
107 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
108 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
109 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */
110 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */
111 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
112 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
113 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
114 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
116 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
117 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
119 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
120 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
121 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
122 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
123 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
124 #define EMAC_DEF_RX_NUM_DESC (128)
125 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
126 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
127 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
129 /* Buffer descriptor parameters */
130 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
131 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
133 /* EMAC register related defines */
134 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
135 #define EMAC_NUM_MULTICAST_BITS (64)
136 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
137 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
138 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
139 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
140 #define EMAC_INT_MASK_CLEAR (0xFF)
142 /* RX MBP register bit positions */
143 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
144 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
145 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
146 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
147 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
148 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
149 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
150 #define EMAC_RXMBP_PROMCH_SHIFT (16)
151 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
152 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
153 #define EMAC_RXMBP_BROADCH_SHIFT (8)
154 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
155 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
156 #define EMAC_RXMBP_MULTICH_SHIFT (0)
157 #define EMAC_RXMBP_MULTICH_MASK (0x7)
158 #define EMAC_RXMBP_CHMASK (0x7)
160 /* EMAC register definitions/bit maps used */
161 # define EMAC_MBP_RXPROMISC (0x00200000)
162 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
163 # define EMAC_MBP_RXBCAST (0x00002000)
164 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
165 # define EMAC_MBP_RXMCAST (0x00000020)
166 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
168 /* EMAC mac_control register */
169 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
170 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
171 #define EMAC_MACCONTROL_GMIIEN BIT(5)
172 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
173 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
174 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
176 /* GIGABIT MODE related bits */
177 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
178 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
180 /* EMAC mac_status register */
181 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
182 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
183 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
184 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
185 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
186 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
187 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
188 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
190 /* EMAC RX register masks */
191 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
192 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
194 /* MAC_IN_VECTOR (0x180) register bit fields */
195 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
196 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
197 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
198 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
200 /** NOTE:: For DM646x the IN_VECTOR has changed */
201 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
202 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
203 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
204 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
206 /* CPPI bit positions */
207 #define EMAC_CPPI_SOP_BIT BIT(31)
208 #define EMAC_CPPI_EOP_BIT BIT(30)
209 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
210 #define EMAC_CPPI_EOQ_BIT BIT(28)
211 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
212 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
213 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
214 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
215 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
217 /* Max hardware defines */
218 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
219 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
221 /* EMAC Peripheral Device Register Memory Layout structure */
222 #define EMAC_MACINVECTOR 0x90
224 #define EMAC_DM646X_MACEOIVECTOR 0x94
226 #define EMAC_MACINTSTATRAW 0xB0
227 #define EMAC_MACINTSTATMASKED 0xB4
228 #define EMAC_MACINTMASKSET 0xB8
229 #define EMAC_MACINTMASKCLEAR 0xBC
231 #define EMAC_RXMBPENABLE 0x100
232 #define EMAC_RXUNICASTSET 0x104
233 #define EMAC_RXUNICASTCLEAR 0x108
234 #define EMAC_RXMAXLEN 0x10C
235 #define EMAC_RXBUFFEROFFSET 0x110
236 #define EMAC_RXFILTERLOWTHRESH 0x114
238 #define EMAC_MACCONTROL 0x160
239 #define EMAC_MACSTATUS 0x164
240 #define EMAC_EMCONTROL 0x168
241 #define EMAC_FIFOCONTROL 0x16C
242 #define EMAC_MACCONFIG 0x170
243 #define EMAC_SOFTRESET 0x174
244 #define EMAC_MACSRCADDRLO 0x1D0
245 #define EMAC_MACSRCADDRHI 0x1D4
246 #define EMAC_MACHASH1 0x1D8
247 #define EMAC_MACHASH2 0x1DC
248 #define EMAC_MACADDRLO 0x500
249 #define EMAC_MACADDRHI 0x504
250 #define EMAC_MACINDEX 0x508
252 /* EMAC statistics registers */
253 #define EMAC_RXGOODFRAMES 0x200
254 #define EMAC_RXBCASTFRAMES 0x204
255 #define EMAC_RXMCASTFRAMES 0x208
256 #define EMAC_RXPAUSEFRAMES 0x20C
257 #define EMAC_RXCRCERRORS 0x210
258 #define EMAC_RXALIGNCODEERRORS 0x214
259 #define EMAC_RXOVERSIZED 0x218
260 #define EMAC_RXJABBER 0x21C
261 #define EMAC_RXUNDERSIZED 0x220
262 #define EMAC_RXFRAGMENTS 0x224
263 #define EMAC_RXFILTERED 0x228
264 #define EMAC_RXQOSFILTERED 0x22C
265 #define EMAC_RXOCTETS 0x230
266 #define EMAC_TXGOODFRAMES 0x234
267 #define EMAC_TXBCASTFRAMES 0x238
268 #define EMAC_TXMCASTFRAMES 0x23C
269 #define EMAC_TXPAUSEFRAMES 0x240
270 #define EMAC_TXDEFERRED 0x244
271 #define EMAC_TXCOLLISION 0x248
272 #define EMAC_TXSINGLECOLL 0x24C
273 #define EMAC_TXMULTICOLL 0x250
274 #define EMAC_TXEXCESSIVECOLL 0x254
275 #define EMAC_TXLATECOLL 0x258
276 #define EMAC_TXUNDERRUN 0x25C
277 #define EMAC_TXCARRIERSENSE 0x260
278 #define EMAC_TXOCTETS 0x264
279 #define EMAC_NETOCTETS 0x280
280 #define EMAC_RXSOFOVERRUNS 0x284
281 #define EMAC_RXMOFOVERRUNS 0x288
282 #define EMAC_RXDMAOVERRUNS 0x28C
284 /* EMAC DM644x control registers */
285 #define EMAC_CTRL_EWCTL (0x4)
286 #define EMAC_CTRL_EWINTTCNT (0x8)
288 /* EMAC DM644x control module masks */
289 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
290 #define EMAC_DM644X_INTMIN_INTVL 0x1
291 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
293 /* EMAC DM646X control module registers */
294 #define EMAC_DM646X_CMINTCTRL 0x0C
295 #define EMAC_DM646X_CMRXINTEN 0x14
296 #define EMAC_DM646X_CMTXINTEN 0x18
297 #define EMAC_DM646X_CMRXINTMAX 0x70
298 #define EMAC_DM646X_CMTXINTMAX 0x74
300 /* EMAC DM646X control module masks */
301 #define EMAC_DM646X_INTPACEEN (0x3 << 16)
302 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
303 #define EMAC_DM646X_CMINTMAX_CNT 63
304 #define EMAC_DM646X_CMINTMIN_CNT 2
305 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
306 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
309 /* EMAC EOI codes for C0 */
310 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
311 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
313 /* EMAC Stats Clear Mask */
314 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
316 /* emac_priv: EMAC private data structure
318 * EMAC adapter private data structure
322 struct net_device *ndev;
323 struct platform_device *pdev;
324 struct napi_struct napi;
326 void __iomem *remap_addr;
328 void __iomem *emac_base;
329 void __iomem *ctrl_base;
330 struct cpdma_ctlr *dma;
331 struct cpdma_chan *txchan;
332 struct cpdma_chan *rxchan;
333 u32 link; /* 1=link on, 0=link off */
334 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
335 u32 duplex; /* Link duplex: 0=Half, 1=Full */
344 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
347 struct device_node *phy_node;
348 struct phy_device *phydev;
350 /*platform specific members*/
351 void (*int_enable) (void);
352 void (*int_disable) (void);
355 /* EMAC TX Host Error description strings */
356 static char *emac_txhost_errcodes[16] = {
357 "No error", "SOP error", "Ownership bit not set in SOP buffer",
358 "Zero Next Buffer Descriptor Pointer Without EOP",
359 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
360 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
361 "Reserved", "Reserved", "Reserved", "Reserved"
364 /* EMAC RX Host Error description strings */
365 static char *emac_rxhost_errcodes[16] = {
366 "No error", "Reserved", "Ownership bit not set in input buffer",
367 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
368 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
369 "Reserved", "Reserved", "Reserved", "Reserved"
373 #define emac_read(reg) ioread32(priv->emac_base + (reg))
374 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
376 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
377 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
380 * emac_dump_regs - Dump important EMAC registers to debug terminal
381 * @priv: The DaVinci EMAC private adapter structure
383 * Executes ethtool set cmd & sets phy mode
386 static void emac_dump_regs(struct emac_priv *priv)
388 struct device *emac_dev = &priv->ndev->dev;
390 /* Print important registers in EMAC */
391 dev_info(emac_dev, "EMAC Basic registers\n");
392 if (priv->version == EMAC_VERSION_1) {
393 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
394 emac_ctrl_read(EMAC_CTRL_EWCTL),
395 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
397 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
398 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
399 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
400 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
401 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
402 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
403 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
404 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
405 dev_info(emac_dev, "EMAC Statistics\n");
406 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
407 emac_read(EMAC_RXGOODFRAMES));
408 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
409 emac_read(EMAC_RXBCASTFRAMES));
410 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
411 emac_read(EMAC_RXMCASTFRAMES));
412 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
413 emac_read(EMAC_RXPAUSEFRAMES));
414 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
415 emac_read(EMAC_RXCRCERRORS));
416 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
417 emac_read(EMAC_RXALIGNCODEERRORS));
418 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
419 emac_read(EMAC_RXOVERSIZED));
420 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
421 emac_read(EMAC_RXJABBER));
422 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
423 emac_read(EMAC_RXUNDERSIZED));
424 dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
425 emac_read(EMAC_RXFRAGMENTS));
426 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
427 emac_read(EMAC_RXFILTERED));
428 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
429 emac_read(EMAC_RXQOSFILTERED));
430 dev_info(emac_dev, "EMAC: rx_octets:%d\n",
431 emac_read(EMAC_RXOCTETS));
432 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
433 emac_read(EMAC_TXGOODFRAMES));
434 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
435 emac_read(EMAC_TXBCASTFRAMES));
436 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
437 emac_read(EMAC_TXMCASTFRAMES));
438 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
439 emac_read(EMAC_TXPAUSEFRAMES));
440 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
441 emac_read(EMAC_TXDEFERRED));
442 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
443 emac_read(EMAC_TXCOLLISION));
444 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
445 emac_read(EMAC_TXSINGLECOLL));
446 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
447 emac_read(EMAC_TXMULTICOLL));
448 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
449 emac_read(EMAC_TXEXCESSIVECOLL));
450 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
451 emac_read(EMAC_TXLATECOLL));
452 dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
453 emac_read(EMAC_TXUNDERRUN));
454 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
455 emac_read(EMAC_TXCARRIERSENSE));
456 dev_info(emac_dev, "EMAC: tx_octets:%d\n",
457 emac_read(EMAC_TXOCTETS));
458 dev_info(emac_dev, "EMAC: net_octets:%d\n",
459 emac_read(EMAC_NETOCTETS));
460 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
461 emac_read(EMAC_RXSOFOVERRUNS));
462 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
463 emac_read(EMAC_RXMOFOVERRUNS));
464 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
465 emac_read(EMAC_RXDMAOVERRUNS));
467 cpdma_ctlr_dump(priv->dma);
471 * emac_get_drvinfo - Get EMAC driver information
472 * @ndev: The DaVinci EMAC network adapter
473 * @info: ethtool info structure containing name and version
475 * Returns EMAC driver information (name and version)
478 static void emac_get_drvinfo(struct net_device *ndev,
479 struct ethtool_drvinfo *info)
481 strlcpy(info->driver, emac_version_string, sizeof(info->driver));
482 strlcpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version));
486 * emac_get_settings - Get EMAC settings
487 * @ndev: The DaVinci EMAC network adapter
488 * @ecmd: ethtool command
490 * Executes ethool get command
493 static int emac_get_settings(struct net_device *ndev,
494 struct ethtool_cmd *ecmd)
496 struct emac_priv *priv = netdev_priv(ndev);
498 return phy_ethtool_gset(priv->phydev, ecmd);
505 * emac_set_settings - Set EMAC settings
506 * @ndev: The DaVinci EMAC network adapter
507 * @ecmd: ethtool command
509 * Executes ethool set command
512 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
514 struct emac_priv *priv = netdev_priv(ndev);
516 return phy_ethtool_sset(priv->phydev, ecmd);
523 * emac_get_coalesce - Get interrupt coalesce settings for this device
524 * @ndev : The DaVinci EMAC network adapter
525 * @coal : ethtool coalesce settings structure
527 * Fetch the current interrupt coalesce settings
530 static int emac_get_coalesce(struct net_device *ndev,
531 struct ethtool_coalesce *coal)
533 struct emac_priv *priv = netdev_priv(ndev);
535 coal->rx_coalesce_usecs = priv->coal_intvl;
541 * emac_set_coalesce - Set interrupt coalesce settings for this device
542 * @ndev : The DaVinci EMAC network adapter
543 * @coal : ethtool coalesce settings structure
545 * Set interrupt coalesce parameters
548 static int emac_set_coalesce(struct net_device *ndev,
549 struct ethtool_coalesce *coal)
551 struct emac_priv *priv = netdev_priv(ndev);
552 u32 int_ctrl, num_interrupts = 0;
553 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
555 if (!coal->rx_coalesce_usecs)
558 coal_intvl = coal->rx_coalesce_usecs;
560 switch (priv->version) {
562 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
563 prescale = priv->bus_freq_mhz * 4;
565 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
566 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
568 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
570 * Interrupt pacer works with 4us Pulse, we can
571 * throttle further by dilating the 4us pulse.
573 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
575 if (addnl_dvdr > 1) {
576 prescale *= addnl_dvdr;
577 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
579 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
583 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
587 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
589 int_ctrl |= EMAC_DM646X_INTPACEEN;
590 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
591 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
592 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
594 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
595 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
599 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
600 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
601 prescale = coal_intvl * priv->bus_freq_mhz;
602 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
603 prescale = EMAC_DM644X_EWINTCNT_MASK;
604 coal_intvl = prescale / priv->bus_freq_mhz;
606 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
611 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
612 priv->coal_intvl = coal_intvl;
619 /* ethtool_ops: DaVinci EMAC Ethtool structure
621 * Ethtool support for EMAC adapter
623 static const struct ethtool_ops ethtool_ops = {
624 .get_drvinfo = emac_get_drvinfo,
625 .get_settings = emac_get_settings,
626 .set_settings = emac_set_settings,
627 .get_link = ethtool_op_get_link,
628 .get_coalesce = emac_get_coalesce,
629 .set_coalesce = emac_set_coalesce,
630 .get_ts_info = ethtool_op_get_ts_info,
634 * emac_update_phystatus - Update Phy status
635 * @priv: The DaVinci EMAC private adapter structure
637 * Updates phy status and takes action for network queue if required
638 * based upon link status
641 static void emac_update_phystatus(struct emac_priv *priv)
646 struct net_device *ndev = priv->ndev;
648 mac_control = emac_read(EMAC_MACCONTROL);
649 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
650 DUPLEX_FULL : DUPLEX_HALF;
652 new_duplex = priv->phydev->duplex;
654 new_duplex = DUPLEX_FULL;
656 /* We get called only if link has changed (speed/duplex/status) */
657 if ((priv->link) && (new_duplex != cur_duplex)) {
658 priv->duplex = new_duplex;
659 if (DUPLEX_FULL == priv->duplex)
660 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
662 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
665 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
666 mac_control = emac_read(EMAC_MACCONTROL);
667 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
668 EMAC_DM646X_MACCONTORL_GIGFORCE);
670 /* Clear the GIG bit and GIGFORCE bit */
671 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
672 EMAC_DM646X_MACCONTORL_GIG);
674 if (priv->rmii_en && (priv->speed == SPEED_100))
675 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
677 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
680 /* Update mac_control if changed */
681 emac_write(EMAC_MACCONTROL, mac_control);
685 if (!netif_carrier_ok(ndev))
686 netif_carrier_on(ndev);
687 /* reactivate the transmit queue if it is stopped */
688 if (netif_running(ndev) && netif_queue_stopped(ndev))
689 netif_wake_queue(ndev);
692 if (netif_carrier_ok(ndev))
693 netif_carrier_off(ndev);
694 if (!netif_queue_stopped(ndev))
695 netif_stop_queue(ndev);
700 * hash_get - Calculate hash value from mac address
701 * @addr: mac address to delete from hash table
703 * Calculates hash value from mac address
706 static u32 hash_get(u8 *addr)
713 for (cnt = 0; cnt < 2; cnt++) {
715 hash ^= (tmpval >> 2) ^ (tmpval << 4);
717 hash ^= (tmpval >> 4) ^ (tmpval << 2);
719 hash ^= (tmpval >> 6) ^ (tmpval);
726 * hash_add - Hash function to add mac addr from hash table
727 * @priv: The DaVinci EMAC private adapter structure
728 * @mac_addr: mac address to delete from hash table
730 * Adds mac address to the internal hash table
733 static int hash_add(struct emac_priv *priv, u8 *mac_addr)
735 struct device *emac_dev = &priv->ndev->dev;
738 u32 hash_value = hash_get(mac_addr);
740 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
741 if (netif_msg_drv(priv)) {
742 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
743 "Hash %08x, should not be greater than %08x",
744 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
749 /* set the hash bit only if not previously set */
750 if (priv->multicast_hash_cnt[hash_value] == 0) {
751 rc = 1; /* hash value changed */
752 if (hash_value < 32) {
753 hash_bit = BIT(hash_value);
754 priv->mac_hash1 |= hash_bit;
756 hash_bit = BIT((hash_value - 32));
757 priv->mac_hash2 |= hash_bit;
761 /* incr counter for num of mcast addr's mapped to "this" hash bit */
762 ++priv->multicast_hash_cnt[hash_value];
768 * hash_del - Hash function to delete mac addr from hash table
769 * @priv: The DaVinci EMAC private adapter structure
770 * @mac_addr: mac address to delete from hash table
772 * Removes mac address from the internal hash table
775 static int hash_del(struct emac_priv *priv, u8 *mac_addr)
780 hash_value = hash_get(mac_addr);
781 if (priv->multicast_hash_cnt[hash_value] > 0) {
782 /* dec cntr for num of mcast addr's mapped to this hash bit */
783 --priv->multicast_hash_cnt[hash_value];
786 /* if counter still > 0, at least one multicast address refers
787 * to this hash bit. so return 0 */
788 if (priv->multicast_hash_cnt[hash_value] > 0)
791 if (hash_value < 32) {
792 hash_bit = BIT(hash_value);
793 priv->mac_hash1 &= ~hash_bit;
795 hash_bit = BIT((hash_value - 32));
796 priv->mac_hash2 &= ~hash_bit;
799 /* return 1 to indicate change in mac_hash registers reqd */
803 /* EMAC multicast operation */
804 #define EMAC_MULTICAST_ADD 0
805 #define EMAC_MULTICAST_DEL 1
806 #define EMAC_ALL_MULTI_SET 2
807 #define EMAC_ALL_MULTI_CLR 3
810 * emac_add_mcast - Set multicast address in the EMAC adapter (Internal)
811 * @priv: The DaVinci EMAC private adapter structure
812 * @action: multicast operation to perform
813 * mac_addr: mac address to set
815 * Set multicast addresses in EMAC adapter - internal function
818 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
820 struct device *emac_dev = &priv->ndev->dev;
824 case EMAC_MULTICAST_ADD:
825 update = hash_add(priv, mac_addr);
827 case EMAC_MULTICAST_DEL:
828 update = hash_del(priv, mac_addr);
830 case EMAC_ALL_MULTI_SET:
832 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
833 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
835 case EMAC_ALL_MULTI_CLR:
839 memset(&(priv->multicast_hash_cnt[0]), 0,
840 sizeof(priv->multicast_hash_cnt[0]) *
841 EMAC_NUM_MULTICAST_BITS);
844 if (netif_msg_drv(priv))
845 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
846 ": bad operation %d", action);
850 /* write to the hardware only if the register status chances */
852 emac_write(EMAC_MACHASH1, priv->mac_hash1);
853 emac_write(EMAC_MACHASH2, priv->mac_hash2);
858 * emac_dev_mcast_set - Set multicast address in the EMAC adapter
859 * @ndev: The DaVinci EMAC network adapter
861 * Set multicast addresses in EMAC adapter
864 static void emac_dev_mcast_set(struct net_device *ndev)
867 struct emac_priv *priv = netdev_priv(ndev);
869 mbp_enable = emac_read(EMAC_RXMBPENABLE);
870 if (ndev->flags & IFF_PROMISC) {
871 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
872 mbp_enable |= (EMAC_MBP_RXPROMISC);
874 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
875 if ((ndev->flags & IFF_ALLMULTI) ||
876 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
877 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
878 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
879 } else if (!netdev_mc_empty(ndev)) {
880 struct netdev_hw_addr *ha;
882 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
883 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
884 /* program multicast address list into EMAC hardware */
885 netdev_for_each_mc_addr(ha, ndev) {
886 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
890 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
891 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
894 /* Set mbp config register */
895 emac_write(EMAC_RXMBPENABLE, mbp_enable);
898 /*************************************************************************
899 * EMAC Hardware manipulation
900 *************************************************************************/
903 * emac_int_disable - Disable EMAC module interrupt (from adapter)
904 * @priv: The DaVinci EMAC private adapter structure
906 * Disable EMAC interrupt on the adapter
909 static void emac_int_disable(struct emac_priv *priv)
911 if (priv->version == EMAC_VERSION_2) {
914 local_irq_save(flags);
916 /* Program C0_Int_En to zero to turn off
917 * interrupts to the CPU */
918 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
919 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
920 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
921 if (priv->int_disable)
924 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
926 /* ack rxen only then a new pulse will be generated */
927 emac_write(EMAC_DM646X_MACEOIVECTOR,
928 EMAC_DM646X_MAC_EOI_C0_RXEN);
930 /* ack txen- only then a new pulse will be generated */
931 emac_write(EMAC_DM646X_MACEOIVECTOR,
932 EMAC_DM646X_MAC_EOI_C0_TXEN);
934 local_irq_restore(flags);
937 /* Set DM644x control registers for interrupt control */
938 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
943 * emac_int_enable - Enable EMAC module interrupt (from adapter)
944 * @priv: The DaVinci EMAC private adapter structure
946 * Enable EMAC interrupt on the adapter
949 static void emac_int_enable(struct emac_priv *priv)
951 if (priv->version == EMAC_VERSION_2) {
952 if (priv->int_enable)
955 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
956 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
958 /* In addition to turning on interrupt Enable, we need
959 * ack by writing appropriate values to the EOI
962 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
964 /* Set DM644x control registers for interrupt control */
965 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
970 * emac_irq - EMAC interrupt handler
971 * @irq: interrupt number
972 * @dev_id: EMAC network adapter data structure ptr
974 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
975 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
977 * Returns interrupt handled condition
979 static irqreturn_t emac_irq(int irq, void *dev_id)
981 struct net_device *ndev = (struct net_device *)dev_id;
982 struct emac_priv *priv = netdev_priv(ndev);
985 if (likely(netif_running(priv->ndev))) {
986 emac_int_disable(priv);
987 napi_schedule(&priv->napi);
989 /* we are closing down, so dont process anything */
994 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
996 struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size);
999 skb_reserve(skb, NET_IP_ALIGN);
1003 static void emac_rx_handler(void *token, int len, int status)
1005 struct sk_buff *skb = token;
1006 struct net_device *ndev = skb->dev;
1007 struct emac_priv *priv = netdev_priv(ndev);
1008 struct device *emac_dev = &ndev->dev;
1011 /* free and bail if we are shutting down */
1012 if (unlikely(!netif_running(ndev))) {
1013 dev_kfree_skb_any(skb);
1017 /* recycle on receive error */
1019 ndev->stats.rx_errors++;
1023 /* feed received packet up the stack */
1025 skb->protocol = eth_type_trans(skb, ndev);
1026 netif_receive_skb(skb);
1027 ndev->stats.rx_bytes += len;
1028 ndev->stats.rx_packets++;
1030 /* alloc a new packet for receive */
1031 skb = emac_rx_alloc(priv);
1033 if (netif_msg_rx_err(priv) && net_ratelimit())
1034 dev_err(emac_dev, "failed rx buffer alloc\n");
1039 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1040 skb_tailroom(skb), 0);
1042 WARN_ON(ret == -ENOMEM);
1043 if (unlikely(ret < 0))
1044 dev_kfree_skb_any(skb);
1047 static void emac_tx_handler(void *token, int len, int status)
1049 struct sk_buff *skb = token;
1050 struct net_device *ndev = skb->dev;
1052 /* Check whether the queue is stopped due to stalled tx dma, if the
1053 * queue is stopped then start the queue as we have free desc for tx
1055 if (unlikely(netif_queue_stopped(ndev)))
1056 netif_wake_queue(ndev);
1057 ndev->stats.tx_packets++;
1058 ndev->stats.tx_bytes += len;
1059 dev_kfree_skb_any(skb);
1063 * emac_dev_xmit - EMAC Transmit function
1065 * @ndev: The DaVinci EMAC network adapter
1067 * Called by the system to transmit a packet - we queue the packet in
1068 * EMAC hardware transmit queue
1070 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1072 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1074 struct device *emac_dev = &ndev->dev;
1076 struct emac_priv *priv = netdev_priv(ndev);
1078 /* If no link, return */
1079 if (unlikely(!priv->link)) {
1080 if (netif_msg_tx_err(priv) && net_ratelimit())
1081 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1085 ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
1086 if (unlikely(ret_code < 0)) {
1087 if (netif_msg_tx_err(priv) && net_ratelimit())
1088 dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
1092 skb_tx_timestamp(skb);
1094 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
1096 if (unlikely(ret_code != 0)) {
1097 if (netif_msg_tx_err(priv) && net_ratelimit())
1098 dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
1102 /* If there is no more tx desc left free then we need to
1103 * tell the kernel to stop sending us tx frames.
1105 if (unlikely(!cpdma_check_free_tx_desc(priv->txchan)))
1106 netif_stop_queue(ndev);
1108 return NETDEV_TX_OK;
1111 ndev->stats.tx_dropped++;
1112 netif_stop_queue(ndev);
1113 return NETDEV_TX_BUSY;
1117 * emac_dev_tx_timeout - EMAC Transmit timeout function
1118 * @ndev: The DaVinci EMAC network adapter
1120 * Called when system detects that a skb timeout period has expired
1121 * potentially due to a fault in the adapter in not being able to send
1122 * it out on the wire. We teardown the TX channel assuming a hardware
1123 * error and re-initialize the TX channel for hardware operation
1126 static void emac_dev_tx_timeout(struct net_device *ndev)
1128 struct emac_priv *priv = netdev_priv(ndev);
1129 struct device *emac_dev = &ndev->dev;
1131 if (netif_msg_tx_err(priv))
1132 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1134 emac_dump_regs(priv);
1136 ndev->stats.tx_errors++;
1137 emac_int_disable(priv);
1138 cpdma_chan_stop(priv->txchan);
1139 cpdma_chan_start(priv->txchan);
1140 emac_int_enable(priv);
1144 * emac_set_type0addr - Set EMAC Type0 mac address
1145 * @priv: The DaVinci EMAC private adapter structure
1146 * @ch: RX channel number
1147 * @mac_addr: MAC address to set in device
1149 * Called internally to set Type0 mac address of the adapter (Device)
1151 * Returns success (0) or appropriate error code (none as of now)
1153 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1156 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1157 emac_write(EMAC_MACSRCADDRLO, val);
1159 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1160 (mac_addr[1] << 8) | (mac_addr[0]));
1161 emac_write(EMAC_MACSRCADDRHI, val);
1162 val = emac_read(EMAC_RXUNICASTSET);
1164 emac_write(EMAC_RXUNICASTSET, val);
1165 val = emac_read(EMAC_RXUNICASTCLEAR);
1167 emac_write(EMAC_RXUNICASTCLEAR, val);
1171 * emac_set_type1addr - Set EMAC Type1 mac address
1172 * @priv: The DaVinci EMAC private adapter structure
1173 * @ch: RX channel number
1174 * @mac_addr: MAC address to set in device
1176 * Called internally to set Type1 mac address of the adapter (Device)
1178 * Returns success (0) or appropriate error code (none as of now)
1180 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1183 emac_write(EMAC_MACINDEX, ch);
1184 val = ((mac_addr[5] << 8) | mac_addr[4]);
1185 emac_write(EMAC_MACADDRLO, val);
1186 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1187 (mac_addr[1] << 8) | (mac_addr[0]));
1188 emac_write(EMAC_MACADDRHI, val);
1189 emac_set_type0addr(priv, ch, mac_addr);
1193 * emac_set_type2addr - Set EMAC Type2 mac address
1194 * @priv: The DaVinci EMAC private adapter structure
1195 * @ch: RX channel number
1196 * @mac_addr: MAC address to set in device
1197 * @index: index into RX address entries
1198 * @match: match parameter for RX address matching logic
1200 * Called internally to set Type2 mac address of the adapter (Device)
1202 * Returns success (0) or appropriate error code (none as of now)
1204 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1205 char *mac_addr, int index, int match)
1208 emac_write(EMAC_MACINDEX, index);
1209 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1210 (mac_addr[1] << 8) | (mac_addr[0]));
1211 emac_write(EMAC_MACADDRHI, val);
1212 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1213 (match << 19) | BIT(20));
1214 emac_write(EMAC_MACADDRLO, val);
1215 emac_set_type0addr(priv, ch, mac_addr);
1219 * emac_setmac - Set mac address in the adapter (internal function)
1220 * @priv: The DaVinci EMAC private adapter structure
1221 * @ch: RX channel number
1222 * @mac_addr: MAC address to set in device
1224 * Called internally to set the mac address of the adapter (Device)
1226 * Returns success (0) or appropriate error code (none as of now)
1228 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1230 struct device *emac_dev = &priv->ndev->dev;
1232 if (priv->rx_addr_type == 0) {
1233 emac_set_type0addr(priv, ch, mac_addr);
1234 } else if (priv->rx_addr_type == 1) {
1236 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1237 emac_set_type1addr(priv, ch, mac_addr);
1238 } else if (priv->rx_addr_type == 2) {
1239 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1240 emac_set_type0addr(priv, ch, mac_addr);
1242 if (netif_msg_drv(priv))
1243 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1248 * emac_dev_setmac_addr - Set mac address in the adapter
1249 * @ndev: The DaVinci EMAC network adapter
1250 * @addr: MAC address to set in device
1252 * Called by the system to set the mac address of the adapter (Device)
1254 * Returns success (0) or appropriate error code (none as of now)
1256 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1258 struct emac_priv *priv = netdev_priv(ndev);
1259 struct device *emac_dev = &priv->ndev->dev;
1260 struct sockaddr *sa = addr;
1262 if (!is_valid_ether_addr(sa->sa_data))
1263 return -EADDRNOTAVAIL;
1265 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1266 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1267 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1269 /* MAC address is configured only after the interface is enabled. */
1270 if (netif_running(ndev)) {
1271 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1274 if (netif_msg_drv(priv))
1275 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1282 * emac_hw_enable - Enable EMAC hardware for packet transmission/reception
1283 * @priv: The DaVinci EMAC private adapter structure
1285 * Enables EMAC hardware for packet processing - enables PHY, enables RX
1286 * for packet reception and enables device interrupts and then NAPI
1288 * Returns success (0) or appropriate error code (none right now)
1290 static int emac_hw_enable(struct emac_priv *priv)
1292 u32 val, mbp_enable, mac_control;
1295 emac_write(EMAC_SOFTRESET, 1);
1296 while (emac_read(EMAC_SOFTRESET))
1299 /* Disable interrupt & Set pacing for more interrupts initially */
1300 emac_int_disable(priv);
1302 /* Full duplex enable bit set when auto negotiation happens */
1304 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
1305 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
1306 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
1307 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
1308 emac_write(EMAC_MACCONTROL, mac_control);
1311 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
1312 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
1313 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
1314 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
1315 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
1316 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
1317 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
1318 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
1319 EMAC_RXMBP_PROMCH_SHIFT) |
1320 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
1321 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
1322 EMAC_RXMBP_BROADCH_SHIFT) |
1323 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
1324 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
1325 EMAC_RXMBP_MULTICH_SHIFT));
1326 emac_write(EMAC_RXMBPENABLE, mbp_enable);
1327 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
1328 EMAC_RX_MAX_LEN_MASK));
1329 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
1330 EMAC_RX_BUFFER_OFFSET_MASK));
1331 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
1332 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
1333 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
1335 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
1337 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1340 val = emac_read(EMAC_MACCONTROL);
1341 val |= (EMAC_MACCONTROL_GMIIEN);
1342 emac_write(EMAC_MACCONTROL, val);
1344 /* Enable NAPI and interrupts */
1345 napi_enable(&priv->napi);
1346 emac_int_enable(priv);
1352 * emac_poll - EMAC NAPI Poll function
1353 * @ndev: The DaVinci EMAC network adapter
1354 * @budget: Number of receive packets to process (as told by NAPI layer)
1356 * NAPI Poll function implemented to process packets as per budget. We check
1357 * the type of interrupt on the device and accordingly call the TX or RX
1358 * packet processing functions. We follow the budget for RX processing and
1359 * also put a cap on number of TX pkts processed through config param. The
1360 * NAPI schedule function is called if more packets pending.
1362 * Returns number of packets received (in most cases; else TX pkts - rarely)
1364 static int emac_poll(struct napi_struct *napi, int budget)
1367 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
1368 struct net_device *ndev = priv->ndev;
1369 struct device *emac_dev = &ndev->dev;
1371 u32 num_tx_pkts = 0, num_rx_pkts = 0;
1373 /* Check interrupt vectors and call packet processing */
1374 status = emac_read(EMAC_MACINVECTOR);
1376 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
1378 if (priv->version == EMAC_VERSION_2)
1379 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
1381 if (status & mask) {
1382 num_tx_pkts = cpdma_chan_process(priv->txchan,
1383 EMAC_DEF_TX_MAX_SERVICE);
1384 } /* TX processing */
1386 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
1388 if (priv->version == EMAC_VERSION_2)
1389 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
1391 if (status & mask) {
1392 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
1393 } /* RX processing */
1395 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
1396 if (priv->version == EMAC_VERSION_2)
1397 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
1399 if (unlikely(status & mask)) {
1401 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
1402 netif_stop_queue(ndev);
1403 napi_disable(&priv->napi);
1405 status = emac_read(EMAC_MACSTATUS);
1406 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
1407 EMAC_MACSTATUS_TXERRCODE_SHIFT);
1409 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
1410 EMAC_MACSTATUS_TXERRCH_SHIFT);
1411 if (net_ratelimit()) {
1412 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
1413 &emac_txhost_errcodes[cause][0], ch);
1416 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
1417 EMAC_MACSTATUS_RXERRCODE_SHIFT);
1419 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
1420 EMAC_MACSTATUS_RXERRCH_SHIFT);
1421 if (netif_msg_hw(priv) && net_ratelimit())
1422 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
1423 &emac_rxhost_errcodes[cause][0], ch);
1425 } else if (num_rx_pkts < budget) {
1426 napi_complete(napi);
1427 emac_int_enable(priv);
1433 #ifdef CONFIG_NET_POLL_CONTROLLER
1435 * emac_poll_controller - EMAC Poll controller function
1436 * @ndev: The DaVinci EMAC network adapter
1438 * Polled functionality used by netconsole and others in non interrupt mode
1441 static void emac_poll_controller(struct net_device *ndev)
1443 struct emac_priv *priv = netdev_priv(ndev);
1445 emac_int_disable(priv);
1446 emac_irq(ndev->irq, ndev);
1447 emac_int_enable(priv);
1451 static void emac_adjust_link(struct net_device *ndev)
1453 struct emac_priv *priv = netdev_priv(ndev);
1454 struct phy_device *phydev = priv->phydev;
1455 unsigned long flags;
1458 spin_lock_irqsave(&priv->lock, flags);
1461 /* check the mode of operation - full/half duplex */
1462 if (phydev->duplex != priv->duplex) {
1464 priv->duplex = phydev->duplex;
1466 if (phydev->speed != priv->speed) {
1468 priv->speed = phydev->speed;
1475 } else if (priv->link) {
1482 emac_update_phystatus(priv);
1483 phy_print_status(priv->phydev);
1486 spin_unlock_irqrestore(&priv->lock, flags);
1489 /*************************************************************************
1490 * Linux Driver Model
1491 *************************************************************************/
1494 * emac_devioctl - EMAC adapter ioctl
1495 * @ndev: The DaVinci EMAC network adapter
1496 * @ifrq: request parameter
1497 * @cmd: command parameter
1499 * EMAC driver ioctl function
1501 * Returns success(0) or appropriate error code
1503 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
1505 struct emac_priv *priv = netdev_priv(ndev);
1507 if (!(netif_running(ndev)))
1510 /* TODO: Add phy read and write and private statistics get feature */
1512 return phy_mii_ioctl(priv->phydev, ifrq, cmd);
1515 static int match_first_device(struct device *dev, void *data)
1517 return !strncmp(dev_name(dev), "davinci_mdio", 12);
1521 * emac_dev_open - EMAC device open
1522 * @ndev: The DaVinci EMAC network adapter
1524 * Called when system wants to start the interface. We init TX/RX channels
1525 * and enable the hardware for packet reception/transmission and start the
1528 * Returns 0 for a successful open, or appropriate error code
1530 static int emac_dev_open(struct net_device *ndev)
1532 struct device *emac_dev = &ndev->dev;
1534 struct resource *res;
1536 int res_num = 0, irq_num = 0;
1538 struct emac_priv *priv = netdev_priv(ndev);
1540 ret = pm_runtime_get_sync(&priv->pdev->dev);
1542 pm_runtime_put_noidle(&priv->pdev->dev);
1543 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
1548 netif_carrier_off(ndev);
1549 for (cnt = 0; cnt < ETH_ALEN; cnt++)
1550 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
1552 /* Configuration items */
1553 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
1555 priv->mac_hash1 = 0;
1556 priv->mac_hash2 = 0;
1557 emac_write(EMAC_MACHASH1, 0);
1558 emac_write(EMAC_MACHASH2, 0);
1560 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
1561 struct sk_buff *skb = emac_rx_alloc(priv);
1566 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1567 skb_tailroom(skb), 0);
1568 if (WARN_ON(ret < 0))
1573 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ,
1575 for (irq_num = res->start; irq_num <= res->end; irq_num++) {
1576 if (request_irq(irq_num, emac_irq, 0, ndev->name,
1579 "DaVinci EMAC: request_irq() failed\n");
1587 /* prepare counters for rollback in case of an error */
1591 /* Start/Enable EMAC hardware */
1592 emac_hw_enable(priv);
1594 /* Enable Interrupt pacing if configured */
1595 if (priv->coal_intvl != 0) {
1596 struct ethtool_coalesce coal;
1598 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1599 emac_set_coalesce(ndev, &coal);
1602 cpdma_ctlr_start(priv->dma);
1604 priv->phydev = NULL;
1606 if (priv->phy_node) {
1607 priv->phydev = of_phy_connect(ndev, priv->phy_node,
1608 &emac_adjust_link, 0, 0);
1609 if (!priv->phydev) {
1610 dev_err(emac_dev, "could not connect to phy %s\n",
1611 priv->phy_node->full_name);
1617 /* use the first phy on the bus if pdata did not give us a phy id */
1618 if (!priv->phydev && !priv->phy_id) {
1621 phy = bus_find_device(&mdio_bus_type, NULL, NULL,
1622 match_first_device);
1624 priv->phy_id = dev_name(phy);
1627 if (!priv->phydev && priv->phy_id && *priv->phy_id) {
1628 priv->phydev = phy_connect(ndev, priv->phy_id,
1630 PHY_INTERFACE_MODE_MII);
1632 if (IS_ERR(priv->phydev)) {
1633 dev_err(emac_dev, "could not connect to phy %s\n",
1635 ret = PTR_ERR(priv->phydev);
1636 priv->phydev = NULL;
1644 dev_info(emac_dev, "attached PHY driver [%s] "
1645 "(mii_bus:phy_addr=%s, id=%x)\n",
1646 priv->phydev->drv->name, dev_name(&priv->phydev->dev),
1647 priv->phydev->phy_id);
1650 if (!priv->phydev) {
1651 /* No PHY , fix the link, speed and duplex settings */
1652 dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
1654 priv->speed = SPEED_100;
1655 priv->duplex = DUPLEX_FULL;
1656 emac_update_phystatus(priv);
1659 if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
1660 emac_dump_regs(priv);
1662 if (netif_msg_drv(priv))
1663 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
1666 phy_start(priv->phydev);
1671 emac_int_disable(priv);
1672 napi_disable(&priv->napi);
1675 for (q = res_num; q >= 0; q--) {
1676 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, q);
1677 /* at the first iteration, irq_num is already set to the
1683 for (m = irq_num; m >= res->start; m--)
1686 cpdma_ctlr_stop(priv->dma);
1687 pm_runtime_put(&priv->pdev->dev);
1692 * emac_dev_stop - EMAC device stop
1693 * @ndev: The DaVinci EMAC network adapter
1695 * Called when system wants to stop or down the interface. We stop the network
1696 * queue, disable interrupts and cleanup TX/RX channels.
1698 * We return the statistics in net_device_stats structure pulled from emac
1700 static int emac_dev_stop(struct net_device *ndev)
1702 struct resource *res;
1705 struct emac_priv *priv = netdev_priv(ndev);
1706 struct device *emac_dev = &ndev->dev;
1708 /* inform the upper layers. */
1709 netif_stop_queue(ndev);
1710 napi_disable(&priv->napi);
1712 netif_carrier_off(ndev);
1713 emac_int_disable(priv);
1714 cpdma_ctlr_stop(priv->dma);
1715 emac_write(EMAC_SOFTRESET, 1);
1718 phy_disconnect(priv->phydev);
1721 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
1722 for (irq_num = res->start; irq_num <= res->end; irq_num++)
1723 free_irq(irq_num, priv->ndev);
1727 if (netif_msg_drv(priv))
1728 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
1730 pm_runtime_put(&priv->pdev->dev);
1735 * emac_dev_getnetstats - EMAC get statistics function
1736 * @ndev: The DaVinci EMAC network adapter
1738 * Called when system wants to get statistics from the device.
1740 * We return the statistics in net_device_stats structure pulled from emac
1742 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
1744 struct emac_priv *priv = netdev_priv(ndev);
1746 u32 stats_clear_mask;
1749 err = pm_runtime_get_sync(&priv->pdev->dev);
1751 pm_runtime_put_noidle(&priv->pdev->dev);
1752 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
1754 return &ndev->stats;
1757 /* update emac hardware stats and reset the registers*/
1759 mac_control = emac_read(EMAC_MACCONTROL);
1761 if (mac_control & EMAC_MACCONTROL_GMIIEN)
1762 stats_clear_mask = EMAC_STATS_CLR_MASK;
1764 stats_clear_mask = 0;
1766 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
1767 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
1769 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
1770 emac_read(EMAC_TXSINGLECOLL) +
1771 emac_read(EMAC_TXMULTICOLL));
1772 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
1773 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
1774 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
1776 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
1777 emac_read(EMAC_RXJABBER) +
1778 emac_read(EMAC_RXUNDERSIZED));
1779 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
1780 emac_write(EMAC_RXJABBER, stats_clear_mask);
1781 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
1783 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
1784 emac_read(EMAC_RXMOFOVERRUNS));
1785 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
1786 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
1788 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
1789 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
1791 ndev->stats.tx_carrier_errors +=
1792 emac_read(EMAC_TXCARRIERSENSE);
1793 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
1795 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
1796 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
1798 pm_runtime_put(&priv->pdev->dev);
1800 return &ndev->stats;
1803 static const struct net_device_ops emac_netdev_ops = {
1804 .ndo_open = emac_dev_open,
1805 .ndo_stop = emac_dev_stop,
1806 .ndo_start_xmit = emac_dev_xmit,
1807 .ndo_set_rx_mode = emac_dev_mcast_set,
1808 .ndo_set_mac_address = emac_dev_setmac_addr,
1809 .ndo_do_ioctl = emac_devioctl,
1810 .ndo_tx_timeout = emac_dev_tx_timeout,
1811 .ndo_get_stats = emac_dev_getnetstats,
1812 #ifdef CONFIG_NET_POLL_CONTROLLER
1813 .ndo_poll_controller = emac_poll_controller,
1817 static const struct of_device_id davinci_emac_of_match[];
1819 static struct emac_platform_data *
1820 davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv)
1822 struct device_node *np;
1823 const struct of_device_id *match;
1824 const struct emac_platform_data *auxdata;
1825 struct emac_platform_data *pdata = NULL;
1828 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
1829 return dev_get_platdata(&pdev->dev);
1831 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1835 np = pdev->dev.of_node;
1836 pdata->version = EMAC_VERSION_2;
1838 if (!is_valid_ether_addr(pdata->mac_addr)) {
1839 mac_addr = of_get_mac_address(np);
1841 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
1844 of_property_read_u32(np, "ti,davinci-ctrl-reg-offset",
1845 &pdata->ctrl_reg_offset);
1847 of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset",
1848 &pdata->ctrl_mod_reg_offset);
1850 of_property_read_u32(np, "ti,davinci-ctrl-ram-offset",
1851 &pdata->ctrl_ram_offset);
1853 of_property_read_u32(np, "ti,davinci-ctrl-ram-size",
1854 &pdata->ctrl_ram_size);
1856 of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en);
1858 pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram");
1860 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
1861 if (!priv->phy_node)
1862 pdata->phy_id = NULL;
1864 auxdata = pdev->dev.platform_data;
1866 pdata->interrupt_enable = auxdata->interrupt_enable;
1867 pdata->interrupt_disable = auxdata->interrupt_disable;
1870 match = of_match_device(davinci_emac_of_match, &pdev->dev);
1871 if (match && match->data) {
1872 auxdata = match->data;
1873 pdata->version = auxdata->version;
1874 pdata->hw_ram_addr = auxdata->hw_ram_addr;
1877 pdev->dev.platform_data = pdata;
1883 * davinci_emac_probe - EMAC device probe
1884 * @pdev: The DaVinci EMAC device that we are removing
1886 * Called when probing for emac devicesr. We get details of instances and
1887 * resource information from platform init and register a network device
1888 * and allocate resources necessary for driver to perform
1890 static int davinci_emac_probe(struct platform_device *pdev)
1893 struct resource *res, *res_ctrl;
1894 struct net_device *ndev;
1895 struct emac_priv *priv;
1896 unsigned long hw_ram_addr;
1897 struct emac_platform_data *pdata;
1898 struct cpdma_params dma_params;
1899 struct clk *emac_clk;
1900 unsigned long emac_bus_frequency;
1903 /* obtain emac clock from kernel */
1904 emac_clk = devm_clk_get(&pdev->dev, NULL);
1905 if (IS_ERR(emac_clk)) {
1906 dev_err(&pdev->dev, "failed to get EMAC clock\n");
1909 emac_bus_frequency = clk_get_rate(emac_clk);
1910 devm_clk_put(&pdev->dev, emac_clk);
1912 /* TODO: Probe PHY here if possible */
1914 ndev = alloc_etherdev(sizeof(struct emac_priv));
1918 platform_set_drvdata(pdev, ndev);
1919 priv = netdev_priv(ndev);
1922 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
1924 spin_lock_init(&priv->lock);
1926 pdata = davinci_emac_of_get_pdata(pdev, priv);
1928 dev_err(&pdev->dev, "no platform data\n");
1933 /* MAC addr and PHY mask , RMII enable info from platform_data */
1934 memcpy(priv->mac_addr, pdata->mac_addr, ETH_ALEN);
1935 priv->phy_id = pdata->phy_id;
1936 priv->rmii_en = pdata->rmii_en;
1937 priv->version = pdata->version;
1938 priv->int_enable = pdata->interrupt_enable;
1939 priv->int_disable = pdata->interrupt_disable;
1941 priv->coal_intvl = 0;
1942 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
1944 /* Get EMAC platform data */
1945 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1946 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
1947 priv->remap_addr = devm_ioremap_resource(&pdev->dev, res);
1948 if (IS_ERR(priv->remap_addr)) {
1949 rc = PTR_ERR(priv->remap_addr);
1953 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1956 devm_ioremap_resource(&pdev->dev, res_ctrl);
1957 if (IS_ERR(priv->ctrl_base))
1960 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
1963 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
1964 ndev->base_addr = (unsigned long)priv->remap_addr;
1966 hw_ram_addr = pdata->hw_ram_addr;
1968 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
1970 memset(&dma_params, 0, sizeof(dma_params));
1971 dma_params.dev = &pdev->dev;
1972 dma_params.dmaregs = priv->emac_base;
1973 dma_params.rxthresh = priv->emac_base + 0x120;
1974 dma_params.rxfree = priv->emac_base + 0x140;
1975 dma_params.txhdp = priv->emac_base + 0x600;
1976 dma_params.rxhdp = priv->emac_base + 0x620;
1977 dma_params.txcp = priv->emac_base + 0x640;
1978 dma_params.rxcp = priv->emac_base + 0x660;
1979 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
1980 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
1981 dma_params.desc_hw_addr = hw_ram_addr;
1982 dma_params.desc_mem_size = pdata->ctrl_ram_size;
1983 dma_params.desc_align = 16;
1985 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
1986 (u32 __force)res->start + pdata->ctrl_ram_offset;
1988 priv->dma = cpdma_ctlr_create(&dma_params);
1990 dev_err(&pdev->dev, "error initializing DMA\n");
1995 priv->txchan = cpdma_chan_create(priv->dma, tx_chan_num(EMAC_DEF_TX_CH),
1997 priv->rxchan = cpdma_chan_create(priv->dma, rx_chan_num(EMAC_DEF_RX_CH),
1999 if (WARN_ON(!priv->txchan || !priv->rxchan)) {
2004 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2006 dev_err(&pdev->dev, "error getting irq res\n");
2010 ndev->irq = res->start;
2012 if (!is_valid_ether_addr(priv->mac_addr)) {
2013 /* Use random MAC if none passed */
2014 eth_hw_addr_random(ndev);
2015 memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len);
2016 dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
2020 ndev->netdev_ops = &emac_netdev_ops;
2021 ndev->ethtool_ops = ðtool_ops;
2022 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
2024 pm_runtime_enable(&pdev->dev);
2025 rc = pm_runtime_get_sync(&pdev->dev);
2027 pm_runtime_put_noidle(&pdev->dev);
2028 dev_err(&pdev->dev, "%s: failed to get_sync(%d)\n",
2033 /* register the network device */
2034 SET_NETDEV_DEV(ndev, &pdev->dev);
2035 rc = register_netdev(ndev);
2037 dev_err(&pdev->dev, "error in register_netdev\n");
2039 pm_runtime_put(&pdev->dev);
2044 if (netif_msg_probe(priv)) {
2045 dev_notice(&pdev->dev, "DaVinci EMAC Probe found device "
2046 "(regs: %p, irq: %d)\n",
2047 (void *)priv->emac_base_phys, ndev->irq);
2049 pm_runtime_put(&pdev->dev);
2055 cpdma_chan_destroy(priv->txchan);
2057 cpdma_chan_destroy(priv->rxchan);
2058 cpdma_ctlr_destroy(priv->dma);
2065 * davinci_emac_remove - EMAC device remove
2066 * @pdev: The DaVinci EMAC device that we are removing
2068 * Called when removing the device driver. We disable clock usage and release
2069 * the resources taken up by the driver and unregister network device
2071 static int davinci_emac_remove(struct platform_device *pdev)
2073 struct net_device *ndev = platform_get_drvdata(pdev);
2074 struct emac_priv *priv = netdev_priv(ndev);
2076 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
2079 cpdma_chan_destroy(priv->txchan);
2081 cpdma_chan_destroy(priv->rxchan);
2082 cpdma_ctlr_destroy(priv->dma);
2084 unregister_netdev(ndev);
2090 static int davinci_emac_suspend(struct device *dev)
2092 struct platform_device *pdev = to_platform_device(dev);
2093 struct net_device *ndev = platform_get_drvdata(pdev);
2095 if (netif_running(ndev))
2096 emac_dev_stop(ndev);
2101 static int davinci_emac_resume(struct device *dev)
2103 struct platform_device *pdev = to_platform_device(dev);
2104 struct net_device *ndev = platform_get_drvdata(pdev);
2106 if (netif_running(ndev))
2107 emac_dev_open(ndev);
2112 static const struct dev_pm_ops davinci_emac_pm_ops = {
2113 .suspend = davinci_emac_suspend,
2114 .resume = davinci_emac_resume,
2117 #if IS_ENABLED(CONFIG_OF)
2118 static const struct emac_platform_data am3517_emac_data = {
2119 .version = EMAC_VERSION_2,
2120 .hw_ram_addr = 0x01e20000,
2123 static const struct emac_platform_data dm816_emac_data = {
2124 .version = EMAC_VERSION_2,
2127 static const struct of_device_id davinci_emac_of_match[] = {
2128 {.compatible = "ti,davinci-dm6467-emac", },
2129 {.compatible = "ti,am3517-emac", .data = &am3517_emac_data, },
2130 {.compatible = "ti,dm816-emac", .data = &dm816_emac_data, },
2133 MODULE_DEVICE_TABLE(of, davinci_emac_of_match);
2136 /* davinci_emac_driver: EMAC platform driver structure */
2137 static struct platform_driver davinci_emac_driver = {
2139 .name = "davinci_emac",
2140 .pm = &davinci_emac_pm_ops,
2141 .of_match_table = of_match_ptr(davinci_emac_of_match),
2143 .probe = davinci_emac_probe,
2144 .remove = davinci_emac_remove,
2148 * davinci_emac_init - EMAC driver module init
2150 * Called when initializing the driver. We register the driver with
2153 static int __init davinci_emac_init(void)
2155 return platform_driver_register(&davinci_emac_driver);
2157 late_initcall(davinci_emac_init);
2160 * davinci_emac_exit - EMAC driver module exit
2162 * Called when exiting the driver completely. We unregister the driver with
2163 * the platform and exit
2165 static void __exit davinci_emac_exit(void)
2167 platform_driver_unregister(&davinci_emac_driver);
2169 module_exit(davinci_emac_exit);
2171 MODULE_LICENSE("GPL");
2172 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2173 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2174 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");