drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c

   1 /*
   2  * Copyright (C) 1999 - 2010 Intel Corporation.
   3  * Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD.
   4  *
   5  * This code was derived from the Intel e1000e Linux driver.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "pch_gbe.h"
  21 #include "pch_gbe_api.h"
  22 #include <linux/module.h>
  23 #include <linux/net_tstamp.h>
  24 #include <linux/ptp_classify.h>
  25 #include <linux/gpio.h>
  26
  27 #define DRV_VERSION     "1.01"
  28 const char pch_driver_version[] = DRV_VERSION;
  29
  30 #define PCI_DEVICE_ID_INTEL_IOH1_GBE    0x8802          /* Pci device ID */
  31 #define PCH_GBE_MAR_ENTRIES             16
  32 #define PCH_GBE_SHORT_PKT               64
  33 #define DSC_INIT16                      0xC000
  34 #define PCH_GBE_DMA_ALIGN               0
  35 #define PCH_GBE_DMA_PADDING             2
  36 #define PCH_GBE_WATCHDOG_PERIOD         (5 * HZ)        /* watchdog time */
  37 #define PCH_GBE_COPYBREAK_DEFAULT       256
  38 #define PCH_GBE_PCI_BAR                 1
  39 #define PCH_GBE_RESERVE_MEMORY          0x200000        /* 2MB */
  40
  41 /* Macros for ML7223 */
  42 #define PCI_VENDOR_ID_ROHM                      0x10db
  43 #define PCI_DEVICE_ID_ROHM_ML7223_GBE           0x8013
  44
  45 /* Macros for ML7831 */
  46 #define PCI_DEVICE_ID_ROHM_ML7831_GBE           0x8802
  47
  48 #define PCH_GBE_TX_WEIGHT         64
  49 #define PCH_GBE_RX_WEIGHT         64
  50 #define PCH_GBE_RX_BUFFER_WRITE   16
  51
  52 /* Initialize the wake-on-LAN settings */
  53 #define PCH_GBE_WL_INIT_SETTING    (PCH_GBE_WLC_MP)
  54
  55 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
  56         PCH_GBE_CHIP_TYPE_INTERNAL | \
  57         PCH_GBE_RGMII_MODE_RGMII     \
  58         )
  59
  60 /* Ethertype field values */
  61 #define PCH_GBE_MAX_RX_BUFFER_SIZE      0x2880
  62 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE    10318
  63 #define PCH_GBE_FRAME_SIZE_2048         2048
  64 #define PCH_GBE_FRAME_SIZE_4096         4096
  65 #define PCH_GBE_FRAME_SIZE_8192         8192
  66
  67 #define PCH_GBE_GET_DESC(R, i, type)    (&(((struct type *)((R).desc))[i]))
  68 #define PCH_GBE_RX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
  69 #define PCH_GBE_TX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
  70 #define PCH_GBE_DESC_UNUSED(R) \
  71         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  72         (R)->next_to_clean - (R)->next_to_use - 1)
  73
  74 /* Pause packet value */
  75 #define PCH_GBE_PAUSE_PKT1_VALUE    0x00C28001
  76 #define PCH_GBE_PAUSE_PKT2_VALUE    0x00000100
  77 #define PCH_GBE_PAUSE_PKT4_VALUE    0x01000888
  78 #define PCH_GBE_PAUSE_PKT5_VALUE    0x0000FFFF
  79
  80
  81 /* This defines the bits that are set in the Interrupt Mask
  82  * Set/Read Register.  Each bit is documented below:
  83  *   o RXT0   = Receiver Timer Interrupt (ring 0)
  84  *   o TXDW   = Transmit Descriptor Written Back
  85  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
  86  *   o RXSEQ  = Receive Sequence Error
  87  *   o LSC    = Link Status Change
  88  */
  89 #define PCH_GBE_INT_ENABLE_MASK ( \
  90         PCH_GBE_INT_RX_DMA_CMPLT |    \
  91         PCH_GBE_INT_RX_DSC_EMP   |    \
  92         PCH_GBE_INT_RX_FIFO_ERR  |    \
  93         PCH_GBE_INT_WOL_DET      |    \
  94         PCH_GBE_INT_TX_CMPLT          \
  95         )
  96
  97 #define PCH_GBE_INT_DISABLE_ALL         0
  98
  99 /* Macros for ieee1588 */
 100 /* 0x40 Time Synchronization Channel Control Register Bits */
 101 #define MASTER_MODE   (1<<0)
 102 #define SLAVE_MODE    (0)
 103 #define V2_MODE       (1<<31)
 104 #define CAP_MODE0     (0)
 105 #define CAP_MODE2     (1<<17)
 106
 107 /* 0x44 Time Synchronization Channel Event Register Bits */
 108 #define TX_SNAPSHOT_LOCKED (1<<0)
 109 #define RX_SNAPSHOT_LOCKED (1<<1)
 110
 111 #define PTP_L4_MULTICAST_SA "01:00:5e:00:01:81"
 112 #define PTP_L2_MULTICAST_SA "01:1b:19:00:00:00"
 113
 114 #define MINNOW_PHY_RESET_GPIO           13
 115
 116 static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
 117
 118 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
 119 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
 120                                int data);
 121 static void pch_gbe_set_multi(struct net_device *netdev);
 122
 123 static struct sock_filter ptp_filter[] = {
 124         PTP_FILTER
 125 };
 126
 127 static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
 128 {
 129         u8 *data = skb->data;
 130         unsigned int offset;
 131         u16 *hi, *id;
 132         u32 lo;
 133
 134         if (sk_run_filter(skb, ptp_filter) == PTP_CLASS_NONE)
 135                 return 0;
 136
 137         offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
 138
 139         if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
 140                 return 0;
 141
 142         hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
 143         id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
 144
 145         memcpy(&lo, &hi[1], sizeof(lo));
 146
 147         return (uid_hi == *hi &&
 148                 uid_lo == lo &&
 149                 seqid  == *id);
 150 }
 151
 152 static void
 153 pch_rx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
 154 {
 155         struct skb_shared_hwtstamps *shhwtstamps;
 156         struct pci_dev *pdev;
 157         u64 ns;
 158         u32 hi, lo, val;
 159         u16 uid, seq;
 160
 161         if (!adapter->hwts_rx_en)
 162                 return;
 163
 164         /* Get ieee1588's dev information */
 165         pdev = adapter->ptp_pdev;
 166
 167         val = pch_ch_event_read(pdev);
 168
 169         if (!(val & RX_SNAPSHOT_LOCKED))
 170                 return;
 171
 172         lo = pch_src_uuid_lo_read(pdev);
 173         hi = pch_src_uuid_hi_read(pdev);
 174
 175         uid = hi & 0xffff;
 176         seq = (hi >> 16) & 0xffff;
 177
 178         if (!pch_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
 179                 goto out;
 180
 181         ns = pch_rx_snap_read(pdev);
 182
 183         shhwtstamps = skb_hwtstamps(skb);
 184         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 185         shhwtstamps->hwtstamp = ns_to_ktime(ns);
 186 out:
 187         pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED);
 188 }
 189
 190 static void
 191 pch_tx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
 192 {
 193         struct skb_shared_hwtstamps shhwtstamps;
 194         struct pci_dev *pdev;
 195         struct skb_shared_info *shtx;
 196         u64 ns;
 197         u32 cnt, val;
 198
 199         shtx = skb_shinfo(skb);
 200         if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en)))
 201                 return;
 202
 203         shtx->tx_flags |= SKBTX_IN_PROGRESS;
 204
 205         /* Get ieee1588's dev information */
 206         pdev = adapter->ptp_pdev;
 207
 208         /*
 209          * This really stinks, but we have to poll for the Tx time stamp.
 210          */
 211         for (cnt = 0; cnt < 100; cnt++) {
 212                 val = pch_ch_event_read(pdev);
 213                 if (val & TX_SNAPSHOT_LOCKED)
 214                         break;
 215                 udelay(1);
 216         }
 217         if (!(val & TX_SNAPSHOT_LOCKED)) {
 218                 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
 219                 return;
 220         }
 221
 222         ns = pch_tx_snap_read(pdev);
 223
 224         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 225         shhwtstamps.hwtstamp = ns_to_ktime(ns);
 226         skb_tstamp_tx(skb, &shhwtstamps);
 227
 228         pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED);
 229 }
 230
 231 static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
 232 {
 233         struct hwtstamp_config cfg;
 234         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 235         struct pci_dev *pdev;
 236         u8 station[20];
 237
 238         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
 239                 return -EFAULT;
 240
 241         if (cfg.flags) /* reserved for future extensions */
 242                 return -EINVAL;
 243
 244         /* Get ieee1588's dev information */
 245         pdev = adapter->ptp_pdev;
 246
 247         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
 248                 return -ERANGE;
 249
 250         switch (cfg.rx_filter) {
 251         case HWTSTAMP_FILTER_NONE:
 252                 adapter->hwts_rx_en = 0;
 253                 break;
 254         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 255                 adapter->hwts_rx_en = 0;
 256                 pch_ch_control_write(pdev, SLAVE_MODE | CAP_MODE0);
 257                 break;
 258         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 259                 adapter->hwts_rx_en = 1;
 260                 pch_ch_control_write(pdev, MASTER_MODE | CAP_MODE0);
 261                 break;
 262         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 263                 adapter->hwts_rx_en = 1;
 264                 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
 265                 strcpy(station, PTP_L4_MULTICAST_SA);
 266                 pch_set_station_address(station, pdev);
 267                 break;
 268         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 269                 adapter->hwts_rx_en = 1;
 270                 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
 271                 strcpy(station, PTP_L2_MULTICAST_SA);
 272                 pch_set_station_address(station, pdev);
 273                 break;
 274         default:
 275                 return -ERANGE;
 276         }
 277
 278         adapter->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
 279
 280         /* Clear out any old time stamps. */
 281         pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED);
 282
 283         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
 284 }
 285
 286 static inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
 287 {
 288         iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
 289 }
 290
 291 /**
 292  * pch_gbe_mac_read_mac_addr - Read MAC address
 293  * @hw:             Pointer to the HW structure
 294  * Returns:
 295  *      0:                      Successful.
 296  */
 297 s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
 298 {
 299         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 300         u32  adr1a, adr1b;
 301
 302         adr1a = ioread32(&hw->reg->mac_adr[0].high);
 303         adr1b = ioread32(&hw->reg->mac_adr[0].low);
 304
 305         hw->mac.addr[0] = (u8)(adr1a & 0xFF);
 306         hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
 307         hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
 308         hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
 309         hw->mac.addr[4] = (u8)(adr1b & 0xFF);
 310         hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
 311
 312         netdev_dbg(adapter->netdev, "hw->mac.addr : %pM\n", hw->mac.addr);
 313         return 0;
 314 }
 315
 316 /**
 317  * pch_gbe_wait_clr_bit - Wait to clear a bit
 318  * @reg:        Pointer of register
 319  * @busy:       Busy bit
 320  */
 321 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
 322 {
 323         u32 tmp;
 324
 325         /* wait busy */
 326         tmp = 1000;
 327         while ((ioread32(reg) & bit) && --tmp)
 328                 cpu_relax();
 329         if (!tmp)
 330                 pr_err("Error: busy bit is not cleared\n");
 331 }
 332
 333 /**
 334  * pch_gbe_mac_mar_set - Set MAC address register
 335  * @hw:     Pointer to the HW structure
 336  * @addr:   Pointer to the MAC address
 337  * @index:  MAC address array register
 338  */
 339 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
 340 {
 341         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 342         u32 mar_low, mar_high, adrmask;
 343
 344         netdev_dbg(adapter->netdev, "index : 0x%x\n", index);
 345
 346         /*
 347          * HW expects these in little endian so we reverse the byte order
 348          * from network order (big endian) to little endian
 349          */
 350         mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
 351                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 352         mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
 353         /* Stop the MAC Address of index. */
 354         adrmask = ioread32(&hw->reg->ADDR_MASK);
 355         iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
 356         /* wait busy */
 357         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 358         /* Set the MAC address to the MAC address 1A/1B register */
 359         iowrite32(mar_high, &hw->reg->mac_adr[index].high);
 360         iowrite32(mar_low, &hw->reg->mac_adr[index].low);
 361         /* Start the MAC address of index */
 362         iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
 363         /* wait busy */
 364         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 365 }
 366
 367 /**
 368  * pch_gbe_mac_reset_hw - Reset hardware
 369  * @hw: Pointer to the HW structure
 370  */
 371 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
 372 {
 373         /* Read the MAC address. and store to the private data */
 374         pch_gbe_mac_read_mac_addr(hw);
 375         iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
 376 #ifdef PCH_GBE_MAC_IFOP_RGMII
 377         iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
 378 #endif
 379         pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
 380         /* Setup the receive addresses */
 381         pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
 382         return;
 383 }
 384
 385 static void pch_gbe_disable_mac_rx(struct pch_gbe_hw *hw)
 386 {
 387         u32 rctl;
 388         /* Disables Receive MAC */
 389         rctl = ioread32(&hw->reg->MAC_RX_EN);
 390         iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
 391 }
 392
 393 static void pch_gbe_enable_mac_rx(struct pch_gbe_hw *hw)
 394 {
 395         u32 rctl;
 396         /* Enables Receive MAC */
 397         rctl = ioread32(&hw->reg->MAC_RX_EN);
 398         iowrite32((rctl | PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
 399 }
 400
 401 /**
 402  * pch_gbe_mac_init_rx_addrs - Initialize receive address's
 403  * @hw: Pointer to the HW structure
 404  * @mar_count: Receive address registers
 405  */
 406 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
 407 {
 408         u32 i;
 409
 410         /* Setup the receive address */
 411         pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
 412
 413         /* Zero out the other receive addresses */
 414         for (i = 1; i < mar_count; i++) {
 415                 iowrite32(0, &hw->reg->mac_adr[i].high);
 416                 iowrite32(0, &hw->reg->mac_adr[i].low);
 417         }
 418         iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
 419         /* wait busy */
 420         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 421 }
 422
 423
 424 /**
 425  * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
 426  * @hw:             Pointer to the HW structure
 427  * @mc_addr_list:   Array of multicast addresses to program
 428  * @mc_addr_count:  Number of multicast addresses to program
 429  * @mar_used_count: The first MAC Address register free to program
 430  * @mar_total_num:  Total number of supported MAC Address Registers
 431  */
 432 static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
 433                                             u8 *mc_addr_list, u32 mc_addr_count,
 434                                             u32 mar_used_count, u32 mar_total_num)
 435 {
 436         u32 i, adrmask;
 437
 438         /* Load the first set of multicast addresses into the exact
 439          * filters (RAR).  If there are not enough to fill the RAR
 440          * array, clear the filters.
 441          */
 442         for (i = mar_used_count; i < mar_total_num; i++) {
 443                 if (mc_addr_count) {
 444                         pch_gbe_mac_mar_set(hw, mc_addr_list, i);
 445                         mc_addr_count--;
 446                         mc_addr_list += ETH_ALEN;
 447                 } else {
 448                         /* Clear MAC address mask */
 449                         adrmask = ioread32(&hw->reg->ADDR_MASK);
 450                         iowrite32((adrmask | (0x0001 << i)),
 451                                         &hw->reg->ADDR_MASK);
 452                         /* wait busy */
 453                         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 454                         /* Clear MAC address */
 455                         iowrite32(0, &hw->reg->mac_adr[i].high);
 456                         iowrite32(0, &hw->reg->mac_adr[i].low);
 457                 }
 458         }
 459 }
 460
 461 /**
 462  * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
 463  * @hw:             Pointer to the HW structure
 464  * Returns:
 465  *      0:                      Successful.
 466  *      Negative value:         Failed.
 467  */
 468 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
 469 {
 470         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 471         struct pch_gbe_mac_info *mac = &hw->mac;
 472         u32 rx_fctrl;
 473
 474         netdev_dbg(adapter->netdev, "mac->fc = %u\n", mac->fc);
 475
 476         rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
 477
 478         switch (mac->fc) {
 479         case PCH_GBE_FC_NONE:
 480                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 481                 mac->tx_fc_enable = false;
 482                 break;
 483         case PCH_GBE_FC_RX_PAUSE:
 484                 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
 485                 mac->tx_fc_enable = false;
 486                 break;
 487         case PCH_GBE_FC_TX_PAUSE:
 488                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 489                 mac->tx_fc_enable = true;
 490                 break;
 491         case PCH_GBE_FC_FULL:
 492                 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
 493                 mac->tx_fc_enable = true;
 494                 break;
 495         default:
 496                 netdev_err(adapter->netdev,
 497                            "Flow control param set incorrectly\n");
 498                 return -EINVAL;
 499         }
 500         if (mac->link_duplex == DUPLEX_HALF)
 501                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 502         iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
 503         netdev_dbg(adapter->netdev,
 504                    "RX_FCTRL reg : 0x%08x  mac->tx_fc_enable : %d\n",
 505                    ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
 506         return 0;
 507 }
 508
 509 /**
 510  * pch_gbe_mac_set_wol_event - Set wake-on-lan event
 511  * @hw:     Pointer to the HW structure
 512  * @wu_evt: Wake up event
 513  */
 514 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
 515 {
 516         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 517         u32 addr_mask;
 518
 519         netdev_dbg(adapter->netdev, "wu_evt : 0x%08x  ADDR_MASK reg : 0x%08x\n",
 520                    wu_evt, ioread32(&hw->reg->ADDR_MASK));
 521
 522         if (wu_evt) {
 523                 /* Set Wake-On-Lan address mask */
 524                 addr_mask = ioread32(&hw->reg->ADDR_MASK);
 525                 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
 526                 /* wait busy */
 527                 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
 528                 iowrite32(0, &hw->reg->WOL_ST);
 529                 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
 530                 iowrite32(0x02, &hw->reg->TCPIP_ACC);
 531                 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
 532         } else {
 533                 iowrite32(0, &hw->reg->WOL_CTRL);
 534                 iowrite32(0, &hw->reg->WOL_ST);
 535         }
 536         return;
 537 }
 538
 539 /**
 540  * pch_gbe_mac_ctrl_miim - Control MIIM interface
 541  * @hw:   Pointer to the HW structure
 542  * @addr: Address of PHY
 543  * @dir:  Operetion. (Write or Read)
 544  * @reg:  Access register of PHY
 545  * @data: Write data.
 546  *
 547  * Returns: Read date.
 548  */
 549 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
 550                         u16 data)
 551 {
 552         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 553         u32 data_out = 0;
 554         unsigned int i;
 555         unsigned long flags;
 556
 557         spin_lock_irqsave(&hw->miim_lock, flags);
 558
 559         for (i = 100; i; --i) {
 560                 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
 561                         break;
 562                 udelay(20);
 563         }
 564         if (i == 0) {
 565                 netdev_err(adapter->netdev, "pch-gbe.miim won't go Ready\n");
 566                 spin_unlock_irqrestore(&hw->miim_lock, flags);
 567                 return 0;       /* No way to indicate timeout error */
 568         }
 569         iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
 570                   (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
 571                   dir | data), &hw->reg->MIIM);
 572         for (i = 0; i < 100; i++) {
 573                 udelay(20);
 574                 data_out = ioread32(&hw->reg->MIIM);
 575                 if ((data_out & PCH_GBE_MIIM_OPER_READY))
 576                         break;
 577         }
 578         spin_unlock_irqrestore(&hw->miim_lock, flags);
 579
 580         netdev_dbg(adapter->netdev, "PHY %s: reg=%d, data=0x%04X\n",
 581                    dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
 582                    dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
 583         return (u16) data_out;
 584 }
 585
 586 /**
 587  * pch_gbe_mac_set_pause_packet - Set pause packet
 588  * @hw:   Pointer to the HW structure
 589  */
 590 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
 591 {
 592         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 593         unsigned long tmp2, tmp3;
 594
 595         /* Set Pause packet */
 596         tmp2 = hw->mac.addr[1];
 597         tmp2 = (tmp2 << 8) | hw->mac.addr[0];
 598         tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
 599
 600         tmp3 = hw->mac.addr[5];
 601         tmp3 = (tmp3 << 8) | hw->mac.addr[4];
 602         tmp3 = (tmp3 << 8) | hw->mac.addr[3];
 603         tmp3 = (tmp3 << 8) | hw->mac.addr[2];
 604
 605         iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
 606         iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
 607         iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
 608         iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
 609         iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
 610
 611         /* Transmit Pause Packet */
 612         iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
 613
 614         netdev_dbg(adapter->netdev,
 615                    "PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
 616                    ioread32(&hw->reg->PAUSE_PKT1),
 617                    ioread32(&hw->reg->PAUSE_PKT2),
 618                    ioread32(&hw->reg->PAUSE_PKT3),
 619                    ioread32(&hw->reg->PAUSE_PKT4),
 620                    ioread32(&hw->reg->PAUSE_PKT5));
 621
 622         return;
 623 }
 624
 625
 626 /**
 627  * pch_gbe_alloc_queues - Allocate memory for all rings
 628  * @adapter:  Board private structure to initialize
 629  * Returns:
 630  *      0:      Successfully
 631  *      Negative value: Failed
 632  */
 633 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
 634 {
 635         adapter->tx_ring = devm_kzalloc(&adapter->pdev->dev,
 636                                         sizeof(*adapter->tx_ring), GFP_KERNEL);
 637         if (!adapter->tx_ring)
 638                 return -ENOMEM;
 639
 640         adapter->rx_ring = devm_kzalloc(&adapter->pdev->dev,
 641                                         sizeof(*adapter->rx_ring), GFP_KERNEL);
 642         if (!adapter->rx_ring)
 643                 return -ENOMEM;
 644         return 0;
 645 }
 646
 647 /**
 648  * pch_gbe_init_stats - Initialize status
 649  * @adapter:  Board private structure to initialize
 650  */
 651 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
 652 {
 653         memset(&adapter->stats, 0, sizeof(adapter->stats));
 654         return;
 655 }
 656
 657 /**
 658  * pch_gbe_init_phy - Initialize PHY
 659  * @adapter:  Board private structure to initialize
 660  * Returns:
 661  *      0:      Successfully
 662  *      Negative value: Failed
 663  */
 664 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
 665 {
 666         struct net_device *netdev = adapter->netdev;
 667         u32 addr;
 668         u16 bmcr, stat;
 669
 670         /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
 671         for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
 672                 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
 673                 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
 674                 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
 675                 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
 676                 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
 677                         break;
 678         }
 679         adapter->hw.phy.addr = adapter->mii.phy_id;
 680         netdev_dbg(netdev, "phy_addr = %d\n", adapter->mii.phy_id);
 681         if (addr == PCH_GBE_PHY_REGS_LEN)
 682                 return -EAGAIN;
 683         /* Selected the phy and isolate the rest */
 684         for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
 685                 if (addr != adapter->mii.phy_id) {
 686                         pch_gbe_mdio_write(netdev, addr, MII_BMCR,
 687                                            BMCR_ISOLATE);
 688                 } else {
 689                         bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
 690                         pch_gbe_mdio_write(netdev, addr, MII_BMCR,
 691                                            bmcr & ~BMCR_ISOLATE);
 692                 }
 693         }
 694
 695         /* MII setup */
 696         adapter->mii.phy_id_mask = 0x1F;
 697         adapter->mii.reg_num_mask = 0x1F;
 698         adapter->mii.dev = adapter->netdev;
 699         adapter->mii.mdio_read = pch_gbe_mdio_read;
 700         adapter->mii.mdio_write = pch_gbe_mdio_write;
 701         adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
 702         return 0;
 703 }
 704
 705 /**
 706  * pch_gbe_mdio_read - The read function for mii
 707  * @netdev: Network interface device structure
 708  * @addr:   Phy ID
 709  * @reg:    Access location
 710  * Returns:
 711  *      0:      Successfully
 712  *      Negative value: Failed
 713  */
 714 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
 715 {
 716         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 717         struct pch_gbe_hw *hw = &adapter->hw;
 718
 719         return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
 720                                      (u16) 0);
 721 }
 722
 723 /**
 724  * pch_gbe_mdio_write - The write function for mii
 725  * @netdev: Network interface device structure
 726  * @addr:   Phy ID (not used)
 727  * @reg:    Access location
 728  * @data:   Write data
 729  */
 730 static void pch_gbe_mdio_write(struct net_device *netdev,
 731                                int addr, int reg, int data)
 732 {
 733         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 734         struct pch_gbe_hw *hw = &adapter->hw;
 735
 736         pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
 737 }
 738
 739 /**
 740  * pch_gbe_reset_task - Reset processing at the time of transmission timeout
 741  * @work:  Pointer of board private structure
 742  */
 743 static void pch_gbe_reset_task(struct work_struct *work)
 744 {
 745         struct pch_gbe_adapter *adapter;
 746         adapter = container_of(work, struct pch_gbe_adapter, reset_task);
 747
 748         rtnl_lock();
 749         pch_gbe_reinit_locked(adapter);
 750         rtnl_unlock();
 751 }
 752
 753 /**
 754  * pch_gbe_reinit_locked- Re-initialization
 755  * @adapter:  Board private structure
 756  */
 757 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
 758 {
 759         pch_gbe_down(adapter);
 760         pch_gbe_up(adapter);
 761 }
 762
 763 /**
 764  * pch_gbe_reset - Reset GbE
 765  * @adapter:  Board private structure
 766  */
 767 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
 768 {
 769         struct net_device *netdev = adapter->netdev;
 770
 771         pch_gbe_mac_reset_hw(&adapter->hw);
 772         /* reprogram multicast address register after reset */
 773         pch_gbe_set_multi(netdev);
 774         /* Setup the receive address. */
 775         pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
 776         if (pch_gbe_hal_init_hw(&adapter->hw))
 777                 netdev_err(netdev, "Hardware Error\n");
 778 }
 779
 780 /**
 781  * pch_gbe_free_irq - Free an interrupt
 782  * @adapter:  Board private structure
 783  */
 784 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
 785 {
 786         struct net_device *netdev = adapter->netdev;
 787
 788         free_irq(adapter->pdev->irq, netdev);
 789         if (adapter->have_msi) {
 790                 pci_disable_msi(adapter->pdev);
 791                 netdev_dbg(netdev, "call pci_disable_msi\n");
 792         }
 793 }
 794
 795 /**
 796  * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
 797  * @adapter:  Board private structure
 798  */
 799 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
 800 {
 801         struct pch_gbe_hw *hw = &adapter->hw;
 802
 803         atomic_inc(&adapter->irq_sem);
 804         iowrite32(0, &hw->reg->INT_EN);
 805         ioread32(&hw->reg->INT_ST);
 806         synchronize_irq(adapter->pdev->irq);
 807
 808         netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
 809                    ioread32(&hw->reg->INT_EN));
 810 }
 811
 812 /**
 813  * pch_gbe_irq_enable - Enable default interrupt generation settings
 814  * @adapter:  Board private structure
 815  */
 816 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
 817 {
 818         struct pch_gbe_hw *hw = &adapter->hw;
 819
 820         if (likely(atomic_dec_and_test(&adapter->irq_sem)))
 821                 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
 822         ioread32(&hw->reg->INT_ST);
 823         netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
 824                    ioread32(&hw->reg->INT_EN));
 825 }
 826
 827
 828
 829 /**
 830  * pch_gbe_setup_tctl - configure the Transmit control registers
 831  * @adapter:  Board private structure
 832  */
 833 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
 834 {
 835         struct pch_gbe_hw *hw = &adapter->hw;
 836         u32 tx_mode, tcpip;
 837
 838         tx_mode = PCH_GBE_TM_LONG_PKT |
 839                 PCH_GBE_TM_ST_AND_FD |
 840                 PCH_GBE_TM_SHORT_PKT |
 841                 PCH_GBE_TM_TH_TX_STRT_8 |
 842                 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
 843
 844         iowrite32(tx_mode, &hw->reg->TX_MODE);
 845
 846         tcpip = ioread32(&hw->reg->TCPIP_ACC);
 847         tcpip |= PCH_GBE_TX_TCPIPACC_EN;
 848         iowrite32(tcpip, &hw->reg->TCPIP_ACC);
 849         return;
 850 }
 851
 852 /**
 853  * pch_gbe_configure_tx - Configure Transmit Unit after Reset
 854  * @adapter:  Board private structure
 855  */
 856 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
 857 {
 858         struct pch_gbe_hw *hw = &adapter->hw;
 859         u32 tdba, tdlen, dctrl;
 860
 861         netdev_dbg(adapter->netdev, "dma addr = 0x%08llx  size = 0x%08x\n",
 862                    (unsigned long long)adapter->tx_ring->dma,
 863                    adapter->tx_ring->size);
 864
 865         /* Setup the HW Tx Head and Tail descriptor pointers */
 866         tdba = adapter->tx_ring->dma;
 867         tdlen = adapter->tx_ring->size - 0x10;
 868         iowrite32(tdba, &hw->reg->TX_DSC_BASE);
 869         iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
 870         iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
 871
 872         /* Enables Transmission DMA */
 873         dctrl = ioread32(&hw->reg->DMA_CTRL);
 874         dctrl |= PCH_GBE_TX_DMA_EN;
 875         iowrite32(dctrl, &hw->reg->DMA_CTRL);
 876 }
 877
 878 /**
 879  * pch_gbe_setup_rctl - Configure the receive control registers
 880  * @adapter:  Board private structure
 881  */
 882 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
 883 {
 884         struct pch_gbe_hw *hw = &adapter->hw;
 885         u32 rx_mode, tcpip;
 886
 887         rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
 888         PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
 889
 890         iowrite32(rx_mode, &hw->reg->RX_MODE);
 891
 892         tcpip = ioread32(&hw->reg->TCPIP_ACC);
 893
 894         tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
 895         tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
 896         iowrite32(tcpip, &hw->reg->TCPIP_ACC);
 897         return;
 898 }
 899
 900 /**
 901  * pch_gbe_configure_rx - Configure Receive Unit after Reset
 902  * @adapter:  Board private structure
 903  */
 904 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
 905 {
 906         struct pch_gbe_hw *hw = &adapter->hw;
 907         u32 rdba, rdlen, rxdma;
 908
 909         netdev_dbg(adapter->netdev, "dma adr = 0x%08llx  size = 0x%08x\n",
 910                    (unsigned long long)adapter->rx_ring->dma,
 911                    adapter->rx_ring->size);
 912
 913         pch_gbe_mac_force_mac_fc(hw);
 914
 915         pch_gbe_disable_mac_rx(hw);
 916
 917         /* Disables Receive DMA */
 918         rxdma = ioread32(&hw->reg->DMA_CTRL);
 919         rxdma &= ~PCH_GBE_RX_DMA_EN;
 920         iowrite32(rxdma, &hw->reg->DMA_CTRL);
 921
 922         netdev_dbg(adapter->netdev,
 923                    "MAC_RX_EN reg = 0x%08x  DMA_CTRL reg = 0x%08x\n",
 924                    ioread32(&hw->reg->MAC_RX_EN),
 925                    ioread32(&hw->reg->DMA_CTRL));
 926
 927         /* Setup the HW Rx Head and Tail Descriptor Pointers and
 928          * the Base and Length of the Rx Descriptor Ring */
 929         rdba = adapter->rx_ring->dma;
 930         rdlen = adapter->rx_ring->size - 0x10;
 931         iowrite32(rdba, &hw->reg->RX_DSC_BASE);
 932         iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
 933         iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
 934 }
 935
 936 /**
 937  * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
 938  * @adapter:     Board private structure
 939  * @buffer_info: Buffer information structure
 940  */
 941 static void pch_gbe_unmap_and_free_tx_resource(
 942         struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
 943 {
 944         if (buffer_info->mapped) {
 945                 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
 946                                  buffer_info->length, DMA_TO_DEVICE);
 947                 buffer_info->mapped = false;
 948         }
 949         if (buffer_info->skb) {
 950                 dev_kfree_skb_any(buffer_info->skb);
 951                 buffer_info->skb = NULL;
 952         }
 953 }
 954
 955 /**
 956  * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
 957  * @adapter:      Board private structure
 958  * @buffer_info:  Buffer information structure
 959  */
 960 static void pch_gbe_unmap_and_free_rx_resource(
 961                                         struct pch_gbe_adapter *adapter,
 962                                         struct pch_gbe_buffer *buffer_info)
 963 {
 964         if (buffer_info->mapped) {
 965                 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
 966                                  buffer_info->length, DMA_FROM_DEVICE);
 967                 buffer_info->mapped = false;
 968         }
 969         if (buffer_info->skb) {
 970                 dev_kfree_skb_any(buffer_info->skb);
 971                 buffer_info->skb = NULL;
 972         }
 973 }
 974
 975 /**
 976  * pch_gbe_clean_tx_ring - Free Tx Buffers
 977  * @adapter:  Board private structure
 978  * @tx_ring:  Ring to be cleaned
 979  */
 980 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
 981                                    struct pch_gbe_tx_ring *tx_ring)
 982 {
 983         struct pch_gbe_hw *hw = &adapter->hw;
 984         struct pch_gbe_buffer *buffer_info;
 985         unsigned long size;
 986         unsigned int i;
 987
 988         /* Free all the Tx ring sk_buffs */
 989         for (i = 0; i < tx_ring->count; i++) {
 990                 buffer_info = &tx_ring->buffer_info[i];
 991                 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
 992         }
 993         netdev_dbg(adapter->netdev,
 994                    "call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
 995
 996         size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
 997         memset(tx_ring->buffer_info, 0, size);
 998
 999         /* Zero out the descriptor ring */
1000         memset(tx_ring->desc, 0, tx_ring->size);
1001         tx_ring->next_to_use = 0;
1002         tx_ring->next_to_clean = 0;
1003         iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
1004         iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
1005 }
1006
1007 /**
1008  * pch_gbe_clean_rx_ring - Free Rx Buffers
1009  * @adapter:  Board private structure
1010  * @rx_ring:  Ring to free buffers from
1011  */
1012 static void
1013 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
1014                       struct pch_gbe_rx_ring *rx_ring)
1015 {
1016         struct pch_gbe_hw *hw = &adapter->hw;
1017         struct pch_gbe_buffer *buffer_info;
1018         unsigned long size;
1019         unsigned int i;
1020
1021         /* Free all the Rx ring sk_buffs */
1022         for (i = 0; i < rx_ring->count; i++) {
1023                 buffer_info = &rx_ring->buffer_info[i];
1024                 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
1025         }
1026         netdev_dbg(adapter->netdev,
1027                    "call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
1028         size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1029         memset(rx_ring->buffer_info, 0, size);
1030
1031         /* Zero out the descriptor ring */
1032         memset(rx_ring->desc, 0, rx_ring->size);
1033         rx_ring->next_to_clean = 0;
1034         rx_ring->next_to_use = 0;
1035         iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
1036         iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
1037 }
1038
1039 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
1040                                     u16 duplex)
1041 {
1042         struct pch_gbe_hw *hw = &adapter->hw;
1043         unsigned long rgmii = 0;
1044
1045         /* Set the RGMII control. */
1046 #ifdef PCH_GBE_MAC_IFOP_RGMII
1047         switch (speed) {
1048         case SPEED_10:
1049                 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
1050                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
1051                 break;
1052         case SPEED_100:
1053                 rgmii = (PCH_GBE_RGMII_RATE_25M |
1054                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
1055                 break;
1056         case SPEED_1000:
1057                 rgmii = (PCH_GBE_RGMII_RATE_125M |
1058                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
1059                 break;
1060         }
1061         iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1062 #else   /* GMII */
1063         rgmii = 0;
1064         iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1065 #endif
1066 }
1067 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
1068                               u16 duplex)
1069 {
1070         struct net_device *netdev = adapter->netdev;
1071         struct pch_gbe_hw *hw = &adapter->hw;
1072         unsigned long mode = 0;
1073
1074         /* Set the communication mode */
1075         switch (speed) {
1076         case SPEED_10:
1077                 mode = PCH_GBE_MODE_MII_ETHER;
1078                 netdev->tx_queue_len = 10;
1079                 break;
1080         case SPEED_100:
1081                 mode = PCH_GBE_MODE_MII_ETHER;
1082                 netdev->tx_queue_len = 100;
1083                 break;
1084         case SPEED_1000:
1085                 mode = PCH_GBE_MODE_GMII_ETHER;
1086                 break;
1087         }
1088         if (duplex == DUPLEX_FULL)
1089                 mode |= PCH_GBE_MODE_FULL_DUPLEX;
1090         else
1091                 mode |= PCH_GBE_MODE_HALF_DUPLEX;
1092         iowrite32(mode, &hw->reg->MODE);
1093 }
1094
1095 /**
1096  * pch_gbe_watchdog - Watchdog process
1097  * @data:  Board private structure
1098  */
1099 static void pch_gbe_watchdog(unsigned long data)
1100 {
1101         struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
1102         struct net_device *netdev = adapter->netdev;
1103         struct pch_gbe_hw *hw = &adapter->hw;
1104
1105         netdev_dbg(netdev, "right now = %ld\n", jiffies);
1106
1107         pch_gbe_update_stats(adapter);
1108         if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
1109                 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
1110                 netdev->tx_queue_len = adapter->tx_queue_len;
1111                 /* mii library handles link maintenance tasks */
1112                 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
1113                         netdev_err(netdev, "ethtool get setting Error\n");
1114                         mod_timer(&adapter->watchdog_timer,
1115                                   round_jiffies(jiffies +
1116                                                 PCH_GBE_WATCHDOG_PERIOD));
1117                         return;
1118                 }
1119                 hw->mac.link_speed = ethtool_cmd_speed(&cmd);
1120                 hw->mac.link_duplex = cmd.duplex;
1121                 /* Set the RGMII control. */
1122                 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
1123                                                 hw->mac.link_duplex);
1124                 /* Set the communication mode */
1125                 pch_gbe_set_mode(adapter, hw->mac.link_speed,
1126                                  hw->mac.link_duplex);
1127                 netdev_dbg(netdev,
1128                            "Link is Up %d Mbps %s-Duplex\n",
1129                            hw->mac.link_speed,
1130                            cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1131                 netif_carrier_on(netdev);
1132                 netif_wake_queue(netdev);
1133         } else if ((!mii_link_ok(&adapter->mii)) &&
1134                    (netif_carrier_ok(netdev))) {
1135                 netdev_dbg(netdev, "NIC Link is Down\n");
1136                 hw->mac.link_speed = SPEED_10;
1137                 hw->mac.link_duplex = DUPLEX_HALF;
1138                 netif_carrier_off(netdev);
1139                 netif_stop_queue(netdev);
1140         }
1141         mod_timer(&adapter->watchdog_timer,
1142                   round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
1143 }
1144
1145 /**
1146  * pch_gbe_tx_queue - Carry out queuing of the transmission data
1147  * @adapter:  Board private structure
1148  * @tx_ring:  Tx descriptor ring structure
1149  * @skb:      Sockt buffer structure
1150  */
1151 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
1152                               struct pch_gbe_tx_ring *tx_ring,
1153                               struct sk_buff *skb)
1154 {
1155         struct pch_gbe_hw *hw = &adapter->hw;
1156         struct pch_gbe_tx_desc *tx_desc;
1157         struct pch_gbe_buffer *buffer_info;
1158         struct sk_buff *tmp_skb;
1159         unsigned int frame_ctrl;
1160         unsigned int ring_num;
1161
1162         /*-- Set frame control --*/
1163         frame_ctrl = 0;
1164         if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
1165                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
1166         if (skb->ip_summed == CHECKSUM_NONE)
1167                 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1168
1169         /* Performs checksum processing */
1170         /*
1171          * It is because the hardware accelerator does not support a checksum,
1172          * when the received data size is less than 64 bytes.
1173          */
1174         if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
1175                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
1176                               PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1177                 if (skb->protocol == htons(ETH_P_IP)) {
1178                         struct iphdr *iph = ip_hdr(skb);
1179                         unsigned int offset;
1180                         offset = skb_transport_offset(skb);
1181                         if (iph->protocol == IPPROTO_TCP) {
1182                                 skb->csum = 0;
1183                                 tcp_hdr(skb)->check = 0;
1184                                 skb->csum = skb_checksum(skb, offset,
1185                                                          skb->len - offset, 0);
1186                                 tcp_hdr(skb)->check =
1187                                         csum_tcpudp_magic(iph->saddr,
1188                                                           iph->daddr,
1189                                                           skb->len - offset,
1190                                                           IPPROTO_TCP,
1191                                                           skb->csum);
1192                         } else if (iph->protocol == IPPROTO_UDP) {
1193                                 skb->csum = 0;
1194                                 udp_hdr(skb)->check = 0;
1195                                 skb->csum =
1196                                         skb_checksum(skb, offset,
1197                                                      skb->len - offset, 0);
1198                                 udp_hdr(skb)->check =
1199                                         csum_tcpudp_magic(iph->saddr,
1200                                                           iph->daddr,
1201                                                           skb->len - offset,
1202                                                           IPPROTO_UDP,
1203                                                           skb->csum);
1204                         }
1205                 }
1206         }
1207
1208         ring_num = tx_ring->next_to_use;
1209         if (unlikely((ring_num + 1) == tx_ring->count))
1210                 tx_ring->next_to_use = 0;
1211         else
1212                 tx_ring->next_to_use = ring_num + 1;
1213
1214
1215         buffer_info = &tx_ring->buffer_info[ring_num];
1216         tmp_skb = buffer_info->skb;
1217
1218         /* [Header:14][payload] ---> [Header:14][paddong:2][payload]    */
1219         memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1220         tmp_skb->data[ETH_HLEN] = 0x00;
1221         tmp_skb->data[ETH_HLEN + 1] = 0x00;
1222         tmp_skb->len = skb->len;
1223         memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1224                (skb->len - ETH_HLEN));
1225         /*-- Set Buffer information --*/
1226         buffer_info->length = tmp_skb->len;
1227         buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1228                                           buffer_info->length,
1229                                           DMA_TO_DEVICE);
1230         if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1231                 netdev_err(adapter->netdev, "TX DMA map failed\n");
1232                 buffer_info->dma = 0;
1233                 buffer_info->time_stamp = 0;
1234                 tx_ring->next_to_use = ring_num;
1235                 return;
1236         }
1237         buffer_info->mapped = true;
1238         buffer_info->time_stamp = jiffies;
1239
1240         /*-- Set Tx descriptor --*/
1241         tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1242         tx_desc->buffer_addr = (buffer_info->dma);
1243         tx_desc->length = (tmp_skb->len);
1244         tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1245         tx_desc->tx_frame_ctrl = (frame_ctrl);
1246         tx_desc->gbec_status = (DSC_INIT16);
1247
1248         if (unlikely(++ring_num == tx_ring->count))
1249                 ring_num = 0;
1250
1251         /* Update software pointer of TX descriptor */
1252         iowrite32(tx_ring->dma +
1253                   (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1254                   &hw->reg->TX_DSC_SW_P);
1255
1256         pch_tx_timestamp(adapter, skb);
1257
1258         dev_kfree_skb_any(skb);
1259 }
1260
1261 /**
1262  * pch_gbe_update_stats - Update the board statistics counters
1263  * @adapter:  Board private structure
1264  */
1265 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1266 {
1267         struct net_device *netdev = adapter->netdev;
1268         struct pci_dev *pdev = adapter->pdev;
1269         struct pch_gbe_hw_stats *stats = &adapter->stats;
1270         unsigned long flags;
1271
1272         /*
1273          * Prevent stats update while adapter is being reset, or if the pci
1274          * connection is down.
1275          */
1276         if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1277                 return;
1278
1279         spin_lock_irqsave(&adapter->stats_lock, flags);
1280
1281         /* Update device status "adapter->stats" */
1282         stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1283         stats->tx_errors = stats->tx_length_errors +
1284             stats->tx_aborted_errors +
1285             stats->tx_carrier_errors + stats->tx_timeout_count;
1286
1287         /* Update network device status "adapter->net_stats" */
1288         netdev->stats.rx_packets = stats->rx_packets;
1289         netdev->stats.rx_bytes = stats->rx_bytes;
1290         netdev->stats.rx_dropped = stats->rx_dropped;
1291         netdev->stats.tx_packets = stats->tx_packets;
1292         netdev->stats.tx_bytes = stats->tx_bytes;
1293         netdev->stats.tx_dropped = stats->tx_dropped;
1294         /* Fill out the OS statistics structure */
1295         netdev->stats.multicast = stats->multicast;
1296         netdev->stats.collisions = stats->collisions;
1297         /* Rx Errors */
1298         netdev->stats.rx_errors = stats->rx_errors;
1299         netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1300         netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1301         /* Tx Errors */
1302         netdev->stats.tx_errors = stats->tx_errors;
1303         netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1304         netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1305
1306         spin_unlock_irqrestore(&adapter->stats_lock, flags);
1307 }
1308
1309 static void pch_gbe_disable_dma_rx(struct pch_gbe_hw *hw)
1310 {
1311         u32 rxdma;
1312
1313         /* Disable Receive DMA */
1314         rxdma = ioread32(&hw->reg->DMA_CTRL);
1315         rxdma &= ~PCH_GBE_RX_DMA_EN;
1316         iowrite32(rxdma, &hw->reg->DMA_CTRL);
1317 }
1318
1319 static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw)
1320 {
1321         u32 rxdma;
1322
1323         /* Enables Receive DMA */
1324         rxdma = ioread32(&hw->reg->DMA_CTRL);
1325         rxdma |= PCH_GBE_RX_DMA_EN;
1326         iowrite32(rxdma, &hw->reg->DMA_CTRL);
1327 }
1328
1329 /**
1330  * pch_gbe_intr - Interrupt Handler
1331  * @irq:   Interrupt number
1332  * @data:  Pointer to a network interface device structure
1333  * Returns:
1334  *      - IRQ_HANDLED:  Our interrupt
1335  *      - IRQ_NONE:     Not our interrupt
1336  */
1337 static irqreturn_t pch_gbe_intr(int irq, void *data)
1338 {
1339         struct net_device *netdev = data;
1340         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1341         struct pch_gbe_hw *hw = &adapter->hw;
1342         u32 int_st;
1343         u32 int_en;
1344
1345         /* Check request status */
1346         int_st = ioread32(&hw->reg->INT_ST);
1347         int_st = int_st & ioread32(&hw->reg->INT_EN);
1348         /* When request status is no interruption factor */
1349         if (unlikely(!int_st))
1350                 return IRQ_NONE;        /* Not our interrupt. End processing. */
1351         netdev_dbg(netdev, "%s occur int_st = 0x%08x\n", __func__, int_st);
1352         if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1353                 adapter->stats.intr_rx_frame_err_count++;
1354         if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1355                 if (!adapter->rx_stop_flag) {
1356                         adapter->stats.intr_rx_fifo_err_count++;
1357                         netdev_dbg(netdev, "Rx fifo over run\n");
1358                         adapter->rx_stop_flag = true;
1359                         int_en = ioread32(&hw->reg->INT_EN);
1360                         iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR),
1361                                   &hw->reg->INT_EN);
1362                         pch_gbe_disable_dma_rx(&adapter->hw);
1363                         int_st |= ioread32(&hw->reg->INT_ST);
1364                         int_st = int_st & ioread32(&hw->reg->INT_EN);
1365                 }
1366         if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1367                 adapter->stats.intr_rx_dma_err_count++;
1368         if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1369                 adapter->stats.intr_tx_fifo_err_count++;
1370         if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1371                 adapter->stats.intr_tx_dma_err_count++;
1372         if (int_st & PCH_GBE_INT_TCPIP_ERR)
1373                 adapter->stats.intr_tcpip_err_count++;
1374         /* When Rx descriptor is empty  */
1375         if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1376                 adapter->stats.intr_rx_dsc_empty_count++;
1377                 netdev_dbg(netdev, "Rx descriptor is empty\n");
1378                 int_en = ioread32(&hw->reg->INT_EN);
1379                 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1380                 if (hw->mac.tx_fc_enable) {
1381                         /* Set Pause packet */
1382                         pch_gbe_mac_set_pause_packet(hw);
1383                 }
1384         }
1385
1386         /* When request status is Receive interruption */
1387         if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) ||
1388             (adapter->rx_stop_flag)) {
1389                 if (likely(napi_schedule_prep(&adapter->napi))) {
1390                         /* Enable only Rx Descriptor empty */
1391                         atomic_inc(&adapter->irq_sem);
1392                         int_en = ioread32(&hw->reg->INT_EN);
1393                         int_en &=
1394                             ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1395                         iowrite32(int_en, &hw->reg->INT_EN);
1396                         /* Start polling for NAPI */
1397                         __napi_schedule(&adapter->napi);
1398                 }
1399         }
1400         netdev_dbg(netdev, "return = 0x%08x  INT_EN reg = 0x%08x\n",
1401                    IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1402         return IRQ_HANDLED;
1403 }
1404
1405 /**
1406  * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1407  * @adapter:       Board private structure
1408  * @rx_ring:       Rx descriptor ring
1409  * @cleaned_count: Cleaned count
1410  */
1411 static void
1412 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1413                          struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1414 {
1415         struct net_device *netdev = adapter->netdev;
1416         struct pci_dev *pdev = adapter->pdev;
1417         struct pch_gbe_hw *hw = &adapter->hw;
1418         struct pch_gbe_rx_desc *rx_desc;
1419         struct pch_gbe_buffer *buffer_info;
1420         struct sk_buff *skb;
1421         unsigned int i;
1422         unsigned int bufsz;
1423
1424         bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1425         i = rx_ring->next_to_use;
1426
1427         while ((cleaned_count--)) {
1428                 buffer_info = &rx_ring->buffer_info[i];
1429                 skb = netdev_alloc_skb(netdev, bufsz);
1430                 if (unlikely(!skb)) {
1431                         /* Better luck next round */
1432                         adapter->stats.rx_alloc_buff_failed++;
1433                         break;
1434                 }
1435                 /* align */
1436                 skb_reserve(skb, NET_IP_ALIGN);
1437                 buffer_info->skb = skb;
1438
1439                 buffer_info->dma = dma_map_single(&pdev->dev,
1440                                                   buffer_info->rx_buffer,
1441                                                   buffer_info->length,
1442                                                   DMA_FROM_DEVICE);
1443                 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1444                         dev_kfree_skb(skb);
1445                         buffer_info->skb = NULL;
1446                         buffer_info->dma = 0;
1447                         adapter->stats.rx_alloc_buff_failed++;
1448                         break; /* while !buffer_info->skb */
1449                 }
1450                 buffer_info->mapped = true;
1451                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1452                 rx_desc->buffer_addr = (buffer_info->dma);
1453                 rx_desc->gbec_status = DSC_INIT16;
1454
1455                 netdev_dbg(netdev,
1456                            "i = %d  buffer_info->dma = 0x08%llx  buffer_info->length = 0x%x\n",
1457                            i, (unsigned long long)buffer_info->dma,
1458                            buffer_info->length);
1459
1460                 if (unlikely(++i == rx_ring->count))
1461                         i = 0;
1462         }
1463         if (likely(rx_ring->next_to_use != i)) {
1464                 rx_ring->next_to_use = i;
1465                 if (unlikely(i-- == 0))
1466                         i = (rx_ring->count - 1);
1467                 iowrite32(rx_ring->dma +
1468                           (int)sizeof(struct pch_gbe_rx_desc) * i,
1469                           &hw->reg->RX_DSC_SW_P);
1470         }
1471         return;
1472 }
1473
1474 static int
1475 pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter,
1476                          struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1477 {
1478         struct pci_dev *pdev = adapter->pdev;
1479         struct pch_gbe_buffer *buffer_info;
1480         unsigned int i;
1481         unsigned int bufsz;
1482         unsigned int size;
1483
1484         bufsz = adapter->rx_buffer_len;
1485
1486         size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY;
1487         rx_ring->rx_buff_pool =
1488                 dma_zalloc_coherent(&pdev->dev, size,
1489                                     &rx_ring->rx_buff_pool_logic, GFP_KERNEL);
1490         if (!rx_ring->rx_buff_pool)
1491                 return -ENOMEM;
1492
1493         rx_ring->rx_buff_pool_size = size;
1494         for (i = 0; i < rx_ring->count; i++) {
1495                 buffer_info = &rx_ring->buffer_info[i];
1496                 buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i;
1497                 buffer_info->length = bufsz;
1498         }
1499         return 0;
1500 }
1501
1502 /**
1503  * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1504  * @adapter:   Board private structure
1505  * @tx_ring:   Tx descriptor ring
1506  */
1507 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1508                                         struct pch_gbe_tx_ring *tx_ring)
1509 {
1510         struct pch_gbe_buffer *buffer_info;
1511         struct sk_buff *skb;
1512         unsigned int i;
1513         unsigned int bufsz;
1514         struct pch_gbe_tx_desc *tx_desc;
1515
1516         bufsz =
1517             adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1518
1519         for (i = 0; i < tx_ring->count; i++) {
1520                 buffer_info = &tx_ring->buffer_info[i];
1521                 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1522                 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1523                 buffer_info->skb = skb;
1524                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1525                 tx_desc->gbec_status = (DSC_INIT16);
1526         }
1527         return;
1528 }
1529
1530 /**
1531  * pch_gbe_clean_tx - Reclaim resources after transmit completes
1532  * @adapter:   Board private structure
1533  * @tx_ring:   Tx descriptor ring
1534  * Returns:
1535  *      true:  Cleaned the descriptor
1536  *      false: Not cleaned the descriptor
1537  */
1538 static bool
1539 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1540                  struct pch_gbe_tx_ring *tx_ring)
1541 {
1542         struct pch_gbe_tx_desc *tx_desc;
1543         struct pch_gbe_buffer *buffer_info;
1544         struct sk_buff *skb;
1545         unsigned int i;
1546         unsigned int cleaned_count = 0;
1547         bool cleaned = false;
1548         int unused, thresh;
1549
1550         netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1551                    tx_ring->next_to_clean);
1552
1553         i = tx_ring->next_to_clean;
1554         tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1555         netdev_dbg(adapter->netdev, "gbec_status:0x%04x  dma_status:0x%04x\n",
1556                    tx_desc->gbec_status, tx_desc->dma_status);
1557
1558         unused = PCH_GBE_DESC_UNUSED(tx_ring);
1559         thresh = tx_ring->count - PCH_GBE_TX_WEIGHT;
1560         if ((tx_desc->gbec_status == DSC_INIT16) && (unused < thresh))
1561         {  /* current marked clean, tx queue filling up, do extra clean */
1562                 int j, k;
1563                 if (unused < 8) {  /* tx queue nearly full */
1564                         netdev_dbg(adapter->netdev,
1565                                    "clean_tx: transmit queue warning (%x,%x) unused=%d\n",
1566                                    tx_ring->next_to_clean, tx_ring->next_to_use,
1567                                    unused);
1568                 }
1569
1570                 /* current marked clean, scan for more that need cleaning. */
1571                 k = i;
1572                 for (j = 0; j < PCH_GBE_TX_WEIGHT; j++)
1573                 {
1574                         tx_desc = PCH_GBE_TX_DESC(*tx_ring, k);
1575                         if (tx_desc->gbec_status != DSC_INIT16) break; /*found*/
1576                         if (++k >= tx_ring->count) k = 0;  /*increment, wrap*/
1577                 }
1578                 if (j < PCH_GBE_TX_WEIGHT) {
1579                         netdev_dbg(adapter->netdev,
1580                                    "clean_tx: unused=%d loops=%d found tx_desc[%x,%x:%x].gbec_status=%04x\n",
1581                                    unused, j, i, k, tx_ring->next_to_use,
1582                                    tx_desc->gbec_status);
1583                         i = k;  /*found one to clean, usu gbec_status==2000.*/
1584                 }
1585         }
1586
1587         while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1588                 netdev_dbg(adapter->netdev, "gbec_status:0x%04x\n",
1589                            tx_desc->gbec_status);
1590                 buffer_info = &tx_ring->buffer_info[i];
1591                 skb = buffer_info->skb;
1592                 cleaned = true;
1593
1594                 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1595                         adapter->stats.tx_aborted_errors++;
1596                         netdev_err(adapter->netdev, "Transfer Abort Error\n");
1597                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1598                           ) {
1599                         adapter->stats.tx_carrier_errors++;
1600                         netdev_err(adapter->netdev,
1601                                    "Transfer Carrier Sense Error\n");
1602                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1603                           ) {
1604                         adapter->stats.tx_aborted_errors++;
1605                         netdev_err(adapter->netdev,
1606                                    "Transfer Collision Abort Error\n");
1607                 } else if ((tx_desc->gbec_status &
1608                             (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1609                              PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1610                         adapter->stats.collisions++;
1611                         adapter->stats.tx_packets++;
1612                         adapter->stats.tx_bytes += skb->len;
1613                         netdev_dbg(adapter->netdev, "Transfer Collision\n");
1614                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1615                           ) {
1616                         adapter->stats.tx_packets++;
1617                         adapter->stats.tx_bytes += skb->len;
1618                 }
1619                 if (buffer_info->mapped) {
1620                         netdev_dbg(adapter->netdev,
1621                                    "unmap buffer_info->dma : %d\n", i);
1622                         dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1623                                          buffer_info->length, DMA_TO_DEVICE);
1624                         buffer_info->mapped = false;
1625                 }
1626                 if (buffer_info->skb) {
1627                         netdev_dbg(adapter->netdev,
1628                                    "trim buffer_info->skb : %d\n", i);
1629                         skb_trim(buffer_info->skb, 0);
1630                 }
1631                 tx_desc->gbec_status = DSC_INIT16;
1632                 if (unlikely(++i == tx_ring->count))
1633                         i = 0;
1634                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1635
1636                 /* weight of a sort for tx, to avoid endless transmit cleanup */
1637                 if (cleaned_count++ == PCH_GBE_TX_WEIGHT) {
1638                         cleaned = false;
1639                         break;
1640                 }
1641         }
1642         netdev_dbg(adapter->netdev,
1643                    "called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1644                    cleaned_count);
1645         if (cleaned_count > 0)  { /*skip this if nothing cleaned*/
1646                 /* Recover from running out of Tx resources in xmit_frame */
1647                 spin_lock(&tx_ring->tx_lock);
1648                 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev))))
1649                 {
1650                         netif_wake_queue(adapter->netdev);
1651                         adapter->stats.tx_restart_count++;
1652                         netdev_dbg(adapter->netdev, "Tx wake queue\n");
1653                 }
1654
1655                 tx_ring->next_to_clean = i;
1656
1657                 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1658                            tx_ring->next_to_clean);
1659                 spin_unlock(&tx_ring->tx_lock);
1660         }
1661         return cleaned;
1662 }
1663
1664 /**
1665  * pch_gbe_clean_rx - Send received data up the network stack; legacy
1666  * @adapter:     Board private structure
1667  * @rx_ring:     Rx descriptor ring
1668  * @work_done:   Completed count
1669  * @work_to_do:  Request count
1670  * Returns:
1671  *      true:  Cleaned the descriptor
1672  *      false: Not cleaned the descriptor
1673  */
1674 static bool
1675 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1676                  struct pch_gbe_rx_ring *rx_ring,
1677                  int *work_done, int work_to_do)
1678 {
1679         struct net_device *netdev = adapter->netdev;
1680         struct pci_dev *pdev = adapter->pdev;
1681         struct pch_gbe_buffer *buffer_info;
1682         struct pch_gbe_rx_desc *rx_desc;
1683         u32 length;
1684         unsigned int i;
1685         unsigned int cleaned_count = 0;
1686         bool cleaned = false;
1687         struct sk_buff *skb;
1688         u8 dma_status;
1689         u16 gbec_status;
1690         u32 tcp_ip_status;
1691
1692         i = rx_ring->next_to_clean;
1693
1694         while (*work_done < work_to_do) {
1695                 /* Check Rx descriptor status */
1696                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1697                 if (rx_desc->gbec_status == DSC_INIT16)
1698                         break;
1699                 cleaned = true;
1700                 cleaned_count++;
1701
1702                 dma_status = rx_desc->dma_status;
1703                 gbec_status = rx_desc->gbec_status;
1704                 tcp_ip_status = rx_desc->tcp_ip_status;
1705                 rx_desc->gbec_status = DSC_INIT16;
1706                 buffer_info = &rx_ring->buffer_info[i];
1707                 skb = buffer_info->skb;
1708                 buffer_info->skb = NULL;
1709
1710                 /* unmap dma */
1711                 dma_unmap_single(&pdev->dev, buffer_info->dma,
1712                                    buffer_info->length, DMA_FROM_DEVICE);
1713                 buffer_info->mapped = false;
1714
1715                 netdev_dbg(netdev,
1716                            "RxDecNo = 0x%04x  Status[DMA:0x%02x GBE:0x%04x TCP:0x%08x]  BufInf = 0x%p\n",
1717                            i, dma_status, gbec_status, tcp_ip_status,
1718                            buffer_info);
1719                 /* Error check */
1720                 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1721                         adapter->stats.rx_frame_errors++;
1722                         netdev_err(netdev, "Receive Not Octal Error\n");
1723                 } else if (unlikely(gbec_status &
1724                                 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1725                         adapter->stats.rx_frame_errors++;
1726                         netdev_err(netdev, "Receive Nibble Error\n");
1727                 } else if (unlikely(gbec_status &
1728                                 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1729                         adapter->stats.rx_crc_errors++;
1730                         netdev_err(netdev, "Receive CRC Error\n");
1731                 } else {
1732                         /* get receive length */
1733                         /* length convert[-3], length includes FCS length */
1734                         length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN;
1735                         if (rx_desc->rx_words_eob & 0x02)
1736                                 length = length - 4;
1737                         /*
1738                          * buffer_info->rx_buffer: [Header:14][payload]
1739                          * skb->data: [Reserve:2][Header:14][payload]
1740                          */
1741                         memcpy(skb->data, buffer_info->rx_buffer, length);
1742
1743                         /* update status of driver */
1744                         adapter->stats.rx_bytes += length;
1745                         adapter->stats.rx_packets++;
1746                         if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1747                                 adapter->stats.multicast++;
1748                         /* Write meta date of skb */
1749                         skb_put(skb, length);
1750
1751                         pch_rx_timestamp(adapter, skb);
1752
1753                         skb->protocol = eth_type_trans(skb, netdev);
1754                         if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
1755                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1756                         else
1757                                 skb->ip_summed = CHECKSUM_NONE;
1758
1759                         napi_gro_receive(&adapter->napi, skb);
1760                         (*work_done)++;
1761                         netdev_dbg(netdev,
1762                                    "Receive skb->ip_summed: %d length: %d\n",
1763                                    skb->ip_summed, length);
1764                 }
1765                 /* return some buffers to hardware, one at a time is too slow */
1766                 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1767                         pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1768                                                  cleaned_count);
1769                         cleaned_count = 0;
1770                 }
1771                 if (++i == rx_ring->count)
1772                         i = 0;
1773         }
1774         rx_ring->next_to_clean = i;
1775         if (cleaned_count)
1776                 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1777         return cleaned;
1778 }
1779
1780 /**
1781  * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1782  * @adapter:  Board private structure
1783  * @tx_ring:  Tx descriptor ring (for a specific queue) to setup
1784  * Returns:
1785  *      0:              Successfully
1786  *      Negative value: Failed
1787  */
1788 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1789                                 struct pch_gbe_tx_ring *tx_ring)
1790 {
1791         struct pci_dev *pdev = adapter->pdev;
1792         struct pch_gbe_tx_desc *tx_desc;
1793         int size;
1794         int desNo;
1795
1796         size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1797         tx_ring->buffer_info = vzalloc(size);
1798         if (!tx_ring->buffer_info)
1799                 return -ENOMEM;
1800
1801         tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1802
1803         tx_ring->desc = dma_zalloc_coherent(&pdev->dev, tx_ring->size,
1804                                             &tx_ring->dma, GFP_KERNEL);
1805         if (!tx_ring->desc) {
1806                 vfree(tx_ring->buffer_info);
1807                 return -ENOMEM;
1808         }
1809
1810         tx_ring->next_to_use = 0;
1811         tx_ring->next_to_clean = 0;
1812         spin_lock_init(&tx_ring->tx_lock);
1813
1814         for (desNo = 0; desNo < tx_ring->count; desNo++) {
1815                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1816                 tx_desc->gbec_status = DSC_INIT16;
1817         }
1818         netdev_dbg(adapter->netdev,
1819                    "tx_ring->desc = 0x%p  tx_ring->dma = 0x%08llx next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1820                    tx_ring->desc, (unsigned long long)tx_ring->dma,
1821                    tx_ring->next_to_clean, tx_ring->next_to_use);
1822         return 0;
1823 }
1824
1825 /**
1826  * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1827  * @adapter:  Board private structure
1828  * @rx_ring:  Rx descriptor ring (for a specific queue) to setup
1829  * Returns:
1830  *      0:              Successfully
1831  *      Negative value: Failed
1832  */
1833 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1834                                 struct pch_gbe_rx_ring *rx_ring)
1835 {
1836         struct pci_dev *pdev = adapter->pdev;
1837         struct pch_gbe_rx_desc *rx_desc;
1838         int size;
1839         int desNo;
1840
1841         size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1842         rx_ring->buffer_info = vzalloc(size);
1843         if (!rx_ring->buffer_info)
1844                 return -ENOMEM;
1845
1846         rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1847         rx_ring->desc = dma_zalloc_coherent(&pdev->dev, rx_ring->size,
1848                                             &rx_ring->dma, GFP_KERNEL);
1849         if (!rx_ring->desc) {
1850                 vfree(rx_ring->buffer_info);
1851                 return -ENOMEM;
1852         }
1853         rx_ring->next_to_clean = 0;
1854         rx_ring->next_to_use = 0;
1855         for (desNo = 0; desNo < rx_ring->count; desNo++) {
1856                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1857                 rx_desc->gbec_status = DSC_INIT16;
1858         }
1859         netdev_dbg(adapter->netdev,
1860                    "rx_ring->desc = 0x%p  rx_ring->dma = 0x%08llx next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1861                    rx_ring->desc, (unsigned long long)rx_ring->dma,
1862                    rx_ring->next_to_clean, rx_ring->next_to_use);
1863         return 0;
1864 }
1865
1866 /**
1867  * pch_gbe_free_tx_resources - Free Tx Resources
1868  * @adapter:  Board private structure
1869  * @tx_ring:  Tx descriptor ring for a specific queue
1870  */
1871 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1872                                 struct pch_gbe_tx_ring *tx_ring)
1873 {
1874         struct pci_dev *pdev = adapter->pdev;
1875
1876         pch_gbe_clean_tx_ring(adapter, tx_ring);
1877         vfree(tx_ring->buffer_info);
1878         tx_ring->buffer_info = NULL;
1879         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1880         tx_ring->desc = NULL;
1881 }
1882
1883 /**
1884  * pch_gbe_free_rx_resources - Free Rx Resources
1885  * @adapter:  Board private structure
1886  * @rx_ring:  Ring to clean the resources from
1887  */
1888 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1889                                 struct pch_gbe_rx_ring *rx_ring)
1890 {
1891         struct pci_dev *pdev = adapter->pdev;
1892
1893         pch_gbe_clean_rx_ring(adapter, rx_ring);
1894         vfree(rx_ring->buffer_info);
1895         rx_ring->buffer_info = NULL;
1896         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1897         rx_ring->desc = NULL;
1898 }
1899
1900 /**
1901  * pch_gbe_request_irq - Allocate an interrupt line
1902  * @adapter:  Board private structure
1903  * Returns:
1904  *      0:              Successfully
1905  *      Negative value: Failed
1906  */
1907 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1908 {
1909         struct net_device *netdev = adapter->netdev;
1910         int err;
1911         int flags;
1912
1913         flags = IRQF_SHARED;
1914         adapter->have_msi = false;
1915         err = pci_enable_msi(adapter->pdev);
1916         netdev_dbg(netdev, "call pci_enable_msi\n");
1917         if (err) {
1918                 netdev_dbg(netdev, "call pci_enable_msi - Error: %d\n", err);
1919         } else {
1920                 flags = 0;
1921                 adapter->have_msi = true;
1922         }
1923         err = request_irq(adapter->pdev->irq, &pch_gbe_intr,
1924                           flags, netdev->name, netdev);
1925         if (err)
1926                 netdev_err(netdev, "Unable to allocate interrupt Error: %d\n",
1927                            err);
1928         netdev_dbg(netdev,
1929                    "adapter->have_msi : %d  flags : 0x%04x  return : 0x%04x\n",
1930                    adapter->have_msi, flags, err);
1931         return err;
1932 }
1933
1934
1935 /**
1936  * pch_gbe_up - Up GbE network device
1937  * @adapter:  Board private structure
1938  * Returns:
1939  *      0:              Successfully
1940  *      Negative value: Failed
1941  */
1942 int pch_gbe_up(struct pch_gbe_adapter *adapter)
1943 {
1944         struct net_device *netdev = adapter->netdev;
1945         struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1946         struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1947         int err = -EINVAL;
1948
1949         /* Ensure we have a valid MAC */
1950         if (!is_valid_ether_addr(adapter->hw.mac.addr)) {
1951                 netdev_err(netdev, "Error: Invalid MAC address\n");
1952                 goto out;
1953         }
1954
1955         /* hardware has been reset, we need to reload some things */
1956         pch_gbe_set_multi(netdev);
1957
1958         pch_gbe_setup_tctl(adapter);
1959         pch_gbe_configure_tx(adapter);
1960         pch_gbe_setup_rctl(adapter);
1961         pch_gbe_configure_rx(adapter);
1962
1963         err = pch_gbe_request_irq(adapter);
1964         if (err) {
1965                 netdev_err(netdev,
1966                            "Error: can't bring device up - irq request failed\n");
1967                 goto out;
1968         }
1969         err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count);
1970         if (err) {
1971                 netdev_err(netdev,
1972                            "Error: can't bring device up - alloc rx buffers pool failed\n");
1973                 goto freeirq;
1974         }
1975         pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1976         pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1977         adapter->tx_queue_len = netdev->tx_queue_len;
1978         pch_gbe_enable_dma_rx(&adapter->hw);
1979         pch_gbe_enable_mac_rx(&adapter->hw);
1980
1981         mod_timer(&adapter->watchdog_timer, jiffies);
1982
1983         napi_enable(&adapter->napi);
1984         pch_gbe_irq_enable(adapter);
1985         netif_start_queue(adapter->netdev);
1986
1987         return 0;
1988
1989 freeirq:
1990         pch_gbe_free_irq(adapter);
1991 out:
1992         return err;
1993 }
1994
1995 /**
1996  * pch_gbe_down - Down GbE network device
1997  * @adapter:  Board private structure
1998  */
1999 void pch_gbe_down(struct pch_gbe_adapter *adapter)
2000 {
2001         struct net_device *netdev = adapter->netdev;
2002         struct pci_dev *pdev = adapter->pdev;
2003         struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
2004
2005         /* signal that we're down so the interrupt handler does not
2006          * reschedule our watchdog timer */
2007         napi_disable(&adapter->napi);
2008         atomic_set(&adapter->irq_sem, 0);
2009
2010         pch_gbe_irq_disable(adapter);
2011         pch_gbe_free_irq(adapter);
2012
2013         del_timer_sync(&adapter->watchdog_timer);
2014
2015         netdev->tx_queue_len = adapter->tx_queue_len;
2016         netif_carrier_off(netdev);
2017         netif_stop_queue(netdev);
2018
2019         if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
2020                 pch_gbe_reset(adapter);
2021         pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
2022         pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
2023
2024         pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size,
2025                             rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic);
2026         rx_ring->rx_buff_pool_logic = 0;
2027         rx_ring->rx_buff_pool_size = 0;
2028         rx_ring->rx_buff_pool = NULL;
2029 }
2030
2031 /**
2032  * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
2033  * @adapter:  Board private structure to initialize
2034  * Returns:
2035  *      0:              Successfully
2036  *      Negative value: Failed
2037  */
2038 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
2039 {
2040         struct pch_gbe_hw *hw = &adapter->hw;
2041         struct net_device *netdev = adapter->netdev;
2042
2043         adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2044         hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2045         hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2046
2047         /* Initialize the hardware-specific values */
2048         if (pch_gbe_hal_setup_init_funcs(hw)) {
2049                 netdev_err(netdev, "Hardware Initialization Failure\n");
2050                 return -EIO;
2051         }
2052         if (pch_gbe_alloc_queues(adapter)) {
2053                 netdev_err(netdev, "Unable to allocate memory for queues\n");
2054                 return -ENOMEM;
2055         }
2056         spin_lock_init(&adapter->hw.miim_lock);
2057         spin_lock_init(&adapter->stats_lock);
2058         spin_lock_init(&adapter->ethtool_lock);
2059         atomic_set(&adapter->irq_sem, 0);
2060         pch_gbe_irq_disable(adapter);
2061
2062         pch_gbe_init_stats(adapter);
2063
2064         netdev_dbg(netdev,
2065                    "rx_buffer_len : %d  mac.min_frame_size : %d  mac.max_frame_size : %d\n",
2066                    (u32) adapter->rx_buffer_len,
2067                    hw->mac.min_frame_size, hw->mac.max_frame_size);
2068         return 0;
2069 }
2070
2071 /**
2072  * pch_gbe_open - Called when a network interface is made active
2073  * @netdev:     Network interface device structure
2074  * Returns:
2075  *      0:              Successfully
2076  *      Negative value: Failed
2077  */
2078 static int pch_gbe_open(struct net_device *netdev)
2079 {
2080         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2081         struct pch_gbe_hw *hw = &adapter->hw;
2082         int err;
2083
2084         /* allocate transmit descriptors */
2085         err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
2086         if (err)
2087                 goto err_setup_tx;
2088         /* allocate receive descriptors */
2089         err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
2090         if (err)
2091                 goto err_setup_rx;
2092         pch_gbe_hal_power_up_phy(hw);
2093         err = pch_gbe_up(adapter);
2094         if (err)
2095                 goto err_up;
2096         netdev_dbg(netdev, "Success End\n");
2097         return 0;
2098
2099 err_up:
2100         if (!adapter->wake_up_evt)
2101                 pch_gbe_hal_power_down_phy(hw);
2102         pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2103 err_setup_rx:
2104         pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2105 err_setup_tx:
2106         pch_gbe_reset(adapter);
2107         netdev_err(netdev, "Error End\n");
2108         return err;
2109 }
2110
2111 /**
2112  * pch_gbe_stop - Disables a network interface
2113  * @netdev:  Network interface device structure
2114  * Returns:
2115  *      0: Successfully
2116  */
2117 static int pch_gbe_stop(struct net_device *netdev)
2118 {
2119         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2120         struct pch_gbe_hw *hw = &adapter->hw;
2121
2122         pch_gbe_down(adapter);
2123         if (!adapter->wake_up_evt)
2124                 pch_gbe_hal_power_down_phy(hw);
2125         pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2126         pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2127         return 0;
2128 }
2129
2130 /**
2131  * pch_gbe_xmit_frame - Packet transmitting start
2132  * @skb:     Socket buffer structure
2133  * @netdev:  Network interface device structure
2134  * Returns:
2135  *      - NETDEV_TX_OK:   Normal end
2136  *      - NETDEV_TX_BUSY: Error end
2137  */
2138 static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2139 {
2140         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2141         struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
2142         unsigned long flags;
2143
2144         if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) {
2145                 /* Collision - tell upper layer to requeue */
2146                 return NETDEV_TX_LOCKED;
2147         }
2148         if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
2149                 netif_stop_queue(netdev);
2150                 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
2151                 netdev_dbg(netdev,
2152                            "Return : BUSY  next_to use : 0x%08x  next_to clean : 0x%08x\n",
2153                            tx_ring->next_to_use, tx_ring->next_to_clean);
2154                 return NETDEV_TX_BUSY;
2155         }
2156
2157         /* CRC,ITAG no support */
2158         pch_gbe_tx_queue(adapter, tx_ring, skb);
2159         spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
2160         return NETDEV_TX_OK;
2161 }
2162
2163 /**
2164  * pch_gbe_get_stats - Get System Network Statistics
2165  * @netdev:  Network interface device structure
2166  * Returns:  The current stats
2167  */
2168 static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev)
2169 {
2170         /* only return the current stats */
2171         return &netdev->stats;
2172 }
2173
2174 /**
2175  * pch_gbe_set_multi - Multicast and Promiscuous mode set
2176  * @netdev:   Network interface device structure
2177  */
2178 static void pch_gbe_set_multi(struct net_device *netdev)
2179 {
2180         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2181         struct pch_gbe_hw *hw = &adapter->hw;
2182         struct netdev_hw_addr *ha;
2183         u8 *mta_list;
2184         u32 rctl;
2185         int i;
2186         int mc_count;
2187
2188         netdev_dbg(netdev, "netdev->flags : 0x%08x\n", netdev->flags);
2189
2190         /* Check for Promiscuous and All Multicast modes */
2191         rctl = ioread32(&hw->reg->RX_MODE);
2192         mc_count = netdev_mc_count(netdev);
2193         if ((netdev->flags & IFF_PROMISC)) {
2194                 rctl &= ~PCH_GBE_ADD_FIL_EN;
2195                 rctl &= ~PCH_GBE_MLT_FIL_EN;
2196         } else if ((netdev->flags & IFF_ALLMULTI)) {
2197                 /* all the multicasting receive permissions */
2198                 rctl |= PCH_GBE_ADD_FIL_EN;
2199                 rctl &= ~PCH_GBE_MLT_FIL_EN;
2200         } else {
2201                 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
2202                         /* all the multicasting receive permissions */
2203                         rctl |= PCH_GBE_ADD_FIL_EN;
2204                         rctl &= ~PCH_GBE_MLT_FIL_EN;
2205                 } else {
2206                         rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
2207                 }
2208         }
2209         iowrite32(rctl, &hw->reg->RX_MODE);
2210
2211         if (mc_count >= PCH_GBE_MAR_ENTRIES)
2212                 return;
2213         mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
2214         if (!mta_list)
2215                 return;
2216
2217         /* The shared function expects a packed array of only addresses. */
2218         i = 0;
2219         netdev_for_each_mc_addr(ha, netdev) {
2220                 if (i == mc_count)
2221                         break;
2222                 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
2223         }
2224         pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
2225                                         PCH_GBE_MAR_ENTRIES);
2226         kfree(mta_list);
2227
2228         netdev_dbg(netdev,
2229                  "RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x  netdev->mc_count : 0x%08x\n",
2230                  ioread32(&hw->reg->RX_MODE), mc_count);
2231 }
2232
2233 /**
2234  * pch_gbe_set_mac - Change the Ethernet Address of the NIC
2235  * @netdev: Network interface device structure
2236  * @addr:   Pointer to an address structure
2237  * Returns:
2238  *      0:              Successfully
2239  *      -EADDRNOTAVAIL: Failed
2240  */
2241 static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
2242 {
2243         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2244         struct sockaddr *skaddr = addr;
2245         int ret_val;
2246
2247         if (!is_valid_ether_addr(skaddr->sa_data)) {
2248                 ret_val = -EADDRNOTAVAIL;
2249         } else {
2250                 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
2251                 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
2252                 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2253                 ret_val = 0;
2254         }
2255         netdev_dbg(netdev, "ret_val : 0x%08x\n", ret_val);
2256         netdev_dbg(netdev, "dev_addr : %pM\n", netdev->dev_addr);
2257         netdev_dbg(netdev, "mac_addr : %pM\n", adapter->hw.mac.addr);
2258         netdev_dbg(netdev, "MAC_ADR1AB reg : 0x%08x 0x%08x\n",
2259                    ioread32(&adapter->hw.reg->mac_adr[0].high),
2260                    ioread32(&adapter->hw.reg->mac_adr[0].low));
2261         return ret_val;
2262 }
2263
2264 /**
2265  * pch_gbe_change_mtu - Change the Maximum Transfer Unit
2266  * @netdev:   Network interface device structure
2267  * @new_mtu:  New value for maximum frame size
2268  * Returns:
2269  *      0:              Successfully
2270  *      -EINVAL:        Failed
2271  */
2272 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2273 {
2274         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2275         int max_frame;
2276         unsigned long old_rx_buffer_len = adapter->rx_buffer_len;
2277         int err;
2278
2279         max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2280         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2281                 (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) {
2282                 netdev_err(netdev, "Invalid MTU setting\n");
2283                 return -EINVAL;
2284         }
2285         if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2286                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2287         else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2288                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2289         else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2290                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2291         else
2292                 adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE;
2293
2294         if (netif_running(netdev)) {
2295                 pch_gbe_down(adapter);
2296                 err = pch_gbe_up(adapter);
2297                 if (err) {
2298                         adapter->rx_buffer_len = old_rx_buffer_len;
2299                         pch_gbe_up(adapter);
2300                         return err;
2301                 } else {
2302                         netdev->mtu = new_mtu;
2303                         adapter->hw.mac.max_frame_size = max_frame;
2304                 }
2305         } else {
2306                 pch_gbe_reset(adapter);
2307                 netdev->mtu = new_mtu;
2308                 adapter->hw.mac.max_frame_size = max_frame;
2309         }
2310
2311         netdev_dbg(netdev,
2312                    "max_frame : %d  rx_buffer_len : %d  mtu : %d  max_frame_size : %d\n",
2313                    max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2314                    adapter->hw.mac.max_frame_size);
2315         return 0;
2316 }
2317
2318 /**
2319  * pch_gbe_set_features - Reset device after features changed
2320  * @netdev:   Network interface device structure
2321  * @features:  New features
2322  * Returns:
2323  *      0:              HW state updated successfully
2324  */
2325 static int pch_gbe_set_features(struct net_device *netdev,
2326         netdev_features_t features)
2327 {
2328         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2329         netdev_features_t changed = features ^ netdev->features;
2330
2331         if (!(changed & NETIF_F_RXCSUM))
2332                 return 0;
2333
2334         if (netif_running(netdev))
2335                 pch_gbe_reinit_locked(adapter);
2336         else
2337                 pch_gbe_reset(adapter);
2338
2339         return 0;
2340 }
2341
2342 /**
2343  * pch_gbe_ioctl - Controls register through a MII interface
2344  * @netdev:   Network interface device structure
2345  * @ifr:      Pointer to ifr structure
2346  * @cmd:      Control command
2347  * Returns:
2348  *      0:      Successfully
2349  *      Negative value: Failed
2350  */
2351 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2352 {
2353         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2354
2355         netdev_dbg(netdev, "cmd : 0x%04x\n", cmd);
2356
2357         if (cmd == SIOCSHWTSTAMP)
2358                 return hwtstamp_ioctl(netdev, ifr, cmd);
2359
2360         return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2361 }
2362
2363 /**
2364  * pch_gbe_tx_timeout - Respond to a Tx Hang
2365  * @netdev:   Network interface device structure
2366  */
2367 static void pch_gbe_tx_timeout(struct net_device *netdev)
2368 {
2369         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2370
2371         /* Do the reset outside of interrupt context */
2372         adapter->stats.tx_timeout_count++;
2373         schedule_work(&adapter->reset_task);
2374 }
2375
2376 /**
2377  * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2378  * @napi:    Pointer of polling device struct
2379  * @budget:  The maximum number of a packet
2380  * Returns:
2381  *      false:  Exit the polling mode
2382  *      true:   Continue the polling mode
2383  */
2384 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2385 {
2386         struct pch_gbe_adapter *adapter =
2387             container_of(napi, struct pch_gbe_adapter, napi);
2388         int work_done = 0;
2389         bool poll_end_flag = false;
2390         bool cleaned = false;
2391
2392         netdev_dbg(adapter->netdev, "budget : %d\n", budget);
2393
2394         pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2395         cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2396
2397         if (cleaned)
2398                 work_done = budget;
2399         /* If no Tx and not enough Rx work done,
2400          * exit the polling mode
2401          */
2402         if (work_done < budget)
2403                 poll_end_flag = true;
2404
2405         if (poll_end_flag) {
2406                 napi_complete(napi);
2407                 pch_gbe_irq_enable(adapter);
2408         }
2409
2410         if (adapter->rx_stop_flag) {
2411                 adapter->rx_stop_flag = false;
2412                 pch_gbe_enable_dma_rx(&adapter->hw);
2413         }
2414
2415         netdev_dbg(adapter->netdev,
2416                    "poll_end_flag : %d  work_done : %d  budget : %d\n",
2417                    poll_end_flag, work_done, budget);
2418
2419         return work_done;
2420 }
2421
2422 #ifdef CONFIG_NET_POLL_CONTROLLER
2423 /**
2424  * pch_gbe_netpoll - Used by things like netconsole to send skbs
2425  * @netdev:  Network interface device structure
2426  */
2427 static void pch_gbe_netpoll(struct net_device *netdev)
2428 {
2429         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2430
2431         disable_irq(adapter->pdev->irq);
2432         pch_gbe_intr(adapter->pdev->irq, netdev);
2433         enable_irq(adapter->pdev->irq);
2434 }
2435 #endif
2436
2437 static const struct net_device_ops pch_gbe_netdev_ops = {
2438         .ndo_open = pch_gbe_open,
2439         .ndo_stop = pch_gbe_stop,
2440         .ndo_start_xmit = pch_gbe_xmit_frame,
2441         .ndo_get_stats = pch_gbe_get_stats,
2442         .ndo_set_mac_address = pch_gbe_set_mac,
2443         .ndo_tx_timeout = pch_gbe_tx_timeout,
2444         .ndo_change_mtu = pch_gbe_change_mtu,
2445         .ndo_set_features = pch_gbe_set_features,
2446         .ndo_do_ioctl = pch_gbe_ioctl,
2447         .ndo_set_rx_mode = pch_gbe_set_multi,
2448 #ifdef CONFIG_NET_POLL_CONTROLLER
2449         .ndo_poll_controller = pch_gbe_netpoll,
2450 #endif
2451 };
2452
2453 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2454                                                 pci_channel_state_t state)
2455 {
2456         struct net_device *netdev = pci_get_drvdata(pdev);
2457         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2458
2459         netif_device_detach(netdev);
2460         if (netif_running(netdev))
2461                 pch_gbe_down(adapter);
2462         pci_disable_device(pdev);
2463         /* Request a slot slot reset. */
2464         return PCI_ERS_RESULT_NEED_RESET;
2465 }
2466
2467 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2468 {
2469         struct net_device *netdev = pci_get_drvdata(pdev);
2470         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2471         struct pch_gbe_hw *hw = &adapter->hw;
2472
2473         if (pci_enable_device(pdev)) {
2474                 netdev_err(netdev, "Cannot re-enable PCI device after reset\n");
2475                 return PCI_ERS_RESULT_DISCONNECT;
2476         }
2477         pci_set_master(pdev);
2478         pci_enable_wake(pdev, PCI_D0, 0);
2479         pch_gbe_hal_power_up_phy(hw);
2480         pch_gbe_reset(adapter);
2481         /* Clear wake up status */
2482         pch_gbe_mac_set_wol_event(hw, 0);
2483
2484         return PCI_ERS_RESULT_RECOVERED;
2485 }
2486
2487 static void pch_gbe_io_resume(struct pci_dev *pdev)
2488 {
2489         struct net_device *netdev = pci_get_drvdata(pdev);
2490         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2491
2492         if (netif_running(netdev)) {
2493                 if (pch_gbe_up(adapter)) {
2494                         netdev_dbg(netdev,
2495                                    "can't bring device back up after reset\n");
2496                         return;
2497                 }
2498         }
2499         netif_device_attach(netdev);
2500 }
2501
2502 static int __pch_gbe_suspend(struct pci_dev *pdev)
2503 {
2504         struct net_device *netdev = pci_get_drvdata(pdev);
2505         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2506         struct pch_gbe_hw *hw = &adapter->hw;
2507         u32 wufc = adapter->wake_up_evt;
2508         int retval = 0;
2509
2510         netif_device_detach(netdev);
2511         if (netif_running(netdev))
2512                 pch_gbe_down(adapter);
2513         if (wufc) {
2514                 pch_gbe_set_multi(netdev);
2515                 pch_gbe_setup_rctl(adapter);
2516                 pch_gbe_configure_rx(adapter);
2517                 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2518                                         hw->mac.link_duplex);
2519                 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2520                                         hw->mac.link_duplex);
2521                 pch_gbe_mac_set_wol_event(hw, wufc);
2522                 pci_disable_device(pdev);
2523         } else {
2524                 pch_gbe_hal_power_down_phy(hw);
2525                 pch_gbe_mac_set_wol_event(hw, wufc);
2526                 pci_disable_device(pdev);
2527         }
2528         return retval;
2529 }
2530
2531 #ifdef CONFIG_PM
2532 static int pch_gbe_suspend(struct device *device)
2533 {
2534         struct pci_dev *pdev = to_pci_dev(device);
2535
2536         return __pch_gbe_suspend(pdev);
2537 }
2538
2539 static int pch_gbe_resume(struct device *device)
2540 {
2541         struct pci_dev *pdev = to_pci_dev(device);
2542         struct net_device *netdev = pci_get_drvdata(pdev);
2543         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2544         struct pch_gbe_hw *hw = &adapter->hw;
2545         u32 err;
2546
2547         err = pci_enable_device(pdev);
2548         if (err) {
2549                 netdev_err(netdev, "Cannot enable PCI device from suspend\n");
2550                 return err;
2551         }
2552         pci_set_master(pdev);
2553         pch_gbe_hal_power_up_phy(hw);
2554         pch_gbe_reset(adapter);
2555         /* Clear wake on lan control and status */
2556         pch_gbe_mac_set_wol_event(hw, 0);
2557
2558         if (netif_running(netdev))
2559                 pch_gbe_up(adapter);
2560         netif_device_attach(netdev);
2561
2562         return 0;
2563 }
2564 #endif /* CONFIG_PM */
2565
2566 static void pch_gbe_shutdown(struct pci_dev *pdev)
2567 {
2568         __pch_gbe_suspend(pdev);
2569         if (system_state == SYSTEM_POWER_OFF) {
2570                 pci_wake_from_d3(pdev, true);
2571                 pci_set_power_state(pdev, PCI_D3hot);
2572         }
2573 }
2574
2575 static void pch_gbe_remove(struct pci_dev *pdev)
2576 {
2577         struct net_device *netdev = pci_get_drvdata(pdev);
2578         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2579
2580         cancel_work_sync(&adapter->reset_task);
2581         unregister_netdev(netdev);
2582
2583         pch_gbe_hal_phy_hw_reset(&adapter->hw);
2584
2585         free_netdev(netdev);
2586 }
2587
2588 static int pch_gbe_probe(struct pci_dev *pdev,
2589                           const struct pci_device_id *pci_id)
2590 {
2591         struct net_device *netdev;
2592         struct pch_gbe_adapter *adapter;
2593         int ret;
2594
2595         ret = pcim_enable_device(pdev);
2596         if (ret)
2597                 return ret;
2598
2599         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2600                 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2601                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2602                 if (ret) {
2603                         ret = pci_set_consistent_dma_mask(pdev,
2604                                                           DMA_BIT_MASK(32));
2605                         if (ret) {
2606                                 dev_err(&pdev->dev, "ERR: No usable DMA "
2607                                         "configuration, aborting\n");
2608                                 return ret;
2609                         }
2610                 }
2611         }
2612
2613         ret = pcim_iomap_regions(pdev, 1 << PCH_GBE_PCI_BAR, pci_name(pdev));
2614         if (ret) {
2615                 dev_err(&pdev->dev,
2616                         "ERR: Can't reserve PCI I/O and memory resources\n");
2617                 return ret;
2618         }
2619         pci_set_master(pdev);
2620
2621         netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2622         if (!netdev)
2623                 return -ENOMEM;
2624         SET_NETDEV_DEV(netdev, &pdev->dev);
2625
2626         pci_set_drvdata(pdev, netdev);
2627         adapter = netdev_priv(netdev);
2628         adapter->netdev = netdev;
2629         adapter->pdev = pdev;
2630         adapter->hw.back = adapter;
2631         adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
2632         adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
2633         if (adapter->pdata && adapter->pdata->platform_init)
2634                 adapter->pdata->platform_init(pdev);
2635
2636         adapter->ptp_pdev = pci_get_bus_and_slot(adapter->pdev->bus->number,
2637                                                PCI_DEVFN(12, 4));
2638         if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) {
2639                 dev_err(&pdev->dev, "Bad ptp filter\n");
2640                 ret = -EINVAL;
2641                 goto err_free_netdev;
2642         }
2643
2644         netdev->netdev_ops = &pch_gbe_netdev_ops;
2645         netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2646         netif_napi_add(netdev, &adapter->napi,
2647                        pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2648         netdev->hw_features = NETIF_F_RXCSUM |
2649                 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2650         netdev->features = netdev->hw_features;
2651         pch_gbe_set_ethtool_ops(netdev);
2652
2653         pch_gbe_mac_load_mac_addr(&adapter->hw);
2654         pch_gbe_mac_reset_hw(&adapter->hw);
2655
2656         /* setup the private structure */
2657         ret = pch_gbe_sw_init(adapter);
2658         if (ret)
2659                 goto err_free_netdev;
2660
2661         /* Initialize PHY */
2662         ret = pch_gbe_init_phy(adapter);
2663         if (ret) {
2664                 dev_err(&pdev->dev, "PHY initialize error\n");
2665                 goto err_free_adapter;
2666         }
2667         pch_gbe_hal_get_bus_info(&adapter->hw);
2668
2669         /* Read the MAC address. and store to the private data */
2670         ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2671         if (ret) {
2672                 dev_err(&pdev->dev, "MAC address Read Error\n");
2673                 goto err_free_adapter;
2674         }
2675
2676         memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2677         if (!is_valid_ether_addr(netdev->dev_addr)) {
2678                 /*
2679                  * If the MAC is invalid (or just missing), display a warning
2680                  * but do not abort setting up the device. pch_gbe_up will
2681                  * prevent the interface from being brought up until a valid MAC
2682                  * is set.
2683                  */
2684                 dev_err(&pdev->dev, "Invalid MAC address, "
2685                                     "interface disabled.\n");
2686         }
2687         setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2688                     (unsigned long)adapter);
2689
2690         INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2691
2692         pch_gbe_check_options(adapter);
2693
2694         /* initialize the wol settings based on the eeprom settings */
2695         adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2696         dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2697
2698         /* reset the hardware with the new settings */
2699         pch_gbe_reset(adapter);
2700
2701         ret = register_netdev(netdev);
2702         if (ret)
2703                 goto err_free_adapter;
2704         /* tell the stack to leave us alone until pch_gbe_open() is called */
2705         netif_carrier_off(netdev);
2706         netif_stop_queue(netdev);
2707
2708         dev_dbg(&pdev->dev, "PCH Network Connection\n");
2709
2710         /* Disable hibernation on certain platforms */
2711         if (adapter->pdata && adapter->pdata->phy_disable_hibernate)
2712                 pch_gbe_phy_disable_hibernate(&adapter->hw);
2713
2714         device_set_wakeup_enable(&pdev->dev, 1);
2715         return 0;
2716
2717 err_free_adapter:
2718         pch_gbe_hal_phy_hw_reset(&adapter->hw);
2719 err_free_netdev:
2720         free_netdev(netdev);
2721         return ret;
2722 }
2723
2724 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
2725  * ensure it is awake for probe and init. Request the line and reset the PHY.
2726  */
2727 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
2728 {
2729         unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH | GPIOF_EXPORT;
2730         unsigned gpio = MINNOW_PHY_RESET_GPIO;
2731         int ret;
2732
2733         ret = devm_gpio_request_one(&pdev->dev, gpio, flags,
2734                                     "minnow_phy_reset");
2735         if (ret) {
2736                 dev_err(&pdev->dev,
2737                         "ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
2738                 return ret;
2739         }
2740
2741         gpio_set_value(gpio, 0);
2742         usleep_range(1250, 1500);
2743         gpio_set_value(gpio, 1);
2744         usleep_range(1250, 1500);
2745
2746         return ret;
2747 }
2748
2749 static struct pch_gbe_privdata pch_gbe_minnow_privdata = {
2750         .phy_tx_clk_delay = true,
2751         .phy_disable_hibernate = true,
2752         .platform_init = pch_gbe_minnow_platform_init,
2753 };
2754
2755 static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = {
2756         {.vendor = PCI_VENDOR_ID_INTEL,
2757          .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2758          .subvendor = PCI_VENDOR_ID_CIRCUITCO,
2759          .subdevice = PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD,
2760          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2761          .class_mask = (0xFFFF00),
2762          .driver_data = (kernel_ulong_t)&pch_gbe_minnow_privdata
2763          },
2764         {.vendor = PCI_VENDOR_ID_INTEL,
2765          .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2766          .subvendor = PCI_ANY_ID,
2767          .subdevice = PCI_ANY_ID,
2768          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2769          .class_mask = (0xFFFF00)
2770          },
2771         {.vendor = PCI_VENDOR_ID_ROHM,
2772          .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2773          .subvendor = PCI_ANY_ID,
2774          .subdevice = PCI_ANY_ID,
2775          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2776          .class_mask = (0xFFFF00)
2777          },
2778         {.vendor = PCI_VENDOR_ID_ROHM,
2779          .device = PCI_DEVICE_ID_ROHM_ML7831_GBE,
2780          .subvendor = PCI_ANY_ID,
2781          .subdevice = PCI_ANY_ID,
2782          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2783          .class_mask = (0xFFFF00)
2784          },
2785         /* required last entry */
2786         {0}
2787 };
2788
2789 #ifdef CONFIG_PM
2790 static const struct dev_pm_ops pch_gbe_pm_ops = {
2791         .suspend = pch_gbe_suspend,
2792         .resume = pch_gbe_resume,
2793         .freeze = pch_gbe_suspend,
2794         .thaw = pch_gbe_resume,
2795         .poweroff = pch_gbe_suspend,
2796         .restore = pch_gbe_resume,
2797 };
2798 #endif
2799
2800 static const struct pci_error_handlers pch_gbe_err_handler = {
2801         .error_detected = pch_gbe_io_error_detected,
2802         .slot_reset = pch_gbe_io_slot_reset,
2803         .resume = pch_gbe_io_resume
2804 };
2805
2806 static struct pci_driver pch_gbe_driver = {
2807         .name = KBUILD_MODNAME,
2808         .id_table = pch_gbe_pcidev_id,
2809         .probe = pch_gbe_probe,
2810         .remove = pch_gbe_remove,
2811 #ifdef CONFIG_PM
2812         .driver.pm = &pch_gbe_pm_ops,
2813 #endif
2814         .shutdown = pch_gbe_shutdown,
2815         .err_handler = &pch_gbe_err_handler
2816 };
2817
2818
2819 static int __init pch_gbe_init_module(void)
2820 {
2821         int ret;
2822
2823         pr_info("EG20T PCH Gigabit Ethernet Driver - version %s\n",DRV_VERSION);
2824         ret = pci_register_driver(&pch_gbe_driver);
2825         if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2826                 if (copybreak == 0) {
2827                         pr_info("copybreak disabled\n");
2828                 } else {
2829                         pr_info("copybreak enabled for packets <= %u bytes\n",
2830                                 copybreak);
2831                 }
2832         }
2833         return ret;
2834 }
2835
2836 static void __exit pch_gbe_exit_module(void)
2837 {
2838         pci_unregister_driver(&pch_gbe_driver);
2839 }
2840
2841 module_init(pch_gbe_init_module);
2842 module_exit(pch_gbe_exit_module);
2843
2844 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2845 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
2846 MODULE_LICENSE("GPL");
2847 MODULE_VERSION(DRV_VERSION);
2848 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2849
2850 module_param(copybreak, uint, 0644);
2851 MODULE_PARM_DESC(copybreak,
2852         "Maximum size of packet that is copied to a new buffer on receive");
2853
2854 /* pch_gbe_main.c */