1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34 #include <linux/types.h>
35 #include <linux/if_ether.h>
36 #include <linux/i2c.h>
38 #include "e1000_mac.h"
39 #include "e1000_82575.h"
40 #include "e1000_i210.h"
42 static s32 igb_get_invariants_82575(struct e1000_hw *);
43 static s32 igb_acquire_phy_82575(struct e1000_hw *);
44 static void igb_release_phy_82575(struct e1000_hw *);
45 static s32 igb_acquire_nvm_82575(struct e1000_hw *);
46 static void igb_release_nvm_82575(struct e1000_hw *);
47 static s32 igb_check_for_link_82575(struct e1000_hw *);
48 static s32 igb_get_cfg_done_82575(struct e1000_hw *);
49 static s32 igb_init_hw_82575(struct e1000_hw *);
50 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
51 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
52 static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
53 static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
54 static s32 igb_reset_hw_82575(struct e1000_hw *);
55 static s32 igb_reset_hw_82580(struct e1000_hw *);
56 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
57 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
58 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
59 static s32 igb_setup_copper_link_82575(struct e1000_hw *);
60 static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
61 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
62 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
63 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
64 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
66 static s32 igb_get_phy_id_82575(struct e1000_hw *);
67 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
68 static bool igb_sgmii_active_82575(struct e1000_hw *);
69 static s32 igb_reset_init_script_82575(struct e1000_hw *);
70 static s32 igb_read_mac_addr_82575(struct e1000_hw *);
71 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
72 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
73 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
74 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
75 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
76 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
77 static const u16 e1000_82580_rxpbs_table[] =
78 { 36, 72, 144, 1, 2, 4, 8, 16,
80 #define E1000_82580_RXPBS_TABLE_SIZE \
81 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
84 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
85 * @hw: pointer to the HW structure
87 * Called to determine if the I2C pins are being used for I2C or as an
88 * external MDIO interface since the two options are mutually exclusive.
90 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
93 bool ext_mdio = false;
95 switch (hw->mac.type) {
98 reg = rd32(E1000_MDIC);
99 ext_mdio = !!(reg & E1000_MDIC_DEST);
106 reg = rd32(E1000_MDICNFG);
107 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
116 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
117 * @hw: pointer to the HW structure
119 * Poll the M88E1112 interfaces to see which interface achieved link.
121 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)
123 struct e1000_phy_info *phy = &hw->phy;
128 /* Check the copper medium. */
129 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
133 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
137 if (data & E1000_M88E1112_STATUS_LINK)
138 port = E1000_MEDIA_PORT_COPPER;
140 /* Check the other medium. */
141 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
145 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
149 /* reset page to 0 */
150 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
154 if (data & E1000_M88E1112_STATUS_LINK)
155 port = E1000_MEDIA_PORT_OTHER;
157 /* Determine if a swap needs to happen. */
158 if (port && (hw->dev_spec._82575.media_port != port)) {
159 hw->dev_spec._82575.media_port = port;
160 hw->dev_spec._82575.media_changed = true;
162 ret_val = igb_check_for_link_82575(hw);
165 return E1000_SUCCESS;
169 * igb_init_phy_params_82575 - Init PHY func ptrs.
170 * @hw: pointer to the HW structure
172 static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
174 struct e1000_phy_info *phy = &hw->phy;
178 if (hw->phy.media_type != e1000_media_type_copper) {
179 phy->type = e1000_phy_none;
183 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
184 phy->reset_delay_us = 100;
186 ctrl_ext = rd32(E1000_CTRL_EXT);
188 if (igb_sgmii_active_82575(hw)) {
189 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
190 ctrl_ext |= E1000_CTRL_I2C_ENA;
192 phy->ops.reset = igb_phy_hw_reset;
193 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
196 wr32(E1000_CTRL_EXT, ctrl_ext);
197 igb_reset_mdicnfg_82580(hw);
199 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
200 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
201 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
203 switch (hw->mac.type) {
207 phy->ops.read_reg = igb_read_phy_reg_82580;
208 phy->ops.write_reg = igb_write_phy_reg_82580;
212 phy->ops.read_reg = igb_read_phy_reg_gs40g;
213 phy->ops.write_reg = igb_write_phy_reg_gs40g;
216 phy->ops.read_reg = igb_read_phy_reg_igp;
217 phy->ops.write_reg = igb_write_phy_reg_igp;
222 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
223 E1000_STATUS_FUNC_SHIFT;
225 /* Set phy->phy_addr and phy->id. */
226 ret_val = igb_get_phy_id_82575(hw);
230 /* Verify phy id and set remaining function pointers */
232 case M88E1543_E_PHY_ID:
233 case I347AT4_E_PHY_ID:
234 case M88E1112_E_PHY_ID:
235 case M88E1111_I_PHY_ID:
236 phy->type = e1000_phy_m88;
237 phy->ops.check_polarity = igb_check_polarity_m88;
238 phy->ops.get_phy_info = igb_get_phy_info_m88;
239 if (phy->id != M88E1111_I_PHY_ID)
240 phy->ops.get_cable_length =
241 igb_get_cable_length_m88_gen2;
243 phy->ops.get_cable_length = igb_get_cable_length_m88;
244 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
245 /* Check if this PHY is confgured for media swap. */
246 if (phy->id == M88E1112_E_PHY_ID) {
249 ret_val = phy->ops.write_reg(hw,
250 E1000_M88E1112_PAGE_ADDR,
255 ret_val = phy->ops.read_reg(hw,
256 E1000_M88E1112_MAC_CTRL_1,
261 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
262 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
263 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
264 data == E1000_M88E1112_AUTO_COPPER_BASEX)
265 hw->mac.ops.check_for_link =
266 igb_check_for_link_media_swap;
269 case IGP03E1000_E_PHY_ID:
270 phy->type = e1000_phy_igp_3;
271 phy->ops.get_phy_info = igb_get_phy_info_igp;
272 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
273 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
274 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
275 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
277 case I82580_I_PHY_ID:
279 phy->type = e1000_phy_82580;
280 phy->ops.force_speed_duplex =
281 igb_phy_force_speed_duplex_82580;
282 phy->ops.get_cable_length = igb_get_cable_length_82580;
283 phy->ops.get_phy_info = igb_get_phy_info_82580;
284 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
285 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
288 phy->type = e1000_phy_i210;
289 phy->ops.check_polarity = igb_check_polarity_m88;
290 phy->ops.get_phy_info = igb_get_phy_info_m88;
291 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
292 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
293 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
294 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
297 ret_val = -E1000_ERR_PHY;
306 * igb_init_nvm_params_82575 - Init NVM func ptrs.
307 * @hw: pointer to the HW structure
309 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
311 struct e1000_nvm_info *nvm = &hw->nvm;
312 u32 eecd = rd32(E1000_EECD);
315 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
316 E1000_EECD_SIZE_EX_SHIFT);
318 /* Added to a constant, "size" becomes the left-shift value
319 * for setting word_size.
321 size += NVM_WORD_SIZE_BASE_SHIFT;
323 /* Just in case size is out of range, cap it to the largest
324 * EEPROM size supported
329 nvm->word_size = 1 << size;
330 nvm->opcode_bits = 8;
333 switch (nvm->override) {
334 case e1000_nvm_override_spi_large:
336 nvm->address_bits = 16;
338 case e1000_nvm_override_spi_small:
340 nvm->address_bits = 8;
343 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
344 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
348 if (nvm->word_size == (1 << 15))
349 nvm->page_size = 128;
351 nvm->type = e1000_nvm_eeprom_spi;
353 /* NVM Function Pointers */
354 nvm->ops.acquire = igb_acquire_nvm_82575;
355 nvm->ops.release = igb_release_nvm_82575;
356 nvm->ops.write = igb_write_nvm_spi;
357 nvm->ops.validate = igb_validate_nvm_checksum;
358 nvm->ops.update = igb_update_nvm_checksum;
359 if (nvm->word_size < (1 << 15))
360 nvm->ops.read = igb_read_nvm_eerd;
362 nvm->ops.read = igb_read_nvm_spi;
364 /* override generic family function pointers for specific descendants */
365 switch (hw->mac.type) {
367 nvm->ops.validate = igb_validate_nvm_checksum_82580;
368 nvm->ops.update = igb_update_nvm_checksum_82580;
372 nvm->ops.validate = igb_validate_nvm_checksum_i350;
373 nvm->ops.update = igb_update_nvm_checksum_i350;
383 * igb_init_mac_params_82575 - Init MAC func ptrs.
384 * @hw: pointer to the HW structure
386 static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
388 struct e1000_mac_info *mac = &hw->mac;
389 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
391 /* Set mta register count */
392 mac->mta_reg_count = 128;
393 /* Set rar entry count */
396 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
399 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
403 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
406 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
410 if (mac->type >= e1000_82580)
411 mac->ops.reset_hw = igb_reset_hw_82580;
413 mac->ops.reset_hw = igb_reset_hw_82575;
415 if (mac->type >= e1000_i210) {
416 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
417 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
420 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
421 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
424 /* Set if part includes ASF firmware */
425 mac->asf_firmware_present = true;
426 /* Set if manageability features are enabled. */
427 mac->arc_subsystem_valid =
428 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
430 /* enable EEE on i350 parts and later parts */
431 if (mac->type >= e1000_i350)
432 dev_spec->eee_disable = false;
434 dev_spec->eee_disable = true;
435 /* Allow a single clear of the SW semaphore on I210 and newer */
436 if (mac->type >= e1000_i210)
437 dev_spec->clear_semaphore_once = true;
438 /* physical interface link setup */
439 mac->ops.setup_physical_interface =
440 (hw->phy.media_type == e1000_media_type_copper)
441 ? igb_setup_copper_link_82575
442 : igb_setup_serdes_link_82575;
444 if (mac->type == e1000_82580) {
445 switch (hw->device_id) {
446 /* feature not supported on these id's */
447 case E1000_DEV_ID_DH89XXCC_SGMII:
448 case E1000_DEV_ID_DH89XXCC_SERDES:
449 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
450 case E1000_DEV_ID_DH89XXCC_SFP:
453 hw->dev_spec._82575.mas_capable = true;
461 * igb_set_sfp_media_type_82575 - derives SFP module media type.
462 * @hw: pointer to the HW structure
464 * The media type is chosen based on SFP module.
465 * compatibility flags retrieved from SFP ID EEPROM.
467 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
469 s32 ret_val = E1000_ERR_CONFIG;
471 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
472 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
473 u8 tranceiver_type = 0;
476 /* Turn I2C interface ON and power on sfp cage */
477 ctrl_ext = rd32(E1000_CTRL_EXT);
478 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
479 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
483 /* Read SFP module data */
485 ret_val = igb_read_sfp_data_byte(hw,
486 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
496 ret_val = igb_read_sfp_data_byte(hw,
497 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
502 /* Check if there is some SFP module plugged and powered */
503 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
504 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
505 dev_spec->module_plugged = true;
506 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
507 hw->phy.media_type = e1000_media_type_internal_serdes;
508 } else if (eth_flags->e100_base_fx) {
509 dev_spec->sgmii_active = true;
510 hw->phy.media_type = e1000_media_type_internal_serdes;
511 } else if (eth_flags->e1000_base_t) {
512 dev_spec->sgmii_active = true;
513 hw->phy.media_type = e1000_media_type_copper;
515 hw->phy.media_type = e1000_media_type_unknown;
516 hw_dbg("PHY module has not been recognized\n");
520 hw->phy.media_type = e1000_media_type_unknown;
524 /* Restore I2C interface setting */
525 wr32(E1000_CTRL_EXT, ctrl_ext);
529 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
531 struct e1000_mac_info *mac = &hw->mac;
532 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
537 switch (hw->device_id) {
538 case E1000_DEV_ID_82575EB_COPPER:
539 case E1000_DEV_ID_82575EB_FIBER_SERDES:
540 case E1000_DEV_ID_82575GB_QUAD_COPPER:
541 mac->type = e1000_82575;
543 case E1000_DEV_ID_82576:
544 case E1000_DEV_ID_82576_NS:
545 case E1000_DEV_ID_82576_NS_SERDES:
546 case E1000_DEV_ID_82576_FIBER:
547 case E1000_DEV_ID_82576_SERDES:
548 case E1000_DEV_ID_82576_QUAD_COPPER:
549 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
550 case E1000_DEV_ID_82576_SERDES_QUAD:
551 mac->type = e1000_82576;
553 case E1000_DEV_ID_82580_COPPER:
554 case E1000_DEV_ID_82580_FIBER:
555 case E1000_DEV_ID_82580_QUAD_FIBER:
556 case E1000_DEV_ID_82580_SERDES:
557 case E1000_DEV_ID_82580_SGMII:
558 case E1000_DEV_ID_82580_COPPER_DUAL:
559 case E1000_DEV_ID_DH89XXCC_SGMII:
560 case E1000_DEV_ID_DH89XXCC_SERDES:
561 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
562 case E1000_DEV_ID_DH89XXCC_SFP:
563 mac->type = e1000_82580;
565 case E1000_DEV_ID_I350_COPPER:
566 case E1000_DEV_ID_I350_FIBER:
567 case E1000_DEV_ID_I350_SERDES:
568 case E1000_DEV_ID_I350_SGMII:
569 mac->type = e1000_i350;
571 case E1000_DEV_ID_I210_COPPER:
572 case E1000_DEV_ID_I210_FIBER:
573 case E1000_DEV_ID_I210_SERDES:
574 case E1000_DEV_ID_I210_SGMII:
575 case E1000_DEV_ID_I210_COPPER_FLASHLESS:
576 case E1000_DEV_ID_I210_SERDES_FLASHLESS:
577 mac->type = e1000_i210;
579 case E1000_DEV_ID_I211_COPPER:
580 mac->type = e1000_i211;
582 case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
583 case E1000_DEV_ID_I354_SGMII:
584 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
585 mac->type = e1000_i354;
588 return -E1000_ERR_MAC_INIT;
593 /* The 82575 uses bits 22:23 for link mode. The mode can be changed
594 * based on the EEPROM. We cannot rely upon device ID. There
595 * is no distinguishable difference between fiber and internal
596 * SerDes mode on the 82575. There can be an external PHY attached
597 * on the SGMII interface. For this, we'll set sgmii_active to true.
599 hw->phy.media_type = e1000_media_type_copper;
600 dev_spec->sgmii_active = false;
601 dev_spec->module_plugged = false;
603 ctrl_ext = rd32(E1000_CTRL_EXT);
605 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
607 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
608 hw->phy.media_type = e1000_media_type_internal_serdes;
610 case E1000_CTRL_EXT_LINK_MODE_SGMII:
611 /* Get phy control interface type set (MDIO vs. I2C)*/
612 if (igb_sgmii_uses_mdio_82575(hw)) {
613 hw->phy.media_type = e1000_media_type_copper;
614 dev_spec->sgmii_active = true;
617 /* fall through for I2C based SGMII */
618 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
619 /* read media type from SFP EEPROM */
620 ret_val = igb_set_sfp_media_type_82575(hw);
621 if ((ret_val != 0) ||
622 (hw->phy.media_type == e1000_media_type_unknown)) {
623 /* If media type was not identified then return media
624 * type defined by the CTRL_EXT settings.
626 hw->phy.media_type = e1000_media_type_internal_serdes;
628 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
629 hw->phy.media_type = e1000_media_type_copper;
630 dev_spec->sgmii_active = true;
636 /* do not change link mode for 100BaseFX */
637 if (dev_spec->eth_flags.e100_base_fx)
640 /* change current link mode setting */
641 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
643 if (hw->phy.media_type == e1000_media_type_copper)
644 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
646 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
648 wr32(E1000_CTRL_EXT, ctrl_ext);
655 /* mac initialization and operations */
656 ret_val = igb_init_mac_params_82575(hw);
660 /* NVM initialization */
661 ret_val = igb_init_nvm_params_82575(hw);
662 switch (hw->mac.type) {
665 ret_val = igb_init_nvm_params_i210(hw);
674 /* if part supports SR-IOV then initialize mailbox parameters */
678 igb_init_mbx_params_pf(hw);
684 /* setup PHY parameters */
685 ret_val = igb_init_phy_params_82575(hw);
692 * igb_acquire_phy_82575 - Acquire rights to access PHY
693 * @hw: pointer to the HW structure
695 * Acquire access rights to the correct PHY. This is a
696 * function pointer entry point called by the api module.
698 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
700 u16 mask = E1000_SWFW_PHY0_SM;
702 if (hw->bus.func == E1000_FUNC_1)
703 mask = E1000_SWFW_PHY1_SM;
704 else if (hw->bus.func == E1000_FUNC_2)
705 mask = E1000_SWFW_PHY2_SM;
706 else if (hw->bus.func == E1000_FUNC_3)
707 mask = E1000_SWFW_PHY3_SM;
709 return hw->mac.ops.acquire_swfw_sync(hw, mask);
713 * igb_release_phy_82575 - Release rights to access PHY
714 * @hw: pointer to the HW structure
716 * A wrapper to release access rights to the correct PHY. This is a
717 * function pointer entry point called by the api module.
719 static void igb_release_phy_82575(struct e1000_hw *hw)
721 u16 mask = E1000_SWFW_PHY0_SM;
723 if (hw->bus.func == E1000_FUNC_1)
724 mask = E1000_SWFW_PHY1_SM;
725 else if (hw->bus.func == E1000_FUNC_2)
726 mask = E1000_SWFW_PHY2_SM;
727 else if (hw->bus.func == E1000_FUNC_3)
728 mask = E1000_SWFW_PHY3_SM;
730 hw->mac.ops.release_swfw_sync(hw, mask);
734 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
735 * @hw: pointer to the HW structure
736 * @offset: register offset to be read
737 * @data: pointer to the read data
739 * Reads the PHY register at offset using the serial gigabit media independent
740 * interface and stores the retrieved information in data.
742 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
745 s32 ret_val = -E1000_ERR_PARAM;
747 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
748 hw_dbg("PHY Address %u is out of range\n", offset);
752 ret_val = hw->phy.ops.acquire(hw);
756 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
758 hw->phy.ops.release(hw);
765 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
766 * @hw: pointer to the HW structure
767 * @offset: register offset to write to
768 * @data: data to write at register offset
770 * Writes the data to PHY register at the offset using the serial gigabit
771 * media independent interface.
773 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
776 s32 ret_val = -E1000_ERR_PARAM;
779 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
780 hw_dbg("PHY Address %d is out of range\n", offset);
784 ret_val = hw->phy.ops.acquire(hw);
788 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
790 hw->phy.ops.release(hw);
797 * igb_get_phy_id_82575 - Retrieve PHY addr and id
798 * @hw: pointer to the HW structure
800 * Retrieves the PHY address and ID for both PHY's which do and do not use
803 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
805 struct e1000_phy_info *phy = &hw->phy;
811 /* Extra read required for some PHY's on i354 */
812 if (hw->mac.type == e1000_i354)
815 /* For SGMII PHYs, we try the list of possible addresses until
816 * we find one that works. For non-SGMII PHYs
817 * (e.g. integrated copper PHYs), an address of 1 should
818 * work. The result of this function should mean phy->phy_addr
819 * and phy->id are set correctly.
821 if (!(igb_sgmii_active_82575(hw))) {
823 ret_val = igb_get_phy_id(hw);
827 if (igb_sgmii_uses_mdio_82575(hw)) {
828 switch (hw->mac.type) {
831 mdic = rd32(E1000_MDIC);
832 mdic &= E1000_MDIC_PHY_MASK;
833 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
840 mdic = rd32(E1000_MDICNFG);
841 mdic &= E1000_MDICNFG_PHY_MASK;
842 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
845 ret_val = -E1000_ERR_PHY;
849 ret_val = igb_get_phy_id(hw);
853 /* Power on sgmii phy if it is disabled */
854 ctrl_ext = rd32(E1000_CTRL_EXT);
855 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
859 /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
860 * Therefore, we need to test 1-7
862 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
863 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
865 hw_dbg("Vendor ID 0x%08X read at address %u\n",
867 /* At the time of this writing, The M88 part is
868 * the only supported SGMII PHY product.
870 if (phy_id == M88_VENDOR)
873 hw_dbg("PHY address %u was unreadable\n", phy->addr);
877 /* A valid PHY type couldn't be found. */
878 if (phy->addr == 8) {
880 ret_val = -E1000_ERR_PHY;
883 ret_val = igb_get_phy_id(hw);
886 /* restore previous sfp cage power state */
887 wr32(E1000_CTRL_EXT, ctrl_ext);
894 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
895 * @hw: pointer to the HW structure
897 * Resets the PHY using the serial gigabit media independent interface.
899 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
903 /* This isn't a true "hard" reset, but is the only reset
904 * available to us at this time.
907 hw_dbg("Soft resetting SGMII attached PHY...\n");
909 /* SFP documentation requires the following to configure the SPF module
910 * to work on SGMII. No further documentation is given.
912 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
916 ret_val = igb_phy_sw_reset(hw);
923 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
924 * @hw: pointer to the HW structure
925 * @active: true to enable LPLU, false to disable
927 * Sets the LPLU D0 state according to the active flag. When
928 * activating LPLU this function also disables smart speed
929 * and vice versa. LPLU will not be activated unless the
930 * device autonegotiation advertisement meets standards of
931 * either 10 or 10/100 or 10/100/1000 at all duplexes.
932 * This is a function pointer entry point only called by
933 * PHY setup routines.
935 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
937 struct e1000_phy_info *phy = &hw->phy;
941 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
946 data |= IGP02E1000_PM_D0_LPLU;
947 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
952 /* When LPLU is enabled, we should disable SmartSpeed */
953 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
955 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
956 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
961 data &= ~IGP02E1000_PM_D0_LPLU;
962 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
964 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
965 * during Dx states where the power conservation is most
966 * important. During driver activity we should enable
967 * SmartSpeed, so performance is maintained.
969 if (phy->smart_speed == e1000_smart_speed_on) {
970 ret_val = phy->ops.read_reg(hw,
971 IGP01E1000_PHY_PORT_CONFIG, &data);
975 data |= IGP01E1000_PSCFR_SMART_SPEED;
976 ret_val = phy->ops.write_reg(hw,
977 IGP01E1000_PHY_PORT_CONFIG, data);
980 } else if (phy->smart_speed == e1000_smart_speed_off) {
981 ret_val = phy->ops.read_reg(hw,
982 IGP01E1000_PHY_PORT_CONFIG, &data);
986 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
987 ret_val = phy->ops.write_reg(hw,
988 IGP01E1000_PHY_PORT_CONFIG, data);
999 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
1000 * @hw: pointer to the HW structure
1001 * @active: true to enable LPLU, false to disable
1003 * Sets the LPLU D0 state according to the active flag. When
1004 * activating LPLU this function also disables smart speed
1005 * and vice versa. LPLU will not be activated unless the
1006 * device autonegotiation advertisement meets standards of
1007 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1008 * This is a function pointer entry point only called by
1009 * PHY setup routines.
1011 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
1013 struct e1000_phy_info *phy = &hw->phy;
1017 data = rd32(E1000_82580_PHY_POWER_MGMT);
1020 data |= E1000_82580_PM_D0_LPLU;
1022 /* When LPLU is enabled, we should disable SmartSpeed */
1023 data &= ~E1000_82580_PM_SPD;
1025 data &= ~E1000_82580_PM_D0_LPLU;
1027 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1028 * during Dx states where the power conservation is most
1029 * important. During driver activity we should enable
1030 * SmartSpeed, so performance is maintained.
1032 if (phy->smart_speed == e1000_smart_speed_on)
1033 data |= E1000_82580_PM_SPD;
1034 else if (phy->smart_speed == e1000_smart_speed_off)
1035 data &= ~E1000_82580_PM_SPD; }
1037 wr32(E1000_82580_PHY_POWER_MGMT, data);
1042 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1043 * @hw: pointer to the HW structure
1044 * @active: boolean used to enable/disable lplu
1046 * Success returns 0, Failure returns 1
1048 * The low power link up (lplu) state is set to the power management level D3
1049 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1050 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1051 * is used during Dx states where the power conservation is most important.
1052 * During driver activity, SmartSpeed should be enabled so performance is
1055 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
1057 struct e1000_phy_info *phy = &hw->phy;
1061 data = rd32(E1000_82580_PHY_POWER_MGMT);
1064 data &= ~E1000_82580_PM_D3_LPLU;
1065 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1066 * during Dx states where the power conservation is most
1067 * important. During driver activity we should enable
1068 * SmartSpeed, so performance is maintained.
1070 if (phy->smart_speed == e1000_smart_speed_on)
1071 data |= E1000_82580_PM_SPD;
1072 else if (phy->smart_speed == e1000_smart_speed_off)
1073 data &= ~E1000_82580_PM_SPD;
1074 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1075 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1076 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1077 data |= E1000_82580_PM_D3_LPLU;
1078 /* When LPLU is enabled, we should disable SmartSpeed */
1079 data &= ~E1000_82580_PM_SPD;
1082 wr32(E1000_82580_PHY_POWER_MGMT, data);
1087 * igb_acquire_nvm_82575 - Request for access to EEPROM
1088 * @hw: pointer to the HW structure
1090 * Acquire the necessary semaphores for exclusive access to the EEPROM.
1091 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1092 * Return successful if access grant bit set, else clear the request for
1093 * EEPROM access and return -E1000_ERR_NVM (-1).
1095 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1099 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1103 ret_val = igb_acquire_nvm(hw);
1106 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1113 * igb_release_nvm_82575 - Release exclusive access to EEPROM
1114 * @hw: pointer to the HW structure
1116 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1117 * then release the semaphores acquired.
1119 static void igb_release_nvm_82575(struct e1000_hw *hw)
1121 igb_release_nvm(hw);
1122 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1126 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1127 * @hw: pointer to the HW structure
1128 * @mask: specifies which semaphore to acquire
1130 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1131 * will also specify which port we're acquiring the lock for.
1133 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1137 u32 fwmask = mask << 16;
1139 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1141 while (i < timeout) {
1142 if (igb_get_hw_semaphore(hw)) {
1143 ret_val = -E1000_ERR_SWFW_SYNC;
1147 swfw_sync = rd32(E1000_SW_FW_SYNC);
1148 if (!(swfw_sync & (fwmask | swmask)))
1151 /* Firmware currently using resource (fwmask)
1152 * or other software thread using resource (swmask)
1154 igb_put_hw_semaphore(hw);
1160 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1161 ret_val = -E1000_ERR_SWFW_SYNC;
1165 swfw_sync |= swmask;
1166 wr32(E1000_SW_FW_SYNC, swfw_sync);
1168 igb_put_hw_semaphore(hw);
1175 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
1176 * @hw: pointer to the HW structure
1177 * @mask: specifies which semaphore to acquire
1179 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1180 * will also specify which port we're releasing the lock for.
1182 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1186 while (igb_get_hw_semaphore(hw) != 0);
1189 swfw_sync = rd32(E1000_SW_FW_SYNC);
1191 wr32(E1000_SW_FW_SYNC, swfw_sync);
1193 igb_put_hw_semaphore(hw);
1197 * igb_get_cfg_done_82575 - Read config done bit
1198 * @hw: pointer to the HW structure
1200 * Read the management control register for the config done bit for
1201 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1202 * to read the config done bit, so an error is *ONLY* logged and returns
1203 * 0. If we were to return with error, EEPROM-less silicon
1204 * would not be able to be reset or change link.
1206 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1208 s32 timeout = PHY_CFG_TIMEOUT;
1210 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1212 if (hw->bus.func == 1)
1213 mask = E1000_NVM_CFG_DONE_PORT_1;
1214 else if (hw->bus.func == E1000_FUNC_2)
1215 mask = E1000_NVM_CFG_DONE_PORT_2;
1216 else if (hw->bus.func == E1000_FUNC_3)
1217 mask = E1000_NVM_CFG_DONE_PORT_3;
1220 if (rd32(E1000_EEMNGCTL) & mask)
1226 hw_dbg("MNG configuration cycle has not completed.\n");
1228 /* If EEPROM is not marked present, init the PHY manually */
1229 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1230 (hw->phy.type == e1000_phy_igp_3))
1231 igb_phy_init_script_igp3(hw);
1237 * igb_get_link_up_info_82575 - Get link speed/duplex info
1238 * @hw: pointer to the HW structure
1239 * @speed: stores the current speed
1240 * @duplex: stores the current duplex
1242 * This is a wrapper function, if using the serial gigabit media independent
1243 * interface, use PCS to retrieve the link speed and duplex information.
1244 * Otherwise, use the generic function to get the link speed and duplex info.
1246 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1251 if (hw->phy.media_type != e1000_media_type_copper)
1252 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1255 ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1262 * igb_check_for_link_82575 - Check for link
1263 * @hw: pointer to the HW structure
1265 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1266 * use the generic interface for determining link.
1268 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1273 if (hw->phy.media_type != e1000_media_type_copper) {
1274 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1276 /* Use this flag to determine if link needs to be checked or
1277 * not. If we have link clear the flag so that we do not
1278 * continue to check for link.
1280 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1282 /* Configure Flow Control now that Auto-Neg has completed.
1283 * First, we need to restore the desired flow control
1284 * settings because we may have had to re-autoneg with a
1285 * different link partner.
1287 ret_val = igb_config_fc_after_link_up(hw);
1289 hw_dbg("Error configuring flow control\n");
1291 ret_val = igb_check_for_copper_link(hw);
1298 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1299 * @hw: pointer to the HW structure
1301 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1306 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1307 !igb_sgmii_active_82575(hw))
1310 /* Enable PCS to turn on link */
1311 reg = rd32(E1000_PCS_CFG0);
1312 reg |= E1000_PCS_CFG_PCS_EN;
1313 wr32(E1000_PCS_CFG0, reg);
1315 /* Power up the laser */
1316 reg = rd32(E1000_CTRL_EXT);
1317 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1318 wr32(E1000_CTRL_EXT, reg);
1320 /* flush the write to verify completion */
1326 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1327 * @hw: pointer to the HW structure
1328 * @speed: stores the current speed
1329 * @duplex: stores the current duplex
1331 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1332 * duplex, then store the values in the pointers provided.
1334 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1337 struct e1000_mac_info *mac = &hw->mac;
1340 /* Set up defaults for the return values of this function */
1341 mac->serdes_has_link = false;
1345 /* Read the PCS Status register for link state. For non-copper mode,
1346 * the status register is not accurate. The PCS status register is
1349 pcs = rd32(E1000_PCS_LSTAT);
1351 /* The link up bit determines when link is up on autoneg. The sync ok
1352 * gets set once both sides sync up and agree upon link. Stable link
1353 * can be determined by checking for both link up and link sync ok
1355 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1356 mac->serdes_has_link = true;
1358 /* Detect and store PCS speed */
1359 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1360 *speed = SPEED_1000;
1361 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1366 /* Detect and store PCS duplex */
1367 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1368 *duplex = FULL_DUPLEX;
1370 *duplex = HALF_DUPLEX;
1372 /* Check if it is an I354 2.5Gb backplane connection. */
1373 if (mac->type == e1000_i354) {
1374 status = rd32(E1000_STATUS);
1375 if ((status & E1000_STATUS_2P5_SKU) &&
1376 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1377 *speed = SPEED_2500;
1378 *duplex = FULL_DUPLEX;
1379 hw_dbg("2500 Mbs, ");
1380 hw_dbg("Full Duplex\n");
1390 * igb_shutdown_serdes_link_82575 - Remove link during power down
1391 * @hw: pointer to the HW structure
1393 * In the case of fiber serdes, shut down optics and PCS on driver unload
1394 * when management pass thru is not enabled.
1396 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1400 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1401 igb_sgmii_active_82575(hw))
1404 if (!igb_enable_mng_pass_thru(hw)) {
1405 /* Disable PCS to turn off link */
1406 reg = rd32(E1000_PCS_CFG0);
1407 reg &= ~E1000_PCS_CFG_PCS_EN;
1408 wr32(E1000_PCS_CFG0, reg);
1410 /* shutdown the laser */
1411 reg = rd32(E1000_CTRL_EXT);
1412 reg |= E1000_CTRL_EXT_SDP3_DATA;
1413 wr32(E1000_CTRL_EXT, reg);
1415 /* flush the write to verify completion */
1422 * igb_reset_hw_82575 - Reset hardware
1423 * @hw: pointer to the HW structure
1425 * This resets the hardware into a known state. This is a
1426 * function pointer entry point called by the api module.
1428 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1433 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1434 * on the last TLP read/write transaction when MAC is reset.
1436 ret_val = igb_disable_pcie_master(hw);
1438 hw_dbg("PCI-E Master disable polling has failed.\n");
1440 /* set the completion timeout for interface */
1441 ret_val = igb_set_pcie_completion_timeout(hw);
1443 hw_dbg("PCI-E Set completion timeout has failed.\n");
1446 hw_dbg("Masking off all interrupts\n");
1447 wr32(E1000_IMC, 0xffffffff);
1449 wr32(E1000_RCTL, 0);
1450 wr32(E1000_TCTL, E1000_TCTL_PSP);
1455 ctrl = rd32(E1000_CTRL);
1457 hw_dbg("Issuing a global reset to MAC\n");
1458 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1460 ret_val = igb_get_auto_rd_done(hw);
1462 /* When auto config read does not complete, do not
1463 * return with an error. This can happen in situations
1464 * where there is no eeprom and prevents getting link.
1466 hw_dbg("Auto Read Done did not complete\n");
1469 /* If EEPROM is not present, run manual init scripts */
1470 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1471 igb_reset_init_script_82575(hw);
1473 /* Clear any pending interrupt events. */
1474 wr32(E1000_IMC, 0xffffffff);
1477 /* Install any alternate MAC address into RAR0 */
1478 ret_val = igb_check_alt_mac_addr(hw);
1484 * igb_init_hw_82575 - Initialize hardware
1485 * @hw: pointer to the HW structure
1487 * This inits the hardware readying it for operation.
1489 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1491 struct e1000_mac_info *mac = &hw->mac;
1493 u16 i, rar_count = mac->rar_entry_count;
1495 /* Initialize identification LED */
1496 ret_val = igb_id_led_init(hw);
1498 hw_dbg("Error initializing identification LED\n");
1499 /* This is not fatal and we should not stop init due to this */
1502 /* Disabling VLAN filtering */
1503 hw_dbg("Initializing the IEEE VLAN\n");
1504 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
1505 igb_clear_vfta_i350(hw);
1509 /* Setup the receive address */
1510 igb_init_rx_addrs(hw, rar_count);
1512 /* Zero out the Multicast HASH table */
1513 hw_dbg("Zeroing the MTA\n");
1514 for (i = 0; i < mac->mta_reg_count; i++)
1515 array_wr32(E1000_MTA, i, 0);
1517 /* Zero out the Unicast HASH table */
1518 hw_dbg("Zeroing the UTA\n");
1519 for (i = 0; i < mac->uta_reg_count; i++)
1520 array_wr32(E1000_UTA, i, 0);
1522 /* Setup link and flow control */
1523 ret_val = igb_setup_link(hw);
1525 /* Clear all of the statistics registers (clear on read). It is
1526 * important that we do this after we have tried to establish link
1527 * because the symbol error count will increment wildly if there
1530 igb_clear_hw_cntrs_82575(hw);
1535 * igb_setup_copper_link_82575 - Configure copper link settings
1536 * @hw: pointer to the HW structure
1538 * Configures the link for auto-neg or forced speed and duplex. Then we check
1539 * for link, once link is established calls to configure collision distance
1540 * and flow control are called.
1542 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1548 ctrl = rd32(E1000_CTRL);
1549 ctrl |= E1000_CTRL_SLU;
1550 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1551 wr32(E1000_CTRL, ctrl);
1553 /* Clear Go Link Disconnect bit on supported devices */
1554 switch (hw->mac.type) {
1559 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1560 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1561 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1567 ret_val = igb_setup_serdes_link_82575(hw);
1571 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1572 /* allow time for SFP cage time to power up phy */
1575 ret_val = hw->phy.ops.reset(hw);
1577 hw_dbg("Error resetting the PHY.\n");
1581 switch (hw->phy.type) {
1582 case e1000_phy_i210:
1584 switch (hw->phy.id) {
1585 case I347AT4_E_PHY_ID:
1586 case M88E1112_E_PHY_ID:
1587 case M88E1543_E_PHY_ID:
1589 ret_val = igb_copper_link_setup_m88_gen2(hw);
1592 ret_val = igb_copper_link_setup_m88(hw);
1596 case e1000_phy_igp_3:
1597 ret_val = igb_copper_link_setup_igp(hw);
1599 case e1000_phy_82580:
1600 ret_val = igb_copper_link_setup_82580(hw);
1603 ret_val = -E1000_ERR_PHY;
1610 ret_val = igb_setup_copper_link(hw);
1616 * igb_setup_serdes_link_82575 - Setup link for serdes
1617 * @hw: pointer to the HW structure
1619 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1620 * used on copper connections where the serialized gigabit media independent
1621 * interface (sgmii), or serdes fiber is being used. Configures the link
1622 * for auto-negotiation or forces speed/duplex.
1624 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1626 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1628 s32 ret_val = E1000_SUCCESS;
1631 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1632 !igb_sgmii_active_82575(hw))
1636 /* On the 82575, SerDes loopback mode persists until it is
1637 * explicitly turned off or a power cycle is performed. A read to
1638 * the register does not indicate its status. Therefore, we ensure
1639 * loopback mode is disabled during initialization.
1641 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1643 /* power on the sfp cage if present and turn on I2C */
1644 ctrl_ext = rd32(E1000_CTRL_EXT);
1645 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1646 ctrl_ext |= E1000_CTRL_I2C_ENA;
1647 wr32(E1000_CTRL_EXT, ctrl_ext);
1649 ctrl_reg = rd32(E1000_CTRL);
1650 ctrl_reg |= E1000_CTRL_SLU;
1652 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1653 /* set both sw defined pins */
1654 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1656 /* Set switch control to serdes energy detect */
1657 reg = rd32(E1000_CONNSW);
1658 reg |= E1000_CONNSW_ENRGSRC;
1659 wr32(E1000_CONNSW, reg);
1662 reg = rd32(E1000_PCS_LCTL);
1664 /* default pcs_autoneg to the same setting as mac autoneg */
1665 pcs_autoneg = hw->mac.autoneg;
1667 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1668 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1669 /* sgmii mode lets the phy handle forcing speed/duplex */
1671 /* autoneg time out should be disabled for SGMII mode */
1672 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1674 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1675 /* disable PCS autoneg and support parallel detect only */
1676 pcs_autoneg = false;
1678 if (hw->mac.type == e1000_82575 ||
1679 hw->mac.type == e1000_82576) {
1680 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1682 printk(KERN_DEBUG "NVM Read Error\n\n");
1686 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1687 pcs_autoneg = false;
1690 /* non-SGMII modes only supports a speed of 1000/Full for the
1691 * link so it is best to just force the MAC and let the pcs
1692 * link either autoneg or be forced to 1000/Full
1694 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1695 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1697 /* set speed of 1000/Full if speed/duplex is forced */
1698 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1702 wr32(E1000_CTRL, ctrl_reg);
1704 /* New SerDes mode allows for forcing speed or autonegotiating speed
1705 * at 1gb. Autoneg should be default set by most drivers. This is the
1706 * mode that will be compatible with older link partners and switches.
1707 * However, both are supported by the hardware and some drivers/tools.
1709 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1710 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1713 /* Set PCS register for autoneg */
1714 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1715 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1717 /* Disable force flow control for autoneg */
1718 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1720 /* Configure flow control advertisement for autoneg */
1721 anadv_reg = rd32(E1000_PCS_ANADV);
1722 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1723 switch (hw->fc.requested_mode) {
1725 case e1000_fc_rx_pause:
1726 anadv_reg |= E1000_TXCW_ASM_DIR;
1727 anadv_reg |= E1000_TXCW_PAUSE;
1729 case e1000_fc_tx_pause:
1730 anadv_reg |= E1000_TXCW_ASM_DIR;
1735 wr32(E1000_PCS_ANADV, anadv_reg);
1737 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1739 /* Set PCS register for forced link */
1740 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1742 /* Force flow control for forced link */
1743 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1745 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1748 wr32(E1000_PCS_LCTL, reg);
1750 if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1751 igb_force_mac_fc(hw);
1757 * igb_sgmii_active_82575 - Return sgmii state
1758 * @hw: pointer to the HW structure
1760 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1761 * which can be enabled for use in the embedded applications. Simply
1762 * return the current state of the sgmii interface.
1764 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1766 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1767 return dev_spec->sgmii_active;
1771 * igb_reset_init_script_82575 - Inits HW defaults after reset
1772 * @hw: pointer to the HW structure
1774 * Inits recommended HW defaults after a reset when there is no EEPROM
1775 * detected. This is only for the 82575.
1777 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1779 if (hw->mac.type == e1000_82575) {
1780 hw_dbg("Running reset init script for 82575\n");
1781 /* SerDes configuration via SERDESCTRL */
1782 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1783 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1784 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1785 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1787 /* CCM configuration via CCMCTL register */
1788 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1789 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1791 /* PCIe lanes configuration */
1792 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1793 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1794 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1795 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1797 /* PCIe PLL Configuration */
1798 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1799 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1800 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1807 * igb_read_mac_addr_82575 - Read device MAC address
1808 * @hw: pointer to the HW structure
1810 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1814 /* If there's an alternate MAC address place it in RAR0
1815 * so that it will override the Si installed default perm
1818 ret_val = igb_check_alt_mac_addr(hw);
1822 ret_val = igb_read_mac_addr(hw);
1829 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1830 * @hw: pointer to the HW structure
1832 * In the case of a PHY power down to save power, or to turn off link during a
1833 * driver unload, or wake on lan is not enabled, remove the link.
1835 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1837 /* If the management interface is not enabled, then power down */
1838 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1839 igb_power_down_phy_copper(hw);
1843 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1844 * @hw: pointer to the HW structure
1846 * Clears the hardware counters by reading the counter registers.
1848 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1850 igb_clear_hw_cntrs_base(hw);
1856 rd32(E1000_PRC1023);
1857 rd32(E1000_PRC1522);
1862 rd32(E1000_PTC1023);
1863 rd32(E1000_PTC1522);
1865 rd32(E1000_ALGNERRC);
1868 rd32(E1000_CEXTERR);
1879 rd32(E1000_ICRXPTC);
1880 rd32(E1000_ICRXATC);
1881 rd32(E1000_ICTXPTC);
1882 rd32(E1000_ICTXATC);
1883 rd32(E1000_ICTXQEC);
1884 rd32(E1000_ICTXQMTC);
1885 rd32(E1000_ICRXDMTC);
1892 rd32(E1000_HTCBDPC);
1897 rd32(E1000_LENERRS);
1899 /* This register should not be read in copper configurations */
1900 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1901 igb_sgmii_active_82575(hw))
1906 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1907 * @hw: pointer to the HW structure
1909 * After rx enable if managability is enabled then there is likely some
1910 * bad data at the start of the fifo and possibly in the DMA fifo. This
1911 * function clears the fifos and flushes any packets that came in as rx was
1914 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1916 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1919 if (hw->mac.type != e1000_82575 ||
1920 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1923 /* Disable all RX queues */
1924 for (i = 0; i < 4; i++) {
1925 rxdctl[i] = rd32(E1000_RXDCTL(i));
1926 wr32(E1000_RXDCTL(i),
1927 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1929 /* Poll all queues to verify they have shut down */
1930 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1933 for (i = 0; i < 4; i++)
1934 rx_enabled |= rd32(E1000_RXDCTL(i));
1935 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1940 hw_dbg("Queue disable timed out after 10ms\n");
1942 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1943 * incoming packets are rejected. Set enable and wait 2ms so that
1944 * any packet that was coming in as RCTL.EN was set is flushed
1946 rfctl = rd32(E1000_RFCTL);
1947 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1949 rlpml = rd32(E1000_RLPML);
1950 wr32(E1000_RLPML, 0);
1952 rctl = rd32(E1000_RCTL);
1953 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1954 temp_rctl |= E1000_RCTL_LPE;
1956 wr32(E1000_RCTL, temp_rctl);
1957 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1961 /* Enable RX queues that were previously enabled and restore our
1964 for (i = 0; i < 4; i++)
1965 wr32(E1000_RXDCTL(i), rxdctl[i]);
1966 wr32(E1000_RCTL, rctl);
1969 wr32(E1000_RLPML, rlpml);
1970 wr32(E1000_RFCTL, rfctl);
1972 /* Flush receive errors generated by workaround */
1979 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1980 * @hw: pointer to the HW structure
1982 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1983 * however the hardware default for these parts is 500us to 1ms which is less
1984 * than the 10ms recommended by the pci-e spec. To address this we need to
1985 * increase the value to either 10ms to 200ms for capability version 1 config,
1986 * or 16ms to 55ms for version 2.
1988 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1990 u32 gcr = rd32(E1000_GCR);
1994 /* only take action if timeout value is defaulted to 0 */
1995 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1998 /* if capabilities version is type 1 we can write the
1999 * timeout of 10ms to 200ms through the GCR register
2001 if (!(gcr & E1000_GCR_CAP_VER2)) {
2002 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2006 /* for version 2 capabilities we need to write the config space
2007 * directly in order to set the completion timeout value for
2010 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2015 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2017 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2020 /* disable completion timeout resend */
2021 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2023 wr32(E1000_GCR, gcr);
2028 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2029 * @hw: pointer to the hardware struct
2030 * @enable: state to enter, either enabled or disabled
2031 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2033 * enables/disables L2 switch anti-spoofing functionality.
2035 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2037 u32 reg_val, reg_offset;
2039 switch (hw->mac.type) {
2041 reg_offset = E1000_DTXSWC;
2045 reg_offset = E1000_TXSWC;
2051 reg_val = rd32(reg_offset);
2053 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2054 E1000_DTXSWC_VLAN_SPOOF_MASK);
2055 /* The PF can spoof - it has to in order to
2056 * support emulation mode NICs
2058 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2060 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2061 E1000_DTXSWC_VLAN_SPOOF_MASK);
2063 wr32(reg_offset, reg_val);
2067 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2068 * @hw: pointer to the hardware struct
2069 * @enable: state to enter, either enabled or disabled
2071 * enables/disables L2 switch loopback functionality.
2073 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2077 switch (hw->mac.type) {
2079 dtxswc = rd32(E1000_DTXSWC);
2081 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2083 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2084 wr32(E1000_DTXSWC, dtxswc);
2088 dtxswc = rd32(E1000_TXSWC);
2090 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2092 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2093 wr32(E1000_TXSWC, dtxswc);
2096 /* Currently no other hardware supports loopback */
2103 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
2104 * @hw: pointer to the hardware struct
2105 * @enable: state to enter, either enabled or disabled
2107 * enables/disables replication of packets across multiple pools.
2109 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2111 u32 vt_ctl = rd32(E1000_VT_CTL);
2114 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2116 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2118 wr32(E1000_VT_CTL, vt_ctl);
2122 * igb_read_phy_reg_82580 - Read 82580 MDI control register
2123 * @hw: pointer to the HW structure
2124 * @offset: register offset to be read
2125 * @data: pointer to the read data
2127 * Reads the MDI control register in the PHY at offset and stores the
2128 * information read to data.
2130 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2134 ret_val = hw->phy.ops.acquire(hw);
2138 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2140 hw->phy.ops.release(hw);
2147 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2148 * @hw: pointer to the HW structure
2149 * @offset: register offset to write to
2150 * @data: data to write to register at offset
2152 * Writes data to MDI control register in the PHY at offset.
2154 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2159 ret_val = hw->phy.ops.acquire(hw);
2163 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2165 hw->phy.ops.release(hw);
2172 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2173 * @hw: pointer to the HW structure
2175 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2176 * the values found in the EEPROM. This addresses an issue in which these
2177 * bits are not restored from EEPROM after reset.
2179 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2185 if (hw->mac.type != e1000_82580)
2187 if (!igb_sgmii_active_82575(hw))
2190 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2191 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2194 hw_dbg("NVM Read Error\n");
2198 mdicnfg = rd32(E1000_MDICNFG);
2199 if (nvm_data & NVM_WORD24_EXT_MDIO)
2200 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2201 if (nvm_data & NVM_WORD24_COM_MDIO)
2202 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2203 wr32(E1000_MDICNFG, mdicnfg);
2209 * igb_reset_hw_82580 - Reset hardware
2210 * @hw: pointer to the HW structure
2212 * This resets function or entire device (all ports, etc.)
2215 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2218 /* BH SW mailbox bit in SW_FW_SYNC */
2219 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2221 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2223 hw->dev_spec._82575.global_device_reset = false;
2225 /* due to hw errata, global device reset doesn't always
2228 if (hw->mac.type == e1000_82580)
2229 global_device_reset = false;
2231 /* Get current control state. */
2232 ctrl = rd32(E1000_CTRL);
2234 /* Prevent the PCI-E bus from sticking if there is no TLP connection
2235 * on the last TLP read/write transaction when MAC is reset.
2237 ret_val = igb_disable_pcie_master(hw);
2239 hw_dbg("PCI-E Master disable polling has failed.\n");
2241 hw_dbg("Masking off all interrupts\n");
2242 wr32(E1000_IMC, 0xffffffff);
2243 wr32(E1000_RCTL, 0);
2244 wr32(E1000_TCTL, E1000_TCTL_PSP);
2249 /* Determine whether or not a global dev reset is requested */
2250 if (global_device_reset &&
2251 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2252 global_device_reset = false;
2254 if (global_device_reset &&
2255 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2256 ctrl |= E1000_CTRL_DEV_RST;
2258 ctrl |= E1000_CTRL_RST;
2260 wr32(E1000_CTRL, ctrl);
2263 /* Add delay to insure DEV_RST has time to complete */
2264 if (global_device_reset)
2267 ret_val = igb_get_auto_rd_done(hw);
2269 /* When auto config read does not complete, do not
2270 * return with an error. This can happen in situations
2271 * where there is no eeprom and prevents getting link.
2273 hw_dbg("Auto Read Done did not complete\n");
2276 /* clear global device reset status bit */
2277 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2279 /* Clear any pending interrupt events. */
2280 wr32(E1000_IMC, 0xffffffff);
2283 ret_val = igb_reset_mdicnfg_82580(hw);
2285 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2287 /* Install any alternate MAC address into RAR0 */
2288 ret_val = igb_check_alt_mac_addr(hw);
2290 /* Release semaphore */
2291 if (global_device_reset)
2292 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2298 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2299 * @data: data received by reading RXPBS register
2301 * The 82580 uses a table based approach for packet buffer allocation sizes.
2302 * This function converts the retrieved value into the correct table value
2303 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2304 * 0x0 36 72 144 1 2 4 8 16
2305 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2307 u16 igb_rxpbs_adjust_82580(u32 data)
2311 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2312 ret_val = e1000_82580_rxpbs_table[data];
2318 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2320 * @hw: pointer to the HW structure
2321 * @offset: offset in words of the checksum protected region
2323 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2324 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2326 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2333 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2334 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2336 hw_dbg("NVM Read Error\n");
2339 checksum += nvm_data;
2342 if (checksum != (u16) NVM_SUM) {
2343 hw_dbg("NVM Checksum Invalid\n");
2344 ret_val = -E1000_ERR_NVM;
2353 * igb_update_nvm_checksum_with_offset - Update EEPROM
2355 * @hw: pointer to the HW structure
2356 * @offset: offset in words of the checksum protected region
2358 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2359 * up to the checksum. Then calculates the EEPROM checksum and writes the
2360 * value to the EEPROM.
2362 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2368 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2369 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2371 hw_dbg("NVM Read Error while updating checksum.\n");
2374 checksum += nvm_data;
2376 checksum = (u16) NVM_SUM - checksum;
2377 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2380 hw_dbg("NVM Write Error while updating checksum.\n");
2387 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2388 * @hw: pointer to the HW structure
2390 * Calculates the EEPROM section checksum by reading/adding each word of
2391 * the EEPROM and then verifies that the sum of the EEPROM is
2394 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2397 u16 eeprom_regions_count = 1;
2401 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2403 hw_dbg("NVM Read Error\n");
2407 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2408 /* if checksums compatibility bit is set validate checksums
2411 eeprom_regions_count = 4;
2414 for (j = 0; j < eeprom_regions_count; j++) {
2415 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2416 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2427 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2428 * @hw: pointer to the HW structure
2430 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2431 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2432 * checksum and writes the value to the EEPROM.
2434 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2440 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2442 hw_dbg("NVM Read Error while updating checksum"
2443 " compatibility bit.\n");
2447 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2448 /* set compatibility bit to validate checksums appropriately */
2449 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2450 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2453 hw_dbg("NVM Write Error while updating checksum"
2454 " compatibility bit.\n");
2459 for (j = 0; j < 4; j++) {
2460 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2461 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2471 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2472 * @hw: pointer to the HW structure
2474 * Calculates the EEPROM section checksum by reading/adding each word of
2475 * the EEPROM and then verifies that the sum of the EEPROM is
2478 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2484 for (j = 0; j < 4; j++) {
2485 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2486 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2497 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2498 * @hw: pointer to the HW structure
2500 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2501 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2502 * checksum and writes the value to the EEPROM.
2504 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2510 for (j = 0; j < 4; j++) {
2511 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2512 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2522 * __igb_access_emi_reg - Read/write EMI register
2523 * @hw: pointer to the HW structure
2524 * @addr: EMI address to program
2525 * @data: pointer to value to read/write from/to the EMI address
2526 * @read: boolean flag to indicate read or write
2528 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2529 u16 *data, bool read)
2531 s32 ret_val = E1000_SUCCESS;
2533 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2538 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2540 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2546 * igb_read_emi_reg - Read Extended Management Interface register
2547 * @hw: pointer to the HW structure
2548 * @addr: EMI address to program
2549 * @data: value to be read from the EMI address
2551 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2553 return __igb_access_emi_reg(hw, addr, data, true);
2557 * igb_set_eee_i350 - Enable/disable EEE support
2558 * @hw: pointer to the HW structure
2560 * Enable/disable EEE based on setting in dev_spec structure.
2563 s32 igb_set_eee_i350(struct e1000_hw *hw)
2568 if ((hw->mac.type < e1000_i350) ||
2569 (hw->phy.media_type != e1000_media_type_copper))
2571 ipcnfg = rd32(E1000_IPCNFG);
2572 eeer = rd32(E1000_EEER);
2574 /* enable or disable per user setting */
2575 if (!(hw->dev_spec._82575.eee_disable)) {
2576 u32 eee_su = rd32(E1000_EEE_SU);
2578 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2579 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2582 /* This bit should not be set in normal operation. */
2583 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2584 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2587 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2588 E1000_IPCNFG_EEE_100M_AN);
2589 eeer &= ~(E1000_EEER_TX_LPI_EN |
2590 E1000_EEER_RX_LPI_EN |
2593 wr32(E1000_IPCNFG, ipcnfg);
2594 wr32(E1000_EEER, eeer);
2603 * igb_set_eee_i354 - Enable/disable EEE support
2604 * @hw: pointer to the HW structure
2606 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2609 s32 igb_set_eee_i354(struct e1000_hw *hw)
2611 struct e1000_phy_info *phy = &hw->phy;
2615 if ((hw->phy.media_type != e1000_media_type_copper) ||
2616 (phy->id != M88E1543_E_PHY_ID))
2619 if (!hw->dev_spec._82575.eee_disable) {
2620 /* Switch to PHY page 18. */
2621 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2625 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2630 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2631 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2636 /* Return the PHY to page 0. */
2637 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2641 /* Turn on EEE advertisement. */
2642 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2643 E1000_EEE_ADV_DEV_I354,
2648 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2649 E1000_EEE_ADV_1000_SUPPORTED;
2650 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2651 E1000_EEE_ADV_DEV_I354,
2654 /* Turn off EEE advertisement. */
2655 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2656 E1000_EEE_ADV_DEV_I354,
2661 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2662 E1000_EEE_ADV_1000_SUPPORTED);
2663 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2664 E1000_EEE_ADV_DEV_I354,
2673 * igb_get_eee_status_i354 - Get EEE status
2674 * @hw: pointer to the HW structure
2675 * @status: EEE status
2677 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2680 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2682 struct e1000_phy_info *phy = &hw->phy;
2686 /* Check if EEE is supported on this device. */
2687 if ((hw->phy.media_type != e1000_media_type_copper) ||
2688 (phy->id != M88E1543_E_PHY_ID))
2691 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2692 E1000_PCS_STATUS_DEV_I354,
2697 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2698 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2704 static const u8 e1000_emc_temp_data[4] = {
2705 E1000_EMC_INTERNAL_DATA,
2706 E1000_EMC_DIODE1_DATA,
2707 E1000_EMC_DIODE2_DATA,
2708 E1000_EMC_DIODE3_DATA
2710 static const u8 e1000_emc_therm_limit[4] = {
2711 E1000_EMC_INTERNAL_THERM_LIMIT,
2712 E1000_EMC_DIODE1_THERM_LIMIT,
2713 E1000_EMC_DIODE2_THERM_LIMIT,
2714 E1000_EMC_DIODE3_THERM_LIMIT
2718 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2719 * @hw: pointer to hardware structure
2721 * Updates the temperatures in mac.thermal_sensor_data
2723 s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2725 s32 status = E1000_SUCCESS;
2733 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2735 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2736 return E1000_NOT_IMPLEMENTED;
2738 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2740 /* Return the internal sensor only if ETS is unsupported */
2741 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2742 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2745 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2746 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2747 != NVM_ETS_TYPE_EMC)
2748 return E1000_NOT_IMPLEMENTED;
2750 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2751 if (num_sensors > E1000_MAX_SENSORS)
2752 num_sensors = E1000_MAX_SENSORS;
2754 for (i = 1; i < num_sensors; i++) {
2755 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2756 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2757 NVM_ETS_DATA_INDEX_SHIFT);
2758 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2759 NVM_ETS_DATA_LOC_SHIFT);
2761 if (sensor_location != 0)
2762 hw->phy.ops.read_i2c_byte(hw,
2763 e1000_emc_temp_data[sensor_index],
2764 E1000_I2C_THERMAL_SENSOR_ADDR,
2765 &data->sensor[i].temp);
2771 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2772 * @hw: pointer to hardware structure
2774 * Sets the thermal sensor thresholds according to the NVM map
2775 * and save off the threshold and location values into mac.thermal_sensor_data
2777 s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2779 s32 status = E1000_SUCCESS;
2783 u8 low_thresh_delta;
2789 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2791 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2792 return E1000_NOT_IMPLEMENTED;
2794 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2796 data->sensor[0].location = 0x1;
2797 data->sensor[0].caution_thresh =
2798 (rd32(E1000_THHIGHTC) & 0xFF);
2799 data->sensor[0].max_op_thresh =
2800 (rd32(E1000_THLOWTC) & 0xFF);
2802 /* Return the internal sensor only if ETS is unsupported */
2803 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2804 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2807 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2808 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2809 != NVM_ETS_TYPE_EMC)
2810 return E1000_NOT_IMPLEMENTED;
2812 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2813 NVM_ETS_LTHRES_DELTA_SHIFT);
2814 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2816 for (i = 1; i <= num_sensors; i++) {
2817 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2818 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2819 NVM_ETS_DATA_INDEX_SHIFT);
2820 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2821 NVM_ETS_DATA_LOC_SHIFT);
2822 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2824 hw->phy.ops.write_i2c_byte(hw,
2825 e1000_emc_therm_limit[sensor_index],
2826 E1000_I2C_THERMAL_SENSOR_ADDR,
2829 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2830 data->sensor[i].location = sensor_location;
2831 data->sensor[i].caution_thresh = therm_limit;
2832 data->sensor[i].max_op_thresh = therm_limit -
2839 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2840 .init_hw = igb_init_hw_82575,
2841 .check_for_link = igb_check_for_link_82575,
2842 .rar_set = igb_rar_set,
2843 .read_mac_addr = igb_read_mac_addr_82575,
2844 .get_speed_and_duplex = igb_get_link_up_info_82575,
2845 #ifdef CONFIG_IGB_HWMON
2846 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2847 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2851 static struct e1000_phy_operations e1000_phy_ops_82575 = {
2852 .acquire = igb_acquire_phy_82575,
2853 .get_cfg_done = igb_get_cfg_done_82575,
2854 .release = igb_release_phy_82575,
2855 .write_i2c_byte = igb_write_i2c_byte,
2856 .read_i2c_byte = igb_read_i2c_byte,
2859 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2860 .acquire = igb_acquire_nvm_82575,
2861 .read = igb_read_nvm_eerd,
2862 .release = igb_release_nvm_82575,
2863 .write = igb_write_nvm_spi,
2866 const struct e1000_info e1000_82575_info = {
2867 .get_invariants = igb_get_invariants_82575,
2868 .mac_ops = &e1000_mac_ops_82575,
2869 .phy_ops = &e1000_phy_ops_82575,
2870 .nvm_ops = &e1000_nvm_ops_82575,