1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 ******************************************************************************/
28 #include "i40e_status.h"
29 #include "i40e_type.h"
30 #include "i40e_register.h"
31 #include "i40e_adminq.h"
32 #include "i40e_prototype.h"
35 * i40e_adminq_init_regs - Initialize AdminQ registers
36 * @hw: pointer to the hardware structure
38 * This assumes the alloc_asq and alloc_arq functions have already been called
40 static void i40e_adminq_init_regs(struct i40e_hw *hw)
42 /* set head and tail registers in our local struct */
43 if (hw->mac.type == I40E_MAC_VF) {
44 hw->aq.asq.tail = I40E_VF_ATQT1;
45 hw->aq.asq.head = I40E_VF_ATQH1;
46 hw->aq.asq.len = I40E_VF_ATQLEN1;
47 hw->aq.arq.tail = I40E_VF_ARQT1;
48 hw->aq.arq.head = I40E_VF_ARQH1;
49 hw->aq.arq.len = I40E_VF_ARQLEN1;
51 hw->aq.asq.tail = I40E_PF_ATQT;
52 hw->aq.asq.head = I40E_PF_ATQH;
53 hw->aq.asq.len = I40E_PF_ATQLEN;
54 hw->aq.arq.tail = I40E_PF_ARQT;
55 hw->aq.arq.head = I40E_PF_ARQH;
56 hw->aq.arq.len = I40E_PF_ARQLEN;
61 * i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings
62 * @hw: pointer to the hardware structure
64 static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
67 struct i40e_virt_mem mem;
69 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq_mem,
71 (hw->aq.num_asq_entries *
72 sizeof(struct i40e_aq_desc)),
73 I40E_ADMINQ_DESC_ALIGNMENT);
77 hw->aq.asq.desc = hw->aq.asq_mem.va;
78 hw->aq.asq.dma_addr = hw->aq.asq_mem.pa;
80 ret_code = i40e_allocate_virt_mem(hw, &mem,
81 (hw->aq.num_asq_entries *
82 sizeof(struct i40e_asq_cmd_details)));
84 i40e_free_dma_mem(hw, &hw->aq.asq_mem);
85 hw->aq.asq_mem.va = NULL;
86 hw->aq.asq_mem.pa = 0;
90 hw->aq.asq.details = mem.va;
96 * i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings
97 * @hw: pointer to the hardware structure
99 static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
101 i40e_status ret_code;
103 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq_mem,
105 (hw->aq.num_arq_entries *
106 sizeof(struct i40e_aq_desc)),
107 I40E_ADMINQ_DESC_ALIGNMENT);
111 hw->aq.arq.desc = hw->aq.arq_mem.va;
112 hw->aq.arq.dma_addr = hw->aq.arq_mem.pa;
118 * i40e_free_adminq_asq - Free Admin Queue send rings
119 * @hw: pointer to the hardware structure
121 * This assumes the posted send buffers have already been cleaned
124 static void i40e_free_adminq_asq(struct i40e_hw *hw)
126 struct i40e_virt_mem mem;
128 i40e_free_dma_mem(hw, &hw->aq.asq_mem);
129 hw->aq.asq_mem.va = NULL;
130 hw->aq.asq_mem.pa = 0;
131 mem.va = hw->aq.asq.details;
132 i40e_free_virt_mem(hw, &mem);
133 hw->aq.asq.details = NULL;
137 * i40e_free_adminq_arq - Free Admin Queue receive rings
138 * @hw: pointer to the hardware structure
140 * This assumes the posted receive buffers have already been cleaned
143 static void i40e_free_adminq_arq(struct i40e_hw *hw)
145 i40e_free_dma_mem(hw, &hw->aq.arq_mem);
146 hw->aq.arq_mem.va = NULL;
147 hw->aq.arq_mem.pa = 0;
151 * i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
152 * @hw: pointer to the hardware structure
154 static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw)
156 i40e_status ret_code;
157 struct i40e_aq_desc *desc;
158 struct i40e_virt_mem mem;
159 struct i40e_dma_mem *bi;
162 /* We'll be allocating the buffer info memory first, then we can
163 * allocate the mapped buffers for the event processing
166 /* buffer_info structures do not need alignment */
167 ret_code = i40e_allocate_virt_mem(hw, &mem, (hw->aq.num_arq_entries *
168 sizeof(struct i40e_dma_mem)));
171 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)mem.va;
173 /* allocate the mapped buffers */
174 for (i = 0; i < hw->aq.num_arq_entries; i++) {
175 bi = &hw->aq.arq.r.arq_bi[i];
176 ret_code = i40e_allocate_dma_mem(hw, bi,
179 I40E_ADMINQ_DESC_ALIGNMENT);
181 goto unwind_alloc_arq_bufs;
183 /* now configure the descriptors for use */
184 desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
186 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
187 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
188 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
190 /* This is in accordance with Admin queue design, there is no
191 * register for buffer size configuration
193 desc->datalen = cpu_to_le16((u16)bi->size);
195 desc->cookie_high = 0;
196 desc->cookie_low = 0;
197 desc->params.external.addr_high =
198 cpu_to_le32(upper_32_bits(bi->pa));
199 desc->params.external.addr_low =
200 cpu_to_le32(lower_32_bits(bi->pa));
201 desc->params.external.param0 = 0;
202 desc->params.external.param1 = 0;
208 unwind_alloc_arq_bufs:
209 /* don't try to free the one that failed... */
212 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
213 mem.va = hw->aq.arq.r.arq_bi;
214 i40e_free_virt_mem(hw, &mem);
220 * i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue
221 * @hw: pointer to the hardware structure
223 static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw)
225 i40e_status ret_code;
226 struct i40e_virt_mem mem;
227 struct i40e_dma_mem *bi;
230 /* No mapped memory needed yet, just the buffer info structures */
231 ret_code = i40e_allocate_virt_mem(hw, &mem, (hw->aq.num_asq_entries *
232 sizeof(struct i40e_dma_mem)));
235 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)mem.va;
237 /* allocate the mapped buffers */
238 for (i = 0; i < hw->aq.num_asq_entries; i++) {
239 bi = &hw->aq.asq.r.asq_bi[i];
240 ret_code = i40e_allocate_dma_mem(hw, bi,
243 I40E_ADMINQ_DESC_ALIGNMENT);
245 goto unwind_alloc_asq_bufs;
250 unwind_alloc_asq_bufs:
251 /* don't try to free the one that failed... */
254 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
255 mem.va = hw->aq.asq.r.asq_bi;
256 i40e_free_virt_mem(hw, &mem);
262 * i40e_free_arq_bufs - Free receive queue buffer info elements
263 * @hw: pointer to the hardware structure
265 static void i40e_free_arq_bufs(struct i40e_hw *hw)
267 struct i40e_virt_mem mem;
270 for (i = 0; i < hw->aq.num_arq_entries; i++)
271 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
273 mem.va = hw->aq.arq.r.arq_bi;
274 i40e_free_virt_mem(hw, &mem);
278 * i40e_free_asq_bufs - Free send queue buffer info elements
279 * @hw: pointer to the hardware structure
281 static void i40e_free_asq_bufs(struct i40e_hw *hw)
283 struct i40e_virt_mem mem;
286 /* only unmap if the address is non-NULL */
287 for (i = 0; i < hw->aq.num_asq_entries; i++)
288 if (hw->aq.asq.r.asq_bi[i].pa)
289 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
291 /* now free the buffer info list */
292 mem.va = hw->aq.asq.r.asq_bi;
293 i40e_free_virt_mem(hw, &mem);
297 * i40e_config_asq_regs - configure ASQ registers
298 * @hw: pointer to the hardware structure
300 * Configure base address and length registers for the transmit queue
302 static void i40e_config_asq_regs(struct i40e_hw *hw)
304 if (hw->mac.type == I40E_MAC_VF) {
305 /* configure the transmit queue */
306 wr32(hw, I40E_VF_ATQBAH1, upper_32_bits(hw->aq.asq.dma_addr));
307 wr32(hw, I40E_VF_ATQBAL1, lower_32_bits(hw->aq.asq.dma_addr));
308 wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries |
309 I40E_VF_ATQLEN1_ATQENABLE_MASK));
311 /* configure the transmit queue */
312 wr32(hw, I40E_PF_ATQBAH, upper_32_bits(hw->aq.asq.dma_addr));
313 wr32(hw, I40E_PF_ATQBAL, lower_32_bits(hw->aq.asq.dma_addr));
314 wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries |
315 I40E_PF_ATQLEN_ATQENABLE_MASK));
320 * i40e_config_arq_regs - ARQ register configuration
321 * @hw: pointer to the hardware structure
323 * Configure base address and length registers for the receive (event queue)
325 static void i40e_config_arq_regs(struct i40e_hw *hw)
327 if (hw->mac.type == I40E_MAC_VF) {
328 /* configure the receive queue */
329 wr32(hw, I40E_VF_ARQBAH1, upper_32_bits(hw->aq.arq.dma_addr));
330 wr32(hw, I40E_VF_ARQBAL1, lower_32_bits(hw->aq.arq.dma_addr));
331 wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries |
332 I40E_VF_ARQLEN1_ARQENABLE_MASK));
334 /* configure the receive queue */
335 wr32(hw, I40E_PF_ARQBAH, upper_32_bits(hw->aq.arq.dma_addr));
336 wr32(hw, I40E_PF_ARQBAL, lower_32_bits(hw->aq.arq.dma_addr));
337 wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries |
338 I40E_PF_ARQLEN_ARQENABLE_MASK));
341 /* Update tail in the HW to post pre-allocated buffers */
342 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
346 * i40e_init_asq - main initialization routine for ASQ
347 * @hw: pointer to the hardware structure
349 * This is the main initialization routine for the Admin Send Queue
350 * Prior to calling this function, drivers *MUST* set the following fields
351 * in the hw->aq structure:
352 * - hw->aq.num_asq_entries
353 * - hw->aq.arq_buf_size
355 * Do *NOT* hold the lock when calling this as the memory allocation routines
356 * called are not going to be atomic context safe
358 static i40e_status i40e_init_asq(struct i40e_hw *hw)
360 i40e_status ret_code = 0;
362 if (hw->aq.asq.count > 0) {
363 /* queue already initialized */
364 ret_code = I40E_ERR_NOT_READY;
365 goto init_adminq_exit;
368 /* verify input for valid configuration */
369 if ((hw->aq.num_asq_entries == 0) ||
370 (hw->aq.asq_buf_size == 0)) {
371 ret_code = I40E_ERR_CONFIG;
372 goto init_adminq_exit;
375 hw->aq.asq.next_to_use = 0;
376 hw->aq.asq.next_to_clean = 0;
377 hw->aq.asq.count = hw->aq.num_asq_entries;
379 /* allocate the ring memory */
380 ret_code = i40e_alloc_adminq_asq_ring(hw);
382 goto init_adminq_exit;
384 /* allocate buffers in the rings */
385 ret_code = i40e_alloc_asq_bufs(hw);
387 goto init_adminq_free_rings;
389 /* initialize base registers */
390 i40e_config_asq_regs(hw);
393 goto init_adminq_exit;
395 init_adminq_free_rings:
396 i40e_free_adminq_asq(hw);
403 * i40e_init_arq - initialize ARQ
404 * @hw: pointer to the hardware structure
406 * The main initialization routine for the Admin Receive (Event) Queue.
407 * Prior to calling this function, drivers *MUST* set the following fields
408 * in the hw->aq structure:
409 * - hw->aq.num_asq_entries
410 * - hw->aq.arq_buf_size
412 * Do *NOT* hold the lock when calling this as the memory allocation routines
413 * called are not going to be atomic context safe
415 static i40e_status i40e_init_arq(struct i40e_hw *hw)
417 i40e_status ret_code = 0;
419 if (hw->aq.arq.count > 0) {
420 /* queue already initialized */
421 ret_code = I40E_ERR_NOT_READY;
422 goto init_adminq_exit;
425 /* verify input for valid configuration */
426 if ((hw->aq.num_arq_entries == 0) ||
427 (hw->aq.arq_buf_size == 0)) {
428 ret_code = I40E_ERR_CONFIG;
429 goto init_adminq_exit;
432 hw->aq.arq.next_to_use = 0;
433 hw->aq.arq.next_to_clean = 0;
434 hw->aq.arq.count = hw->aq.num_arq_entries;
436 /* allocate the ring memory */
437 ret_code = i40e_alloc_adminq_arq_ring(hw);
439 goto init_adminq_exit;
441 /* allocate buffers in the rings */
442 ret_code = i40e_alloc_arq_bufs(hw);
444 goto init_adminq_free_rings;
446 /* initialize base registers */
447 i40e_config_arq_regs(hw);
450 goto init_adminq_exit;
452 init_adminq_free_rings:
453 i40e_free_adminq_arq(hw);
460 * i40e_shutdown_asq - shutdown the ASQ
461 * @hw: pointer to the hardware structure
463 * The main shutdown routine for the Admin Send Queue
465 static i40e_status i40e_shutdown_asq(struct i40e_hw *hw)
467 i40e_status ret_code = 0;
469 if (hw->aq.asq.count == 0)
470 return I40E_ERR_NOT_READY;
472 /* Stop firmware AdminQ processing */
473 wr32(hw, hw->aq.asq.head, 0);
474 wr32(hw, hw->aq.asq.tail, 0);
475 wr32(hw, hw->aq.asq.len, 0);
477 /* make sure lock is available */
478 mutex_lock(&hw->aq.asq_mutex);
480 hw->aq.asq.count = 0; /* to indicate uninitialized queue */
482 /* free ring buffers */
483 i40e_free_asq_bufs(hw);
484 /* free the ring descriptors */
485 i40e_free_adminq_asq(hw);
487 mutex_unlock(&hw->aq.asq_mutex);
493 * i40e_shutdown_arq - shutdown ARQ
494 * @hw: pointer to the hardware structure
496 * The main shutdown routine for the Admin Receive Queue
498 static i40e_status i40e_shutdown_arq(struct i40e_hw *hw)
500 i40e_status ret_code = 0;
502 if (hw->aq.arq.count == 0)
503 return I40E_ERR_NOT_READY;
505 /* Stop firmware AdminQ processing */
506 wr32(hw, hw->aq.arq.head, 0);
507 wr32(hw, hw->aq.arq.tail, 0);
508 wr32(hw, hw->aq.arq.len, 0);
510 /* make sure lock is available */
511 mutex_lock(&hw->aq.arq_mutex);
513 hw->aq.arq.count = 0; /* to indicate uninitialized queue */
515 /* free ring buffers */
516 i40e_free_arq_bufs(hw);
517 /* free the ring descriptors */
518 i40e_free_adminq_arq(hw);
520 mutex_unlock(&hw->aq.arq_mutex);
526 * i40e_init_adminq - main initialization routine for Admin Queue
527 * @hw: pointer to the hardware structure
529 * Prior to calling this function, drivers *MUST* set the following fields
530 * in the hw->aq structure:
531 * - hw->aq.num_asq_entries
532 * - hw->aq.num_arq_entries
533 * - hw->aq.arq_buf_size
534 * - hw->aq.asq_buf_size
536 i40e_status i40e_init_adminq(struct i40e_hw *hw)
538 i40e_status ret_code;
539 u16 eetrack_lo, eetrack_hi;
542 /* verify input for valid configuration */
543 if ((hw->aq.num_arq_entries == 0) ||
544 (hw->aq.num_asq_entries == 0) ||
545 (hw->aq.arq_buf_size == 0) ||
546 (hw->aq.asq_buf_size == 0)) {
547 ret_code = I40E_ERR_CONFIG;
548 goto init_adminq_exit;
551 /* initialize locks */
552 mutex_init(&hw->aq.asq_mutex);
553 mutex_init(&hw->aq.arq_mutex);
555 /* Set up register offsets */
556 i40e_adminq_init_regs(hw);
558 /* allocate the ASQ */
559 ret_code = i40e_init_asq(hw);
561 goto init_adminq_destroy_locks;
563 /* allocate the ARQ */
564 ret_code = i40e_init_arq(hw);
566 goto init_adminq_free_asq;
568 /* There are some cases where the firmware may not be quite ready
569 * for AdminQ operations, so we retry the AdminQ setup a few times
570 * if we see timeouts in this first AQ call.
573 ret_code = i40e_aq_get_firmware_version(hw,
579 if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT)
584 } while (retry < 10);
585 if (ret_code != I40E_SUCCESS)
586 goto init_adminq_free_arq;
588 if (hw->aq.api_maj_ver != I40E_FW_API_VERSION_MAJOR ||
589 hw->aq.api_min_ver != I40E_FW_API_VERSION_MINOR) {
590 ret_code = I40E_ERR_FIRMWARE_API_VERSION;
591 goto init_adminq_free_arq;
593 i40e_read_nvm_word(hw, I40E_SR_NVM_IMAGE_VERSION, &hw->nvm.version);
594 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo);
595 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi);
596 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
598 ret_code = i40e_aq_set_hmc_resource_profile(hw,
599 I40E_HMC_PROFILE_DEFAULT,
605 goto init_adminq_exit;
607 init_adminq_free_arq:
608 i40e_shutdown_arq(hw);
609 init_adminq_free_asq:
610 i40e_shutdown_asq(hw);
611 init_adminq_destroy_locks:
618 * i40e_shutdown_adminq - shutdown routine for the Admin Queue
619 * @hw: pointer to the hardware structure
621 i40e_status i40e_shutdown_adminq(struct i40e_hw *hw)
623 i40e_status ret_code = 0;
625 i40e_shutdown_asq(hw);
626 i40e_shutdown_arq(hw);
628 /* destroy the locks */
634 * i40e_clean_asq - cleans Admin send queue
635 * @asq: pointer to the adminq send ring
637 * returns the number of free desc
639 static u16 i40e_clean_asq(struct i40e_hw *hw)
641 struct i40e_adminq_ring *asq = &(hw->aq.asq);
642 struct i40e_asq_cmd_details *details;
643 u16 ntc = asq->next_to_clean;
644 struct i40e_aq_desc desc_cb;
645 struct i40e_aq_desc *desc;
647 desc = I40E_ADMINQ_DESC(*asq, ntc);
648 details = I40E_ADMINQ_DETAILS(*asq, ntc);
649 while (rd32(hw, hw->aq.asq.head) != ntc) {
650 if (details->callback) {
651 I40E_ADMINQ_CALLBACK cb_func =
652 (I40E_ADMINQ_CALLBACK)details->callback;
654 cb_func(hw, &desc_cb);
656 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
657 memset((void *)details, 0,
658 sizeof(struct i40e_asq_cmd_details));
660 if (ntc == asq->count)
662 desc = I40E_ADMINQ_DESC(*asq, ntc);
663 details = I40E_ADMINQ_DETAILS(*asq, ntc);
666 asq->next_to_clean = ntc;
668 return I40E_DESC_UNUSED(asq);
672 * i40e_asq_done - check if FW has processed the Admin Send Queue
673 * @hw: pointer to the hw struct
675 * Returns true if the firmware has processed all descriptors on the
676 * admin send queue. Returns false if there are still requests pending.
678 bool i40e_asq_done(struct i40e_hw *hw)
680 /* AQ designers suggest use of head for better
681 * timing reliability than DD bit
683 return (rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use);
688 * i40e_asq_send_command - send command to Admin Queue
689 * @hw: pointer to the hw struct
690 * @desc: prefilled descriptor describing the command (non DMA mem)
691 * @buff: buffer to use for indirect commands
692 * @buff_size: size of buffer for indirect commands
693 * @opaque: pointer to info to be used in async cleanup
695 * This is the main send command driver routine for the Admin Queue send
696 * queue. It runs the queue, cleans the queue, etc
698 i40e_status i40e_asq_send_command(struct i40e_hw *hw,
699 struct i40e_aq_desc *desc,
700 void *buff, /* can be NULL */
702 struct i40e_asq_cmd_details *cmd_details)
704 i40e_status status = 0;
705 struct i40e_dma_mem *dma_buff = NULL;
706 struct i40e_asq_cmd_details *details;
707 struct i40e_aq_desc *desc_on_ring;
708 bool cmd_completed = false;
711 if (hw->aq.asq.count == 0) {
712 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
713 "AQTX: Admin queue not initialized.\n");
714 status = I40E_ERR_QUEUE_EMPTY;
715 goto asq_send_command_exit;
718 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
720 *details = *cmd_details;
722 /* If the cmd_details are defined copy the cookie. The
723 * cpu_to_le32 is not needed here because the data is ignored
724 * by the FW, only used by the driver
726 if (details->cookie) {
728 cpu_to_le32(upper_32_bits(details->cookie));
730 cpu_to_le32(lower_32_bits(details->cookie));
733 memset(details, 0, sizeof(struct i40e_asq_cmd_details));
736 /* clear requested flags and then set additional flags if defined */
737 desc->flags &= ~cpu_to_le16(details->flags_dis);
738 desc->flags |= cpu_to_le16(details->flags_ena);
740 mutex_lock(&hw->aq.asq_mutex);
742 if (buff_size > hw->aq.asq_buf_size) {
744 I40E_DEBUG_AQ_MESSAGE,
745 "AQTX: Invalid buffer size: %d.\n",
747 status = I40E_ERR_INVALID_SIZE;
748 goto asq_send_command_error;
751 if (details->postpone && !details->async) {
753 I40E_DEBUG_AQ_MESSAGE,
754 "AQTX: Async flag not set along with postpone flag");
755 status = I40E_ERR_PARAM;
756 goto asq_send_command_error;
759 /* call clean and check queue available function to reclaim the
760 * descriptors that were processed by FW, the function returns the
761 * number of desc available
763 /* the clean function called here could be called in a separate thread
764 * in case of asynchronous completions
766 if (i40e_clean_asq(hw) == 0) {
768 I40E_DEBUG_AQ_MESSAGE,
769 "AQTX: Error queue is full.\n");
770 status = I40E_ERR_ADMIN_QUEUE_FULL;
771 goto asq_send_command_error;
774 /* initialize the temp desc pointer with the right desc */
775 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
777 /* if the desc is available copy the temp desc to the right place */
778 *desc_on_ring = *desc;
780 /* if buff is not NULL assume indirect command */
782 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
783 /* copy the user buff into the respective DMA buff */
784 memcpy(dma_buff->va, buff, buff_size);
785 desc_on_ring->datalen = cpu_to_le16(buff_size);
787 /* Update the address values in the desc with the pa value
788 * for respective buffer
790 desc_on_ring->params.external.addr_high =
791 cpu_to_le32(upper_32_bits(dma_buff->pa));
792 desc_on_ring->params.external.addr_low =
793 cpu_to_le32(lower_32_bits(dma_buff->pa));
797 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff);
798 (hw->aq.asq.next_to_use)++;
799 if (hw->aq.asq.next_to_use == hw->aq.asq.count)
800 hw->aq.asq.next_to_use = 0;
801 if (!details->postpone)
802 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
804 /* if cmd_details are not defined or async flag is not set,
805 * we need to wait for desc write back
807 if (!details->async && !details->postpone) {
812 /* AQ designers suggest use of head for better
813 * timing reliability than DD bit
815 if (i40e_asq_done(hw))
817 /* ugh! delay while spin_lock */
819 total_delay += delay_len;
820 } while (total_delay < I40E_ASQ_CMD_TIMEOUT);
823 /* if ready, copy the desc back to temp */
824 if (i40e_asq_done(hw)) {
825 *desc = *desc_on_ring;
827 memcpy(buff, dma_buff->va, buff_size);
828 retval = le16_to_cpu(desc->retval);
831 I40E_DEBUG_AQ_MESSAGE,
832 "AQTX: Command completed with error 0x%X.\n",
834 /* strip off FW internal code */
837 cmd_completed = true;
838 if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)
841 status = I40E_ERR_ADMIN_QUEUE_ERROR;
842 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
845 /* update the error if time out occurred */
846 if ((!cmd_completed) &&
847 (!details->async && !details->postpone)) {
849 I40E_DEBUG_AQ_MESSAGE,
850 "AQTX: Writeback timeout.\n");
851 status = I40E_ERR_ADMIN_QUEUE_TIMEOUT;
854 asq_send_command_error:
855 mutex_unlock(&hw->aq.asq_mutex);
856 asq_send_command_exit:
861 * i40e_fill_default_direct_cmd_desc - AQ descriptor helper function
862 * @desc: pointer to the temp descriptor (non DMA mem)
863 * @opcode: the opcode can be used to decide which flags to turn off or on
865 * Fill the desc with default values
867 void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
870 /* zero out the desc */
871 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
872 desc->opcode = cpu_to_le16(opcode);
873 desc->flags = cpu_to_le16(I40E_AQ_FLAG_EI | I40E_AQ_FLAG_SI);
877 * i40e_clean_arq_element
878 * @hw: pointer to the hw struct
879 * @e: event info from the receive descriptor, includes any buffers
880 * @pending: number of events that could be left to process
882 * This function cleans one Admin Receive Queue element and returns
883 * the contents through e. It can also return how many events are
884 * left to process through 'pending'
886 i40e_status i40e_clean_arq_element(struct i40e_hw *hw,
887 struct i40e_arq_event_info *e,
890 i40e_status ret_code = 0;
891 u16 ntc = hw->aq.arq.next_to_clean;
892 struct i40e_aq_desc *desc;
893 struct i40e_dma_mem *bi;
899 /* take the lock before we start messing with the ring */
900 mutex_lock(&hw->aq.arq_mutex);
902 /* set next_to_use to head */
903 ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK);
905 /* nothing to do - shouldn't need to update ring's values */
907 I40E_DEBUG_AQ_MESSAGE,
908 "AQRX: Queue is empty.\n");
909 ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;
910 goto clean_arq_element_out;
913 /* now clean the next descriptor */
914 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
917 I40E_DEBUG_AQ_COMMAND,
919 hw->aq.arq.r.arq_bi[desc_idx].va);
921 flags = le16_to_cpu(desc->flags);
922 if (flags & I40E_AQ_FLAG_ERR) {
923 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
924 hw->aq.arq_last_status =
925 (enum i40e_admin_queue_err)le16_to_cpu(desc->retval);
927 I40E_DEBUG_AQ_MESSAGE,
928 "AQRX: Event received with error 0x%X.\n",
929 hw->aq.arq_last_status);
931 memcpy(&e->desc, desc, sizeof(struct i40e_aq_desc));
932 datalen = le16_to_cpu(desc->datalen);
933 e->msg_size = min(datalen, e->msg_size);
934 if (e->msg_buf != NULL && (e->msg_size != 0))
935 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va,
939 /* Restore the original datalen and buffer address in the desc,
940 * FW updates datalen to indicate the event message
943 bi = &hw->aq.arq.r.arq_bi[ntc];
944 desc->datalen = cpu_to_le16((u16)bi->size);
945 desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
946 desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
948 /* set tail = the last cleaned desc index. */
949 wr32(hw, hw->aq.arq.tail, ntc);
950 /* ntc is updated to tail + 1 */
952 if (ntc == hw->aq.num_arq_entries)
954 hw->aq.arq.next_to_clean = ntc;
955 hw->aq.arq.next_to_use = ntu;
957 clean_arq_element_out:
958 /* Set pending if needed, unlock and return */
960 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
961 mutex_unlock(&hw->aq.arq_mutex);
966 void i40e_resume_aq(struct i40e_hw *hw)
970 /* Registers are reset after PF reset */
971 hw->aq.asq.next_to_use = 0;
972 hw->aq.asq.next_to_clean = 0;
974 i40e_config_asq_regs(hw);
975 reg = hw->aq.num_asq_entries | I40E_PF_ATQLEN_ATQENABLE_MASK;
976 wr32(hw, hw->aq.asq.len, reg);
978 hw->aq.arq.next_to_use = 0;
979 hw->aq.arq.next_to_clean = 0;
981 i40e_config_arq_regs(hw);
982 reg = hw->aq.num_arq_entries | I40E_PF_ATQLEN_ATQENABLE_MASK;
983 wr32(hw, hw->aq.arq.len, reg);