drivers/net/ethernet/intel/e1000e/80003es2lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)
  30  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  31  */
  32
  33 #include "e1000.h"
  34
  35 /* A table for the GG82563 cable length where the range is defined
  36  * with a lower bound at "index" and the upper bound at
  37  * "index + 5".
  38  */
  39 static const u16 e1000_gg82563_cable_length_table[] = {
  40         0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF
  41 };
  42
  43 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
  44                 ARRAY_SIZE(e1000_gg82563_cable_length_table)
  45
  46 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
  47 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  48 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  49 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
  50 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
  51 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
  52 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
  53 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  54                                            u16 *data);
  55 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  56                                             u16 data);
  57 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
  58
  59 /**
  60  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
  61  *  @hw: pointer to the HW structure
  62  **/
  63 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
  64 {
  65         struct e1000_phy_info *phy = &hw->phy;
  66         s32 ret_val;
  67
  68         if (hw->phy.media_type != e1000_media_type_copper) {
  69                 phy->type = e1000_phy_none;
  70                 return 0;
  71         } else {
  72                 phy->ops.power_up = e1000_power_up_phy_copper;
  73                 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
  74         }
  75
  76         phy->addr = 1;
  77         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  78         phy->reset_delay_us = 100;
  79         phy->type = e1000_phy_gg82563;
  80
  81         /* This can only be done after all function pointers are setup. */
  82         ret_val = e1000e_get_phy_id(hw);
  83
  84         /* Verify phy id */
  85         if (phy->id != GG82563_E_PHY_ID)
  86                 return -E1000_ERR_PHY;
  87
  88         return ret_val;
  89 }
  90
  91 /**
  92  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
  93  *  @hw: pointer to the HW structure
  94  **/
  95 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
  96 {
  97         struct e1000_nvm_info *nvm = &hw->nvm;
  98         u32 eecd = er32(EECD);
  99         u16 size;
 100
 101         nvm->opcode_bits = 8;
 102         nvm->delay_usec = 1;
 103         switch (nvm->override) {
 104         case e1000_nvm_override_spi_large:
 105                 nvm->page_size = 32;
 106                 nvm->address_bits = 16;
 107                 break;
 108         case e1000_nvm_override_spi_small:
 109                 nvm->page_size = 8;
 110                 nvm->address_bits = 8;
 111                 break;
 112         default:
 113                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 114                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 115                 break;
 116         }
 117
 118         nvm->type = e1000_nvm_eeprom_spi;
 119
 120         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 121                      E1000_EECD_SIZE_EX_SHIFT);
 122
 123         /* Added to a constant, "size" becomes the left-shift value
 124          * for setting word_size.
 125          */
 126         size += NVM_WORD_SIZE_BASE_SHIFT;
 127
 128         /* EEPROM access above 16k is unsupported */
 129         if (size > 14)
 130                 size = 14;
 131         nvm->word_size = 1 << size;
 132
 133         return 0;
 134 }
 135
 136 /**
 137  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
 138  *  @hw: pointer to the HW structure
 139  **/
 140 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
 141 {
 142         struct e1000_mac_info *mac = &hw->mac;
 143
 144         /* Set media type and media-dependent function pointers */
 145         switch (hw->adapter->pdev->device) {
 146         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 147                 hw->phy.media_type = e1000_media_type_internal_serdes;
 148                 mac->ops.check_for_link = e1000e_check_for_serdes_link;
 149                 mac->ops.setup_physical_interface =
 150                     e1000e_setup_fiber_serdes_link;
 151                 break;
 152         default:
 153                 hw->phy.media_type = e1000_media_type_copper;
 154                 mac->ops.check_for_link = e1000e_check_for_copper_link;
 155                 mac->ops.setup_physical_interface =
 156                     e1000_setup_copper_link_80003es2lan;
 157                 break;
 158         }
 159
 160         /* Set mta register count */
 161         mac->mta_reg_count = 128;
 162         /* Set rar entry count */
 163         mac->rar_entry_count = E1000_RAR_ENTRIES;
 164         /* FWSM register */
 165         mac->has_fwsm = true;
 166         /* ARC supported; valid only if manageability features are enabled. */
 167         mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);
 168         /* Adaptive IFS not supported */
 169         mac->adaptive_ifs = false;
 170
 171         /* set lan id for port to determine which phy lock to use */
 172         hw->mac.ops.set_lan_id(hw);
 173
 174         return 0;
 175 }
 176
 177 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
 178 {
 179         struct e1000_hw *hw = &adapter->hw;
 180         s32 rc;
 181
 182         rc = e1000_init_mac_params_80003es2lan(hw);
 183         if (rc)
 184                 return rc;
 185
 186         rc = e1000_init_nvm_params_80003es2lan(hw);
 187         if (rc)
 188                 return rc;
 189
 190         rc = e1000_init_phy_params_80003es2lan(hw);
 191         if (rc)
 192                 return rc;
 193
 194         return 0;
 195 }
 196
 197 /**
 198  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
 199  *  @hw: pointer to the HW structure
 200  *
 201  *  A wrapper to acquire access rights to the correct PHY.
 202  **/
 203 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
 204 {
 205         u16 mask;
 206
 207         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 208         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 209 }
 210
 211 /**
 212  *  e1000_release_phy_80003es2lan - Release rights to access PHY
 213  *  @hw: pointer to the HW structure
 214  *
 215  *  A wrapper to release access rights to the correct PHY.
 216  **/
 217 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 218 {
 219         u16 mask;
 220
 221         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 222         e1000_release_swfw_sync_80003es2lan(hw, mask);
 223 }
 224
 225 /**
 226  *  e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
 227  *  @hw: pointer to the HW structure
 228  *
 229  *  Acquire the semaphore to access the Kumeran interface.
 230  *
 231  **/
 232 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
 233 {
 234         u16 mask;
 235
 236         mask = E1000_SWFW_CSR_SM;
 237
 238         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 239 }
 240
 241 /**
 242  *  e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
 243  *  @hw: pointer to the HW structure
 244  *
 245  *  Release the semaphore used to access the Kumeran interface
 246  **/
 247 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
 248 {
 249         u16 mask;
 250
 251         mask = E1000_SWFW_CSR_SM;
 252
 253         e1000_release_swfw_sync_80003es2lan(hw, mask);
 254 }
 255
 256 /**
 257  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
 258  *  @hw: pointer to the HW structure
 259  *
 260  *  Acquire the semaphore to access the EEPROM.
 261  **/
 262 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
 263 {
 264         s32 ret_val;
 265
 266         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 267         if (ret_val)
 268                 return ret_val;
 269
 270         ret_val = e1000e_acquire_nvm(hw);
 271
 272         if (ret_val)
 273                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 274
 275         return ret_val;
 276 }
 277
 278 /**
 279  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
 280  *  @hw: pointer to the HW structure
 281  *
 282  *  Release the semaphore used to access the EEPROM.
 283  **/
 284 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
 285 {
 286         e1000e_release_nvm(hw);
 287         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 288 }
 289
 290 /**
 291  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
 292  *  @hw: pointer to the HW structure
 293  *  @mask: specifies which semaphore to acquire
 294  *
 295  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 296  *  will also specify which port we're acquiring the lock for.
 297  **/
 298 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 299 {
 300         u32 swfw_sync;
 301         u32 swmask = mask;
 302         u32 fwmask = mask << 16;
 303         s32 i = 0;
 304         s32 timeout = 50;
 305
 306         while (i < timeout) {
 307                 if (e1000e_get_hw_semaphore(hw))
 308                         return -E1000_ERR_SWFW_SYNC;
 309
 310                 swfw_sync = er32(SW_FW_SYNC);
 311                 if (!(swfw_sync & (fwmask | swmask)))
 312                         break;
 313
 314                 /* Firmware currently using resource (fwmask)
 315                  * or other software thread using resource (swmask)
 316                  */
 317                 e1000e_put_hw_semaphore(hw);
 318                 mdelay(5);
 319                 i++;
 320         }
 321
 322         if (i == timeout) {
 323                 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
 324                 return -E1000_ERR_SWFW_SYNC;
 325         }
 326
 327         swfw_sync |= swmask;
 328         ew32(SW_FW_SYNC, swfw_sync);
 329
 330         e1000e_put_hw_semaphore(hw);
 331
 332         return 0;
 333 }
 334
 335 /**
 336  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
 337  *  @hw: pointer to the HW structure
 338  *  @mask: specifies which semaphore to acquire
 339  *
 340  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 341  *  will also specify which port we're releasing the lock for.
 342  **/
 343 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 344 {
 345         u32 swfw_sync;
 346
 347         while (e1000e_get_hw_semaphore(hw) != 0)
 348                 ; /* Empty */
 349
 350         swfw_sync = er32(SW_FW_SYNC);
 351         swfw_sync &= ~mask;
 352         ew32(SW_FW_SYNC, swfw_sync);
 353
 354         e1000e_put_hw_semaphore(hw);
 355 }
 356
 357 /**
 358  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
 359  *  @hw: pointer to the HW structure
 360  *  @offset: offset of the register to read
 361  *  @data: pointer to the data returned from the operation
 362  *
 363  *  Read the GG82563 PHY register.
 364  **/
 365 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 366                                                   u32 offset, u16 *data)
 367 {
 368         s32 ret_val;
 369         u32 page_select;
 370         u16 temp;
 371
 372         ret_val = e1000_acquire_phy_80003es2lan(hw);
 373         if (ret_val)
 374                 return ret_val;
 375
 376         /* Select Configuration Page */
 377         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 378                 page_select = GG82563_PHY_PAGE_SELECT;
 379         } else {
 380                 /* Use Alternative Page Select register to access
 381                  * registers 30 and 31
 382                  */
 383                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 384         }
 385
 386         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 387         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 388         if (ret_val) {
 389                 e1000_release_phy_80003es2lan(hw);
 390                 return ret_val;
 391         }
 392
 393         if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
 394                 /* The "ready" bit in the MDIC register may be incorrectly set
 395                  * before the device has completed the "Page Select" MDI
 396                  * transaction.  So we wait 200us after each MDI command...
 397                  */
 398                 usleep_range(200, 400);
 399
 400                 /* ...and verify the command was successful. */
 401                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 402
 403                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 404                         e1000_release_phy_80003es2lan(hw);
 405                         return -E1000_ERR_PHY;
 406                 }
 407
 408                 usleep_range(200, 400);
 409
 410                 ret_val = e1000e_read_phy_reg_mdic(hw,
 411                                                    MAX_PHY_REG_ADDRESS & offset,
 412                                                    data);
 413
 414                 usleep_range(200, 400);
 415         } else {
 416                 ret_val = e1000e_read_phy_reg_mdic(hw,
 417                                                    MAX_PHY_REG_ADDRESS & offset,
 418                                                    data);
 419         }
 420
 421         e1000_release_phy_80003es2lan(hw);
 422
 423         return ret_val;
 424 }
 425
 426 /**
 427  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 428  *  @hw: pointer to the HW structure
 429  *  @offset: offset of the register to read
 430  *  @data: value to write to the register
 431  *
 432  *  Write to the GG82563 PHY register.
 433  **/
 434 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 435                                                    u32 offset, u16 data)
 436 {
 437         s32 ret_val;
 438         u32 page_select;
 439         u16 temp;
 440
 441         ret_val = e1000_acquire_phy_80003es2lan(hw);
 442         if (ret_val)
 443                 return ret_val;
 444
 445         /* Select Configuration Page */
 446         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 447                 page_select = GG82563_PHY_PAGE_SELECT;
 448         } else {
 449                 /* Use Alternative Page Select register to access
 450                  * registers 30 and 31
 451                  */
 452                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 453         }
 454
 455         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 456         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 457         if (ret_val) {
 458                 e1000_release_phy_80003es2lan(hw);
 459                 return ret_val;
 460         }
 461
 462         if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
 463                 /* The "ready" bit in the MDIC register may be incorrectly set
 464                  * before the device has completed the "Page Select" MDI
 465                  * transaction.  So we wait 200us after each MDI command...
 466                  */
 467                 usleep_range(200, 400);
 468
 469                 /* ...and verify the command was successful. */
 470                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 471
 472                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 473                         e1000_release_phy_80003es2lan(hw);
 474                         return -E1000_ERR_PHY;
 475                 }
 476
 477                 usleep_range(200, 400);
 478
 479                 ret_val = e1000e_write_phy_reg_mdic(hw,
 480                                                     MAX_PHY_REG_ADDRESS &
 481                                                     offset, data);
 482
 483                 usleep_range(200, 400);
 484         } else {
 485                 ret_val = e1000e_write_phy_reg_mdic(hw,
 486                                                     MAX_PHY_REG_ADDRESS &
 487                                                     offset, data);
 488         }
 489
 490         e1000_release_phy_80003es2lan(hw);
 491
 492         return ret_val;
 493 }
 494
 495 /**
 496  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
 497  *  @hw: pointer to the HW structure
 498  *  @offset: offset of the register to read
 499  *  @words: number of words to write
 500  *  @data: buffer of data to write to the NVM
 501  *
 502  *  Write "words" of data to the ESB2 NVM.
 503  **/
 504 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
 505                                        u16 words, u16 *data)
 506 {
 507         return e1000e_write_nvm_spi(hw, offset, words, data);
 508 }
 509
 510 /**
 511  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
 512  *  @hw: pointer to the HW structure
 513  *
 514  *  Wait a specific amount of time for manageability processes to complete.
 515  *  This is a function pointer entry point called by the phy module.
 516  **/
 517 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
 518 {
 519         s32 timeout = PHY_CFG_TIMEOUT;
 520         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 521
 522         if (hw->bus.func == 1)
 523                 mask = E1000_NVM_CFG_DONE_PORT_1;
 524
 525         while (timeout) {
 526                 if (er32(EEMNGCTL) & mask)
 527                         break;
 528                 usleep_range(1000, 2000);
 529                 timeout--;
 530         }
 531         if (!timeout) {
 532                 e_dbg("MNG configuration cycle has not completed.\n");
 533                 return -E1000_ERR_RESET;
 534         }
 535
 536         return 0;
 537 }
 538
 539 /**
 540  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
 541  *  @hw: pointer to the HW structure
 542  *
 543  *  Force the speed and duplex settings onto the PHY.  This is a
 544  *  function pointer entry point called by the phy module.
 545  **/
 546 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 547 {
 548         s32 ret_val;
 549         u16 phy_data;
 550         bool link;
 551
 552         /* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
 553          * forced whenever speed and duplex are forced.
 554          */
 555         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 556         if (ret_val)
 557                 return ret_val;
 558
 559         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
 560         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 561         if (ret_val)
 562                 return ret_val;
 563
 564         e_dbg("GG82563 PSCR: %X\n", phy_data);
 565
 566         ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
 567         if (ret_val)
 568                 return ret_val;
 569
 570         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
 571
 572         /* Reset the phy to commit changes. */
 573         phy_data |= BMCR_RESET;
 574
 575         ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
 576         if (ret_val)
 577                 return ret_val;
 578
 579         udelay(1);
 580
 581         if (hw->phy.autoneg_wait_to_complete) {
 582                 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");
 583
 584                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 585                                                       100000, &link);
 586                 if (ret_val)
 587                         return ret_val;
 588
 589                 if (!link) {
 590                         /* We didn't get link.
 591                          * Reset the DSP and cross our fingers.
 592                          */
 593                         ret_val = e1000e_phy_reset_dsp(hw);
 594                         if (ret_val)
 595                                 return ret_val;
 596                 }
 597
 598                 /* Try once more */
 599                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 600                                                       100000, &link);
 601                 if (ret_val)
 602                         return ret_val;
 603         }
 604
 605         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
 606         if (ret_val)
 607                 return ret_val;
 608
 609         /* Resetting the phy means we need to verify the TX_CLK corresponds
 610          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
 611          */
 612         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 613         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
 614                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
 615         else
 616                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 617
 618         /* In addition, we must re-enable CRS on Tx for both half and full
 619          * duplex.
 620          */
 621         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 622         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
 623
 624         return ret_val;
 625 }
 626
 627 /**
 628  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
 629  *  @hw: pointer to the HW structure
 630  *
 631  *  Find the approximate cable length as measured by the GG82563 PHY.
 632  *  This is a function pointer entry point called by the phy module.
 633  **/
 634 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 635 {
 636         struct e1000_phy_info *phy = &hw->phy;
 637         s32 ret_val;
 638         u16 phy_data, index;
 639
 640         ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
 641         if (ret_val)
 642                 return ret_val;
 643
 644         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 645
 646         if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
 647                 return -E1000_ERR_PHY;
 648
 649         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
 650         phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
 651
 652         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 653
 654         return 0;
 655 }
 656
 657 /**
 658  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
 659  *  @hw: pointer to the HW structure
 660  *  @speed: pointer to speed buffer
 661  *  @duplex: pointer to duplex buffer
 662  *
 663  *  Retrieve the current speed and duplex configuration.
 664  **/
 665 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
 666                                               u16 *duplex)
 667 {
 668         s32 ret_val;
 669
 670         if (hw->phy.media_type == e1000_media_type_copper) {
 671                 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
 672                 hw->phy.ops.cfg_on_link_up(hw);
 673         } else {
 674                 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
 675                                                                    speed,
 676                                                                    duplex);
 677         }
 678
 679         return ret_val;
 680 }
 681
 682 /**
 683  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
 684  *  @hw: pointer to the HW structure
 685  *
 686  *  Perform a global reset to the ESB2 controller.
 687  **/
 688 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 689 {
 690         u32 ctrl;
 691         s32 ret_val;
 692         u16 kum_reg_data;
 693
 694         /* Prevent the PCI-E bus from sticking if there is no TLP connection
 695          * on the last TLP read/write transaction when MAC is reset.
 696          */
 697         ret_val = e1000e_disable_pcie_master(hw);
 698         if (ret_val)
 699                 e_dbg("PCI-E Master disable polling has failed.\n");
 700
 701         e_dbg("Masking off all interrupts\n");
 702         ew32(IMC, 0xffffffff);
 703
 704         ew32(RCTL, 0);
 705         ew32(TCTL, E1000_TCTL_PSP);
 706         e1e_flush();
 707
 708         usleep_range(10000, 20000);
 709
 710         ctrl = er32(CTRL);
 711
 712         ret_val = e1000_acquire_phy_80003es2lan(hw);
 713         if (ret_val)
 714                 return ret_val;
 715
 716         e_dbg("Issuing a global reset to MAC\n");
 717         ew32(CTRL, ctrl | E1000_CTRL_RST);
 718         e1000_release_phy_80003es2lan(hw);
 719
 720         /* Disable IBIST slave mode (far-end loopback) */
 721         ret_val =
 722             e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 723                                             &kum_reg_data);
 724         if (ret_val)
 725                 return ret_val;
 726         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 727         e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 728                                          kum_reg_data);
 729
 730         ret_val = e1000e_get_auto_rd_done(hw);
 731         if (ret_val)
 732                 /* We don't want to continue accessing MAC registers. */
 733                 return ret_val;
 734
 735         /* Clear any pending interrupt events. */
 736         ew32(IMC, 0xffffffff);
 737         er32(ICR);
 738
 739         return e1000_check_alt_mac_addr_generic(hw);
 740 }
 741
 742 /**
 743  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
 744  *  @hw: pointer to the HW structure
 745  *
 746  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
 747  **/
 748 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 749 {
 750         struct e1000_mac_info *mac = &hw->mac;
 751         u32 reg_data;
 752         s32 ret_val;
 753         u16 kum_reg_data;
 754         u16 i;
 755
 756         e1000_initialize_hw_bits_80003es2lan(hw);
 757
 758         /* Initialize identification LED */
 759         ret_val = mac->ops.id_led_init(hw);
 760         /* An error is not fatal and we should not stop init due to this */
 761         if (ret_val)
 762                 e_dbg("Error initializing identification LED\n");
 763
 764         /* Disabling VLAN filtering */
 765         e_dbg("Initializing the IEEE VLAN\n");
 766         mac->ops.clear_vfta(hw);
 767
 768         /* Setup the receive address. */
 769         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
 770
 771         /* Zero out the Multicast HASH table */
 772         e_dbg("Zeroing the MTA\n");
 773         for (i = 0; i < mac->mta_reg_count; i++)
 774                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 775
 776         /* Setup link and flow control */
 777         ret_val = mac->ops.setup_link(hw);
 778         if (ret_val)
 779                 return ret_val;
 780
 781         /* Disable IBIST slave mode (far-end loopback) */
 782         e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 783                                         &kum_reg_data);
 784         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 785         e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 786                                          kum_reg_data);
 787
 788         /* Set the transmit descriptor write-back policy */
 789         reg_data = er32(TXDCTL(0));
 790         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
 791                     E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
 792         ew32(TXDCTL(0), reg_data);
 793
 794         /* ...for both queues. */
 795         reg_data = er32(TXDCTL(1));
 796         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
 797                     E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
 798         ew32(TXDCTL(1), reg_data);
 799
 800         /* Enable retransmit on late collisions */
 801         reg_data = er32(TCTL);
 802         reg_data |= E1000_TCTL_RTLC;
 803         ew32(TCTL, reg_data);
 804
 805         /* Configure Gigabit Carry Extend Padding */
 806         reg_data = er32(TCTL_EXT);
 807         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
 808         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
 809         ew32(TCTL_EXT, reg_data);
 810
 811         /* Configure Transmit Inter-Packet Gap */
 812         reg_data = er32(TIPG);
 813         reg_data &= ~E1000_TIPG_IPGT_MASK;
 814         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 815         ew32(TIPG, reg_data);
 816
 817         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
 818         reg_data &= ~0x00100000;
 819         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 820
 821         /* default to true to enable the MDIC W/A */
 822         hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
 823
 824         ret_val =
 825             e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
 826                                             E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
 827         if (!ret_val) {
 828                 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
 829                     E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
 830                         hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
 831         }
 832
 833         /* Clear all of the statistics registers (clear on read).  It is
 834          * important that we do this after we have tried to establish link
 835          * because the symbol error count will increment wildly if there
 836          * is no link.
 837          */
 838         e1000_clear_hw_cntrs_80003es2lan(hw);
 839
 840         return ret_val;
 841 }
 842
 843 /**
 844  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
 845  *  @hw: pointer to the HW structure
 846  *
 847  *  Initializes required hardware-dependent bits needed for normal operation.
 848  **/
 849 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
 850 {
 851         u32 reg;
 852
 853         /* Transmit Descriptor Control 0 */
 854         reg = er32(TXDCTL(0));
 855         reg |= (1 << 22);
 856         ew32(TXDCTL(0), reg);
 857
 858         /* Transmit Descriptor Control 1 */
 859         reg = er32(TXDCTL(1));
 860         reg |= (1 << 22);
 861         ew32(TXDCTL(1), reg);
 862
 863         /* Transmit Arbitration Control 0 */
 864         reg = er32(TARC(0));
 865         reg &= ~(0xF << 27);    /* 30:27 */
 866         if (hw->phy.media_type != e1000_media_type_copper)
 867                 reg &= ~(1 << 20);
 868         ew32(TARC(0), reg);
 869
 870         /* Transmit Arbitration Control 1 */
 871         reg = er32(TARC(1));
 872         if (er32(TCTL) & E1000_TCTL_MULR)
 873                 reg &= ~(1 << 28);
 874         else
 875                 reg |= (1 << 28);
 876         ew32(TARC(1), reg);
 877
 878         /* Disable IPv6 extension header parsing because some malformed
 879          * IPv6 headers can hang the Rx.
 880          */
 881         reg = er32(RFCTL);
 882         reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
 883         ew32(RFCTL, reg);
 884 }
 885
 886 /**
 887  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
 888  *  @hw: pointer to the HW structure
 889  *
 890  *  Setup some GG82563 PHY registers for obtaining link
 891  **/
 892 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 893 {
 894         struct e1000_phy_info *phy = &hw->phy;
 895         s32 ret_val;
 896         u32 reg;
 897         u16 data;
 898
 899         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
 900         if (ret_val)
 901                 return ret_val;
 902
 903         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 904         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
 905         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
 906
 907         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
 908         if (ret_val)
 909                 return ret_val;
 910
 911         /* Options:
 912          *   MDI/MDI-X = 0 (default)
 913          *   0 - Auto for all speeds
 914          *   1 - MDI mode
 915          *   2 - MDI-X mode
 916          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
 917          */
 918         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
 919         if (ret_val)
 920                 return ret_val;
 921
 922         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
 923
 924         switch (phy->mdix) {
 925         case 1:
 926                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
 927                 break;
 928         case 2:
 929                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
 930                 break;
 931         case 0:
 932         default:
 933                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
 934                 break;
 935         }
 936
 937         /* Options:
 938          *   disable_polarity_correction = 0 (default)
 939          *       Automatic Correction for Reversed Cable Polarity
 940          *   0 - Disabled
 941          *   1 - Enabled
 942          */
 943         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 944         if (phy->disable_polarity_correction)
 945                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 946
 947         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
 948         if (ret_val)
 949                 return ret_val;
 950
 951         /* SW Reset the PHY so all changes take effect */
 952         ret_val = hw->phy.ops.commit(hw);
 953         if (ret_val) {
 954                 e_dbg("Error Resetting the PHY\n");
 955                 return ret_val;
 956         }
 957
 958         /* Bypass Rx and Tx FIFO's */
 959         reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
 960         data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
 961                 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
 962         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
 963         if (ret_val)
 964                 return ret_val;
 965
 966         reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
 967         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
 968         if (ret_val)
 969                 return ret_val;
 970         data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
 971         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
 972         if (ret_val)
 973                 return ret_val;
 974
 975         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
 976         if (ret_val)
 977                 return ret_val;
 978
 979         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
 980         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
 981         if (ret_val)
 982                 return ret_val;
 983
 984         reg = er32(CTRL_EXT);
 985         reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
 986         ew32(CTRL_EXT, reg);
 987
 988         ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
 989         if (ret_val)
 990                 return ret_val;
 991
 992         /* Do not init these registers when the HW is in IAMT mode, since the
 993          * firmware will have already initialized them.  We only initialize
 994          * them if the HW is not in IAMT mode.
 995          */
 996         if (!hw->mac.ops.check_mng_mode(hw)) {
 997                 /* Enable Electrical Idle on the PHY */
 998                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
 999                 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
1000                 if (ret_val)
1001                         return ret_val;
1002
1003                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1004                 if (ret_val)
1005                         return ret_val;
1006
1007                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1008                 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1009                 if (ret_val)
1010                         return ret_val;
1011         }
1012
1013         /* Workaround: Disable padding in Kumeran interface in the MAC
1014          * and in the PHY to avoid CRC errors.
1015          */
1016         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1017         if (ret_val)
1018                 return ret_val;
1019
1020         data |= GG82563_ICR_DIS_PADDING;
1021         ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1022         if (ret_val)
1023                 return ret_val;
1024
1025         return 0;
1026 }
1027
1028 /**
1029  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1030  *  @hw: pointer to the HW structure
1031  *
1032  *  Essentially a wrapper for setting up all things "copper" related.
1033  *  This is a function pointer entry point called by the mac module.
1034  **/
1035 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1036 {
1037         u32 ctrl;
1038         s32 ret_val;
1039         u16 reg_data;
1040
1041         ctrl = er32(CTRL);
1042         ctrl |= E1000_CTRL_SLU;
1043         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1044         ew32(CTRL, ctrl);
1045
1046         /* Set the mac to wait the maximum time between each
1047          * iteration and increase the max iterations when
1048          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1049          */
1050         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1051                                                    0xFFFF);
1052         if (ret_val)
1053                 return ret_val;
1054         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1055                                                   &reg_data);
1056         if (ret_val)
1057                 return ret_val;
1058         reg_data |= 0x3F;
1059         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1060                                                    reg_data);
1061         if (ret_val)
1062                 return ret_val;
1063         ret_val =
1064             e1000_read_kmrn_reg_80003es2lan(hw,
1065                                             E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1066                                             &reg_data);
1067         if (ret_val)
1068                 return ret_val;
1069         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1070         ret_val =
1071             e1000_write_kmrn_reg_80003es2lan(hw,
1072                                              E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1073                                              reg_data);
1074         if (ret_val)
1075                 return ret_val;
1076
1077         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1078         if (ret_val)
1079                 return ret_val;
1080
1081         return e1000e_setup_copper_link(hw);
1082 }
1083
1084 /**
1085  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1086  *  @hw: pointer to the HW structure
1087  *  @duplex: current duplex setting
1088  *
1089  *  Configure the KMRN interface by applying last minute quirks for
1090  *  10/100 operation.
1091  **/
1092 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1093 {
1094         s32 ret_val = 0;
1095         u16 speed;
1096         u16 duplex;
1097
1098         if (hw->phy.media_type == e1000_media_type_copper) {
1099                 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1100                                                              &duplex);
1101                 if (ret_val)
1102                         return ret_val;
1103
1104                 if (speed == SPEED_1000)
1105                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1106                 else
1107                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1108         }
1109
1110         return ret_val;
1111 }
1112
1113 /**
1114  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1115  *  @hw: pointer to the HW structure
1116  *  @duplex: current duplex setting
1117  *
1118  *  Configure the KMRN interface by applying last minute quirks for
1119  *  10/100 operation.
1120  **/
1121 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1122 {
1123         s32 ret_val;
1124         u32 tipg;
1125         u32 i = 0;
1126         u16 reg_data, reg_data2;
1127
1128         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1129         ret_val =
1130             e1000_write_kmrn_reg_80003es2lan(hw,
1131                                              E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1132                                              reg_data);
1133         if (ret_val)
1134                 return ret_val;
1135
1136         /* Configure Transmit Inter-Packet Gap */
1137         tipg = er32(TIPG);
1138         tipg &= ~E1000_TIPG_IPGT_MASK;
1139         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1140         ew32(TIPG, tipg);
1141
1142         do {
1143                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1144                 if (ret_val)
1145                         return ret_val;
1146
1147                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1148                 if (ret_val)
1149                         return ret_val;
1150                 i++;
1151         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1152
1153         if (duplex == HALF_DUPLEX)
1154                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1155         else
1156                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1157
1158         return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1159 }
1160
1161 /**
1162  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1163  *  @hw: pointer to the HW structure
1164  *
1165  *  Configure the KMRN interface by applying last minute quirks for
1166  *  gigabit operation.
1167  **/
1168 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1169 {
1170         s32 ret_val;
1171         u16 reg_data, reg_data2;
1172         u32 tipg;
1173         u32 i = 0;
1174
1175         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1176         ret_val =
1177             e1000_write_kmrn_reg_80003es2lan(hw,
1178                                              E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1179                                              reg_data);
1180         if (ret_val)
1181                 return ret_val;
1182
1183         /* Configure Transmit Inter-Packet Gap */
1184         tipg = er32(TIPG);
1185         tipg &= ~E1000_TIPG_IPGT_MASK;
1186         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1187         ew32(TIPG, tipg);
1188
1189         do {
1190                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1191                 if (ret_val)
1192                         return ret_val;
1193
1194                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1195                 if (ret_val)
1196                         return ret_val;
1197                 i++;
1198         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1199
1200         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1201
1202         return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1203 }
1204
1205 /**
1206  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1207  *  @hw: pointer to the HW structure
1208  *  @offset: register offset to be read
1209  *  @data: pointer to the read data
1210  *
1211  *  Acquire semaphore, then read the PHY register at offset
1212  *  using the kumeran interface.  The information retrieved is stored in data.
1213  *  Release the semaphore before exiting.
1214  **/
1215 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1216                                            u16 *data)
1217 {
1218         u32 kmrnctrlsta;
1219         s32 ret_val;
1220
1221         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1222         if (ret_val)
1223                 return ret_val;
1224
1225         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1226                        E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1227         ew32(KMRNCTRLSTA, kmrnctrlsta);
1228         e1e_flush();
1229
1230         udelay(2);
1231
1232         kmrnctrlsta = er32(KMRNCTRLSTA);
1233         *data = (u16)kmrnctrlsta;
1234
1235         e1000_release_mac_csr_80003es2lan(hw);
1236
1237         return ret_val;
1238 }
1239
1240 /**
1241  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1242  *  @hw: pointer to the HW structure
1243  *  @offset: register offset to write to
1244  *  @data: data to write at register offset
1245  *
1246  *  Acquire semaphore, then write the data to PHY register
1247  *  at the offset using the kumeran interface.  Release semaphore
1248  *  before exiting.
1249  **/
1250 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1251                                             u16 data)
1252 {
1253         u32 kmrnctrlsta;
1254         s32 ret_val;
1255
1256         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1257         if (ret_val)
1258                 return ret_val;
1259
1260         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1261                        E1000_KMRNCTRLSTA_OFFSET) | data;
1262         ew32(KMRNCTRLSTA, kmrnctrlsta);
1263         e1e_flush();
1264
1265         udelay(2);
1266
1267         e1000_release_mac_csr_80003es2lan(hw);
1268
1269         return ret_val;
1270 }
1271
1272 /**
1273  *  e1000_read_mac_addr_80003es2lan - Read device MAC address
1274  *  @hw: pointer to the HW structure
1275  **/
1276 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1277 {
1278         s32 ret_val;
1279
1280         /* If there's an alternate MAC address place it in RAR0
1281          * so that it will override the Si installed default perm
1282          * address.
1283          */
1284         ret_val = e1000_check_alt_mac_addr_generic(hw);
1285         if (ret_val)
1286                 return ret_val;
1287
1288         return e1000_read_mac_addr_generic(hw);
1289 }
1290
1291 /**
1292  * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1293  * @hw: pointer to the HW structure
1294  *
1295  * In the case of a PHY power down to save power, or to turn off link during a
1296  * driver unload, or wake on lan is not enabled, remove the link.
1297  **/
1298 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1299 {
1300         /* If the management interface is not enabled, then power down */
1301         if (!(hw->mac.ops.check_mng_mode(hw) ||
1302               hw->phy.ops.check_reset_block(hw)))
1303                 e1000_power_down_phy_copper(hw);
1304 }
1305
1306 /**
1307  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1308  *  @hw: pointer to the HW structure
1309  *
1310  *  Clears the hardware counters by reading the counter registers.
1311  **/
1312 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1313 {
1314         e1000e_clear_hw_cntrs_base(hw);
1315
1316         er32(PRC64);
1317         er32(PRC127);
1318         er32(PRC255);
1319         er32(PRC511);
1320         er32(PRC1023);
1321         er32(PRC1522);
1322         er32(PTC64);
1323         er32(PTC127);
1324         er32(PTC255);
1325         er32(PTC511);
1326         er32(PTC1023);
1327         er32(PTC1522);
1328
1329         er32(ALGNERRC);
1330         er32(RXERRC);
1331         er32(TNCRS);
1332         er32(CEXTERR);
1333         er32(TSCTC);
1334         er32(TSCTFC);
1335
1336         er32(MGTPRC);
1337         er32(MGTPDC);
1338         er32(MGTPTC);
1339
1340         er32(IAC);
1341         er32(ICRXOC);
1342
1343         er32(ICRXPTC);
1344         er32(ICRXATC);
1345         er32(ICTXPTC);
1346         er32(ICTXATC);
1347         er32(ICTXQEC);
1348         er32(ICTXQMTC);
1349         er32(ICRXDMTC);
1350 }
1351
1352 static const struct e1000_mac_operations es2_mac_ops = {
1353         .read_mac_addr          = e1000_read_mac_addr_80003es2lan,
1354         .id_led_init            = e1000e_id_led_init_generic,
1355         .blink_led              = e1000e_blink_led_generic,
1356         .check_mng_mode         = e1000e_check_mng_mode_generic,
1357         /* check_for_link dependent on media type */
1358         .cleanup_led            = e1000e_cleanup_led_generic,
1359         .clear_hw_cntrs         = e1000_clear_hw_cntrs_80003es2lan,
1360         .get_bus_info           = e1000e_get_bus_info_pcie,
1361         .set_lan_id             = e1000_set_lan_id_multi_port_pcie,
1362         .get_link_up_info       = e1000_get_link_up_info_80003es2lan,
1363         .led_on                 = e1000e_led_on_generic,
1364         .led_off                = e1000e_led_off_generic,
1365         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1366         .write_vfta             = e1000_write_vfta_generic,
1367         .clear_vfta             = e1000_clear_vfta_generic,
1368         .reset_hw               = e1000_reset_hw_80003es2lan,
1369         .init_hw                = e1000_init_hw_80003es2lan,
1370         .setup_link             = e1000e_setup_link_generic,
1371         /* setup_physical_interface dependent on media type */
1372         .setup_led              = e1000e_setup_led_generic,
1373         .config_collision_dist  = e1000e_config_collision_dist_generic,
1374         .rar_set                = e1000e_rar_set_generic,
1375 };
1376
1377 static const struct e1000_phy_operations es2_phy_ops = {
1378         .acquire                = e1000_acquire_phy_80003es2lan,
1379         .check_polarity         = e1000_check_polarity_m88,
1380         .check_reset_block      = e1000e_check_reset_block_generic,
1381         .commit                 = e1000e_phy_sw_reset,
1382         .force_speed_duplex     = e1000_phy_force_speed_duplex_80003es2lan,
1383         .get_cfg_done           = e1000_get_cfg_done_80003es2lan,
1384         .get_cable_length       = e1000_get_cable_length_80003es2lan,
1385         .get_info               = e1000e_get_phy_info_m88,
1386         .read_reg               = e1000_read_phy_reg_gg82563_80003es2lan,
1387         .release                = e1000_release_phy_80003es2lan,
1388         .reset                  = e1000e_phy_hw_reset_generic,
1389         .set_d0_lplu_state      = NULL,
1390         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1391         .write_reg              = e1000_write_phy_reg_gg82563_80003es2lan,
1392         .cfg_on_link_up         = e1000_cfg_on_link_up_80003es2lan,
1393 };
1394
1395 static const struct e1000_nvm_operations es2_nvm_ops = {
1396         .acquire                = e1000_acquire_nvm_80003es2lan,
1397         .read                   = e1000e_read_nvm_eerd,
1398         .release                = e1000_release_nvm_80003es2lan,
1399         .reload                 = e1000e_reload_nvm_generic,
1400         .update                 = e1000e_update_nvm_checksum_generic,
1401         .valid_led_default      = e1000e_valid_led_default,
1402         .validate               = e1000e_validate_nvm_checksum_generic,
1403         .write                  = e1000_write_nvm_80003es2lan,
1404 };
1405
1406 const struct e1000_info e1000_es2_info = {
1407         .mac                    = e1000_80003es2lan,
1408         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1409                                   | FLAG_HAS_JUMBO_FRAMES
1410                                   | FLAG_HAS_WOL
1411                                   | FLAG_APME_IN_CTRL3
1412                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1413                                   | FLAG_RX_NEEDS_RESTART /* errata */
1414                                   | FLAG_TARC_SET_BIT_ZERO /* errata */
1415                                   | FLAG_APME_CHECK_PORT_B
1416                                   | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */
1417         .flags2                 = FLAG2_DMA_BURST,
1418         .pba                    = 38,
1419         .max_hw_frame_size      = DEFAULT_JUMBO,
1420         .get_variants           = e1000_get_variants_80003es2lan,
1421         .mac_ops                = &es2_mac_ops,
1422         .phy_ops                = &es2_phy_ops,
1423         .nvm_ops                = &es2_nvm_ops,
1424 };