drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/init.h>
  74 #include <linux/delay.h>
  75 #include <linux/netdevice.h>
  76 #include <linux/etherdevice.h>
  77 #include <linux/skbuff.h>
  78 #include <linux/if_vlan.h>
  79 #include <linux/spinlock.h>
  80 #include <linux/mm.h>
  81 #include <linux/of_address.h>
  82 #include <linux/of_irq.h>
  83 #include <linux/of_mdio.h>
  84 #include <linux/of_platform.h>
  85 #include <linux/ip.h>
  86 #include <linux/tcp.h>
  87 #include <linux/udp.h>
  88 #include <linux/in.h>
  89 #include <linux/net_tstamp.h>
  90
  91 #include <asm/io.h>
  92 #include <asm/reg.h>
  93 #include <asm/mpc85xx.h>
  94 #include <asm/irq.h>
  95 #include <asm/uaccess.h>
  96 #include <linux/module.h>
  97 #include <linux/dma-mapping.h>
  98 #include <linux/crc32.h>
  99 #include <linux/mii.h>
 100 #include <linux/phy.h>
 101 #include <linux/phy_fixed.h>
 102 #include <linux/of.h>
 103 #include <linux/of_net.h>
 104
 105 #include "gianfar.h"
 106
 107 #define TX_TIMEOUT      (1*HZ)
 108
 109 const char gfar_driver_version[] = "1.3";
 110
 111 static int gfar_enet_open(struct net_device *dev);
 112 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 113 static void gfar_reset_task(struct work_struct *work);
 114 static void gfar_timeout(struct net_device *dev);
 115 static int gfar_close(struct net_device *dev);
 116 struct sk_buff *gfar_new_skb(struct net_device *dev);
 117 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 118                            struct sk_buff *skb);
 119 static int gfar_set_mac_address(struct net_device *dev);
 120 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 121 static irqreturn_t gfar_error(int irq, void *dev_id);
 122 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 123 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 124 static void adjust_link(struct net_device *dev);
 125 static void init_registers(struct net_device *dev);
 126 static int init_phy(struct net_device *dev);
 127 static int gfar_probe(struct platform_device *ofdev);
 128 static int gfar_remove(struct platform_device *ofdev);
 129 static void free_skb_resources(struct gfar_private *priv);
 130 static void gfar_set_multi(struct net_device *dev);
 131 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 132 static void gfar_configure_serdes(struct net_device *dev);
 133 static int gfar_poll(struct napi_struct *napi, int budget);
 134 static int gfar_poll_sq(struct napi_struct *napi, int budget);
 135 #ifdef CONFIG_NET_POLL_CONTROLLER
 136 static void gfar_netpoll(struct net_device *dev);
 137 #endif
 138 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 139 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 140 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 141                                int amount_pull, struct napi_struct *napi);
 142 void gfar_halt(struct net_device *dev);
 143 static void gfar_halt_nodisable(struct net_device *dev);
 144 void gfar_start(struct net_device *dev);
 145 static void gfar_clear_exact_match(struct net_device *dev);
 146 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 147                                   const u8 *addr);
 148 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 149
 150 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 151 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 152 MODULE_LICENSE("GPL");
 153
 154 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 155                             dma_addr_t buf)
 156 {
 157         u32 lstatus;
 158
 159         bdp->bufPtr = buf;
 160
 161         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 162         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 163                 lstatus |= BD_LFLAG(RXBD_WRAP);
 164
 165         eieio();
 166
 167         bdp->lstatus = lstatus;
 168 }
 169
 170 static int gfar_init_bds(struct net_device *ndev)
 171 {
 172         struct gfar_private *priv = netdev_priv(ndev);
 173         struct gfar_priv_tx_q *tx_queue = NULL;
 174         struct gfar_priv_rx_q *rx_queue = NULL;
 175         struct txbd8 *txbdp;
 176         struct rxbd8 *rxbdp;
 177         int i, j;
 178
 179         for (i = 0; i < priv->num_tx_queues; i++) {
 180                 tx_queue = priv->tx_queue[i];
 181                 /* Initialize some variables in our dev structure */
 182                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 183                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 184                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 185                 tx_queue->skb_curtx = 0;
 186                 tx_queue->skb_dirtytx = 0;
 187
 188                 /* Initialize Transmit Descriptor Ring */
 189                 txbdp = tx_queue->tx_bd_base;
 190                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 191                         txbdp->lstatus = 0;
 192                         txbdp->bufPtr = 0;
 193                         txbdp++;
 194                 }
 195
 196                 /* Set the last descriptor in the ring to indicate wrap */
 197                 txbdp--;
 198                 txbdp->status |= TXBD_WRAP;
 199         }
 200
 201         for (i = 0; i < priv->num_rx_queues; i++) {
 202                 rx_queue = priv->rx_queue[i];
 203                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 204                 rx_queue->skb_currx = 0;
 205                 rxbdp = rx_queue->rx_bd_base;
 206
 207                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 208                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 209
 210                         if (skb) {
 211                                 gfar_init_rxbdp(rx_queue, rxbdp,
 212                                                 rxbdp->bufPtr);
 213                         } else {
 214                                 skb = gfar_new_skb(ndev);
 215                                 if (!skb) {
 216                                         netdev_err(ndev, "Can't allocate RX buffers\n");
 217                                         return -ENOMEM;
 218                                 }
 219                                 rx_queue->rx_skbuff[j] = skb;
 220
 221                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 222                         }
 223
 224                         rxbdp++;
 225                 }
 226
 227         }
 228
 229         return 0;
 230 }
 231
 232 static int gfar_alloc_skb_resources(struct net_device *ndev)
 233 {
 234         void *vaddr;
 235         dma_addr_t addr;
 236         int i, j, k;
 237         struct gfar_private *priv = netdev_priv(ndev);
 238         struct device *dev = priv->dev;
 239         struct gfar_priv_tx_q *tx_queue = NULL;
 240         struct gfar_priv_rx_q *rx_queue = NULL;
 241
 242         priv->total_tx_ring_size = 0;
 243         for (i = 0; i < priv->num_tx_queues; i++)
 244                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 245
 246         priv->total_rx_ring_size = 0;
 247         for (i = 0; i < priv->num_rx_queues; i++)
 248                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 249
 250         /* Allocate memory for the buffer descriptors */
 251         vaddr = dma_alloc_coherent(dev,
 252                                    (priv->total_tx_ring_size *
 253                                     sizeof(struct txbd8)) +
 254                                    (priv->total_rx_ring_size *
 255                                     sizeof(struct rxbd8)),
 256                                    &addr, GFP_KERNEL);
 257         if (!vaddr)
 258                 return -ENOMEM;
 259
 260         for (i = 0; i < priv->num_tx_queues; i++) {
 261                 tx_queue = priv->tx_queue[i];
 262                 tx_queue->tx_bd_base = vaddr;
 263                 tx_queue->tx_bd_dma_base = addr;
 264                 tx_queue->dev = ndev;
 265                 /* enet DMA only understands physical addresses */
 266                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 267                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 268         }
 269
 270         /* Start the rx descriptor ring where the tx ring leaves off */
 271         for (i = 0; i < priv->num_rx_queues; i++) {
 272                 rx_queue = priv->rx_queue[i];
 273                 rx_queue->rx_bd_base = vaddr;
 274                 rx_queue->rx_bd_dma_base = addr;
 275                 rx_queue->dev = ndev;
 276                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 277                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 278         }
 279
 280         /* Setup the skbuff rings */
 281         for (i = 0; i < priv->num_tx_queues; i++) {
 282                 tx_queue = priv->tx_queue[i];
 283                 tx_queue->tx_skbuff =
 284                         kmalloc_array(tx_queue->tx_ring_size,
 285                                       sizeof(*tx_queue->tx_skbuff),
 286                                       GFP_KERNEL);
 287                 if (!tx_queue->tx_skbuff)
 288                         goto cleanup;
 289
 290                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 291                         tx_queue->tx_skbuff[k] = NULL;
 292         }
 293
 294         for (i = 0; i < priv->num_rx_queues; i++) {
 295                 rx_queue = priv->rx_queue[i];
 296                 rx_queue->rx_skbuff =
 297                         kmalloc_array(rx_queue->rx_ring_size,
 298                                       sizeof(*rx_queue->rx_skbuff),
 299                                       GFP_KERNEL);
 300                 if (!rx_queue->rx_skbuff)
 301                         goto cleanup;
 302
 303                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 304                         rx_queue->rx_skbuff[j] = NULL;
 305         }
 306
 307         if (gfar_init_bds(ndev))
 308                 goto cleanup;
 309
 310         return 0;
 311
 312 cleanup:
 313         free_skb_resources(priv);
 314         return -ENOMEM;
 315 }
 316
 317 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 318 {
 319         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 320         u32 __iomem *baddr;
 321         int i;
 322
 323         baddr = &regs->tbase0;
 324         for (i = 0; i < priv->num_tx_queues; i++) {
 325                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 326                 baddr += 2;
 327         }
 328
 329         baddr = &regs->rbase0;
 330         for (i = 0; i < priv->num_rx_queues; i++) {
 331                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 332                 baddr += 2;
 333         }
 334 }
 335
 336 static void gfar_init_mac(struct net_device *ndev)
 337 {
 338         struct gfar_private *priv = netdev_priv(ndev);
 339         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 340         u32 rctrl = 0;
 341         u32 tctrl = 0;
 342         u32 attrs = 0;
 343
 344         /* write the tx/rx base registers */
 345         gfar_init_tx_rx_base(priv);
 346
 347         /* Configure the coalescing support */
 348         gfar_configure_coalescing_all(priv);
 349
 350         /* set this when rx hw offload (TOE) functions are being used */
 351         priv->uses_rxfcb = 0;
 352
 353         if (priv->rx_filer_enable) {
 354                 rctrl |= RCTRL_FILREN;
 355                 /* Program the RIR0 reg with the required distribution */
 356                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 357         }
 358
 359         /* Restore PROMISC mode */
 360         if (ndev->flags & IFF_PROMISC)
 361                 rctrl |= RCTRL_PROM;
 362
 363         if (ndev->features & NETIF_F_RXCSUM) {
 364                 rctrl |= RCTRL_CHECKSUMMING;
 365                 priv->uses_rxfcb = 1;
 366         }
 367
 368         if (priv->extended_hash) {
 369                 rctrl |= RCTRL_EXTHASH;
 370
 371                 gfar_clear_exact_match(ndev);
 372                 rctrl |= RCTRL_EMEN;
 373         }
 374
 375         if (priv->padding) {
 376                 rctrl &= ~RCTRL_PAL_MASK;
 377                 rctrl |= RCTRL_PADDING(priv->padding);
 378         }
 379
 380         /* Insert receive time stamps into padding alignment bytes */
 381         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 382                 rctrl &= ~RCTRL_PAL_MASK;
 383                 rctrl |= RCTRL_PADDING(8);
 384                 priv->padding = 8;
 385         }
 386
 387         /* Enable HW time stamping if requested from user space */
 388         if (priv->hwts_rx_en) {
 389                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 390                 priv->uses_rxfcb = 1;
 391         }
 392
 393         if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) {
 394                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 395                 priv->uses_rxfcb = 1;
 396         }
 397
 398         /* Init rctrl based on our settings */
 399         gfar_write(&regs->rctrl, rctrl);
 400
 401         if (ndev->features & NETIF_F_IP_CSUM)
 402                 tctrl |= TCTRL_INIT_CSUM;
 403
 404         if (priv->prio_sched_en)
 405                 tctrl |= TCTRL_TXSCHED_PRIO;
 406         else {
 407                 tctrl |= TCTRL_TXSCHED_WRRS;
 408                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 409                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 410         }
 411
 412         gfar_write(&regs->tctrl, tctrl);
 413
 414         /* Set the extraction length and index */
 415         attrs = ATTRELI_EL(priv->rx_stash_size) |
 416                 ATTRELI_EI(priv->rx_stash_index);
 417
 418         gfar_write(&regs->attreli, attrs);
 419
 420         /* Start with defaults, and add stashing or locking
 421          * depending on the approprate variables
 422          */
 423         attrs = ATTR_INIT_SETTINGS;
 424
 425         if (priv->bd_stash_en)
 426                 attrs |= ATTR_BDSTASH;
 427
 428         if (priv->rx_stash_size != 0)
 429                 attrs |= ATTR_BUFSTASH;
 430
 431         gfar_write(&regs->attr, attrs);
 432
 433         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 434         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 435         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 436 }
 437
 438 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 439 {
 440         struct gfar_private *priv = netdev_priv(dev);
 441         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 442         unsigned long tx_packets = 0, tx_bytes = 0;
 443         int i;
 444
 445         for (i = 0; i < priv->num_rx_queues; i++) {
 446                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 447                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 448                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 449         }
 450
 451         dev->stats.rx_packets = rx_packets;
 452         dev->stats.rx_bytes   = rx_bytes;
 453         dev->stats.rx_dropped = rx_dropped;
 454
 455         for (i = 0; i < priv->num_tx_queues; i++) {
 456                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 457                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 458         }
 459
 460         dev->stats.tx_bytes   = tx_bytes;
 461         dev->stats.tx_packets = tx_packets;
 462
 463         return &dev->stats;
 464 }
 465
 466 static const struct net_device_ops gfar_netdev_ops = {
 467         .ndo_open = gfar_enet_open,
 468         .ndo_start_xmit = gfar_start_xmit,
 469         .ndo_stop = gfar_close,
 470         .ndo_change_mtu = gfar_change_mtu,
 471         .ndo_set_features = gfar_set_features,
 472         .ndo_set_rx_mode = gfar_set_multi,
 473         .ndo_tx_timeout = gfar_timeout,
 474         .ndo_do_ioctl = gfar_ioctl,
 475         .ndo_get_stats = gfar_get_stats,
 476         .ndo_set_mac_address = eth_mac_addr,
 477         .ndo_validate_addr = eth_validate_addr,
 478 #ifdef CONFIG_NET_POLL_CONTROLLER
 479         .ndo_poll_controller = gfar_netpoll,
 480 #endif
 481 };
 482
 483 void lock_rx_qs(struct gfar_private *priv)
 484 {
 485         int i;
 486
 487         for (i = 0; i < priv->num_rx_queues; i++)
 488                 spin_lock(&priv->rx_queue[i]->rxlock);
 489 }
 490
 491 void lock_tx_qs(struct gfar_private *priv)
 492 {
 493         int i;
 494
 495         for (i = 0; i < priv->num_tx_queues; i++)
 496                 spin_lock(&priv->tx_queue[i]->txlock);
 497 }
 498
 499 void unlock_rx_qs(struct gfar_private *priv)
 500 {
 501         int i;
 502
 503         for (i = 0; i < priv->num_rx_queues; i++)
 504                 spin_unlock(&priv->rx_queue[i]->rxlock);
 505 }
 506
 507 void unlock_tx_qs(struct gfar_private *priv)
 508 {
 509         int i;
 510
 511         for (i = 0; i < priv->num_tx_queues; i++)
 512                 spin_unlock(&priv->tx_queue[i]->txlock);
 513 }
 514
 515 static void free_tx_pointers(struct gfar_private *priv)
 516 {
 517         int i;
 518
 519         for (i = 0; i < priv->num_tx_queues; i++)
 520                 kfree(priv->tx_queue[i]);
 521 }
 522
 523 static void free_rx_pointers(struct gfar_private *priv)
 524 {
 525         int i;
 526
 527         for (i = 0; i < priv->num_rx_queues; i++)
 528                 kfree(priv->rx_queue[i]);
 529 }
 530
 531 static void unmap_group_regs(struct gfar_private *priv)
 532 {
 533         int i;
 534
 535         for (i = 0; i < MAXGROUPS; i++)
 536                 if (priv->gfargrp[i].regs)
 537                         iounmap(priv->gfargrp[i].regs);
 538 }
 539
 540 static void free_gfar_dev(struct gfar_private *priv)
 541 {
 542         int i, j;
 543
 544         for (i = 0; i < priv->num_grps; i++)
 545                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 546                         kfree(priv->gfargrp[i].irqinfo[j]);
 547                         priv->gfargrp[i].irqinfo[j] = NULL;
 548                 }
 549
 550         free_netdev(priv->ndev);
 551 }
 552
 553 static void disable_napi(struct gfar_private *priv)
 554 {
 555         int i;
 556
 557         for (i = 0; i < priv->num_grps; i++)
 558                 napi_disable(&priv->gfargrp[i].napi);
 559 }
 560
 561 static void enable_napi(struct gfar_private *priv)
 562 {
 563         int i;
 564
 565         for (i = 0; i < priv->num_grps; i++)
 566                 napi_enable(&priv->gfargrp[i].napi);
 567 }
 568
 569 static int gfar_parse_group(struct device_node *np,
 570                             struct gfar_private *priv, const char *model)
 571 {
 572         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 573         u32 *queue_mask;
 574         int i;
 575
 576         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 577                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 578                                           GFP_KERNEL);
 579                 if (!grp->irqinfo[i])
 580                         return -ENOMEM;
 581         }
 582
 583         grp->regs = of_iomap(np, 0);
 584         if (!grp->regs)
 585                 return -ENOMEM;
 586
 587         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 588
 589         /* If we aren't the FEC we have multiple interrupts */
 590         if (model && strcasecmp(model, "FEC")) {
 591                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 592                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 593                 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
 594                     gfar_irq(grp, RX)->irq == NO_IRQ ||
 595                     gfar_irq(grp, ER)->irq == NO_IRQ)
 596                         return -EINVAL;
 597         }
 598
 599         grp->priv = priv;
 600         spin_lock_init(&grp->grplock);
 601         if (priv->mode == MQ_MG_MODE) {
 602                 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
 603                 grp->rx_bit_map = queue_mask ?
 604                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 605                 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
 606                 grp->tx_bit_map = queue_mask ?
 607                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 608         } else {
 609                 grp->rx_bit_map = 0xFF;
 610                 grp->tx_bit_map = 0xFF;
 611         }
 612         priv->num_grps++;
 613
 614         return 0;
 615 }
 616
 617 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 618 {
 619         const char *model;
 620         const char *ctype;
 621         const void *mac_addr;
 622         int err = 0, i;
 623         struct net_device *dev = NULL;
 624         struct gfar_private *priv = NULL;
 625         struct device_node *np = ofdev->dev.of_node;
 626         struct device_node *child = NULL;
 627         const u32 *stash;
 628         const u32 *stash_len;
 629         const u32 *stash_idx;
 630         unsigned int num_tx_qs, num_rx_qs;
 631         u32 *tx_queues, *rx_queues;
 632
 633         if (!np || !of_device_is_available(np))
 634                 return -ENODEV;
 635
 636         /* parse the num of tx and rx queues */
 637         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 638         num_tx_qs = tx_queues ? *tx_queues : 1;
 639
 640         if (num_tx_qs > MAX_TX_QS) {
 641                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 642                        num_tx_qs, MAX_TX_QS);
 643                 pr_err("Cannot do alloc_etherdev, aborting\n");
 644                 return -EINVAL;
 645         }
 646
 647         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 648         num_rx_qs = rx_queues ? *rx_queues : 1;
 649
 650         if (num_rx_qs > MAX_RX_QS) {
 651                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 652                        num_rx_qs, MAX_RX_QS);
 653                 pr_err("Cannot do alloc_etherdev, aborting\n");
 654                 return -EINVAL;
 655         }
 656
 657         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 658         dev = *pdev;
 659         if (NULL == dev)
 660                 return -ENOMEM;
 661
 662         priv = netdev_priv(dev);
 663         priv->ndev = dev;
 664
 665         priv->num_tx_queues = num_tx_qs;
 666         netif_set_real_num_rx_queues(dev, num_rx_qs);
 667         priv->num_rx_queues = num_rx_qs;
 668         priv->num_grps = 0x0;
 669
 670         /* Init Rx queue filer rule set linked list */
 671         INIT_LIST_HEAD(&priv->rx_list.list);
 672         priv->rx_list.count = 0;
 673         mutex_init(&priv->rx_queue_access);
 674
 675         model = of_get_property(np, "model", NULL);
 676
 677         for (i = 0; i < MAXGROUPS; i++)
 678                 priv->gfargrp[i].regs = NULL;
 679
 680         /* Parse and initialize group specific information */
 681         if (of_device_is_compatible(np, "fsl,etsec2")) {
 682                 priv->mode = MQ_MG_MODE;
 683                 for_each_child_of_node(np, child) {
 684                         err = gfar_parse_group(child, priv, model);
 685                         if (err)
 686                                 goto err_grp_init;
 687                 }
 688         } else {
 689                 priv->mode = SQ_SG_MODE;
 690                 err = gfar_parse_group(np, priv, model);
 691                 if (err)
 692                         goto err_grp_init;
 693         }
 694
 695         for (i = 0; i < priv->num_tx_queues; i++)
 696                 priv->tx_queue[i] = NULL;
 697         for (i = 0; i < priv->num_rx_queues; i++)
 698                 priv->rx_queue[i] = NULL;
 699
 700         for (i = 0; i < priv->num_tx_queues; i++) {
 701                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 702                                             GFP_KERNEL);
 703                 if (!priv->tx_queue[i]) {
 704                         err = -ENOMEM;
 705                         goto tx_alloc_failed;
 706                 }
 707                 priv->tx_queue[i]->tx_skbuff = NULL;
 708                 priv->tx_queue[i]->qindex = i;
 709                 priv->tx_queue[i]->dev = dev;
 710                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 711         }
 712
 713         for (i = 0; i < priv->num_rx_queues; i++) {
 714                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 715                                             GFP_KERNEL);
 716                 if (!priv->rx_queue[i]) {
 717                         err = -ENOMEM;
 718                         goto rx_alloc_failed;
 719                 }
 720                 priv->rx_queue[i]->rx_skbuff = NULL;
 721                 priv->rx_queue[i]->qindex = i;
 722                 priv->rx_queue[i]->dev = dev;
 723                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 724         }
 725
 726
 727         stash = of_get_property(np, "bd-stash", NULL);
 728
 729         if (stash) {
 730                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 731                 priv->bd_stash_en = 1;
 732         }
 733
 734         stash_len = of_get_property(np, "rx-stash-len", NULL);
 735
 736         if (stash_len)
 737                 priv->rx_stash_size = *stash_len;
 738
 739         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 740
 741         if (stash_idx)
 742                 priv->rx_stash_index = *stash_idx;
 743
 744         if (stash_len || stash_idx)
 745                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 746
 747         mac_addr = of_get_mac_address(np);
 748
 749         if (mac_addr)
 750                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 751
 752         if (model && !strcasecmp(model, "TSEC"))
 753                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 754                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 755                                      FSL_GIANFAR_DEV_HAS_RMON |
 756                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 757
 758         if (model && !strcasecmp(model, "eTSEC"))
 759                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 760                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 761                                      FSL_GIANFAR_DEV_HAS_RMON |
 762                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 763                                      FSL_GIANFAR_DEV_HAS_PADDING |
 764                                      FSL_GIANFAR_DEV_HAS_CSUM |
 765                                      FSL_GIANFAR_DEV_HAS_VLAN |
 766                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 767                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 768                                      FSL_GIANFAR_DEV_HAS_TIMER;
 769
 770         ctype = of_get_property(np, "phy-connection-type", NULL);
 771
 772         /* We only care about rgmii-id.  The rest are autodetected */
 773         if (ctype && !strcmp(ctype, "rgmii-id"))
 774                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 775         else
 776                 priv->interface = PHY_INTERFACE_MODE_MII;
 777
 778         if (of_get_property(np, "fsl,magic-packet", NULL))
 779                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 780
 781         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 782
 783         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 784         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 785
 786         return 0;
 787
 788 rx_alloc_failed:
 789         free_rx_pointers(priv);
 790 tx_alloc_failed:
 791         free_tx_pointers(priv);
 792 err_grp_init:
 793         unmap_group_regs(priv);
 794         free_gfar_dev(priv);
 795         return err;
 796 }
 797
 798 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
 799 {
 800         struct hwtstamp_config config;
 801         struct gfar_private *priv = netdev_priv(netdev);
 802
 803         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 804                 return -EFAULT;
 805
 806         /* reserved for future extensions */
 807         if (config.flags)
 808                 return -EINVAL;
 809
 810         switch (config.tx_type) {
 811         case HWTSTAMP_TX_OFF:
 812                 priv->hwts_tx_en = 0;
 813                 break;
 814         case HWTSTAMP_TX_ON:
 815                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 816                         return -ERANGE;
 817                 priv->hwts_tx_en = 1;
 818                 break;
 819         default:
 820                 return -ERANGE;
 821         }
 822
 823         switch (config.rx_filter) {
 824         case HWTSTAMP_FILTER_NONE:
 825                 if (priv->hwts_rx_en) {
 826                         stop_gfar(netdev);
 827                         priv->hwts_rx_en = 0;
 828                         startup_gfar(netdev);
 829                 }
 830                 break;
 831         default:
 832                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 833                         return -ERANGE;
 834                 if (!priv->hwts_rx_en) {
 835                         stop_gfar(netdev);
 836                         priv->hwts_rx_en = 1;
 837                         startup_gfar(netdev);
 838                 }
 839                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 840                 break;
 841         }
 842
 843         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 844                 -EFAULT : 0;
 845 }
 846
 847 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
 848 {
 849         struct hwtstamp_config config;
 850         struct gfar_private *priv = netdev_priv(netdev);
 851
 852         config.flags = 0;
 853         config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
 854         config.rx_filter = (priv->hwts_rx_en ?
 855                             HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
 856
 857         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 858                 -EFAULT : 0;
 859 }
 860
 861 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 862 {
 863         struct gfar_private *priv = netdev_priv(dev);
 864
 865         if (!netif_running(dev))
 866                 return -EINVAL;
 867
 868         if (cmd == SIOCSHWTSTAMP)
 869                 return gfar_hwtstamp_set(dev, rq);
 870         if (cmd == SIOCGHWTSTAMP)
 871                 return gfar_hwtstamp_get(dev, rq);
 872
 873         if (!priv->phydev)
 874                 return -ENODEV;
 875
 876         return phy_mii_ioctl(priv->phydev, rq, cmd);
 877 }
 878
 879 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 880 {
 881         unsigned int new_bit_map = 0x0;
 882         int mask = 0x1 << (max_qs - 1), i;
 883
 884         for (i = 0; i < max_qs; i++) {
 885                 if (bit_map & mask)
 886                         new_bit_map = new_bit_map + (1 << i);
 887                 mask = mask >> 0x1;
 888         }
 889         return new_bit_map;
 890 }
 891
 892 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 893                                    u32 class)
 894 {
 895         u32 rqfpr = FPR_FILER_MASK;
 896         u32 rqfcr = 0x0;
 897
 898         rqfar--;
 899         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 900         priv->ftp_rqfpr[rqfar] = rqfpr;
 901         priv->ftp_rqfcr[rqfar] = rqfcr;
 902         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 903
 904         rqfar--;
 905         rqfcr = RQFCR_CMP_NOMATCH;
 906         priv->ftp_rqfpr[rqfar] = rqfpr;
 907         priv->ftp_rqfcr[rqfar] = rqfcr;
 908         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 909
 910         rqfar--;
 911         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 912         rqfpr = class;
 913         priv->ftp_rqfcr[rqfar] = rqfcr;
 914         priv->ftp_rqfpr[rqfar] = rqfpr;
 915         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 916
 917         rqfar--;
 918         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 919         rqfpr = class;
 920         priv->ftp_rqfcr[rqfar] = rqfcr;
 921         priv->ftp_rqfpr[rqfar] = rqfpr;
 922         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 923
 924         return rqfar;
 925 }
 926
 927 static void gfar_init_filer_table(struct gfar_private *priv)
 928 {
 929         int i = 0x0;
 930         u32 rqfar = MAX_FILER_IDX;
 931         u32 rqfcr = 0x0;
 932         u32 rqfpr = FPR_FILER_MASK;
 933
 934         /* Default rule */
 935         rqfcr = RQFCR_CMP_MATCH;
 936         priv->ftp_rqfcr[rqfar] = rqfcr;
 937         priv->ftp_rqfpr[rqfar] = rqfpr;
 938         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 939
 940         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 941         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 942         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 943         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 944         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 945         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 946
 947         /* cur_filer_idx indicated the first non-masked rule */
 948         priv->cur_filer_idx = rqfar;
 949
 950         /* Rest are masked rules */
 951         rqfcr = RQFCR_CMP_NOMATCH;
 952         for (i = 0; i < rqfar; i++) {
 953                 priv->ftp_rqfcr[i] = rqfcr;
 954                 priv->ftp_rqfpr[i] = rqfpr;
 955                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 956         }
 957 }
 958
 959 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
 960 {
 961         unsigned int pvr = mfspr(SPRN_PVR);
 962         unsigned int svr = mfspr(SPRN_SVR);
 963         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 964         unsigned int rev = svr & 0xffff;
 965
 966         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 967         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 968             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 969                 priv->errata |= GFAR_ERRATA_74;
 970
 971         /* MPC8313 and MPC837x all rev */
 972         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 973             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 974                 priv->errata |= GFAR_ERRATA_76;
 975
 976         /* MPC8313 Rev < 2.0 */
 977         if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
 978                 priv->errata |= GFAR_ERRATA_12;
 979 }
 980
 981 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
 982 {
 983         unsigned int svr = mfspr(SPRN_SVR);
 984
 985         if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
 986                 priv->errata |= GFAR_ERRATA_12;
 987         if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
 988             ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
 989                 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
 990 }
 991
 992 static void gfar_detect_errata(struct gfar_private *priv)
 993 {
 994         struct device *dev = &priv->ofdev->dev;
 995
 996         /* no plans to fix */
 997         priv->errata |= GFAR_ERRATA_A002;
 998
 999         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1000                 __gfar_detect_errata_85xx(priv);
1001         else /* non-mpc85xx parts, i.e. e300 core based */
1002                 __gfar_detect_errata_83xx(priv);
1003
1004         if (priv->errata)
1005                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1006                          priv->errata);
1007 }
1008
1009 /* Set up the ethernet device structure, private data,
1010  * and anything else we need before we start
1011  */
1012 static int gfar_probe(struct platform_device *ofdev)
1013 {
1014         u32 tempval;
1015         struct net_device *dev = NULL;
1016         struct gfar_private *priv = NULL;
1017         struct gfar __iomem *regs = NULL;
1018         int err = 0, i, grp_idx = 0;
1019         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
1020         u32 isrg = 0;
1021         u32 __iomem *baddr;
1022
1023         err = gfar_of_init(ofdev, &dev);
1024
1025         if (err)
1026                 return err;
1027
1028         priv = netdev_priv(dev);
1029         priv->ndev = dev;
1030         priv->ofdev = ofdev;
1031         priv->dev = &ofdev->dev;
1032         SET_NETDEV_DEV(dev, &ofdev->dev);
1033
1034         spin_lock_init(&priv->bflock);
1035         INIT_WORK(&priv->reset_task, gfar_reset_task);
1036
1037         platform_set_drvdata(ofdev, priv);
1038         regs = priv->gfargrp[0].regs;
1039
1040         gfar_detect_errata(priv);
1041
1042         /* Stop the DMA engine now, in case it was running before
1043          * (The firmware could have used it, and left it running).
1044          */
1045         gfar_halt(dev);
1046
1047         /* Reset MAC layer */
1048         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1049
1050         /* We need to delay at least 3 TX clocks */
1051         udelay(2);
1052
1053         tempval = 0;
1054         if (!priv->pause_aneg_en && priv->tx_pause_en)
1055                 tempval |= MACCFG1_TX_FLOW;
1056         if (!priv->pause_aneg_en && priv->rx_pause_en)
1057                 tempval |= MACCFG1_RX_FLOW;
1058         /* the soft reset bit is not self-resetting, so we need to
1059          * clear it before resuming normal operation
1060          */
1061         gfar_write(&regs->maccfg1, tempval);
1062
1063         /* Initialize MACCFG2. */
1064         tempval = MACCFG2_INIT_SETTINGS;
1065         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1066                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1067         gfar_write(&regs->maccfg2, tempval);
1068
1069         /* Initialize ECNTRL */
1070         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1071
1072         /* Set the dev->base_addr to the gfar reg region */
1073         dev->base_addr = (unsigned long) regs;
1074
1075         /* Fill in the dev structure */
1076         dev->watchdog_timeo = TX_TIMEOUT;
1077         dev->mtu = 1500;
1078         dev->netdev_ops = &gfar_netdev_ops;
1079         dev->ethtool_ops = &gfar_ethtool_ops;
1080
1081         /* Register for napi ...We are registering NAPI for each grp */
1082         if (priv->mode == SQ_SG_MODE)
1083                 netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq,
1084                                GFAR_DEV_WEIGHT);
1085         else
1086                 for (i = 0; i < priv->num_grps; i++)
1087                         netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1088                                        GFAR_DEV_WEIGHT);
1089
1090         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1091                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1092                                    NETIF_F_RXCSUM;
1093                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1094                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1095         }
1096
1097         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1098                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1099                                     NETIF_F_HW_VLAN_CTAG_RX;
1100                 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1101         }
1102
1103         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1104                 priv->extended_hash = 1;
1105                 priv->hash_width = 9;
1106
1107                 priv->hash_regs[0] = &regs->igaddr0;
1108                 priv->hash_regs[1] = &regs->igaddr1;
1109                 priv->hash_regs[2] = &regs->igaddr2;
1110                 priv->hash_regs[3] = &regs->igaddr3;
1111                 priv->hash_regs[4] = &regs->igaddr4;
1112                 priv->hash_regs[5] = &regs->igaddr5;
1113                 priv->hash_regs[6] = &regs->igaddr6;
1114                 priv->hash_regs[7] = &regs->igaddr7;
1115                 priv->hash_regs[8] = &regs->gaddr0;
1116                 priv->hash_regs[9] = &regs->gaddr1;
1117                 priv->hash_regs[10] = &regs->gaddr2;
1118                 priv->hash_regs[11] = &regs->gaddr3;
1119                 priv->hash_regs[12] = &regs->gaddr4;
1120                 priv->hash_regs[13] = &regs->gaddr5;
1121                 priv->hash_regs[14] = &regs->gaddr6;
1122                 priv->hash_regs[15] = &regs->gaddr7;
1123
1124         } else {
1125                 priv->extended_hash = 0;
1126                 priv->hash_width = 8;
1127
1128                 priv->hash_regs[0] = &regs->gaddr0;
1129                 priv->hash_regs[1] = &regs->gaddr1;
1130                 priv->hash_regs[2] = &regs->gaddr2;
1131                 priv->hash_regs[3] = &regs->gaddr3;
1132                 priv->hash_regs[4] = &regs->gaddr4;
1133                 priv->hash_regs[5] = &regs->gaddr5;
1134                 priv->hash_regs[6] = &regs->gaddr6;
1135                 priv->hash_regs[7] = &regs->gaddr7;
1136         }
1137
1138         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1139                 priv->padding = DEFAULT_PADDING;
1140         else
1141                 priv->padding = 0;
1142
1143         if (dev->features & NETIF_F_IP_CSUM ||
1144             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1145                 dev->needed_headroom = GMAC_FCB_LEN;
1146
1147         /* Program the isrg regs only if number of grps > 1 */
1148         if (priv->num_grps > 1) {
1149                 baddr = &regs->isrg0;
1150                 for (i = 0; i < priv->num_grps; i++) {
1151                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1152                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1153                         gfar_write(baddr, isrg);
1154                         baddr++;
1155                         isrg = 0x0;
1156                 }
1157         }
1158
1159         /* Need to reverse the bit maps as  bit_map's MSB is q0
1160          * but, for_each_set_bit parses from right to left, which
1161          * basically reverses the queue numbers
1162          */
1163         for (i = 0; i< priv->num_grps; i++) {
1164                 priv->gfargrp[i].tx_bit_map =
1165                         reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1166                 priv->gfargrp[i].rx_bit_map =
1167                         reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1168         }
1169
1170         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1171          * also assign queues to groups
1172          */
1173         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1174                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1175
1176                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1177                                  priv->num_rx_queues) {
1178                         priv->gfargrp[grp_idx].num_rx_queues++;
1179                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1180                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1181                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1182                 }
1183                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1184
1185                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1186                                  priv->num_tx_queues) {
1187                         priv->gfargrp[grp_idx].num_tx_queues++;
1188                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1189                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1190                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1191                 }
1192                 priv->gfargrp[grp_idx].rstat = rstat;
1193                 priv->gfargrp[grp_idx].tstat = tstat;
1194                 rstat = tstat =0;
1195         }
1196
1197         gfar_write(&regs->rqueue, rqueue);
1198         gfar_write(&regs->tqueue, tqueue);
1199
1200         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1201
1202         /* Initializing some of the rx/tx queue level parameters */
1203         for (i = 0; i < priv->num_tx_queues; i++) {
1204                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1205                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1206                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1207                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1208         }
1209
1210         for (i = 0; i < priv->num_rx_queues; i++) {
1211                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1212                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1213                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1214         }
1215
1216         /* always enable rx filer */
1217         priv->rx_filer_enable = 1;
1218         /* Enable most messages by default */
1219         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1220         /* use pritority h/w tx queue scheduling for single queue devices */
1221         if (priv->num_tx_queues == 1)
1222                 priv->prio_sched_en = 1;
1223
1224         /* Carrier starts down, phylib will bring it up */
1225         netif_carrier_off(dev);
1226
1227         err = register_netdev(dev);
1228
1229         if (err) {
1230                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1231                 goto register_fail;
1232         }
1233
1234         device_init_wakeup(&dev->dev,
1235                            priv->device_flags &
1236                            FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1237
1238         /* fill out IRQ number and name fields */
1239         for (i = 0; i < priv->num_grps; i++) {
1240                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1241                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1242                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1243                                 dev->name, "_g", '0' + i, "_tx");
1244                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1245                                 dev->name, "_g", '0' + i, "_rx");
1246                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1247                                 dev->name, "_g", '0' + i, "_er");
1248                 } else
1249                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1250         }
1251
1252         /* Initialize the filer table */
1253         gfar_init_filer_table(priv);
1254
1255         /* Create all the sysfs files */
1256         gfar_init_sysfs(dev);
1257
1258         /* Print out the device info */
1259         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1260
1261         /* Even more device info helps when determining which kernel
1262          * provided which set of benchmarks.
1263          */
1264         netdev_info(dev, "Running with NAPI enabled\n");
1265         for (i = 0; i < priv->num_rx_queues; i++)
1266                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1267                             i, priv->rx_queue[i]->rx_ring_size);
1268         for (i = 0; i < priv->num_tx_queues; i++)
1269                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1270                             i, priv->tx_queue[i]->tx_ring_size);
1271
1272         return 0;
1273
1274 register_fail:
1275         unmap_group_regs(priv);
1276         free_tx_pointers(priv);
1277         free_rx_pointers(priv);
1278         if (priv->phy_node)
1279                 of_node_put(priv->phy_node);
1280         if (priv->tbi_node)
1281                 of_node_put(priv->tbi_node);
1282         free_gfar_dev(priv);
1283         return err;
1284 }
1285
1286 static int gfar_remove(struct platform_device *ofdev)
1287 {
1288         struct gfar_private *priv = platform_get_drvdata(ofdev);
1289
1290         if (priv->phy_node)
1291                 of_node_put(priv->phy_node);
1292         if (priv->tbi_node)
1293                 of_node_put(priv->tbi_node);
1294
1295         unregister_netdev(priv->ndev);
1296         unmap_group_regs(priv);
1297         free_gfar_dev(priv);
1298
1299         return 0;
1300 }
1301
1302 #ifdef CONFIG_PM
1303
1304 static int gfar_suspend(struct device *dev)
1305 {
1306         struct gfar_private *priv = dev_get_drvdata(dev);
1307         struct net_device *ndev = priv->ndev;
1308         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1309         unsigned long flags;
1310         u32 tempval;
1311
1312         int magic_packet = priv->wol_en &&
1313                            (priv->device_flags &
1314                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1315
1316         netif_device_detach(ndev);
1317
1318         if (netif_running(ndev)) {
1319
1320                 local_irq_save(flags);
1321                 lock_tx_qs(priv);
1322                 lock_rx_qs(priv);
1323
1324                 gfar_halt_nodisable(ndev);
1325
1326                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1327                 tempval = gfar_read(&regs->maccfg1);
1328
1329                 tempval &= ~MACCFG1_TX_EN;
1330
1331                 if (!magic_packet)
1332                         tempval &= ~MACCFG1_RX_EN;
1333
1334                 gfar_write(&regs->maccfg1, tempval);
1335
1336                 unlock_rx_qs(priv);
1337                 unlock_tx_qs(priv);
1338                 local_irq_restore(flags);
1339
1340                 disable_napi(priv);
1341
1342                 if (magic_packet) {
1343                         /* Enable interrupt on Magic Packet */
1344                         gfar_write(&regs->imask, IMASK_MAG);
1345
1346                         /* Enable Magic Packet mode */
1347                         tempval = gfar_read(&regs->maccfg2);
1348                         tempval |= MACCFG2_MPEN;
1349                         gfar_write(&regs->maccfg2, tempval);
1350                 } else {
1351                         phy_stop(priv->phydev);
1352                 }
1353         }
1354
1355         return 0;
1356 }
1357
1358 static int gfar_resume(struct device *dev)
1359 {
1360         struct gfar_private *priv = dev_get_drvdata(dev);
1361         struct net_device *ndev = priv->ndev;
1362         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1363         unsigned long flags;
1364         u32 tempval;
1365         int magic_packet = priv->wol_en &&
1366                            (priv->device_flags &
1367                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1368
1369         if (!netif_running(ndev)) {
1370                 netif_device_attach(ndev);
1371                 return 0;
1372         }
1373
1374         if (!magic_packet && priv->phydev)
1375                 phy_start(priv->phydev);
1376
1377         /* Disable Magic Packet mode, in case something
1378          * else woke us up.
1379          */
1380         local_irq_save(flags);
1381         lock_tx_qs(priv);
1382         lock_rx_qs(priv);
1383
1384         tempval = gfar_read(&regs->maccfg2);
1385         tempval &= ~MACCFG2_MPEN;
1386         gfar_write(&regs->maccfg2, tempval);
1387
1388         gfar_start(ndev);
1389
1390         unlock_rx_qs(priv);
1391         unlock_tx_qs(priv);
1392         local_irq_restore(flags);
1393
1394         netif_device_attach(ndev);
1395
1396         enable_napi(priv);
1397
1398         return 0;
1399 }
1400
1401 static int gfar_restore(struct device *dev)
1402 {
1403         struct gfar_private *priv = dev_get_drvdata(dev);
1404         struct net_device *ndev = priv->ndev;
1405
1406         if (!netif_running(ndev)) {
1407                 netif_device_attach(ndev);
1408
1409                 return 0;
1410         }
1411
1412         if (gfar_init_bds(ndev)) {
1413                 free_skb_resources(priv);
1414                 return -ENOMEM;
1415         }
1416
1417         init_registers(ndev);
1418         gfar_set_mac_address(ndev);
1419         gfar_init_mac(ndev);
1420         gfar_start(ndev);
1421
1422         priv->oldlink = 0;
1423         priv->oldspeed = 0;
1424         priv->oldduplex = -1;
1425
1426         if (priv->phydev)
1427                 phy_start(priv->phydev);
1428
1429         netif_device_attach(ndev);
1430         enable_napi(priv);
1431
1432         return 0;
1433 }
1434
1435 static struct dev_pm_ops gfar_pm_ops = {
1436         .suspend = gfar_suspend,
1437         .resume = gfar_resume,
1438         .freeze = gfar_suspend,
1439         .thaw = gfar_resume,
1440         .restore = gfar_restore,
1441 };
1442
1443 #define GFAR_PM_OPS (&gfar_pm_ops)
1444
1445 #else
1446
1447 #define GFAR_PM_OPS NULL
1448
1449 #endif
1450
1451 /* Reads the controller's registers to determine what interface
1452  * connects it to the PHY.
1453  */
1454 static phy_interface_t gfar_get_interface(struct net_device *dev)
1455 {
1456         struct gfar_private *priv = netdev_priv(dev);
1457         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1458         u32 ecntrl;
1459
1460         ecntrl = gfar_read(&regs->ecntrl);
1461
1462         if (ecntrl & ECNTRL_SGMII_MODE)
1463                 return PHY_INTERFACE_MODE_SGMII;
1464
1465         if (ecntrl & ECNTRL_TBI_MODE) {
1466                 if (ecntrl & ECNTRL_REDUCED_MODE)
1467                         return PHY_INTERFACE_MODE_RTBI;
1468                 else
1469                         return PHY_INTERFACE_MODE_TBI;
1470         }
1471
1472         if (ecntrl & ECNTRL_REDUCED_MODE) {
1473                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1474                         return PHY_INTERFACE_MODE_RMII;
1475                 }
1476                 else {
1477                         phy_interface_t interface = priv->interface;
1478
1479                         /* This isn't autodetected right now, so it must
1480                          * be set by the device tree or platform code.
1481                          */
1482                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1483                                 return PHY_INTERFACE_MODE_RGMII_ID;
1484
1485                         return PHY_INTERFACE_MODE_RGMII;
1486                 }
1487         }
1488
1489         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1490                 return PHY_INTERFACE_MODE_GMII;
1491
1492         return PHY_INTERFACE_MODE_MII;
1493 }
1494
1495
1496 /* Initializes driver's PHY state, and attaches to the PHY.
1497  * Returns 0 on success.
1498  */
1499 static int init_phy(struct net_device *dev)
1500 {
1501         struct gfar_private *priv = netdev_priv(dev);
1502         uint gigabit_support =
1503                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1504                 GFAR_SUPPORTED_GBIT : 0;
1505         phy_interface_t interface;
1506
1507         priv->oldlink = 0;
1508         priv->oldspeed = 0;
1509         priv->oldduplex = -1;
1510
1511         interface = gfar_get_interface(dev);
1512
1513         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1514                                       interface);
1515         if (!priv->phydev)
1516                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1517                                                          interface);
1518         if (!priv->phydev) {
1519                 dev_err(&dev->dev, "could not attach to PHY\n");
1520                 return -ENODEV;
1521         }
1522
1523         if (interface == PHY_INTERFACE_MODE_SGMII)
1524                 gfar_configure_serdes(dev);
1525
1526         /* Remove any features not supported by the controller */
1527         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1528         priv->phydev->advertising = priv->phydev->supported;
1529
1530         return 0;
1531 }
1532
1533 /* Initialize TBI PHY interface for communicating with the
1534  * SERDES lynx PHY on the chip.  We communicate with this PHY
1535  * through the MDIO bus on each controller, treating it as a
1536  * "normal" PHY at the address found in the TBIPA register.  We assume
1537  * that the TBIPA register is valid.  Either the MDIO bus code will set
1538  * it to a value that doesn't conflict with other PHYs on the bus, or the
1539  * value doesn't matter, as there are no other PHYs on the bus.
1540  */
1541 static void gfar_configure_serdes(struct net_device *dev)
1542 {
1543         struct gfar_private *priv = netdev_priv(dev);
1544         struct phy_device *tbiphy;
1545
1546         if (!priv->tbi_node) {
1547                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1548                                     "device tree specify a tbi-handle\n");
1549                 return;
1550         }
1551
1552         tbiphy = of_phy_find_device(priv->tbi_node);
1553         if (!tbiphy) {
1554                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1555                 return;
1556         }
1557
1558         /* If the link is already up, we must already be ok, and don't need to
1559          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1560          * everything for us?  Resetting it takes the link down and requires
1561          * several seconds for it to come back.
1562          */
1563         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1564                 return;
1565
1566         /* Single clk mode, mii mode off(for serdes communication) */
1567         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1568
1569         phy_write(tbiphy, MII_ADVERTISE,
1570                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1571                   ADVERTISE_1000XPSE_ASYM);
1572
1573         phy_write(tbiphy, MII_BMCR,
1574                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1575                   BMCR_SPEED1000);
1576 }
1577
1578 static void init_registers(struct net_device *dev)
1579 {
1580         struct gfar_private *priv = netdev_priv(dev);
1581         struct gfar __iomem *regs = NULL;
1582         int i;
1583
1584         for (i = 0; i < priv->num_grps; i++) {
1585                 regs = priv->gfargrp[i].regs;
1586                 /* Clear IEVENT */
1587                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1588
1589                 /* Initialize IMASK */
1590                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1591         }
1592
1593         regs = priv->gfargrp[0].regs;
1594         /* Init hash registers to zero */
1595         gfar_write(&regs->igaddr0, 0);
1596         gfar_write(&regs->igaddr1, 0);
1597         gfar_write(&regs->igaddr2, 0);
1598         gfar_write(&regs->igaddr3, 0);
1599         gfar_write(&regs->igaddr4, 0);
1600         gfar_write(&regs->igaddr5, 0);
1601         gfar_write(&regs->igaddr6, 0);
1602         gfar_write(&regs->igaddr7, 0);
1603
1604         gfar_write(&regs->gaddr0, 0);
1605         gfar_write(&regs->gaddr1, 0);
1606         gfar_write(&regs->gaddr2, 0);
1607         gfar_write(&regs->gaddr3, 0);
1608         gfar_write(&regs->gaddr4, 0);
1609         gfar_write(&regs->gaddr5, 0);
1610         gfar_write(&regs->gaddr6, 0);
1611         gfar_write(&regs->gaddr7, 0);
1612
1613         /* Zero out the rmon mib registers if it has them */
1614         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1615                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1616
1617                 /* Mask off the CAM interrupts */
1618                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1619                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1620         }
1621
1622         /* Initialize the max receive buffer length */
1623         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1624
1625         /* Initialize the Minimum Frame Length Register */
1626         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1627 }
1628
1629 static int __gfar_is_rx_idle(struct gfar_private *priv)
1630 {
1631         u32 res;
1632
1633         /* Normaly TSEC should not hang on GRS commands, so we should
1634          * actually wait for IEVENT_GRSC flag.
1635          */
1636         if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1637                 return 0;
1638
1639         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1640          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1641          * and the Rx can be safely reset.
1642          */
1643         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1644         res &= 0x7f807f80;
1645         if ((res & 0xffff) == (res >> 16))
1646                 return 1;
1647
1648         return 0;
1649 }
1650
1651 /* Halt the receive and transmit queues */
1652 static void gfar_halt_nodisable(struct net_device *dev)
1653 {
1654         struct gfar_private *priv = netdev_priv(dev);
1655         struct gfar __iomem *regs = NULL;
1656         u32 tempval;
1657         int i;
1658
1659         for (i = 0; i < priv->num_grps; i++) {
1660                 regs = priv->gfargrp[i].regs;
1661                 /* Mask all interrupts */
1662                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1663
1664                 /* Clear all interrupts */
1665                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1666         }
1667
1668         regs = priv->gfargrp[0].regs;
1669         /* Stop the DMA, and wait for it to stop */
1670         tempval = gfar_read(&regs->dmactrl);
1671         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1672             (DMACTRL_GRS | DMACTRL_GTS)) {
1673                 int ret;
1674
1675                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1676                 gfar_write(&regs->dmactrl, tempval);
1677
1678                 do {
1679                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1680                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1681                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1682                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1683                                 ret = __gfar_is_rx_idle(priv);
1684                 } while (!ret);
1685         }
1686 }
1687
1688 /* Halt the receive and transmit queues */
1689 void gfar_halt(struct net_device *dev)
1690 {
1691         struct gfar_private *priv = netdev_priv(dev);
1692         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1693         u32 tempval;
1694
1695         gfar_halt_nodisable(dev);
1696
1697         /* Disable Rx and Tx */
1698         tempval = gfar_read(&regs->maccfg1);
1699         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1700         gfar_write(&regs->maccfg1, tempval);
1701 }
1702
1703 static void free_grp_irqs(struct gfar_priv_grp *grp)
1704 {
1705         free_irq(gfar_irq(grp, TX)->irq, grp);
1706         free_irq(gfar_irq(grp, RX)->irq, grp);
1707         free_irq(gfar_irq(grp, ER)->irq, grp);
1708 }
1709
1710 void stop_gfar(struct net_device *dev)
1711 {
1712         struct gfar_private *priv = netdev_priv(dev);
1713         unsigned long flags;
1714         int i;
1715
1716         phy_stop(priv->phydev);
1717
1718
1719         /* Lock it down */
1720         local_irq_save(flags);
1721         lock_tx_qs(priv);
1722         lock_rx_qs(priv);
1723
1724         gfar_halt(dev);
1725
1726         unlock_rx_qs(priv);
1727         unlock_tx_qs(priv);
1728         local_irq_restore(flags);
1729
1730         /* Free the IRQs */
1731         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1732                 for (i = 0; i < priv->num_grps; i++)
1733                         free_grp_irqs(&priv->gfargrp[i]);
1734         } else {
1735                 for (i = 0; i < priv->num_grps; i++)
1736                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
1737                                  &priv->gfargrp[i]);
1738         }
1739
1740         free_skb_resources(priv);
1741 }
1742
1743 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1744 {
1745         struct txbd8 *txbdp;
1746         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1747         int i, j;
1748
1749         txbdp = tx_queue->tx_bd_base;
1750
1751         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1752                 if (!tx_queue->tx_skbuff[i])
1753                         continue;
1754
1755                 dma_unmap_single(priv->dev, txbdp->bufPtr,
1756                                  txbdp->length, DMA_TO_DEVICE);
1757                 txbdp->lstatus = 0;
1758                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1759                      j++) {
1760                         txbdp++;
1761                         dma_unmap_page(priv->dev, txbdp->bufPtr,
1762                                        txbdp->length, DMA_TO_DEVICE);
1763                 }
1764                 txbdp++;
1765                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1766                 tx_queue->tx_skbuff[i] = NULL;
1767         }
1768         kfree(tx_queue->tx_skbuff);
1769         tx_queue->tx_skbuff = NULL;
1770 }
1771
1772 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1773 {
1774         struct rxbd8 *rxbdp;
1775         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1776         int i;
1777
1778         rxbdp = rx_queue->rx_bd_base;
1779
1780         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1781                 if (rx_queue->rx_skbuff[i]) {
1782                         dma_unmap_single(priv->dev, rxbdp->bufPtr,
1783                                          priv->rx_buffer_size,
1784                                          DMA_FROM_DEVICE);
1785                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1786                         rx_queue->rx_skbuff[i] = NULL;
1787                 }
1788                 rxbdp->lstatus = 0;
1789                 rxbdp->bufPtr = 0;
1790                 rxbdp++;
1791         }
1792         kfree(rx_queue->rx_skbuff);
1793         rx_queue->rx_skbuff = NULL;
1794 }
1795
1796 /* If there are any tx skbs or rx skbs still around, free them.
1797  * Then free tx_skbuff and rx_skbuff
1798  */
1799 static void free_skb_resources(struct gfar_private *priv)
1800 {
1801         struct gfar_priv_tx_q *tx_queue = NULL;
1802         struct gfar_priv_rx_q *rx_queue = NULL;
1803         int i;
1804
1805         /* Go through all the buffer descriptors and free their data buffers */
1806         for (i = 0; i < priv->num_tx_queues; i++) {
1807                 struct netdev_queue *txq;
1808
1809                 tx_queue = priv->tx_queue[i];
1810                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1811                 if (tx_queue->tx_skbuff)
1812                         free_skb_tx_queue(tx_queue);
1813                 netdev_tx_reset_queue(txq);
1814         }
1815
1816         for (i = 0; i < priv->num_rx_queues; i++) {
1817                 rx_queue = priv->rx_queue[i];
1818                 if (rx_queue->rx_skbuff)
1819                         free_skb_rx_queue(rx_queue);
1820         }
1821
1822         dma_free_coherent(priv->dev,
1823                           sizeof(struct txbd8) * priv->total_tx_ring_size +
1824                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
1825                           priv->tx_queue[0]->tx_bd_base,
1826                           priv->tx_queue[0]->tx_bd_dma_base);
1827 }
1828
1829 void gfar_start(struct net_device *dev)
1830 {
1831         struct gfar_private *priv = netdev_priv(dev);
1832         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1833         u32 tempval;
1834         int i = 0;
1835
1836         /* Enable Rx and Tx in MACCFG1 */
1837         tempval = gfar_read(&regs->maccfg1);
1838         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1839         gfar_write(&regs->maccfg1, tempval);
1840
1841         /* Initialize DMACTRL to have WWR and WOP */
1842         tempval = gfar_read(&regs->dmactrl);
1843         tempval |= DMACTRL_INIT_SETTINGS;
1844         gfar_write(&regs->dmactrl, tempval);
1845
1846         /* Make sure we aren't stopped */
1847         tempval = gfar_read(&regs->dmactrl);
1848         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1849         gfar_write(&regs->dmactrl, tempval);
1850
1851         for (i = 0; i < priv->num_grps; i++) {
1852                 regs = priv->gfargrp[i].regs;
1853                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1854                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1855                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1856                 /* Unmask the interrupts we look for */
1857                 gfar_write(&regs->imask, IMASK_DEFAULT);
1858         }
1859
1860         dev->trans_start = jiffies; /* prevent tx timeout */
1861 }
1862
1863 static void gfar_configure_coalescing(struct gfar_private *priv,
1864                                unsigned long tx_mask, unsigned long rx_mask)
1865 {
1866         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1867         u32 __iomem *baddr;
1868
1869         if (priv->mode == MQ_MG_MODE) {
1870                 int i = 0;
1871
1872                 baddr = &regs->txic0;
1873                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1874                         gfar_write(baddr + i, 0);
1875                         if (likely(priv->tx_queue[i]->txcoalescing))
1876                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1877                 }
1878
1879                 baddr = &regs->rxic0;
1880                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1881                         gfar_write(baddr + i, 0);
1882                         if (likely(priv->rx_queue[i]->rxcoalescing))
1883                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1884                 }
1885         } else {
1886                 /* Backward compatible case -- even if we enable
1887                  * multiple queues, there's only single reg to program
1888                  */
1889                 gfar_write(&regs->txic, 0);
1890                 if (likely(priv->tx_queue[0]->txcoalescing))
1891                         gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1892
1893                 gfar_write(&regs->rxic, 0);
1894                 if (unlikely(priv->rx_queue[0]->rxcoalescing))
1895                         gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1896         }
1897 }
1898
1899 void gfar_configure_coalescing_all(struct gfar_private *priv)
1900 {
1901         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1902 }
1903
1904 static int register_grp_irqs(struct gfar_priv_grp *grp)
1905 {
1906         struct gfar_private *priv = grp->priv;
1907         struct net_device *dev = priv->ndev;
1908         int err;
1909
1910         /* If the device has multiple interrupts, register for
1911          * them.  Otherwise, only register for the one
1912          */
1913         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1914                 /* Install our interrupt handlers for Error,
1915                  * Transmit, and Receive
1916                  */
1917                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1918                                   gfar_irq(grp, ER)->name, grp);
1919                 if (err < 0) {
1920                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1921                                   gfar_irq(grp, ER)->irq);
1922
1923                         goto err_irq_fail;
1924                 }
1925                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1926                                   gfar_irq(grp, TX)->name, grp);
1927                 if (err < 0) {
1928                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1929                                   gfar_irq(grp, TX)->irq);
1930                         goto tx_irq_fail;
1931                 }
1932                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1933                                   gfar_irq(grp, RX)->name, grp);
1934                 if (err < 0) {
1935                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1936                                   gfar_irq(grp, RX)->irq);
1937                         goto rx_irq_fail;
1938                 }
1939         } else {
1940                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1941                                   gfar_irq(grp, TX)->name, grp);
1942                 if (err < 0) {
1943                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1944                                   gfar_irq(grp, TX)->irq);
1945                         goto err_irq_fail;
1946                 }
1947         }
1948
1949         return 0;
1950
1951 rx_irq_fail:
1952         free_irq(gfar_irq(grp, TX)->irq, grp);
1953 tx_irq_fail:
1954         free_irq(gfar_irq(grp, ER)->irq, grp);
1955 err_irq_fail:
1956         return err;
1957
1958 }
1959
1960 /* Bring the controller up and running */
1961 int startup_gfar(struct net_device *ndev)
1962 {
1963         struct gfar_private *priv = netdev_priv(ndev);
1964         struct gfar __iomem *regs = NULL;
1965         int err, i, j;
1966
1967         for (i = 0; i < priv->num_grps; i++) {
1968                 regs= priv->gfargrp[i].regs;
1969                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1970         }
1971
1972         regs= priv->gfargrp[0].regs;
1973         err = gfar_alloc_skb_resources(ndev);
1974         if (err)
1975                 return err;
1976
1977         gfar_init_mac(ndev);
1978
1979         for (i = 0; i < priv->num_grps; i++) {
1980                 err = register_grp_irqs(&priv->gfargrp[i]);
1981                 if (err) {
1982                         for (j = 0; j < i; j++)
1983                                 free_grp_irqs(&priv->gfargrp[j]);
1984                         goto irq_fail;
1985                 }
1986         }
1987
1988         /* Start the controller */
1989         gfar_start(ndev);
1990
1991         phy_start(priv->phydev);
1992
1993         gfar_configure_coalescing_all(priv);
1994
1995         return 0;
1996
1997 irq_fail:
1998         free_skb_resources(priv);
1999         return err;
2000 }
2001
2002 /* Called when something needs to use the ethernet device
2003  * Returns 0 for success.
2004  */
2005 static int gfar_enet_open(struct net_device *dev)
2006 {
2007         struct gfar_private *priv = netdev_priv(dev);
2008         int err;
2009
2010         enable_napi(priv);
2011
2012         /* Initialize a bunch of registers */
2013         init_registers(dev);
2014
2015         gfar_set_mac_address(dev);
2016
2017         err = init_phy(dev);
2018
2019         if (err) {
2020                 disable_napi(priv);
2021                 return err;
2022         }
2023
2024         err = startup_gfar(dev);
2025         if (err) {
2026                 disable_napi(priv);
2027                 return err;
2028         }
2029
2030         netif_tx_start_all_queues(dev);
2031
2032         device_set_wakeup_enable(&dev->dev, priv->wol_en);
2033
2034         return err;
2035 }
2036
2037 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2038 {
2039         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2040
2041         memset(fcb, 0, GMAC_FCB_LEN);
2042
2043         return fcb;
2044 }
2045
2046 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2047                                     int fcb_length)
2048 {
2049         /* If we're here, it's a IP packet with a TCP or UDP
2050          * payload.  We set it to checksum, using a pseudo-header
2051          * we provide
2052          */
2053         u8 flags = TXFCB_DEFAULT;
2054
2055         /* Tell the controller what the protocol is
2056          * And provide the already calculated phcs
2057          */
2058         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2059                 flags |= TXFCB_UDP;
2060                 fcb->phcs = udp_hdr(skb)->check;
2061         } else
2062                 fcb->phcs = tcp_hdr(skb)->check;
2063
2064         /* l3os is the distance between the start of the
2065          * frame (skb->data) and the start of the IP hdr.
2066          * l4os is the distance between the start of the
2067          * l3 hdr and the l4 hdr
2068          */
2069         fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2070         fcb->l4os = skb_network_header_len(skb);
2071
2072         fcb->flags = flags;
2073 }
2074
2075 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2076 {
2077         fcb->flags |= TXFCB_VLN;
2078         fcb->vlctl = vlan_tx_tag_get(skb);
2079 }
2080
2081 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2082                                       struct txbd8 *base, int ring_size)
2083 {
2084         struct txbd8 *new_bd = bdp + stride;
2085
2086         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2087 }
2088
2089 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2090                                       int ring_size)
2091 {
2092         return skip_txbd(bdp, 1, base, ring_size);
2093 }
2094
2095 /* eTSEC12: csum generation not supported for some fcb offsets */
2096 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2097                                        unsigned long fcb_addr)
2098 {
2099         return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2100                (fcb_addr % 0x20) > 0x18);
2101 }
2102
2103 /* eTSEC76: csum generation for frames larger than 2500 may
2104  * cause excess delays before start of transmission
2105  */
2106 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2107                                        unsigned int len)
2108 {
2109         return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2110                (len > 2500));
2111 }
2112
2113 /* This is called by the kernel when a frame is ready for transmission.
2114  * It is pointed to by the dev->hard_start_xmit function pointer
2115  */
2116 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2117 {
2118         struct gfar_private *priv = netdev_priv(dev);
2119         struct gfar_priv_tx_q *tx_queue = NULL;
2120         struct netdev_queue *txq;
2121         struct gfar __iomem *regs = NULL;
2122         struct txfcb *fcb = NULL;
2123         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2124         u32 lstatus;
2125         int i, rq = 0;
2126         int do_tstamp, do_csum, do_vlan;
2127         u32 bufaddr;
2128         unsigned long flags;
2129         unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2130
2131         rq = skb->queue_mapping;
2132         tx_queue = priv->tx_queue[rq];
2133         txq = netdev_get_tx_queue(dev, rq);
2134         base = tx_queue->tx_bd_base;
2135         regs = tx_queue->grp->regs;
2136
2137         do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2138         do_vlan = vlan_tx_tag_present(skb);
2139         do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2140                     priv->hwts_tx_en;
2141
2142         if (do_csum || do_vlan)
2143                 fcb_len = GMAC_FCB_LEN;
2144
2145         /* check if time stamp should be generated */
2146         if (unlikely(do_tstamp))
2147                 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2148
2149         /* make space for additional header when fcb is needed */
2150         if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2151                 struct sk_buff *skb_new;
2152
2153                 skb_new = skb_realloc_headroom(skb, fcb_len);
2154                 if (!skb_new) {
2155                         dev->stats.tx_errors++;
2156                         kfree_skb(skb);
2157                         return NETDEV_TX_OK;
2158                 }
2159
2160                 if (skb->sk)
2161                         skb_set_owner_w(skb_new, skb->sk);
2162                 consume_skb(skb);
2163                 skb = skb_new;
2164         }
2165
2166         /* total number of fragments in the SKB */
2167         nr_frags = skb_shinfo(skb)->nr_frags;
2168
2169         /* calculate the required number of TxBDs for this skb */
2170         if (unlikely(do_tstamp))
2171                 nr_txbds = nr_frags + 2;
2172         else
2173                 nr_txbds = nr_frags + 1;
2174
2175         /* check if there is space to queue this packet */
2176         if (nr_txbds > tx_queue->num_txbdfree) {
2177                 /* no space, stop the queue */
2178                 netif_tx_stop_queue(txq);
2179                 dev->stats.tx_fifo_errors++;
2180                 return NETDEV_TX_BUSY;
2181         }
2182
2183         /* Update transmit stats */
2184         bytes_sent = skb->len;
2185         tx_queue->stats.tx_bytes += bytes_sent;
2186         /* keep Tx bytes on wire for BQL accounting */
2187         GFAR_CB(skb)->bytes_sent = bytes_sent;
2188         tx_queue->stats.tx_packets++;
2189
2190         txbdp = txbdp_start = tx_queue->cur_tx;
2191         lstatus = txbdp->lstatus;
2192
2193         /* Time stamp insertion requires one additional TxBD */
2194         if (unlikely(do_tstamp))
2195                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2196                                                  tx_queue->tx_ring_size);
2197
2198         if (nr_frags == 0) {
2199                 if (unlikely(do_tstamp))
2200                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2201                                                           TXBD_INTERRUPT);
2202                 else
2203                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2204         } else {
2205                 /* Place the fragment addresses and lengths into the TxBDs */
2206                 for (i = 0; i < nr_frags; i++) {
2207                         unsigned int frag_len;
2208                         /* Point at the next BD, wrapping as needed */
2209                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2210
2211                         frag_len = skb_shinfo(skb)->frags[i].size;
2212
2213                         lstatus = txbdp->lstatus | frag_len |
2214                                   BD_LFLAG(TXBD_READY);
2215
2216                         /* Handle the last BD specially */
2217                         if (i == nr_frags - 1)
2218                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2219
2220                         bufaddr = skb_frag_dma_map(priv->dev,
2221                                                    &skb_shinfo(skb)->frags[i],
2222                                                    0,
2223                                                    frag_len,
2224                                                    DMA_TO_DEVICE);
2225
2226                         /* set the TxBD length and buffer pointer */
2227                         txbdp->bufPtr = bufaddr;
2228                         txbdp->lstatus = lstatus;
2229                 }
2230
2231                 lstatus = txbdp_start->lstatus;
2232         }
2233
2234         /* Add TxPAL between FCB and frame if required */
2235         if (unlikely(do_tstamp)) {
2236                 skb_push(skb, GMAC_TXPAL_LEN);
2237                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2238         }
2239
2240         /* Add TxFCB if required */
2241         if (fcb_len) {
2242                 fcb = gfar_add_fcb(skb);
2243                 lstatus |= BD_LFLAG(TXBD_TOE);
2244         }
2245
2246         /* Set up checksumming */
2247         if (do_csum) {
2248                 gfar_tx_checksum(skb, fcb, fcb_len);
2249
2250                 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2251                     unlikely(gfar_csum_errata_76(priv, skb->len))) {
2252                         __skb_pull(skb, GMAC_FCB_LEN);
2253                         skb_checksum_help(skb);
2254                         if (do_vlan || do_tstamp) {
2255                                 /* put back a new fcb for vlan/tstamp TOE */
2256                                 fcb = gfar_add_fcb(skb);
2257                         } else {
2258                                 /* Tx TOE not used */
2259                                 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2260                                 fcb = NULL;
2261                         }
2262                 }
2263         }
2264
2265         if (do_vlan)
2266                 gfar_tx_vlan(skb, fcb);
2267
2268         /* Setup tx hardware time stamping if requested */
2269         if (unlikely(do_tstamp)) {
2270                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2271                 fcb->ptp = 1;
2272         }
2273
2274         txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data,
2275                                              skb_headlen(skb), DMA_TO_DEVICE);
2276
2277         /* If time stamping is requested one additional TxBD must be set up. The
2278          * first TxBD points to the FCB and must have a data length of
2279          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2280          * the full frame length.
2281          */
2282         if (unlikely(do_tstamp)) {
2283                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len;
2284                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2285                                          (skb_headlen(skb) - fcb_len);
2286                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2287         } else {
2288                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2289         }
2290
2291         netdev_tx_sent_queue(txq, bytes_sent);
2292
2293         /* We can work in parallel with gfar_clean_tx_ring(), except
2294          * when modifying num_txbdfree. Note that we didn't grab the lock
2295          * when we were reading the num_txbdfree and checking for available
2296          * space, that's because outside of this function it can only grow,
2297          * and once we've got needed space, it cannot suddenly disappear.
2298          *
2299          * The lock also protects us from gfar_error(), which can modify
2300          * regs->tstat and thus retrigger the transfers, which is why we
2301          * also must grab the lock before setting ready bit for the first
2302          * to be transmitted BD.
2303          */
2304         spin_lock_irqsave(&tx_queue->txlock, flags);
2305
2306         /* The powerpc-specific eieio() is used, as wmb() has too strong
2307          * semantics (it requires synchronization between cacheable and
2308          * uncacheable mappings, which eieio doesn't provide and which we
2309          * don't need), thus requiring a more expensive sync instruction.  At
2310          * some point, the set of architecture-independent barrier functions
2311          * should be expanded to include weaker barriers.
2312          */
2313         eieio();
2314
2315         txbdp_start->lstatus = lstatus;
2316
2317         eieio(); /* force lstatus write before tx_skbuff */
2318
2319         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2320
2321         /* Update the current skb pointer to the next entry we will use
2322          * (wrapping if necessary)
2323          */
2324         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2325                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2326
2327         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2328
2329         /* reduce TxBD free count */
2330         tx_queue->num_txbdfree -= (nr_txbds);
2331
2332         /* If the next BD still needs to be cleaned up, then the bds
2333          * are full.  We need to tell the kernel to stop sending us stuff.
2334          */
2335         if (!tx_queue->num_txbdfree) {
2336                 netif_tx_stop_queue(txq);
2337
2338                 dev->stats.tx_fifo_errors++;
2339         }
2340
2341         /* Tell the DMA to go go go */
2342         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2343
2344         /* Unlock priv */
2345         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2346
2347         return NETDEV_TX_OK;
2348 }
2349
2350 /* Stops the kernel queue, and halts the controller */
2351 static int gfar_close(struct net_device *dev)
2352 {
2353         struct gfar_private *priv = netdev_priv(dev);
2354
2355         disable_napi(priv);
2356
2357         cancel_work_sync(&priv->reset_task);
2358         stop_gfar(dev);
2359
2360         /* Disconnect from the PHY */
2361         phy_disconnect(priv->phydev);
2362         priv->phydev = NULL;
2363
2364         netif_tx_stop_all_queues(dev);
2365
2366         return 0;
2367 }
2368
2369 /* Changes the mac address if the controller is not running. */
2370 static int gfar_set_mac_address(struct net_device *dev)
2371 {
2372         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2373
2374         return 0;
2375 }
2376
2377 /* Check if rx parser should be activated */
2378 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2379 {
2380         struct gfar __iomem *regs;
2381         u32 tempval;
2382
2383         regs = priv->gfargrp[0].regs;
2384
2385         tempval = gfar_read(&regs->rctrl);
2386         /* If parse is no longer required, then disable parser */
2387         if (tempval & RCTRL_REQ_PARSER) {
2388                 tempval |= RCTRL_PRSDEP_INIT;
2389                 priv->uses_rxfcb = 1;
2390         } else {
2391                 tempval &= ~RCTRL_PRSDEP_INIT;
2392                 priv->uses_rxfcb = 0;
2393         }
2394         gfar_write(&regs->rctrl, tempval);
2395 }
2396
2397 /* Enables and disables VLAN insertion/extraction */
2398 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2399 {
2400         struct gfar_private *priv = netdev_priv(dev);
2401         struct gfar __iomem *regs = NULL;
2402         unsigned long flags;
2403         u32 tempval;
2404
2405         regs = priv->gfargrp[0].regs;
2406         local_irq_save(flags);
2407         lock_rx_qs(priv);
2408
2409         if (features & NETIF_F_HW_VLAN_CTAG_TX) {
2410                 /* Enable VLAN tag insertion */
2411                 tempval = gfar_read(&regs->tctrl);
2412                 tempval |= TCTRL_VLINS;
2413                 gfar_write(&regs->tctrl, tempval);
2414         } else {
2415                 /* Disable VLAN tag insertion */
2416                 tempval = gfar_read(&regs->tctrl);
2417                 tempval &= ~TCTRL_VLINS;
2418                 gfar_write(&regs->tctrl, tempval);
2419         }
2420
2421         if (features & NETIF_F_HW_VLAN_CTAG_RX) {
2422                 /* Enable VLAN tag extraction */
2423                 tempval = gfar_read(&regs->rctrl);
2424                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2425                 gfar_write(&regs->rctrl, tempval);
2426                 priv->uses_rxfcb = 1;
2427         } else {
2428                 /* Disable VLAN tag extraction */
2429                 tempval = gfar_read(&regs->rctrl);
2430                 tempval &= ~RCTRL_VLEX;
2431                 gfar_write(&regs->rctrl, tempval);
2432
2433                 gfar_check_rx_parser_mode(priv);
2434         }
2435
2436         gfar_change_mtu(dev, dev->mtu);
2437
2438         unlock_rx_qs(priv);
2439         local_irq_restore(flags);
2440 }
2441
2442 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2443 {
2444         int tempsize, tempval;
2445         struct gfar_private *priv = netdev_priv(dev);
2446         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2447         int oldsize = priv->rx_buffer_size;
2448         int frame_size = new_mtu + ETH_HLEN;
2449
2450         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2451                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2452                 return -EINVAL;
2453         }
2454
2455         if (priv->uses_rxfcb)
2456                 frame_size += GMAC_FCB_LEN;
2457
2458         frame_size += priv->padding;
2459
2460         tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2461                    INCREMENTAL_BUFFER_SIZE;
2462
2463         /* Only stop and start the controller if it isn't already
2464          * stopped, and we changed something
2465          */
2466         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2467                 stop_gfar(dev);
2468
2469         priv->rx_buffer_size = tempsize;
2470
2471         dev->mtu = new_mtu;
2472
2473         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2474         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2475
2476         /* If the mtu is larger than the max size for standard
2477          * ethernet frames (ie, a jumbo frame), then set maccfg2
2478          * to allow huge frames, and to check the length
2479          */
2480         tempval = gfar_read(&regs->maccfg2);
2481
2482         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2483             gfar_has_errata(priv, GFAR_ERRATA_74))
2484                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2485         else
2486                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2487
2488         gfar_write(&regs->maccfg2, tempval);
2489
2490         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2491                 startup_gfar(dev);
2492
2493         return 0;
2494 }
2495
2496 /* gfar_reset_task gets scheduled when a packet has not been
2497  * transmitted after a set amount of time.
2498  * For now, assume that clearing out all the structures, and
2499  * starting over will fix the problem.
2500  */
2501 static void gfar_reset_task(struct work_struct *work)
2502 {
2503         struct gfar_private *priv = container_of(work, struct gfar_private,
2504                                                  reset_task);
2505         struct net_device *dev = priv->ndev;
2506
2507         if (dev->flags & IFF_UP) {
2508                 netif_tx_stop_all_queues(dev);
2509                 stop_gfar(dev);
2510                 startup_gfar(dev);
2511                 netif_tx_start_all_queues(dev);
2512         }
2513
2514         netif_tx_schedule_all(dev);
2515 }
2516
2517 static void gfar_timeout(struct net_device *dev)
2518 {
2519         struct gfar_private *priv = netdev_priv(dev);
2520
2521         dev->stats.tx_errors++;
2522         schedule_work(&priv->reset_task);
2523 }
2524
2525 static void gfar_align_skb(struct sk_buff *skb)
2526 {
2527         /* We need the data buffer to be aligned properly.  We will reserve
2528          * as many bytes as needed to align the data properly
2529          */
2530         skb_reserve(skb, RXBUF_ALIGNMENT -
2531                     (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2532 }
2533
2534 /* Interrupt Handler for Transmit complete */
2535 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2536 {
2537         struct net_device *dev = tx_queue->dev;
2538         struct netdev_queue *txq;
2539         struct gfar_private *priv = netdev_priv(dev);
2540         struct txbd8 *bdp, *next = NULL;
2541         struct txbd8 *lbdp = NULL;
2542         struct txbd8 *base = tx_queue->tx_bd_base;
2543         struct sk_buff *skb;
2544         int skb_dirtytx;
2545         int tx_ring_size = tx_queue->tx_ring_size;
2546         int frags = 0, nr_txbds = 0;
2547         int i;
2548         int howmany = 0;
2549         int tqi = tx_queue->qindex;
2550         unsigned int bytes_sent = 0;
2551         u32 lstatus;
2552         size_t buflen;
2553
2554         txq = netdev_get_tx_queue(dev, tqi);
2555         bdp = tx_queue->dirty_tx;
2556         skb_dirtytx = tx_queue->skb_dirtytx;
2557
2558         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2559                 unsigned long flags;
2560
2561                 frags = skb_shinfo(skb)->nr_frags;
2562
2563                 /* When time stamping, one additional TxBD must be freed.
2564                  * Also, we need to dma_unmap_single() the TxPAL.
2565                  */
2566                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2567                         nr_txbds = frags + 2;
2568                 else
2569                         nr_txbds = frags + 1;
2570
2571                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2572
2573                 lstatus = lbdp->lstatus;
2574
2575                 /* Only clean completed frames */
2576                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2577                     (lstatus & BD_LENGTH_MASK))
2578                         break;
2579
2580                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2581                         next = next_txbd(bdp, base, tx_ring_size);
2582                         buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2583                 } else
2584                         buflen = bdp->length;
2585
2586                 dma_unmap_single(priv->dev, bdp->bufPtr,
2587                                  buflen, DMA_TO_DEVICE);
2588
2589                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2590                         struct skb_shared_hwtstamps shhwtstamps;
2591                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2592
2593                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2594                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2595                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2596                         skb_tstamp_tx(skb, &shhwtstamps);
2597                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2598                         bdp = next;
2599                 }
2600
2601                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2602                 bdp = next_txbd(bdp, base, tx_ring_size);
2603
2604                 for (i = 0; i < frags; i++) {
2605                         dma_unmap_page(priv->dev, bdp->bufPtr,
2606                                        bdp->length, DMA_TO_DEVICE);
2607                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2608                         bdp = next_txbd(bdp, base, tx_ring_size);
2609                 }
2610
2611                 bytes_sent += GFAR_CB(skb)->bytes_sent;
2612
2613                 dev_kfree_skb_any(skb);
2614
2615                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2616
2617                 skb_dirtytx = (skb_dirtytx + 1) &
2618                               TX_RING_MOD_MASK(tx_ring_size);
2619
2620                 howmany++;
2621                 spin_lock_irqsave(&tx_queue->txlock, flags);
2622                 tx_queue->num_txbdfree += nr_txbds;
2623                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2624         }
2625
2626         /* If we freed a buffer, we can restart transmission, if necessary */
2627         if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2628                 netif_wake_subqueue(dev, tqi);
2629
2630         /* Update dirty indicators */
2631         tx_queue->skb_dirtytx = skb_dirtytx;
2632         tx_queue->dirty_tx = bdp;
2633
2634         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2635 }
2636
2637 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2638 {
2639         unsigned long flags;
2640
2641         spin_lock_irqsave(&gfargrp->grplock, flags);
2642         if (napi_schedule_prep(&gfargrp->napi)) {
2643                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2644                 __napi_schedule(&gfargrp->napi);
2645         } else {
2646                 /* Clear IEVENT, so interrupts aren't called again
2647                  * because of the packets that have already arrived.
2648                  */
2649                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2650         }
2651         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2652
2653 }
2654
2655 /* Interrupt Handler for Transmit complete */
2656 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2657 {
2658         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2659         return IRQ_HANDLED;
2660 }
2661
2662 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2663                            struct sk_buff *skb)
2664 {
2665         struct net_device *dev = rx_queue->dev;
2666         struct gfar_private *priv = netdev_priv(dev);
2667         dma_addr_t buf;
2668
2669         buf = dma_map_single(priv->dev, skb->data,
2670                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2671         gfar_init_rxbdp(rx_queue, bdp, buf);
2672 }
2673
2674 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2675 {
2676         struct gfar_private *priv = netdev_priv(dev);
2677         struct sk_buff *skb;
2678
2679         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2680         if (!skb)
2681                 return NULL;
2682
2683         gfar_align_skb(skb);
2684
2685         return skb;
2686 }
2687
2688 struct sk_buff *gfar_new_skb(struct net_device *dev)
2689 {
2690         return gfar_alloc_skb(dev);
2691 }
2692
2693 static inline void count_errors(unsigned short status, struct net_device *dev)
2694 {
2695         struct gfar_private *priv = netdev_priv(dev);
2696         struct net_device_stats *stats = &dev->stats;
2697         struct gfar_extra_stats *estats = &priv->extra_stats;
2698
2699         /* If the packet was truncated, none of the other errors matter */
2700         if (status & RXBD_TRUNCATED) {
2701                 stats->rx_length_errors++;
2702
2703                 atomic64_inc(&estats->rx_trunc);
2704
2705                 return;
2706         }
2707         /* Count the errors, if there were any */
2708         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2709                 stats->rx_length_errors++;
2710
2711                 if (status & RXBD_LARGE)
2712                         atomic64_inc(&estats->rx_large);
2713                 else
2714                         atomic64_inc(&estats->rx_short);
2715         }
2716         if (status & RXBD_NONOCTET) {
2717                 stats->rx_frame_errors++;
2718                 atomic64_inc(&estats->rx_nonoctet);
2719         }
2720         if (status & RXBD_CRCERR) {
2721                 atomic64_inc(&estats->rx_crcerr);
2722                 stats->rx_crc_errors++;
2723         }
2724         if (status & RXBD_OVERRUN) {
2725                 atomic64_inc(&estats->rx_overrun);
2726                 stats->rx_crc_errors++;
2727         }
2728 }
2729
2730 irqreturn_t gfar_receive(int irq, void *grp_id)
2731 {
2732         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2733         return IRQ_HANDLED;
2734 }
2735
2736 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2737 {
2738         /* If valid headers were found, and valid sums
2739          * were verified, then we tell the kernel that no
2740          * checksumming is necessary.  Otherwise, it is [FIXME]
2741          */
2742         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2743                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2744         else
2745                 skb_checksum_none_assert(skb);
2746 }
2747
2748
2749 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2750 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2751                                int amount_pull, struct napi_struct *napi)
2752 {
2753         struct gfar_private *priv = netdev_priv(dev);
2754         struct rxfcb *fcb = NULL;
2755
2756         /* fcb is at the beginning if exists */
2757         fcb = (struct rxfcb *)skb->data;
2758
2759         /* Remove the FCB from the skb
2760          * Remove the padded bytes, if there are any
2761          */
2762         if (amount_pull) {
2763                 skb_record_rx_queue(skb, fcb->rq);
2764                 skb_pull(skb, amount_pull);
2765         }
2766
2767         /* Get receive timestamp from the skb */
2768         if (priv->hwts_rx_en) {
2769                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2770                 u64 *ns = (u64 *) skb->data;
2771
2772                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2773                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2774         }
2775
2776         if (priv->padding)
2777                 skb_pull(skb, priv->padding);
2778
2779         if (dev->features & NETIF_F_RXCSUM)
2780                 gfar_rx_checksum(skb, fcb);
2781
2782         /* Tell the skb what kind of packet this is */
2783         skb->protocol = eth_type_trans(skb, dev);
2784
2785         /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2786          * Even if vlan rx accel is disabled, on some chips
2787          * RXFCB_VLN is pseudo randomly set.
2788          */
2789         if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2790             fcb->flags & RXFCB_VLN)
2791                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl);
2792
2793         /* Send the packet up the stack */
2794         napi_gro_receive(napi, skb);
2795
2796 }
2797
2798 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2799  * until the budget/quota has been reached. Returns the number
2800  * of frames handled
2801  */
2802 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2803 {
2804         struct net_device *dev = rx_queue->dev;
2805         struct rxbd8 *bdp, *base;
2806         struct sk_buff *skb;
2807         int pkt_len;
2808         int amount_pull;
2809         int howmany = 0;
2810         struct gfar_private *priv = netdev_priv(dev);
2811
2812         /* Get the first full descriptor */
2813         bdp = rx_queue->cur_rx;
2814         base = rx_queue->rx_bd_base;
2815
2816         amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2817
2818         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2819                 struct sk_buff *newskb;
2820
2821                 rmb();
2822
2823                 /* Add another skb for the future */
2824                 newskb = gfar_new_skb(dev);
2825
2826                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2827
2828                 dma_unmap_single(priv->dev, bdp->bufPtr,
2829                                  priv->rx_buffer_size, DMA_FROM_DEVICE);
2830
2831                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2832                              bdp->length > priv->rx_buffer_size))
2833                         bdp->status = RXBD_LARGE;
2834
2835                 /* We drop the frame if we failed to allocate a new buffer */
2836                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2837                              bdp->status & RXBD_ERR)) {
2838                         count_errors(bdp->status, dev);
2839
2840                         if (unlikely(!newskb))
2841                                 newskb = skb;
2842                         else if (skb)
2843                                 dev_kfree_skb(skb);
2844                 } else {
2845                         /* Increment the number of packets */
2846                         rx_queue->stats.rx_packets++;
2847                         howmany++;
2848
2849                         if (likely(skb)) {
2850                                 pkt_len = bdp->length - ETH_FCS_LEN;
2851                                 /* Remove the FCS from the packet length */
2852                                 skb_put(skb, pkt_len);
2853                                 rx_queue->stats.rx_bytes += pkt_len;
2854                                 skb_record_rx_queue(skb, rx_queue->qindex);
2855                                 gfar_process_frame(dev, skb, amount_pull,
2856                                                    &rx_queue->grp->napi);
2857
2858                         } else {
2859                                 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2860                                 rx_queue->stats.rx_dropped++;
2861                                 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2862                         }
2863
2864                 }
2865
2866                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2867
2868                 /* Setup the new bdp */
2869                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2870
2871                 /* Update to the next pointer */
2872                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2873
2874                 /* update to point at the next skb */
2875                 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2876                                       RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2877         }
2878
2879         /* Update the current rxbd pointer to be the next one */
2880         rx_queue->cur_rx = bdp;
2881
2882         return howmany;
2883 }
2884
2885 static int gfar_poll_sq(struct napi_struct *napi, int budget)
2886 {
2887         struct gfar_priv_grp *gfargrp =
2888                 container_of(napi, struct gfar_priv_grp, napi);
2889         struct gfar __iomem *regs = gfargrp->regs;
2890         struct gfar_priv_tx_q *tx_queue = gfargrp->priv->tx_queue[0];
2891         struct gfar_priv_rx_q *rx_queue = gfargrp->priv->rx_queue[0];
2892         int work_done = 0;
2893
2894         /* Clear IEVENT, so interrupts aren't called again
2895          * because of the packets that have already arrived
2896          */
2897         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2898
2899         /* run Tx cleanup to completion */
2900         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2901                 gfar_clean_tx_ring(tx_queue);
2902
2903         work_done = gfar_clean_rx_ring(rx_queue, budget);
2904
2905         if (work_done < budget) {
2906                 napi_complete(napi);
2907                 /* Clear the halt bit in RSTAT */
2908                 gfar_write(&regs->rstat, gfargrp->rstat);
2909
2910                 gfar_write(&regs->imask, IMASK_DEFAULT);
2911
2912                 /* If we are coalescing interrupts, update the timer
2913                  * Otherwise, clear it
2914                  */
2915                 gfar_write(&regs->txic, 0);
2916                 if (likely(tx_queue->txcoalescing))
2917                         gfar_write(&regs->txic, tx_queue->txic);
2918
2919                 gfar_write(&regs->rxic, 0);
2920                 if (unlikely(rx_queue->rxcoalescing))
2921                         gfar_write(&regs->rxic, rx_queue->rxic);
2922         }
2923
2924         return work_done;
2925 }
2926
2927 static int gfar_poll(struct napi_struct *napi, int budget)
2928 {
2929         struct gfar_priv_grp *gfargrp =
2930                 container_of(napi, struct gfar_priv_grp, napi);
2931         struct gfar_private *priv = gfargrp->priv;
2932         struct gfar __iomem *regs = gfargrp->regs;
2933         struct gfar_priv_tx_q *tx_queue = NULL;
2934         struct gfar_priv_rx_q *rx_queue = NULL;
2935         int work_done = 0, work_done_per_q = 0;
2936         int i, budget_per_q = 0;
2937         int has_tx_work = 0;
2938         unsigned long rstat_rxf;
2939         int num_act_queues;
2940
2941         /* Clear IEVENT, so interrupts aren't called again
2942          * because of the packets that have already arrived
2943          */
2944         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2945
2946         rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
2947
2948         num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2949         if (num_act_queues)
2950                 budget_per_q = budget/num_act_queues;
2951
2952         for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2953                 tx_queue = priv->tx_queue[i];
2954                 /* run Tx cleanup to completion */
2955                 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2956                         gfar_clean_tx_ring(tx_queue);
2957                         has_tx_work = 1;
2958                 }
2959         }
2960
2961         for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2962                 /* skip queue if not active */
2963                 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2964                         continue;
2965
2966                 rx_queue = priv->rx_queue[i];
2967                 work_done_per_q =
2968                         gfar_clean_rx_ring(rx_queue, budget_per_q);
2969                 work_done += work_done_per_q;
2970
2971                 /* finished processing this queue */
2972                 if (work_done_per_q < budget_per_q) {
2973                         /* clear active queue hw indication */
2974                         gfar_write(&regs->rstat,
2975                                    RSTAT_CLEAR_RXF0 >> i);
2976                         num_act_queues--;
2977
2978                         if (!num_act_queues)
2979                                 break;
2980                 }
2981         }
2982
2983         if (!num_act_queues && !has_tx_work) {
2984
2985                 napi_complete(napi);
2986
2987                 /* Clear the halt bit in RSTAT */
2988                 gfar_write(&regs->rstat, gfargrp->rstat);
2989
2990                 gfar_write(&regs->imask, IMASK_DEFAULT);
2991
2992                 /* If we are coalescing interrupts, update the timer
2993                  * Otherwise, clear it
2994                  */
2995                 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2996                                           gfargrp->tx_bit_map);
2997         }
2998
2999         return work_done;
3000 }
3001
3002 #ifdef CONFIG_NET_POLL_CONTROLLER
3003 /* Polling 'interrupt' - used by things like netconsole to send skbs
3004  * without having to re-enable interrupts. It's not called while
3005  * the interrupt routine is executing.
3006  */
3007 static void gfar_netpoll(struct net_device *dev)
3008 {
3009         struct gfar_private *priv = netdev_priv(dev);
3010         int i;
3011
3012         /* If the device has multiple interrupts, run tx/rx */
3013         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3014                 for (i = 0; i < priv->num_grps; i++) {
3015                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3016
3017                         disable_irq(gfar_irq(grp, TX)->irq);
3018                         disable_irq(gfar_irq(grp, RX)->irq);
3019                         disable_irq(gfar_irq(grp, ER)->irq);
3020                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3021                         enable_irq(gfar_irq(grp, ER)->irq);
3022                         enable_irq(gfar_irq(grp, RX)->irq);
3023                         enable_irq(gfar_irq(grp, TX)->irq);
3024                 }
3025         } else {
3026                 for (i = 0; i < priv->num_grps; i++) {
3027                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3028
3029                         disable_irq(gfar_irq(grp, TX)->irq);
3030                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3031                         enable_irq(gfar_irq(grp, TX)->irq);
3032                 }
3033         }
3034 }
3035 #endif
3036
3037 /* The interrupt handler for devices with one interrupt */
3038 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3039 {
3040         struct gfar_priv_grp *gfargrp = grp_id;
3041
3042         /* Save ievent for future reference */
3043         u32 events = gfar_read(&gfargrp->regs->ievent);
3044
3045         /* Check for reception */
3046         if (events & IEVENT_RX_MASK)
3047                 gfar_receive(irq, grp_id);
3048
3049         /* Check for transmit completion */
3050         if (events & IEVENT_TX_MASK)
3051                 gfar_transmit(irq, grp_id);
3052
3053         /* Check for errors */
3054         if (events & IEVENT_ERR_MASK)
3055                 gfar_error(irq, grp_id);
3056
3057         return IRQ_HANDLED;
3058 }
3059
3060 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3061 {
3062         struct phy_device *phydev = priv->phydev;
3063         u32 val = 0;
3064
3065         if (!phydev->duplex)
3066                 return val;
3067
3068         if (!priv->pause_aneg_en) {
3069                 if (priv->tx_pause_en)
3070                         val |= MACCFG1_TX_FLOW;
3071                 if (priv->rx_pause_en)
3072                         val |= MACCFG1_RX_FLOW;
3073         } else {
3074                 u16 lcl_adv, rmt_adv;
3075                 u8 flowctrl;
3076                 /* get link partner capabilities */
3077                 rmt_adv = 0;
3078                 if (phydev->pause)
3079                         rmt_adv = LPA_PAUSE_CAP;
3080                 if (phydev->asym_pause)
3081                         rmt_adv |= LPA_PAUSE_ASYM;
3082
3083                 lcl_adv = mii_advertise_flowctrl(phydev->advertising);
3084
3085                 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3086                 if (flowctrl & FLOW_CTRL_TX)
3087                         val |= MACCFG1_TX_FLOW;
3088                 if (flowctrl & FLOW_CTRL_RX)
3089                         val |= MACCFG1_RX_FLOW;
3090         }
3091
3092         return val;
3093 }
3094
3095 /* Called every time the controller might need to be made
3096  * aware of new link state.  The PHY code conveys this
3097  * information through variables in the phydev structure, and this
3098  * function converts those variables into the appropriate
3099  * register values, and can bring down the device if needed.
3100  */
3101 static void adjust_link(struct net_device *dev)
3102 {
3103         struct gfar_private *priv = netdev_priv(dev);
3104         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3105         unsigned long flags;
3106         struct phy_device *phydev = priv->phydev;
3107         int new_state = 0;
3108
3109         local_irq_save(flags);
3110         lock_tx_qs(priv);
3111
3112         if (phydev->link) {
3113                 u32 tempval1 = gfar_read(&regs->maccfg1);
3114                 u32 tempval = gfar_read(&regs->maccfg2);
3115                 u32 ecntrl = gfar_read(&regs->ecntrl);
3116
3117                 /* Now we make sure that we can be in full duplex mode.
3118                  * If not, we operate in half-duplex mode.
3119                  */
3120                 if (phydev->duplex != priv->oldduplex) {
3121                         new_state = 1;
3122                         if (!(phydev->duplex))
3123                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
3124                         else
3125                                 tempval |= MACCFG2_FULL_DUPLEX;
3126
3127                         priv->oldduplex = phydev->duplex;
3128                 }
3129
3130                 if (phydev->speed != priv->oldspeed) {
3131                         new_state = 1;
3132                         switch (phydev->speed) {
3133                         case 1000:
3134                                 tempval =
3135                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3136
3137                                 ecntrl &= ~(ECNTRL_R100);
3138                                 break;
3139                         case 100:
3140                         case 10:
3141                                 tempval =
3142                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3143
3144                                 /* Reduced mode distinguishes
3145                                  * between 10 and 100
3146                                  */
3147                                 if (phydev->speed == SPEED_100)
3148                                         ecntrl |= ECNTRL_R100;
3149                                 else
3150                                         ecntrl &= ~(ECNTRL_R100);
3151                                 break;
3152                         default:
3153                                 netif_warn(priv, link, dev,
3154                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3155                                            phydev->speed);
3156                                 break;
3157                         }
3158
3159                         priv->oldspeed = phydev->speed;
3160                 }
3161
3162                 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3163                 tempval1 |= gfar_get_flowctrl_cfg(priv);
3164
3165                 gfar_write(&regs->maccfg1, tempval1);
3166                 gfar_write(&regs->maccfg2, tempval);
3167                 gfar_write(&regs->ecntrl, ecntrl);
3168
3169                 if (!priv->oldlink) {
3170                         new_state = 1;
3171                         priv->oldlink = 1;
3172                 }
3173         } else if (priv->oldlink) {
3174                 new_state = 1;
3175                 priv->oldlink = 0;
3176                 priv->oldspeed = 0;
3177                 priv->oldduplex = -1;
3178         }
3179
3180         if (new_state && netif_msg_link(priv))
3181                 phy_print_status(phydev);
3182         unlock_tx_qs(priv);
3183         local_irq_restore(flags);
3184 }
3185
3186 /* Update the hash table based on the current list of multicast
3187  * addresses we subscribe to.  Also, change the promiscuity of
3188  * the device based on the flags (this function is called
3189  * whenever dev->flags is changed
3190  */
3191 static void gfar_set_multi(struct net_device *dev)
3192 {
3193         struct netdev_hw_addr *ha;
3194         struct gfar_private *priv = netdev_priv(dev);
3195         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3196         u32 tempval;
3197
3198         if (dev->flags & IFF_PROMISC) {
3199                 /* Set RCTRL to PROM */
3200                 tempval = gfar_read(&regs->rctrl);
3201                 tempval |= RCTRL_PROM;
3202                 gfar_write(&regs->rctrl, tempval);
3203         } else {
3204                 /* Set RCTRL to not PROM */
3205                 tempval = gfar_read(&regs->rctrl);
3206                 tempval &= ~(RCTRL_PROM);
3207                 gfar_write(&regs->rctrl, tempval);
3208         }
3209
3210         if (dev->flags & IFF_ALLMULTI) {
3211                 /* Set the hash to rx all multicast frames */
3212                 gfar_write(&regs->igaddr0, 0xffffffff);
3213                 gfar_write(&regs->igaddr1, 0xffffffff);
3214                 gfar_write(&regs->igaddr2, 0xffffffff);
3215                 gfar_write(&regs->igaddr3, 0xffffffff);
3216                 gfar_write(&regs->igaddr4, 0xffffffff);
3217                 gfar_write(&regs->igaddr5, 0xffffffff);
3218                 gfar_write(&regs->igaddr6, 0xffffffff);
3219                 gfar_write(&regs->igaddr7, 0xffffffff);
3220                 gfar_write(&regs->gaddr0, 0xffffffff);
3221                 gfar_write(&regs->gaddr1, 0xffffffff);
3222                 gfar_write(&regs->gaddr2, 0xffffffff);
3223                 gfar_write(&regs->gaddr3, 0xffffffff);
3224                 gfar_write(&regs->gaddr4, 0xffffffff);
3225                 gfar_write(&regs->gaddr5, 0xffffffff);
3226                 gfar_write(&regs->gaddr6, 0xffffffff);
3227                 gfar_write(&regs->gaddr7, 0xffffffff);
3228         } else {
3229                 int em_num;
3230                 int idx;
3231
3232                 /* zero out the hash */
3233                 gfar_write(&regs->igaddr0, 0x0);
3234                 gfar_write(&regs->igaddr1, 0x0);
3235                 gfar_write(&regs->igaddr2, 0x0);
3236                 gfar_write(&regs->igaddr3, 0x0);
3237                 gfar_write(&regs->igaddr4, 0x0);
3238                 gfar_write(&regs->igaddr5, 0x0);
3239                 gfar_write(&regs->igaddr6, 0x0);
3240                 gfar_write(&regs->igaddr7, 0x0);
3241                 gfar_write(&regs->gaddr0, 0x0);
3242                 gfar_write(&regs->gaddr1, 0x0);
3243                 gfar_write(&regs->gaddr2, 0x0);
3244                 gfar_write(&regs->gaddr3, 0x0);
3245                 gfar_write(&regs->gaddr4, 0x0);
3246                 gfar_write(&regs->gaddr5, 0x0);
3247                 gfar_write(&regs->gaddr6, 0x0);
3248                 gfar_write(&regs->gaddr7, 0x0);
3249
3250                 /* If we have extended hash tables, we need to
3251                  * clear the exact match registers to prepare for
3252                  * setting them
3253                  */
3254                 if (priv->extended_hash) {
3255                         em_num = GFAR_EM_NUM + 1;
3256                         gfar_clear_exact_match(dev);
3257                         idx = 1;
3258                 } else {
3259                         idx = 0;
3260                         em_num = 0;
3261                 }
3262
3263                 if (netdev_mc_empty(dev))
3264                         return;
3265
3266                 /* Parse the list, and set the appropriate bits */
3267                 netdev_for_each_mc_addr(ha, dev) {
3268                         if (idx < em_num) {
3269                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3270                                 idx++;
3271                         } else
3272                                 gfar_set_hash_for_addr(dev, ha->addr);
3273                 }
3274         }
3275 }
3276
3277
3278 /* Clears each of the exact match registers to zero, so they
3279  * don't interfere with normal reception
3280  */
3281 static void gfar_clear_exact_match(struct net_device *dev)
3282 {
3283         int idx;
3284         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3285
3286         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3287                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3288 }
3289
3290 /* Set the appropriate hash bit for the given addr */
3291 /* The algorithm works like so:
3292  * 1) Take the Destination Address (ie the multicast address), and
3293  * do a CRC on it (little endian), and reverse the bits of the
3294  * result.
3295  * 2) Use the 8 most significant bits as a hash into a 256-entry
3296  * table.  The table is controlled through 8 32-bit registers:
3297  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3298  * gaddr7.  This means that the 3 most significant bits in the
3299  * hash index which gaddr register to use, and the 5 other bits
3300  * indicate which bit (assuming an IBM numbering scheme, which
3301  * for PowerPC (tm) is usually the case) in the register holds
3302  * the entry.
3303  */
3304 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3305 {
3306         u32 tempval;
3307         struct gfar_private *priv = netdev_priv(dev);
3308         u32 result = ether_crc(ETH_ALEN, addr);
3309         int width = priv->hash_width;
3310         u8 whichbit = (result >> (32 - width)) & 0x1f;
3311         u8 whichreg = result >> (32 - width + 5);
3312         u32 value = (1 << (31-whichbit));
3313
3314         tempval = gfar_read(priv->hash_regs[whichreg]);
3315         tempval |= value;
3316         gfar_write(priv->hash_regs[whichreg], tempval);
3317 }
3318
3319
3320 /* There are multiple MAC Address register pairs on some controllers
3321  * This function sets the numth pair to a given address
3322  */
3323 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3324                                   const u8 *addr)
3325 {
3326         struct gfar_private *priv = netdev_priv(dev);
3327         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3328         int idx;
3329         char tmpbuf[ETH_ALEN];
3330         u32 tempval;
3331         u32 __iomem *macptr = &regs->macstnaddr1;
3332
3333         macptr += num*2;
3334
3335         /* Now copy it into the mac registers backwards, cuz
3336          * little endian is silly
3337          */
3338         for (idx = 0; idx < ETH_ALEN; idx++)
3339                 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3340
3341         gfar_write(macptr, *((u32 *) (tmpbuf)));
3342
3343         tempval = *((u32 *) (tmpbuf + 4));
3344
3345         gfar_write(macptr+1, tempval);
3346 }
3347
3348 /* GFAR error interrupt handler */
3349 static irqreturn_t gfar_error(int irq, void *grp_id)
3350 {
3351         struct gfar_priv_grp *gfargrp = grp_id;
3352         struct gfar __iomem *regs = gfargrp->regs;
3353         struct gfar_private *priv= gfargrp->priv;
3354         struct net_device *dev = priv->ndev;
3355
3356         /* Save ievent for future reference */
3357         u32 events = gfar_read(&regs->ievent);
3358
3359         /* Clear IEVENT */
3360         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3361
3362         /* Magic Packet is not an error. */
3363         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3364             (events & IEVENT_MAG))
3365                 events &= ~IEVENT_MAG;
3366
3367         /* Hmm... */
3368         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3369                 netdev_dbg(dev,
3370                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3371                            events, gfar_read(&regs->imask));
3372
3373         /* Update the error counters */
3374         if (events & IEVENT_TXE) {
3375                 dev->stats.tx_errors++;
3376
3377                 if (events & IEVENT_LC)
3378                         dev->stats.tx_window_errors++;
3379                 if (events & IEVENT_CRL)
3380                         dev->stats.tx_aborted_errors++;
3381                 if (events & IEVENT_XFUN) {
3382                         unsigned long flags;
3383
3384                         netif_dbg(priv, tx_err, dev,
3385                                   "TX FIFO underrun, packet dropped\n");
3386                         dev->stats.tx_dropped++;
3387                         atomic64_inc(&priv->extra_stats.tx_underrun);
3388
3389                         local_irq_save(flags);
3390                         lock_tx_qs(priv);
3391
3392                         /* Reactivate the Tx Queues */
3393                         gfar_write(&regs->tstat, gfargrp->tstat);
3394
3395                         unlock_tx_qs(priv);
3396                         local_irq_restore(flags);
3397                 }
3398                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3399         }
3400         if (events & IEVENT_BSY) {
3401                 dev->stats.rx_errors++;
3402                 atomic64_inc(&priv->extra_stats.rx_bsy);
3403
3404                 gfar_receive(irq, grp_id);
3405
3406                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3407                           gfar_read(&regs->rstat));
3408         }
3409         if (events & IEVENT_BABR) {
3410                 dev->stats.rx_errors++;
3411                 atomic64_inc(&priv->extra_stats.rx_babr);
3412
3413                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3414         }
3415         if (events & IEVENT_EBERR) {
3416                 atomic64_inc(&priv->extra_stats.eberr);
3417                 netif_dbg(priv, rx_err, dev, "bus error\n");
3418         }
3419         if (events & IEVENT_RXC)
3420                 netif_dbg(priv, rx_status, dev, "control frame\n");
3421
3422         if (events & IEVENT_BABT) {
3423                 atomic64_inc(&priv->extra_stats.tx_babt);
3424                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3425         }
3426         return IRQ_HANDLED;
3427 }
3428
3429 static struct of_device_id gfar_match[] =
3430 {
3431         {
3432                 .type = "network",
3433                 .compatible = "gianfar",
3434         },
3435         {
3436                 .compatible = "fsl,etsec2",
3437         },
3438         {},
3439 };
3440 MODULE_DEVICE_TABLE(of, gfar_match);
3441
3442 /* Structure for a device driver */
3443 static struct platform_driver gfar_driver = {
3444         .driver = {
3445                 .name = "fsl-gianfar",
3446                 .owner = THIS_MODULE,
3447                 .pm = GFAR_PM_OPS,
3448                 .of_match_table = gfar_match,
3449         },
3450         .probe = gfar_probe,
3451         .remove = gfar_remove,
3452 };
3453
3454 module_platform_driver(gfar_driver);