2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_net.h>
56 #include <linux/regulator/consumer.h>
57 #include <linux/if_vlan.h>
59 #include <asm/cacheflush.h>
63 static void set_multicast_list(struct net_device *ndev);
65 #if defined(CONFIG_ARM)
66 #define FEC_ALIGNMENT 0xf
68 #define FEC_ALIGNMENT 0x3
71 #define DRIVER_NAME "fec"
73 /* Pause frame feild and FIFO threshold */
74 #define FEC_ENET_FCE (1 << 5)
75 #define FEC_ENET_RSEM_V 0x84
76 #define FEC_ENET_RSFL_V 16
77 #define FEC_ENET_RAEM_V 0x8
78 #define FEC_ENET_RAFL_V 0x8
79 #define FEC_ENET_OPD_V 0xFFF0
81 /* Controller is ENET-MAC */
82 #define FEC_QUIRK_ENET_MAC (1 << 0)
83 /* Controller needs driver to swap frame */
84 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
85 /* Controller uses gasket */
86 #define FEC_QUIRK_USE_GASKET (1 << 2)
87 /* Controller has GBIT support */
88 #define FEC_QUIRK_HAS_GBIT (1 << 3)
89 /* Controller has extend desc buffer */
90 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
91 /* Controller has hardware checksum support */
92 #define FEC_QUIRK_HAS_CSUM (1 << 5)
93 /* Controller has hardware vlan support */
94 #define FEC_QUIRK_HAS_VLAN (1 << 6)
95 /* ENET IP errata ERR006358
97 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
98 * detected as not set during a prior frame transmission, then the
99 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
100 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
101 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
102 * detected as not set during a prior frame transmission, then the
103 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
104 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
105 * frames not being transmitted until there is a 0-to-1 transition on
108 #define FEC_QUIRK_ERR006358 (1 << 7)
110 static struct platform_device_id fec_devtype[] = {
112 /* keep it for coldfire */
117 .driver_data = FEC_QUIRK_USE_GASKET,
123 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
126 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
127 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
128 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
130 .name = "mvf600-fec",
131 .driver_data = FEC_QUIRK_ENET_MAC,
136 MODULE_DEVICE_TABLE(platform, fec_devtype);
139 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
140 IMX27_FEC, /* runs on i.mx27/35/51 */
146 static const struct of_device_id fec_dt_ids[] = {
147 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
148 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
149 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
150 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
151 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
154 MODULE_DEVICE_TABLE(of, fec_dt_ids);
156 static unsigned char macaddr[ETH_ALEN];
157 module_param_array(macaddr, byte, NULL, 0);
158 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
160 #if defined(CONFIG_M5272)
162 * Some hardware gets it MAC address out of local flash memory.
163 * if this is non-zero then assume it is the address to get MAC from.
165 #if defined(CONFIG_NETtel)
166 #define FEC_FLASHMAC 0xf0006006
167 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
168 #define FEC_FLASHMAC 0xf0006000
169 #elif defined(CONFIG_CANCam)
170 #define FEC_FLASHMAC 0xf0020000
171 #elif defined (CONFIG_M5272C3)
172 #define FEC_FLASHMAC (0xffe04000 + 4)
173 #elif defined(CONFIG_MOD5272)
174 #define FEC_FLASHMAC 0xffc0406b
176 #define FEC_FLASHMAC 0
178 #endif /* CONFIG_M5272 */
180 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
181 #error "FEC: descriptor ring size constants too large"
184 /* Interrupt events/masks. */
185 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
186 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
187 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
188 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
189 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
190 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
191 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
192 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
193 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
194 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
196 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
197 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
199 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
201 #define PKT_MAXBUF_SIZE 1522
202 #define PKT_MINBUF_SIZE 64
203 #define PKT_MAXBLR_SIZE 1536
205 /* FEC receive acceleration */
206 #define FEC_RACC_IPDIS (1 << 1)
207 #define FEC_RACC_PRODIS (1 << 2)
208 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
211 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
212 * size bits. Other FEC hardware does not, so we need to take that into
213 * account when setting it.
215 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
216 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
217 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
219 #define OPT_FRAME_SIZE 0
222 /* FEC MII MMFR bits definition */
223 #define FEC_MMFR_ST (1 << 30)
224 #define FEC_MMFR_OP_READ (2 << 28)
225 #define FEC_MMFR_OP_WRITE (1 << 28)
226 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
227 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
228 #define FEC_MMFR_TA (2 << 16)
229 #define FEC_MMFR_DATA(v) (v & 0xffff)
231 #define FEC_MII_TIMEOUT 30000 /* us */
233 /* Transmitter timeout */
234 #define TX_TIMEOUT (2 * HZ)
236 #define FEC_PAUSE_FLAG_AUTONEG 0x1
237 #define FEC_PAUSE_FLAG_ENABLE 0x2
242 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
244 struct bufdesc *new_bd = bdp + 1;
245 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
246 struct bufdesc_ex *ex_base;
247 struct bufdesc *base;
250 if (bdp >= fep->tx_bd_base) {
251 base = fep->tx_bd_base;
252 ring_size = fep->tx_ring_size;
253 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
255 base = fep->rx_bd_base;
256 ring_size = fep->rx_ring_size;
257 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
261 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
262 ex_base : ex_new_bd);
264 return (new_bd >= (base + ring_size)) ?
269 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
271 struct bufdesc *new_bd = bdp - 1;
272 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
273 struct bufdesc_ex *ex_base;
274 struct bufdesc *base;
277 if (bdp >= fep->tx_bd_base) {
278 base = fep->tx_bd_base;
279 ring_size = fep->tx_ring_size;
280 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
282 base = fep->rx_bd_base;
283 ring_size = fep->rx_ring_size;
284 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
288 return (struct bufdesc *)((ex_new_bd < ex_base) ?
289 (ex_new_bd + ring_size) : ex_new_bd);
291 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
294 static void *swap_buffer(void *bufaddr, int len)
297 unsigned int *buf = bufaddr;
299 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
300 *buf = cpu_to_be32(*buf);
306 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
308 /* Only run for packets requiring a checksum. */
309 if (skb->ip_summed != CHECKSUM_PARTIAL)
312 if (unlikely(skb_cow_head(skb, 0)))
315 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
321 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
323 struct fec_enet_private *fep = netdev_priv(ndev);
324 const struct platform_device_id *id_entry =
325 platform_get_device_id(fep->pdev);
326 struct bufdesc *bdp, *bdp_pre;
328 unsigned short status;
331 /* Fill in a Tx ring entry */
334 status = bdp->cbd_sc;
336 if (status & BD_ENET_TX_READY) {
337 /* Ooops. All transmit buffers are full. Bail out.
338 * This should not happen, since ndev->tbusy should be set.
340 netdev_err(ndev, "tx queue full!\n");
341 return NETDEV_TX_BUSY;
344 /* Protocol checksum off-load for TCP and UDP. */
345 if (fec_enet_clear_csum(skb, ndev)) {
350 /* Clear all of the status flags */
351 status &= ~BD_ENET_TX_STATS;
353 /* Set buffer length and buffer pointer */
355 bdp->cbd_datlen = skb->len;
358 * On some FEC implementations data must be aligned on
359 * 4-byte boundaries. Use bounce buffers to copy data
360 * and get it aligned. Ugh.
363 index = (struct bufdesc_ex *)bdp -
364 (struct bufdesc_ex *)fep->tx_bd_base;
366 index = bdp - fep->tx_bd_base;
368 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
369 memcpy(fep->tx_bounce[index], skb->data, skb->len);
370 bufaddr = fep->tx_bounce[index];
374 * Some design made an incorrect assumption on endian mode of
375 * the system that it's running on. As the result, driver has to
376 * swap every frame going to and coming from the controller.
378 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
379 swap_buffer(bufaddr, skb->len);
381 /* Save skb pointer */
382 fep->tx_skbuff[index] = skb;
384 /* Push the data cache so the CPM does not get stale memory
387 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
388 skb->len, DMA_TO_DEVICE);
389 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
390 bdp->cbd_bufaddr = 0;
391 fep->tx_skbuff[index] = NULL;
392 dev_kfree_skb_any(skb);
394 netdev_err(ndev, "Tx DMA memory map failed\n");
397 /* Send it on its way. Tell FEC it's ready, interrupt when done,
398 * it's the last BD of the frame, and to put the CRC on the end.
400 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
401 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
402 bdp->cbd_sc = status;
404 if (fep->bufdesc_ex) {
406 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
408 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
410 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
411 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
413 ebdp->cbd_esc = BD_ENET_TX_INT;
415 /* Enable protocol checksum flags
416 * We do not bother with the IP Checksum bits as they
417 * are done by the kernel
419 if (skb->ip_summed == CHECKSUM_PARTIAL)
420 ebdp->cbd_esc |= BD_ENET_TX_PINS;
424 bdp_pre = fec_enet_get_prevdesc(bdp, fep);
425 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) &&
426 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) {
427 fep->delay_work.trig_tx = true;
428 schedule_delayed_work(&(fep->delay_work.delay_work),
429 msecs_to_jiffies(1));
432 /* If this was the last BD in the ring, start at the beginning again. */
433 bdp = fec_enet_get_nextdesc(bdp, fep);
437 if (fep->cur_tx == fep->dirty_tx)
438 netif_stop_queue(ndev);
440 /* Trigger transmission start */
441 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
443 skb_tx_timestamp(skb);
448 /* Init RX & TX buffer descriptors
450 static void fec_enet_bd_init(struct net_device *dev)
452 struct fec_enet_private *fep = netdev_priv(dev);
456 /* Initialize the receive buffer descriptors. */
457 bdp = fep->rx_bd_base;
458 for (i = 0; i < fep->rx_ring_size; i++) {
460 /* Initialize the BD for every fragment in the page. */
461 if (bdp->cbd_bufaddr)
462 bdp->cbd_sc = BD_ENET_RX_EMPTY;
465 bdp = fec_enet_get_nextdesc(bdp, fep);
468 /* Set the last buffer to wrap */
469 bdp = fec_enet_get_prevdesc(bdp, fep);
470 bdp->cbd_sc |= BD_SC_WRAP;
472 fep->cur_rx = fep->rx_bd_base;
474 /* ...and the same for transmit */
475 bdp = fep->tx_bd_base;
477 for (i = 0; i < fep->tx_ring_size; i++) {
479 /* Initialize the BD for every fragment in the page. */
481 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
482 dev_kfree_skb_any(fep->tx_skbuff[i]);
483 fep->tx_skbuff[i] = NULL;
485 bdp->cbd_bufaddr = 0;
486 bdp = fec_enet_get_nextdesc(bdp, fep);
489 /* Set the last buffer to wrap */
490 bdp = fec_enet_get_prevdesc(bdp, fep);
491 bdp->cbd_sc |= BD_SC_WRAP;
495 /* This function is called to start or restart the FEC during a link
496 * change. This only happens when switching between half and full
500 fec_restart(struct net_device *ndev, int duplex)
502 struct fec_enet_private *fep = netdev_priv(ndev);
503 const struct platform_device_id *id_entry =
504 platform_get_device_id(fep->pdev);
508 u32 rcntl = OPT_FRAME_SIZE | 0x04;
509 u32 ecntl = 0x2; /* ETHEREN */
511 if (netif_running(ndev)) {
512 netif_device_detach(ndev);
513 napi_disable(&fep->napi);
514 netif_stop_queue(ndev);
515 netif_tx_lock_bh(ndev);
518 /* Whack a reset. We should wait for this. */
519 writel(1, fep->hwp + FEC_ECNTRL);
523 * enet-mac reset will reset mac address registers too,
524 * so need to reconfigure it.
526 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
527 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
528 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
529 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
532 /* Clear any outstanding interrupt. */
533 writel(0xffc00000, fep->hwp + FEC_IEVENT);
535 /* Setup multicast filter. */
536 set_multicast_list(ndev);
538 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
539 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
542 /* Set maximum receive buffer size. */
543 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
545 fec_enet_bd_init(ndev);
547 /* Set receive and transmit descriptor base. */
548 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
550 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
551 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
553 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
554 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
557 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
558 if (fep->tx_skbuff[i]) {
559 dev_kfree_skb_any(fep->tx_skbuff[i]);
560 fep->tx_skbuff[i] = NULL;
564 /* Enable MII mode */
567 writel(0x04, fep->hwp + FEC_X_CNTRL);
571 writel(0x0, fep->hwp + FEC_X_CNTRL);
574 fep->full_duplex = duplex;
577 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
579 #if !defined(CONFIG_M5272)
580 /* set RX checksum */
581 val = readl(fep->hwp + FEC_RACC);
582 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
583 val |= FEC_RACC_OPTIONS;
585 val &= ~FEC_RACC_OPTIONS;
586 writel(val, fep->hwp + FEC_RACC);
590 * The phy interface and speed need to get configured
591 * differently on enet-mac.
593 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
594 /* Enable flow control and length check */
595 rcntl |= 0x40000000 | 0x00000020;
597 /* RGMII, RMII or MII */
598 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
600 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
605 /* 1G, 100M or 10M */
607 if (fep->phy_dev->speed == SPEED_1000)
609 else if (fep->phy_dev->speed == SPEED_100)
615 #ifdef FEC_MIIGSK_ENR
616 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
618 /* disable the gasket and wait */
619 writel(0, fep->hwp + FEC_MIIGSK_ENR);
620 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
624 * configure the gasket:
625 * RMII, 50 MHz, no loopback, no echo
626 * MII, 25 MHz, no loopback, no echo
628 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
629 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
630 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
631 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
632 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
634 /* re-enable the gasket */
635 writel(2, fep->hwp + FEC_MIIGSK_ENR);
640 #if !defined(CONFIG_M5272)
641 /* enable pause frame*/
642 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
643 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
644 fep->phy_dev && fep->phy_dev->pause)) {
645 rcntl |= FEC_ENET_FCE;
647 /* set FIFO threshold parameter to reduce overrun */
648 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
649 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
650 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
651 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
654 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
656 rcntl &= ~FEC_ENET_FCE;
658 #endif /* !defined(CONFIG_M5272) */
660 writel(rcntl, fep->hwp + FEC_R_CNTRL);
662 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
663 /* enable ENET endian swap */
665 /* enable ENET store and forward mode */
666 writel(1 << 8, fep->hwp + FEC_X_WMRK);
673 /* Enable the MIB statistic event counters */
674 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
677 /* And last, enable the transmit and receive processing */
678 writel(ecntl, fep->hwp + FEC_ECNTRL);
679 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
682 fec_ptp_start_cyclecounter(ndev);
684 /* Enable interrupts we wish to service */
685 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
687 if (netif_running(ndev)) {
688 netif_tx_unlock_bh(ndev);
689 netif_wake_queue(ndev);
690 napi_enable(&fep->napi);
691 netif_device_attach(ndev);
696 fec_stop(struct net_device *ndev)
698 struct fec_enet_private *fep = netdev_priv(ndev);
699 const struct platform_device_id *id_entry =
700 platform_get_device_id(fep->pdev);
701 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
703 /* We cannot expect a graceful transmit stop without link !!! */
705 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
707 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
708 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
711 /* Whack a reset. We should wait for this. */
712 writel(1, fep->hwp + FEC_ECNTRL);
714 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
715 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
717 /* We have to keep ENET enabled to have MII interrupt stay working */
718 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
719 writel(2, fep->hwp + FEC_ECNTRL);
720 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
726 fec_timeout(struct net_device *ndev)
728 struct fec_enet_private *fep = netdev_priv(ndev);
730 ndev->stats.tx_errors++;
732 fep->delay_work.timeout = true;
733 schedule_delayed_work(&(fep->delay_work.delay_work), 0);
736 static void fec_enet_work(struct work_struct *work)
738 struct fec_enet_private *fep =
740 struct fec_enet_private,
741 delay_work.delay_work.work);
743 if (fep->delay_work.timeout) {
744 fep->delay_work.timeout = false;
745 fec_restart(fep->netdev, fep->full_duplex);
746 netif_wake_queue(fep->netdev);
749 if (fep->delay_work.trig_tx) {
750 fep->delay_work.trig_tx = false;
751 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
756 fec_enet_tx(struct net_device *ndev)
758 struct fec_enet_private *fep;
760 unsigned short status;
764 fep = netdev_priv(ndev);
767 /* get next bdp of dirty_tx */
768 bdp = fec_enet_get_nextdesc(bdp, fep);
770 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
772 /* current queue is empty */
773 if (bdp == fep->cur_tx)
777 index = (struct bufdesc_ex *)bdp -
778 (struct bufdesc_ex *)fep->tx_bd_base;
780 index = bdp - fep->tx_bd_base;
782 skb = fep->tx_skbuff[index];
783 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, skb->len,
785 bdp->cbd_bufaddr = 0;
787 /* Check for errors. */
788 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
789 BD_ENET_TX_RL | BD_ENET_TX_UN |
791 ndev->stats.tx_errors++;
792 if (status & BD_ENET_TX_HB) /* No heartbeat */
793 ndev->stats.tx_heartbeat_errors++;
794 if (status & BD_ENET_TX_LC) /* Late collision */
795 ndev->stats.tx_window_errors++;
796 if (status & BD_ENET_TX_RL) /* Retrans limit */
797 ndev->stats.tx_aborted_errors++;
798 if (status & BD_ENET_TX_UN) /* Underrun */
799 ndev->stats.tx_fifo_errors++;
800 if (status & BD_ENET_TX_CSL) /* Carrier lost */
801 ndev->stats.tx_carrier_errors++;
803 ndev->stats.tx_packets++;
804 ndev->stats.tx_bytes += bdp->cbd_datlen;
807 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
809 struct skb_shared_hwtstamps shhwtstamps;
811 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
813 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
814 spin_lock_irqsave(&fep->tmreg_lock, flags);
815 shhwtstamps.hwtstamp = ns_to_ktime(
816 timecounter_cyc2time(&fep->tc, ebdp->ts));
817 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
818 skb_tstamp_tx(skb, &shhwtstamps);
821 if (status & BD_ENET_TX_READY)
822 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
824 /* Deferred means some collisions occurred during transmit,
825 * but we eventually sent the packet OK.
827 if (status & BD_ENET_TX_DEF)
828 ndev->stats.collisions++;
830 /* Free the sk buffer associated with this last transmit */
831 dev_kfree_skb_any(skb);
832 fep->tx_skbuff[index] = NULL;
836 /* Update pointer to next buffer descriptor to be transmitted */
837 bdp = fec_enet_get_nextdesc(bdp, fep);
839 /* Since we have freed up a buffer, the ring is no longer full
841 if (fep->dirty_tx != fep->cur_tx) {
842 if (netif_queue_stopped(ndev))
843 netif_wake_queue(ndev);
850 /* During a receive, the cur_rx points to the current incoming buffer.
851 * When we update through the ring, if the next incoming buffer has
852 * not been given to the system, we just set the empty indicator,
853 * effectively tossing the packet.
856 fec_enet_rx(struct net_device *ndev, int budget)
858 struct fec_enet_private *fep = netdev_priv(ndev);
859 const struct platform_device_id *id_entry =
860 platform_get_device_id(fep->pdev);
862 unsigned short status;
866 int pkt_received = 0;
867 struct bufdesc_ex *ebdp = NULL;
868 bool vlan_packet_rcvd = false;
876 /* First, grab all of the stats for the incoming packet.
877 * These get messed up if we get called due to a busy condition.
881 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
883 if (pkt_received >= budget)
887 /* Since we have allocated space to hold a complete frame,
888 * the last indicator should be set.
890 if ((status & BD_ENET_RX_LAST) == 0)
891 netdev_err(ndev, "rcv is not +last\n");
894 goto rx_processing_done;
896 /* Check for errors. */
897 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
898 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
899 ndev->stats.rx_errors++;
900 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
901 /* Frame too long or too short. */
902 ndev->stats.rx_length_errors++;
904 if (status & BD_ENET_RX_NO) /* Frame alignment */
905 ndev->stats.rx_frame_errors++;
906 if (status & BD_ENET_RX_CR) /* CRC Error */
907 ndev->stats.rx_crc_errors++;
908 if (status & BD_ENET_RX_OV) /* FIFO overrun */
909 ndev->stats.rx_fifo_errors++;
912 /* Report late collisions as a frame error.
913 * On this error, the BD is closed, but we don't know what we
914 * have in the buffer. So, just drop this frame on the floor.
916 if (status & BD_ENET_RX_CL) {
917 ndev->stats.rx_errors++;
918 ndev->stats.rx_frame_errors++;
919 goto rx_processing_done;
922 /* Process the incoming frame. */
923 ndev->stats.rx_packets++;
924 pkt_len = bdp->cbd_datlen;
925 ndev->stats.rx_bytes += pkt_len;
928 index = (struct bufdesc_ex *)bdp -
929 (struct bufdesc_ex *)fep->rx_bd_base;
931 index = bdp - fep->rx_bd_base;
932 data = fep->rx_skbuff[index]->data;
933 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
934 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
936 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
937 swap_buffer(data, pkt_len);
939 /* Extract the enhanced buffer descriptor */
942 ebdp = (struct bufdesc_ex *)bdp;
944 /* If this is a VLAN packet remove the VLAN Tag */
945 vlan_packet_rcvd = false;
946 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
947 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
948 /* Push and remove the vlan tag */
949 struct vlan_hdr *vlan_header =
950 (struct vlan_hdr *) (data + ETH_HLEN);
951 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
952 pkt_len -= VLAN_HLEN;
954 vlan_packet_rcvd = true;
957 /* This does 16 byte alignment, exactly what we need.
958 * The packet length includes FCS, but we don't want to
959 * include that when passing upstream as it messes up
960 * bridging applications.
962 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
964 if (unlikely(!skb)) {
965 ndev->stats.rx_dropped++;
967 int payload_offset = (2 * ETH_ALEN);
968 skb_reserve(skb, NET_IP_ALIGN);
969 skb_put(skb, pkt_len - 4); /* Make room */
971 /* Extract the frame data without the VLAN header. */
972 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
973 if (vlan_packet_rcvd)
974 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
975 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
976 data + payload_offset,
977 pkt_len - 4 - (2 * ETH_ALEN));
979 skb->protocol = eth_type_trans(skb, ndev);
981 /* Get receive timestamp from the skb */
982 if (fep->hwts_rx_en && fep->bufdesc_ex) {
983 struct skb_shared_hwtstamps *shhwtstamps =
987 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
989 spin_lock_irqsave(&fep->tmreg_lock, flags);
990 shhwtstamps->hwtstamp = ns_to_ktime(
991 timecounter_cyc2time(&fep->tc, ebdp->ts));
992 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
995 if (fep->bufdesc_ex &&
996 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
997 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
999 skb->ip_summed = CHECKSUM_UNNECESSARY;
1001 skb_checksum_none_assert(skb);
1005 /* Handle received VLAN packets */
1006 if (vlan_packet_rcvd)
1007 __vlan_hwaccel_put_tag(skb,
1011 napi_gro_receive(&fep->napi, skb);
1014 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1015 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1017 /* Clear the status flags for this buffer */
1018 status &= ~BD_ENET_RX_STATS;
1020 /* Mark the buffer empty */
1021 status |= BD_ENET_RX_EMPTY;
1022 bdp->cbd_sc = status;
1024 if (fep->bufdesc_ex) {
1025 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1027 ebdp->cbd_esc = BD_ENET_RX_INT;
1032 /* Update BD pointer to next entry */
1033 bdp = fec_enet_get_nextdesc(bdp, fep);
1035 /* Doing this here will keep the FEC running while we process
1036 * incoming frames. On a heavily loaded network, we should be
1037 * able to keep up at the expense of system resources.
1039 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1043 return pkt_received;
1047 fec_enet_interrupt(int irq, void *dev_id)
1049 struct net_device *ndev = dev_id;
1050 struct fec_enet_private *fep = netdev_priv(ndev);
1052 irqreturn_t ret = IRQ_NONE;
1055 int_events = readl(fep->hwp + FEC_IEVENT);
1056 writel(int_events, fep->hwp + FEC_IEVENT);
1058 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
1061 /* Disable the RX interrupt */
1062 if (napi_schedule_prep(&fep->napi)) {
1063 writel(FEC_RX_DISABLED_IMASK,
1064 fep->hwp + FEC_IMASK);
1065 __napi_schedule(&fep->napi);
1069 if (int_events & FEC_ENET_MII) {
1071 complete(&fep->mdio_done);
1073 } while (int_events);
1078 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1080 struct net_device *ndev = napi->dev;
1081 int pkts = fec_enet_rx(ndev, budget);
1082 struct fec_enet_private *fep = netdev_priv(ndev);
1086 if (pkts < budget) {
1087 napi_complete(napi);
1088 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1093 /* ------------------------------------------------------------------------- */
1094 static void fec_get_mac(struct net_device *ndev)
1096 struct fec_enet_private *fep = netdev_priv(ndev);
1097 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1098 unsigned char *iap, tmpaddr[ETH_ALEN];
1101 * try to get mac address in following order:
1103 * 1) module parameter via kernel command line in form
1104 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1109 * 2) from device tree data
1111 if (!is_valid_ether_addr(iap)) {
1112 struct device_node *np = fep->pdev->dev.of_node;
1114 const char *mac = of_get_mac_address(np);
1116 iap = (unsigned char *) mac;
1121 * 3) from flash or fuse (via platform data)
1123 if (!is_valid_ether_addr(iap)) {
1126 iap = (unsigned char *)FEC_FLASHMAC;
1129 iap = (unsigned char *)&pdata->mac;
1134 * 4) FEC mac registers set by bootloader
1136 if (!is_valid_ether_addr(iap)) {
1137 *((__be32 *) &tmpaddr[0]) =
1138 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1139 *((__be16 *) &tmpaddr[4]) =
1140 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1145 * 5) random mac address
1147 if (!is_valid_ether_addr(iap)) {
1148 /* Report it and use a random ethernet address instead */
1149 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1150 eth_hw_addr_random(ndev);
1151 netdev_info(ndev, "Using random MAC address: %pM\n",
1156 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1158 /* Adjust MAC if using macaddr */
1160 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1163 /* ------------------------------------------------------------------------- */
1168 static void fec_enet_adjust_link(struct net_device *ndev)
1170 struct fec_enet_private *fep = netdev_priv(ndev);
1171 struct phy_device *phy_dev = fep->phy_dev;
1172 int status_change = 0;
1174 /* Prevent a state halted on mii error */
1175 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1176 phy_dev->state = PHY_RESUMING;
1180 if (phy_dev->link) {
1182 fep->link = phy_dev->link;
1186 if (fep->full_duplex != phy_dev->duplex)
1189 if (phy_dev->speed != fep->speed) {
1190 fep->speed = phy_dev->speed;
1194 /* if any of the above changed restart the FEC */
1196 fec_restart(ndev, phy_dev->duplex);
1200 fep->link = phy_dev->link;
1206 phy_print_status(phy_dev);
1209 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1211 struct fec_enet_private *fep = bus->priv;
1212 unsigned long time_left;
1214 fep->mii_timeout = 0;
1215 init_completion(&fep->mdio_done);
1217 /* start a read op */
1218 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1219 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1220 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1222 /* wait for end of transfer */
1223 time_left = wait_for_completion_timeout(&fep->mdio_done,
1224 usecs_to_jiffies(FEC_MII_TIMEOUT));
1225 if (time_left == 0) {
1226 fep->mii_timeout = 1;
1227 netdev_err(fep->netdev, "MDIO read timeout\n");
1232 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1235 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1238 struct fec_enet_private *fep = bus->priv;
1239 unsigned long time_left;
1241 fep->mii_timeout = 0;
1242 init_completion(&fep->mdio_done);
1244 /* start a write op */
1245 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1246 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1247 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1248 fep->hwp + FEC_MII_DATA);
1250 /* wait for end of transfer */
1251 time_left = wait_for_completion_timeout(&fep->mdio_done,
1252 usecs_to_jiffies(FEC_MII_TIMEOUT));
1253 if (time_left == 0) {
1254 fep->mii_timeout = 1;
1255 netdev_err(fep->netdev, "MDIO write timeout\n");
1262 static int fec_enet_mdio_reset(struct mii_bus *bus)
1267 static int fec_enet_mii_probe(struct net_device *ndev)
1269 struct fec_enet_private *fep = netdev_priv(ndev);
1270 const struct platform_device_id *id_entry =
1271 platform_get_device_id(fep->pdev);
1272 struct phy_device *phy_dev = NULL;
1273 char mdio_bus_id[MII_BUS_ID_SIZE];
1274 char phy_name[MII_BUS_ID_SIZE + 3];
1276 int dev_id = fep->dev_id;
1278 fep->phy_dev = NULL;
1280 /* check for attached phy */
1281 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1282 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1284 if (fep->mii_bus->phy_map[phy_id] == NULL)
1286 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1290 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1294 if (phy_id >= PHY_MAX_ADDR) {
1295 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1296 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1300 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1301 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1302 fep->phy_interface);
1303 if (IS_ERR(phy_dev)) {
1304 netdev_err(ndev, "could not attach to PHY\n");
1305 return PTR_ERR(phy_dev);
1308 /* mask with MAC supported features */
1309 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1310 phy_dev->supported &= PHY_GBIT_FEATURES;
1311 #if !defined(CONFIG_M5272)
1312 phy_dev->supported |= SUPPORTED_Pause;
1316 phy_dev->supported &= PHY_BASIC_FEATURES;
1318 phy_dev->advertising = phy_dev->supported;
1320 fep->phy_dev = phy_dev;
1322 fep->full_duplex = 0;
1324 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1325 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1331 static int fec_enet_mii_init(struct platform_device *pdev)
1333 static struct mii_bus *fec0_mii_bus;
1334 struct net_device *ndev = platform_get_drvdata(pdev);
1335 struct fec_enet_private *fep = netdev_priv(ndev);
1336 const struct platform_device_id *id_entry =
1337 platform_get_device_id(fep->pdev);
1338 int err = -ENXIO, i;
1341 * The dual fec interfaces are not equivalent with enet-mac.
1342 * Here are the differences:
1344 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1345 * - fec0 acts as the 1588 time master while fec1 is slave
1346 * - external phys can only be configured by fec0
1348 * That is to say fec1 can not work independently. It only works
1349 * when fec0 is working. The reason behind this design is that the
1350 * second interface is added primarily for Switch mode.
1352 * Because of the last point above, both phys are attached on fec0
1353 * mdio interface in board design, and need to be configured by
1356 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1357 /* fec1 uses fec0 mii_bus */
1358 if (mii_cnt && fec0_mii_bus) {
1359 fep->mii_bus = fec0_mii_bus;
1366 fep->mii_timeout = 0;
1369 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1371 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1372 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1373 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1376 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1377 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1379 fep->phy_speed <<= 1;
1380 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1382 fep->mii_bus = mdiobus_alloc();
1383 if (fep->mii_bus == NULL) {
1388 fep->mii_bus->name = "fec_enet_mii_bus";
1389 fep->mii_bus->read = fec_enet_mdio_read;
1390 fep->mii_bus->write = fec_enet_mdio_write;
1391 fep->mii_bus->reset = fec_enet_mdio_reset;
1392 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1393 pdev->name, fep->dev_id + 1);
1394 fep->mii_bus->priv = fep;
1395 fep->mii_bus->parent = &pdev->dev;
1397 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1398 if (!fep->mii_bus->irq) {
1400 goto err_out_free_mdiobus;
1403 for (i = 0; i < PHY_MAX_ADDR; i++)
1404 fep->mii_bus->irq[i] = PHY_POLL;
1406 if (mdiobus_register(fep->mii_bus))
1407 goto err_out_free_mdio_irq;
1411 /* save fec0 mii_bus */
1412 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1413 fec0_mii_bus = fep->mii_bus;
1417 err_out_free_mdio_irq:
1418 kfree(fep->mii_bus->irq);
1419 err_out_free_mdiobus:
1420 mdiobus_free(fep->mii_bus);
1425 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1427 if (--mii_cnt == 0) {
1428 mdiobus_unregister(fep->mii_bus);
1429 kfree(fep->mii_bus->irq);
1430 mdiobus_free(fep->mii_bus);
1434 static int fec_enet_get_settings(struct net_device *ndev,
1435 struct ethtool_cmd *cmd)
1437 struct fec_enet_private *fep = netdev_priv(ndev);
1438 struct phy_device *phydev = fep->phy_dev;
1443 return phy_ethtool_gset(phydev, cmd);
1446 static int fec_enet_set_settings(struct net_device *ndev,
1447 struct ethtool_cmd *cmd)
1449 struct fec_enet_private *fep = netdev_priv(ndev);
1450 struct phy_device *phydev = fep->phy_dev;
1455 return phy_ethtool_sset(phydev, cmd);
1458 static void fec_enet_get_drvinfo(struct net_device *ndev,
1459 struct ethtool_drvinfo *info)
1461 struct fec_enet_private *fep = netdev_priv(ndev);
1463 strlcpy(info->driver, fep->pdev->dev.driver->name,
1464 sizeof(info->driver));
1465 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1466 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1469 static int fec_enet_get_ts_info(struct net_device *ndev,
1470 struct ethtool_ts_info *info)
1472 struct fec_enet_private *fep = netdev_priv(ndev);
1474 if (fep->bufdesc_ex) {
1476 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1477 SOF_TIMESTAMPING_RX_SOFTWARE |
1478 SOF_TIMESTAMPING_SOFTWARE |
1479 SOF_TIMESTAMPING_TX_HARDWARE |
1480 SOF_TIMESTAMPING_RX_HARDWARE |
1481 SOF_TIMESTAMPING_RAW_HARDWARE;
1483 info->phc_index = ptp_clock_index(fep->ptp_clock);
1485 info->phc_index = -1;
1487 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1488 (1 << HWTSTAMP_TX_ON);
1490 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1491 (1 << HWTSTAMP_FILTER_ALL);
1494 return ethtool_op_get_ts_info(ndev, info);
1498 #if !defined(CONFIG_M5272)
1500 static void fec_enet_get_pauseparam(struct net_device *ndev,
1501 struct ethtool_pauseparam *pause)
1503 struct fec_enet_private *fep = netdev_priv(ndev);
1505 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1506 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1507 pause->rx_pause = pause->tx_pause;
1510 static int fec_enet_set_pauseparam(struct net_device *ndev,
1511 struct ethtool_pauseparam *pause)
1513 struct fec_enet_private *fep = netdev_priv(ndev);
1515 if (pause->tx_pause != pause->rx_pause) {
1517 "hardware only support enable/disable both tx and rx");
1521 fep->pause_flag = 0;
1523 /* tx pause must be same as rx pause */
1524 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1525 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1527 if (pause->rx_pause || pause->autoneg) {
1528 fep->phy_dev->supported |= ADVERTISED_Pause;
1529 fep->phy_dev->advertising |= ADVERTISED_Pause;
1531 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1532 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1535 if (pause->autoneg) {
1536 if (netif_running(ndev))
1538 phy_start_aneg(fep->phy_dev);
1540 if (netif_running(ndev))
1541 fec_restart(ndev, 0);
1546 static const struct fec_stat {
1547 char name[ETH_GSTRING_LEN];
1551 { "tx_dropped", RMON_T_DROP },
1552 { "tx_packets", RMON_T_PACKETS },
1553 { "tx_broadcast", RMON_T_BC_PKT },
1554 { "tx_multicast", RMON_T_MC_PKT },
1555 { "tx_crc_errors", RMON_T_CRC_ALIGN },
1556 { "tx_undersize", RMON_T_UNDERSIZE },
1557 { "tx_oversize", RMON_T_OVERSIZE },
1558 { "tx_fragment", RMON_T_FRAG },
1559 { "tx_jabber", RMON_T_JAB },
1560 { "tx_collision", RMON_T_COL },
1561 { "tx_64byte", RMON_T_P64 },
1562 { "tx_65to127byte", RMON_T_P65TO127 },
1563 { "tx_128to255byte", RMON_T_P128TO255 },
1564 { "tx_256to511byte", RMON_T_P256TO511 },
1565 { "tx_512to1023byte", RMON_T_P512TO1023 },
1566 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
1567 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
1568 { "tx_octets", RMON_T_OCTETS },
1571 { "IEEE_tx_drop", IEEE_T_DROP },
1572 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
1573 { "IEEE_tx_1col", IEEE_T_1COL },
1574 { "IEEE_tx_mcol", IEEE_T_MCOL },
1575 { "IEEE_tx_def", IEEE_T_DEF },
1576 { "IEEE_tx_lcol", IEEE_T_LCOL },
1577 { "IEEE_tx_excol", IEEE_T_EXCOL },
1578 { "IEEE_tx_macerr", IEEE_T_MACERR },
1579 { "IEEE_tx_cserr", IEEE_T_CSERR },
1580 { "IEEE_tx_sqe", IEEE_T_SQE },
1581 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
1582 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
1585 { "rx_packets", RMON_R_PACKETS },
1586 { "rx_broadcast", RMON_R_BC_PKT },
1587 { "rx_multicast", RMON_R_MC_PKT },
1588 { "rx_crc_errors", RMON_R_CRC_ALIGN },
1589 { "rx_undersize", RMON_R_UNDERSIZE },
1590 { "rx_oversize", RMON_R_OVERSIZE },
1591 { "rx_fragment", RMON_R_FRAG },
1592 { "rx_jabber", RMON_R_JAB },
1593 { "rx_64byte", RMON_R_P64 },
1594 { "rx_65to127byte", RMON_R_P65TO127 },
1595 { "rx_128to255byte", RMON_R_P128TO255 },
1596 { "rx_256to511byte", RMON_R_P256TO511 },
1597 { "rx_512to1023byte", RMON_R_P512TO1023 },
1598 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
1599 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
1600 { "rx_octets", RMON_R_OCTETS },
1603 { "IEEE_rx_drop", IEEE_R_DROP },
1604 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
1605 { "IEEE_rx_crc", IEEE_R_CRC },
1606 { "IEEE_rx_align", IEEE_R_ALIGN },
1607 { "IEEE_rx_macerr", IEEE_R_MACERR },
1608 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
1609 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
1612 static void fec_enet_get_ethtool_stats(struct net_device *dev,
1613 struct ethtool_stats *stats, u64 *data)
1615 struct fec_enet_private *fep = netdev_priv(dev);
1618 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1619 data[i] = readl(fep->hwp + fec_stats[i].offset);
1622 static void fec_enet_get_strings(struct net_device *netdev,
1623 u32 stringset, u8 *data)
1626 switch (stringset) {
1628 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1629 memcpy(data + i * ETH_GSTRING_LEN,
1630 fec_stats[i].name, ETH_GSTRING_LEN);
1635 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
1639 return ARRAY_SIZE(fec_stats);
1644 #endif /* !defined(CONFIG_M5272) */
1646 static int fec_enet_nway_reset(struct net_device *dev)
1648 struct fec_enet_private *fep = netdev_priv(dev);
1649 struct phy_device *phydev = fep->phy_dev;
1654 return genphy_restart_aneg(phydev);
1657 static const struct ethtool_ops fec_enet_ethtool_ops = {
1658 #if !defined(CONFIG_M5272)
1659 .get_pauseparam = fec_enet_get_pauseparam,
1660 .set_pauseparam = fec_enet_set_pauseparam,
1662 .get_settings = fec_enet_get_settings,
1663 .set_settings = fec_enet_set_settings,
1664 .get_drvinfo = fec_enet_get_drvinfo,
1665 .get_link = ethtool_op_get_link,
1666 .get_ts_info = fec_enet_get_ts_info,
1667 .nway_reset = fec_enet_nway_reset,
1668 #ifndef CONFIG_M5272
1669 .get_ethtool_stats = fec_enet_get_ethtool_stats,
1670 .get_strings = fec_enet_get_strings,
1671 .get_sset_count = fec_enet_get_sset_count,
1675 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1677 struct fec_enet_private *fep = netdev_priv(ndev);
1678 struct phy_device *phydev = fep->phy_dev;
1680 if (!netif_running(ndev))
1686 if (fep->bufdesc_ex) {
1687 if (cmd == SIOCSHWTSTAMP)
1688 return fec_ptp_set(ndev, rq);
1689 if (cmd == SIOCGHWTSTAMP)
1690 return fec_ptp_get(ndev, rq);
1693 return phy_mii_ioctl(phydev, rq, cmd);
1696 static void fec_enet_free_buffers(struct net_device *ndev)
1698 struct fec_enet_private *fep = netdev_priv(ndev);
1700 struct sk_buff *skb;
1701 struct bufdesc *bdp;
1703 bdp = fep->rx_bd_base;
1704 for (i = 0; i < fep->rx_ring_size; i++) {
1705 skb = fep->rx_skbuff[i];
1707 if (bdp->cbd_bufaddr)
1708 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1709 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1712 bdp = fec_enet_get_nextdesc(bdp, fep);
1715 bdp = fep->tx_bd_base;
1716 for (i = 0; i < fep->tx_ring_size; i++)
1717 kfree(fep->tx_bounce[i]);
1720 static int fec_enet_alloc_buffers(struct net_device *ndev)
1722 struct fec_enet_private *fep = netdev_priv(ndev);
1724 struct sk_buff *skb;
1725 struct bufdesc *bdp;
1727 bdp = fep->rx_bd_base;
1728 for (i = 0; i < fep->rx_ring_size; i++) {
1729 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1731 fec_enet_free_buffers(ndev);
1734 fep->rx_skbuff[i] = skb;
1736 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1737 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1738 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1739 fec_enet_free_buffers(ndev);
1740 if (net_ratelimit())
1741 netdev_err(ndev, "Rx DMA memory map failed\n");
1744 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1746 if (fep->bufdesc_ex) {
1747 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1748 ebdp->cbd_esc = BD_ENET_RX_INT;
1751 bdp = fec_enet_get_nextdesc(bdp, fep);
1754 /* Set the last buffer to wrap. */
1755 bdp = fec_enet_get_prevdesc(bdp, fep);
1756 bdp->cbd_sc |= BD_SC_WRAP;
1758 bdp = fep->tx_bd_base;
1759 for (i = 0; i < fep->tx_ring_size; i++) {
1760 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1763 bdp->cbd_bufaddr = 0;
1765 if (fep->bufdesc_ex) {
1766 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1767 ebdp->cbd_esc = BD_ENET_TX_INT;
1770 bdp = fec_enet_get_nextdesc(bdp, fep);
1773 /* Set the last buffer to wrap. */
1774 bdp = fec_enet_get_prevdesc(bdp, fep);
1775 bdp->cbd_sc |= BD_SC_WRAP;
1781 fec_enet_open(struct net_device *ndev)
1783 struct fec_enet_private *fep = netdev_priv(ndev);
1786 napi_enable(&fep->napi);
1788 /* I should reset the ring buffers here, but I don't yet know
1789 * a simple way to do that.
1792 ret = fec_enet_alloc_buffers(ndev);
1796 /* Probe and connect to PHY when open the interface */
1797 ret = fec_enet_mii_probe(ndev);
1799 fec_enet_free_buffers(ndev);
1802 phy_start(fep->phy_dev);
1803 netif_start_queue(ndev);
1809 fec_enet_close(struct net_device *ndev)
1811 struct fec_enet_private *fep = netdev_priv(ndev);
1813 /* Don't know what to do yet. */
1814 napi_disable(&fep->napi);
1816 netif_stop_queue(ndev);
1820 phy_stop(fep->phy_dev);
1821 phy_disconnect(fep->phy_dev);
1824 fec_enet_free_buffers(ndev);
1829 /* Set or clear the multicast filter for this adaptor.
1830 * Skeleton taken from sunlance driver.
1831 * The CPM Ethernet implementation allows Multicast as well as individual
1832 * MAC address filtering. Some of the drivers check to make sure it is
1833 * a group multicast address, and discard those that are not. I guess I
1834 * will do the same for now, but just remove the test if you want
1835 * individual filtering as well (do the upper net layers want or support
1836 * this kind of feature?).
1839 #define HASH_BITS 6 /* #bits in hash */
1840 #define CRC32_POLY 0xEDB88320
1842 static void set_multicast_list(struct net_device *ndev)
1844 struct fec_enet_private *fep = netdev_priv(ndev);
1845 struct netdev_hw_addr *ha;
1846 unsigned int i, bit, data, crc, tmp;
1849 if (ndev->flags & IFF_PROMISC) {
1850 tmp = readl(fep->hwp + FEC_R_CNTRL);
1852 writel(tmp, fep->hwp + FEC_R_CNTRL);
1856 tmp = readl(fep->hwp + FEC_R_CNTRL);
1858 writel(tmp, fep->hwp + FEC_R_CNTRL);
1860 if (ndev->flags & IFF_ALLMULTI) {
1861 /* Catch all multicast addresses, so set the
1864 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1865 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1870 /* Clear filter and add the addresses in hash register
1872 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1873 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1875 netdev_for_each_mc_addr(ha, ndev) {
1876 /* calculate crc32 value of mac address */
1879 for (i = 0; i < ndev->addr_len; i++) {
1881 for (bit = 0; bit < 8; bit++, data >>= 1) {
1883 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1887 /* only upper 6 bits (HASH_BITS) are used
1888 * which point to specific bit in he hash registers
1890 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1893 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1894 tmp |= 1 << (hash - 32);
1895 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1897 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1899 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1904 /* Set a MAC change in hardware. */
1906 fec_set_mac_address(struct net_device *ndev, void *p)
1908 struct fec_enet_private *fep = netdev_priv(ndev);
1909 struct sockaddr *addr = p;
1911 if (!is_valid_ether_addr(addr->sa_data))
1912 return -EADDRNOTAVAIL;
1914 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1916 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1917 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1918 fep->hwp + FEC_ADDR_LOW);
1919 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1920 fep->hwp + FEC_ADDR_HIGH);
1924 #ifdef CONFIG_NET_POLL_CONTROLLER
1926 * fec_poll_controller - FEC Poll controller function
1927 * @dev: The FEC network adapter
1929 * Polled functionality used by netconsole and others in non interrupt mode
1932 static void fec_poll_controller(struct net_device *dev)
1935 struct fec_enet_private *fep = netdev_priv(dev);
1937 for (i = 0; i < FEC_IRQ_NUM; i++) {
1938 if (fep->irq[i] > 0) {
1939 disable_irq(fep->irq[i]);
1940 fec_enet_interrupt(fep->irq[i], dev);
1941 enable_irq(fep->irq[i]);
1947 static int fec_set_features(struct net_device *netdev,
1948 netdev_features_t features)
1950 struct fec_enet_private *fep = netdev_priv(netdev);
1951 netdev_features_t changed = features ^ netdev->features;
1953 netdev->features = features;
1955 /* Receive checksum has been changed */
1956 if (changed & NETIF_F_RXCSUM) {
1957 if (features & NETIF_F_RXCSUM)
1958 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
1960 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
1962 if (netif_running(netdev)) {
1964 fec_restart(netdev, fep->phy_dev->duplex);
1965 netif_wake_queue(netdev);
1967 fec_restart(netdev, fep->phy_dev->duplex);
1974 static const struct net_device_ops fec_netdev_ops = {
1975 .ndo_open = fec_enet_open,
1976 .ndo_stop = fec_enet_close,
1977 .ndo_start_xmit = fec_enet_start_xmit,
1978 .ndo_set_rx_mode = set_multicast_list,
1979 .ndo_change_mtu = eth_change_mtu,
1980 .ndo_validate_addr = eth_validate_addr,
1981 .ndo_tx_timeout = fec_timeout,
1982 .ndo_set_mac_address = fec_set_mac_address,
1983 .ndo_do_ioctl = fec_enet_ioctl,
1984 #ifdef CONFIG_NET_POLL_CONTROLLER
1985 .ndo_poll_controller = fec_poll_controller,
1987 .ndo_set_features = fec_set_features,
1991 * XXX: We need to clean up on failure exits here.
1994 static int fec_enet_init(struct net_device *ndev)
1996 struct fec_enet_private *fep = netdev_priv(ndev);
1997 const struct platform_device_id *id_entry =
1998 platform_get_device_id(fep->pdev);
1999 struct bufdesc *cbd_base;
2001 /* Allocate memory for buffer descriptors. */
2002 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
2007 memset(cbd_base, 0, PAGE_SIZE);
2011 /* Get the Ethernet address */
2014 /* init the tx & rx ring size */
2015 fep->tx_ring_size = TX_RING_SIZE;
2016 fep->rx_ring_size = RX_RING_SIZE;
2018 /* Set receive and transmit descriptor base. */
2019 fep->rx_bd_base = cbd_base;
2020 if (fep->bufdesc_ex)
2021 fep->tx_bd_base = (struct bufdesc *)
2022 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size);
2024 fep->tx_bd_base = cbd_base + fep->rx_ring_size;
2026 /* The FEC Ethernet specific entries in the device structure */
2027 ndev->watchdog_timeo = TX_TIMEOUT;
2028 ndev->netdev_ops = &fec_netdev_ops;
2029 ndev->ethtool_ops = &fec_enet_ethtool_ops;
2031 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
2032 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
2034 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) {
2035 /* enable hw VLAN support */
2036 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2037 ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2040 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
2041 /* enable hw accelerator */
2042 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2044 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2046 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2049 fec_restart(ndev, 0);
2055 static void fec_reset_phy(struct platform_device *pdev)
2059 struct device_node *np = pdev->dev.of_node;
2064 of_property_read_u32(np, "phy-reset-duration", &msec);
2065 /* A sane reset duration should not be longer than 1s */
2069 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
2070 if (!gpio_is_valid(phy_reset))
2073 err = devm_gpio_request_one(&pdev->dev, phy_reset,
2074 GPIOF_OUT_INIT_LOW, "phy-reset");
2076 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
2080 gpio_set_value(phy_reset, 1);
2082 #else /* CONFIG_OF */
2083 static void fec_reset_phy(struct platform_device *pdev)
2086 * In case of platform probe, the reset has been done
2090 #endif /* CONFIG_OF */
2093 fec_probe(struct platform_device *pdev)
2095 struct fec_enet_private *fep;
2096 struct fec_platform_data *pdata;
2097 struct net_device *ndev;
2098 int i, irq, ret = 0;
2100 const struct of_device_id *of_id;
2103 of_id = of_match_device(fec_dt_ids, &pdev->dev);
2105 pdev->id_entry = of_id->data;
2107 /* Init network device */
2108 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
2112 SET_NETDEV_DEV(ndev, &pdev->dev);
2114 /* setup board info structure */
2115 fep = netdev_priv(ndev);
2117 #if !defined(CONFIG_M5272)
2118 /* default enable pause frame auto negotiation */
2119 if (pdev->id_entry &&
2120 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
2121 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
2124 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2125 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
2126 if (IS_ERR(fep->hwp)) {
2127 ret = PTR_ERR(fep->hwp);
2128 goto failed_ioremap;
2132 fep->dev_id = dev_id++;
2134 fep->bufdesc_ex = 0;
2136 platform_set_drvdata(pdev, ndev);
2138 ret = of_get_phy_mode(pdev->dev.of_node);
2140 pdata = dev_get_platdata(&pdev->dev);
2142 fep->phy_interface = pdata->phy;
2144 fep->phy_interface = PHY_INTERFACE_MODE_MII;
2146 fep->phy_interface = ret;
2149 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2150 if (IS_ERR(fep->clk_ipg)) {
2151 ret = PTR_ERR(fep->clk_ipg);
2155 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2156 if (IS_ERR(fep->clk_ahb)) {
2157 ret = PTR_ERR(fep->clk_ahb);
2161 /* enet_out is optional, depends on board */
2162 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
2163 if (IS_ERR(fep->clk_enet_out))
2164 fep->clk_enet_out = NULL;
2166 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
2168 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
2169 if (IS_ERR(fep->clk_ptp)) {
2170 fep->clk_ptp = NULL;
2171 fep->bufdesc_ex = 0;
2174 ret = clk_prepare_enable(fep->clk_ahb);
2178 ret = clk_prepare_enable(fep->clk_ipg);
2180 goto failed_clk_ipg;
2182 if (fep->clk_enet_out) {
2183 ret = clk_prepare_enable(fep->clk_enet_out);
2185 goto failed_clk_enet_out;
2189 ret = clk_prepare_enable(fep->clk_ptp);
2191 goto failed_clk_ptp;
2194 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
2195 if (!IS_ERR(fep->reg_phy)) {
2196 ret = regulator_enable(fep->reg_phy);
2199 "Failed to enable phy regulator: %d\n", ret);
2200 goto failed_regulator;
2203 fep->reg_phy = NULL;
2206 fec_reset_phy(pdev);
2208 if (fep->bufdesc_ex)
2211 ret = fec_enet_init(ndev);
2215 for (i = 0; i < FEC_IRQ_NUM; i++) {
2216 irq = platform_get_irq(pdev, i);
2223 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
2224 0, pdev->name, ndev);
2229 ret = fec_enet_mii_init(pdev);
2231 goto failed_mii_init;
2233 /* Carrier starts down, phylib will bring it up */
2234 netif_carrier_off(ndev);
2236 ret = register_netdev(ndev);
2238 goto failed_register;
2240 if (fep->bufdesc_ex && fep->ptp_clock)
2241 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
2243 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
2247 fec_enet_mii_remove(fep);
2252 regulator_disable(fep->reg_phy);
2255 clk_disable_unprepare(fep->clk_ptp);
2257 if (fep->clk_enet_out)
2258 clk_disable_unprepare(fep->clk_enet_out);
2259 failed_clk_enet_out:
2260 clk_disable_unprepare(fep->clk_ipg);
2262 clk_disable_unprepare(fep->clk_ahb);
2271 fec_drv_remove(struct platform_device *pdev)
2273 struct net_device *ndev = platform_get_drvdata(pdev);
2274 struct fec_enet_private *fep = netdev_priv(ndev);
2276 cancel_delayed_work_sync(&(fep->delay_work.delay_work));
2277 unregister_netdev(ndev);
2278 fec_enet_mii_remove(fep);
2279 del_timer_sync(&fep->time_keep);
2281 regulator_disable(fep->reg_phy);
2283 clk_disable_unprepare(fep->clk_ptp);
2285 ptp_clock_unregister(fep->ptp_clock);
2286 if (fep->clk_enet_out)
2287 clk_disable_unprepare(fep->clk_enet_out);
2288 clk_disable_unprepare(fep->clk_ipg);
2289 clk_disable_unprepare(fep->clk_ahb);
2295 #ifdef CONFIG_PM_SLEEP
2297 fec_suspend(struct device *dev)
2299 struct net_device *ndev = dev_get_drvdata(dev);
2300 struct fec_enet_private *fep = netdev_priv(ndev);
2302 if (netif_running(ndev)) {
2304 netif_device_detach(ndev);
2307 clk_disable_unprepare(fep->clk_ptp);
2308 if (fep->clk_enet_out)
2309 clk_disable_unprepare(fep->clk_enet_out);
2310 clk_disable_unprepare(fep->clk_ipg);
2311 clk_disable_unprepare(fep->clk_ahb);
2314 regulator_disable(fep->reg_phy);
2320 fec_resume(struct device *dev)
2322 struct net_device *ndev = dev_get_drvdata(dev);
2323 struct fec_enet_private *fep = netdev_priv(ndev);
2327 ret = regulator_enable(fep->reg_phy);
2332 ret = clk_prepare_enable(fep->clk_ahb);
2334 goto failed_clk_ahb;
2336 ret = clk_prepare_enable(fep->clk_ipg);
2338 goto failed_clk_ipg;
2340 if (fep->clk_enet_out) {
2341 ret = clk_prepare_enable(fep->clk_enet_out);
2343 goto failed_clk_enet_out;
2347 ret = clk_prepare_enable(fep->clk_ptp);
2349 goto failed_clk_ptp;
2352 if (netif_running(ndev)) {
2353 fec_restart(ndev, fep->full_duplex);
2354 netif_device_attach(ndev);
2360 if (fep->clk_enet_out)
2361 clk_disable_unprepare(fep->clk_enet_out);
2362 failed_clk_enet_out:
2363 clk_disable_unprepare(fep->clk_ipg);
2365 clk_disable_unprepare(fep->clk_ahb);
2368 regulator_disable(fep->reg_phy);
2371 #endif /* CONFIG_PM_SLEEP */
2373 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
2375 static struct platform_driver fec_driver = {
2377 .name = DRIVER_NAME,
2378 .owner = THIS_MODULE,
2380 .of_match_table = fec_dt_ids,
2382 .id_table = fec_devtype,
2384 .remove = fec_drv_remove,
2387 module_platform_driver(fec_driver);
2389 MODULE_ALIAS("platform:"DRIVER_NAME);
2390 MODULE_LICENSE("GPL");