2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/bitops.h>
41 #include <linux/cache.h>
42 #include <linux/interrupt.h>
43 #include <linux/list.h>
44 #include <linux/netdevice.h>
45 #include <linux/pci.h>
46 #include <linux/spinlock.h>
47 #include <linux/timer.h>
48 #include <linux/vmalloc.h>
50 #include "cxgb4_uld.h"
52 #define T4FW_VERSION_MAJOR 0x01
53 #define T4FW_VERSION_MINOR 0x06
54 #define T4FW_VERSION_MICRO 0x18
55 #define T4FW_VERSION_BUILD 0x00
57 #define T5FW_VERSION_MAJOR 0x01
58 #define T5FW_VERSION_MINOR 0x08
59 #define T5FW_VERSION_MICRO 0x1C
60 #define T5FW_VERSION_BUILD 0x00
62 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
65 MAX_NPORTS = 4, /* max # of ports */
66 SERNUM_LEN = 24, /* Serial # length */
67 EC_LEN = 16, /* E/C length */
68 ID_LEN = 16, /* ID length */
80 MEMWIN0_APERTURE = 2048,
81 MEMWIN0_BASE = 0x1b800,
82 MEMWIN1_APERTURE = 32768,
83 MEMWIN1_BASE = 0x28000,
84 MEMWIN1_BASE_T5 = 0x52000,
85 MEMWIN2_APERTURE = 65536,
86 MEMWIN2_BASE = 0x30000,
87 MEMWIN2_BASE_T5 = 0x54000,
105 PAUSE_AUTONEG = 1 << 2
109 u64 tx_octets; /* total # of octets in good frames */
110 u64 tx_frames; /* all good frames */
111 u64 tx_bcast_frames; /* all broadcast frames */
112 u64 tx_mcast_frames; /* all multicast frames */
113 u64 tx_ucast_frames; /* all unicast frames */
114 u64 tx_error_frames; /* all error frames */
116 u64 tx_frames_64; /* # of Tx frames in a particular range */
117 u64 tx_frames_65_127;
118 u64 tx_frames_128_255;
119 u64 tx_frames_256_511;
120 u64 tx_frames_512_1023;
121 u64 tx_frames_1024_1518;
122 u64 tx_frames_1519_max;
124 u64 tx_drop; /* # of dropped Tx frames */
125 u64 tx_pause; /* # of transmitted pause frames */
126 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
127 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
128 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
129 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
130 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
131 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
132 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
133 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
135 u64 rx_octets; /* total # of octets in good frames */
136 u64 rx_frames; /* all good frames */
137 u64 rx_bcast_frames; /* all broadcast frames */
138 u64 rx_mcast_frames; /* all multicast frames */
139 u64 rx_ucast_frames; /* all unicast frames */
140 u64 rx_too_long; /* # of frames exceeding MTU */
141 u64 rx_jabber; /* # of jabber frames */
142 u64 rx_fcs_err; /* # of received frames with bad FCS */
143 u64 rx_len_err; /* # of received frames with length error */
144 u64 rx_symbol_err; /* symbol errors */
145 u64 rx_runt; /* # of short frames */
147 u64 rx_frames_64; /* # of Rx frames in a particular range */
148 u64 rx_frames_65_127;
149 u64 rx_frames_128_255;
150 u64 rx_frames_256_511;
151 u64 rx_frames_512_1023;
152 u64 rx_frames_1024_1518;
153 u64 rx_frames_1519_max;
155 u64 rx_pause; /* # of received pause frames */
156 u64 rx_ppp0; /* # of received PPP prio 0 frames */
157 u64 rx_ppp1; /* # of received PPP prio 1 frames */
158 u64 rx_ppp2; /* # of received PPP prio 2 frames */
159 u64 rx_ppp3; /* # of received PPP prio 3 frames */
160 u64 rx_ppp4; /* # of received PPP prio 4 frames */
161 u64 rx_ppp5; /* # of received PPP prio 5 frames */
162 u64 rx_ppp6; /* # of received PPP prio 6 frames */
163 u64 rx_ppp7; /* # of received PPP prio 7 frames */
165 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
166 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
167 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
168 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
169 u64 rx_trunc0; /* buffer-group 0 truncated packets */
170 u64 rx_trunc1; /* buffer-group 1 truncated packets */
171 u64 rx_trunc2; /* buffer-group 2 truncated packets */
172 u64 rx_trunc3; /* buffer-group 3 truncated packets */
175 struct lb_port_stats {
188 u64 frames_1024_1518;
203 struct tp_tcp_stats {
210 struct tp_err_stats {
215 u32 ofldChanDrops[4];
217 u32 ofldVlanDrops[4];
224 unsigned int ntxchan; /* # of Tx channels */
225 unsigned int tre; /* log2 of core clocks per TP tick */
226 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
229 uint32_t dack_re; /* DACK timer resolution */
230 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
232 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
233 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
235 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
236 * subset of the set of fields which may be present in the Compressed
237 * Filter Tuple portion of filters and TCP TCB connections. The
238 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
239 * Since a variable number of fields may or may not be present, their
240 * shifted field positions within the Compressed Filter Tuple may
241 * vary, or not even be present if the field isn't selected in
242 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
243 * places we store their offsets here, or a -1 if the field isn't
255 u8 sn[SERNUM_LEN + 1];
264 #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
265 #define CHELSIO_CHIP_FPGA 0x100
266 #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
267 #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
269 #define CHELSIO_T4 0x4
270 #define CHELSIO_T5 0x5
273 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
274 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
275 T4_FIRST_REV = T4_A1,
278 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
279 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
280 T5_FIRST_REV = T5_A0,
284 struct adapter_params {
286 struct vpd_params vpd;
287 struct pci_params pci;
289 unsigned int sf_size; /* serial flash size in bytes */
290 unsigned int sf_nsec; /* # of flash sectors */
291 unsigned int sf_fw_start; /* start of FW image in flash */
293 unsigned int fw_vers;
294 unsigned int tp_vers;
297 unsigned short mtus[NMTUS];
298 unsigned short a_wnd[NCCTRL_WIN];
299 unsigned short b_wnd[NCCTRL_WIN];
301 unsigned char nports; /* # of ethernet ports */
302 unsigned char portvec;
303 enum chip_type chip; /* chip code */
304 unsigned char offload;
306 unsigned char bypass;
308 unsigned int ofldq_wr_cred;
311 #include "t4fw_api.h"
313 #define FW_VERSION(chip) ( \
314 FW_HDR_FW_VER_MAJOR_GET(chip##FW_VERSION_MAJOR) | \
315 FW_HDR_FW_VER_MINOR_GET(chip##FW_VERSION_MINOR) | \
316 FW_HDR_FW_VER_MICRO_GET(chip##FW_VERSION_MICRO) | \
317 FW_HDR_FW_VER_BUILD_GET(chip##FW_VERSION_BUILD))
318 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
324 struct fw_hdr fw_hdr;
328 struct trace_params {
329 u32 data[TRACE_LEN / 4];
330 u32 mask[TRACE_LEN / 4];
331 unsigned short snap_len;
332 unsigned short min_len;
333 unsigned char skip_ofst;
334 unsigned char skip_len;
335 unsigned char invert;
340 unsigned short supported; /* link capabilities */
341 unsigned short advertising; /* advertised capabilities */
342 unsigned short requested_speed; /* speed user has requested */
343 unsigned short speed; /* actual link speed */
344 unsigned char requested_fc; /* flow control user has requested */
345 unsigned char fc; /* actual link flow control */
346 unsigned char autoneg; /* autonegotiating? */
347 unsigned char link_ok; /* link up? */
350 #define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
353 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
354 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
355 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
356 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
360 MAX_EGRQ = 128, /* max # of egress queues, including FLs */
361 MAX_INGQ = 64 /* max # of interrupt-capable ingress queues */
368 struct adapter *adapter;
370 s16 xact_addr_filt; /* index of exact MAC address filter */
371 u16 rss_size; /* size of VI's RSS table slice */
377 u8 lport; /* associated offload logical port */
378 u8 nqsets; /* # of qsets */
379 u8 first_qset; /* index of first qset */
381 struct link_config link_cfg;
388 enum { /* adapter flags */
389 FULL_INIT_DONE = (1 << 0),
390 USING_MSI = (1 << 1),
391 USING_MSIX = (1 << 2),
393 RSS_TNLALLLOOKUP = (1 << 5),
394 USING_SOFT_PARAMS = (1 << 6),
395 MASTER_PF = (1 << 7),
396 FW_OFLD_CONN = (1 << 9),
401 struct sge_fl { /* SGE free-buffer queue state */
402 unsigned int avail; /* # of available Rx buffers */
403 unsigned int pend_cred; /* new buffers since last FL DB ring */
404 unsigned int cidx; /* consumer index */
405 unsigned int pidx; /* producer index */
406 unsigned long alloc_failed; /* # of times buffer allocation failed */
407 unsigned long large_alloc_failed;
408 unsigned long starving;
410 unsigned int cntxt_id; /* SGE context id for the free list */
411 unsigned int size; /* capacity of free list */
412 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
413 __be64 *desc; /* address of HW Rx descriptor ring */
414 dma_addr_t addr; /* bus address of HW ring start */
417 /* A packet gather list */
419 struct page_frag frags[MAX_SKB_FRAGS];
420 void *va; /* virtual address of first byte */
421 unsigned int nfrags; /* # of fragments */
422 unsigned int tot_len; /* total length of fragments */
425 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
426 const struct pkt_gl *gl);
428 struct sge_rspq { /* state for an SGE response queue */
429 struct napi_struct napi;
430 const __be64 *cur_desc; /* current descriptor in queue */
431 unsigned int cidx; /* consumer index */
432 u8 gen; /* current generation bit */
433 u8 intr_params; /* interrupt holdoff parameters */
434 u8 next_intr_params; /* holdoff params for next interrupt */
435 u8 pktcnt_idx; /* interrupt packet threshold */
436 u8 uld; /* ULD handling this queue */
437 u8 idx; /* queue index within its group */
438 int offset; /* offset into current Rx buffer */
439 u16 cntxt_id; /* SGE context id for the response q */
440 u16 abs_id; /* absolute SGE id for the response q */
441 __be64 *desc; /* address of HW response ring */
442 dma_addr_t phys_addr; /* physical address of the ring */
443 unsigned int iqe_len; /* entry size */
444 unsigned int size; /* capacity of response queue */
445 struct adapter *adap;
446 struct net_device *netdev; /* associated net device */
447 rspq_handler_t handler;
450 struct sge_eth_stats { /* Ethernet queue statistics */
451 unsigned long pkts; /* # of ethernet packets */
452 unsigned long lro_pkts; /* # of LRO super packets */
453 unsigned long lro_merged; /* # of wire packets merged by LRO */
454 unsigned long rx_cso; /* # of Rx checksum offloads */
455 unsigned long vlan_ex; /* # of Rx VLAN extractions */
456 unsigned long rx_drops; /* # of packets dropped due to no mem */
459 struct sge_eth_rxq { /* SW Ethernet Rx queue */
460 struct sge_rspq rspq;
462 struct sge_eth_stats stats;
463 } ____cacheline_aligned_in_smp;
465 struct sge_ofld_stats { /* offload queue statistics */
466 unsigned long pkts; /* # of packets */
467 unsigned long imm; /* # of immediate-data packets */
468 unsigned long an; /* # of asynchronous notifications */
469 unsigned long nomem; /* # of responses deferred due to no mem */
472 struct sge_ofld_rxq { /* SW offload Rx queue */
473 struct sge_rspq rspq;
475 struct sge_ofld_stats stats;
476 } ____cacheline_aligned_in_smp;
485 unsigned int in_use; /* # of in-use Tx descriptors */
486 unsigned int size; /* # of descriptors */
487 unsigned int cidx; /* SW consumer index */
488 unsigned int pidx; /* producer index */
489 unsigned long stops; /* # of times q has been stopped */
490 unsigned long restarts; /* # of queue restarts */
491 unsigned int cntxt_id; /* SGE context id for the Tx q */
492 struct tx_desc *desc; /* address of HW Tx descriptor ring */
493 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
494 struct sge_qstat *stat; /* queue status entry */
495 dma_addr_t phys_addr; /* physical address of the ring */
498 unsigned short db_pidx;
502 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
504 struct netdev_queue *txq; /* associated netdev TX queue */
505 unsigned long tso; /* # of TSO requests */
506 unsigned long tx_cso; /* # of Tx checksum offloads */
507 unsigned long vlan_ins; /* # of Tx VLAN insertions */
508 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
509 } ____cacheline_aligned_in_smp;
511 struct sge_ofld_txq { /* state for an SGE offload Tx queue */
513 struct adapter *adap;
514 struct sk_buff_head sendq; /* list of backpressured packets */
515 struct tasklet_struct qresume_tsk; /* restarts the queue */
516 u8 full; /* the Tx ring is full */
517 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
518 } ____cacheline_aligned_in_smp;
520 struct sge_ctrl_txq { /* state for an SGE control Tx queue */
522 struct adapter *adap;
523 struct sk_buff_head sendq; /* list of backpressured packets */
524 struct tasklet_struct qresume_tsk; /* restarts the queue */
525 u8 full; /* the Tx ring is full */
526 } ____cacheline_aligned_in_smp;
529 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
530 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
531 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
533 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
534 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
535 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
536 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
538 struct sge_rspq intrq ____cacheline_aligned_in_smp;
539 spinlock_t intrq_lock;
541 u16 max_ethqsets; /* # of available Ethernet queue sets */
542 u16 ethqsets; /* # of active Ethernet queue sets */
543 u16 ethtxq_rover; /* Tx queue to clean up next */
544 u16 ofldqsets; /* # of active offload queue sets */
545 u16 rdmaqs; /* # of available RDMA Rx queues */
546 u16 ofld_rxq[MAX_OFLD_QSETS];
548 u16 timer_val[SGE_NTIMERS];
549 u8 counter_val[SGE_NCOUNTERS];
550 u32 fl_pg_order; /* large page allocation size */
551 u32 stat_len; /* length of status page at ring end */
552 u32 pktshift; /* padding between CPL & packet data */
553 u32 fl_align; /* response queue message alignment */
554 u32 fl_starve_thres; /* Free List starvation threshold */
555 unsigned int starve_thres;
557 unsigned int egr_start;
558 unsigned int ingr_start;
559 void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */
560 struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */
561 DECLARE_BITMAP(starving_fl, MAX_EGRQ);
562 DECLARE_BITMAP(txq_maperr, MAX_EGRQ);
563 struct timer_list rx_timer; /* refills starving FLs */
564 struct timer_list tx_timer; /* checks Tx queues */
567 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
568 #define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
569 #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
573 #ifdef CONFIG_PCI_IOV
575 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
576 * Configuration initialization for T5 only has SR-IOV functionality enabled
577 * on PF0-3 in order to simplify everything.
579 #define NUM_OF_PF_WITH_SRIOV 4
586 struct pci_dev *pdev;
587 struct device *pdev_dev;
595 struct adapter_params params;
596 struct cxgb4_virt_res vres;
603 char desc[IFNAMSIZ + 10];
604 } msix_info[MAX_INGQ + 1];
608 struct net_device *port[MAX_NPORTS];
609 u8 chan_map[NCHAN]; /* channel -> port map */
612 unsigned int l2t_start;
613 unsigned int l2t_end;
614 struct l2t_data *l2t;
615 void *uld_handle[CXGB4_ULD_MAX];
616 struct list_head list_node;
617 struct list_head rcu_node;
619 struct tid_info tids;
620 void **tid_release_head;
621 spinlock_t tid_release_lock;
622 struct work_struct tid_release_task;
623 struct work_struct db_full_task;
624 struct work_struct db_drop_task;
625 bool tid_release_task_busy;
627 struct dentry *debugfs_root;
629 spinlock_t stats_lock;
632 /* Defined bit width of user definable filter tuples
634 #define ETHTYPE_BITWIDTH 16
635 #define FRAG_BITWIDTH 1
636 #define MACIDX_BITWIDTH 9
637 #define FCOE_BITWIDTH 1
638 #define IPORT_BITWIDTH 3
639 #define MATCHTYPE_BITWIDTH 3
640 #define PROTO_BITWIDTH 8
641 #define TOS_BITWIDTH 8
642 #define PF_BITWIDTH 8
643 #define VF_BITWIDTH 8
644 #define IVLAN_BITWIDTH 16
645 #define OVLAN_BITWIDTH 16
647 /* Filter matching rules. These consist of a set of ingress packet field
648 * (value, mask) tuples. The associated ingress packet field matches the
649 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
650 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
651 * matches an ingress packet when all of the individual individual field
652 * matching rules are true.
654 * Partial field masks are always valid, however, while it may be easy to
655 * understand their meanings for some fields (e.g. IP address to match a
656 * subnet), for others making sensible partial masks is less intuitive (e.g.
657 * MPS match type) ...
659 * Most of the following data structures are modeled on T4 capabilities.
660 * Drivers for earlier chips use the subsets which make sense for those chips.
661 * We really need to come up with a hardware-independent mechanism to
662 * represent hardware filter capabilities ...
664 struct ch_filter_tuple {
665 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
666 * register selects which of these fields will participate in the
667 * filter match rules -- up to a maximum of 36 bits. Because
668 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
671 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
672 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
673 uint32_t ivlan_vld:1; /* inner VLAN valid */
674 uint32_t ovlan_vld:1; /* outer VLAN valid */
675 uint32_t pfvf_vld:1; /* PF/VF valid */
676 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
677 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
678 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
679 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
680 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
681 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
682 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
683 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
684 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
685 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
687 /* Uncompressed header matching field rules. These are always
688 * available for field rules.
690 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
691 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
692 uint16_t lport; /* local port */
693 uint16_t fport; /* foreign port */
696 /* A filter ioctl command.
698 struct ch_filter_specification {
699 /* Administrative fields for filter.
701 uint32_t hitcnts:1; /* count filter hits in TCB */
702 uint32_t prio:1; /* filter has priority over active/server */
704 /* Fundamental filter typing. This is the one element of filter
705 * matching that doesn't exist as a (value, mask) tuple.
707 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
709 /* Packet dispatch information. Ingress packets which match the
710 * filter rules will be dropped, passed to the host or switched back
711 * out as egress packets.
713 uint32_t action:2; /* drop, pass, switch */
715 uint32_t rpttid:1; /* report TID in RSS hash field */
717 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
718 uint32_t iq:10; /* ingress queue */
720 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
721 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
722 /* 1 => TCB contains IQ ID */
724 /* Switch proxy/rewrite fields. An ingress packet which matches a
725 * filter with "switch" set will be looped back out as an egress
726 * packet -- potentially with some Ethernet header rewriting.
728 uint32_t eport:2; /* egress port to switch packet out */
729 uint32_t newdmac:1; /* rewrite destination MAC address */
730 uint32_t newsmac:1; /* rewrite source MAC address */
731 uint32_t newvlan:2; /* rewrite VLAN Tag */
732 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
733 uint8_t smac[ETH_ALEN]; /* new source MAC address */
734 uint16_t vlan; /* VLAN Tag to insert */
736 /* Filter rule value/mask pairs.
738 struct ch_filter_tuple val;
739 struct ch_filter_tuple mask;
743 FILTER_PASS = 0, /* default */
749 VLAN_NOCHANGE = 0, /* default */
755 static inline int is_t5(enum chip_type chip)
757 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;
760 static inline int is_t4(enum chip_type chip)
762 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
765 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
767 return readl(adap->regs + reg_addr);
770 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
772 writel(val, adap->regs + reg_addr);
776 static inline u64 readq(const volatile void __iomem *addr)
778 return readl(addr) + ((u64)readl(addr + 4) << 32);
781 static inline void writeq(u64 val, volatile void __iomem *addr)
784 writel(val >> 32, addr + 4);
788 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
790 return readq(adap->regs + reg_addr);
793 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
795 writeq(val, adap->regs + reg_addr);
799 * netdev2pinfo - return the port_info structure associated with a net_device
802 * Return the struct port_info associated with a net_device
804 static inline struct port_info *netdev2pinfo(const struct net_device *dev)
806 return netdev_priv(dev);
810 * adap2pinfo - return the port_info of a port
812 * @idx: the port index
814 * Return the port_info structure for the port of the given index.
816 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
818 return netdev_priv(adap->port[idx]);
822 * netdev2adap - return the adapter structure associated with a net_device
825 * Return the struct adapter associated with a net_device
827 static inline struct adapter *netdev2adap(const struct net_device *dev)
829 return netdev2pinfo(dev)->adapter;
832 void t4_os_portmod_changed(const struct adapter *adap, int port_id);
833 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
835 void *t4_alloc_mem(size_t size);
837 void t4_free_sge_resources(struct adapter *adap);
838 irq_handler_t t4_intr_handler(struct adapter *adap);
839 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
840 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
841 const struct pkt_gl *gl);
842 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
843 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
844 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
845 struct net_device *dev, int intr_idx,
846 struct sge_fl *fl, rspq_handler_t hnd);
847 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
848 struct net_device *dev, struct netdev_queue *netdevq,
850 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
851 struct net_device *dev, unsigned int iqid,
852 unsigned int cmplqid);
853 int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
854 struct net_device *dev, unsigned int iqid);
855 irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
856 int t4_sge_init(struct adapter *adap);
857 void t4_sge_start(struct adapter *adap);
858 void t4_sge_stop(struct adapter *adap);
859 extern int dbfifo_int_thresh;
861 #define for_each_port(adapter, iter) \
862 for (iter = 0; iter < (adapter)->params.nports; ++iter)
864 static inline int is_bypass(struct adapter *adap)
866 return adap->params.bypass;
869 static inline int is_bypass_device(int device)
871 /* this should be set based upon device capabilities */
881 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
883 return adap->params.vpd.cclk / 1000;
886 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
889 return (us * adap->params.vpd.cclk) / 1000;
892 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
895 /* add Core Clock / 2 to round ticks to nearest uS */
896 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
897 adapter->params.vpd.cclk);
900 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
903 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
904 void *rpl, bool sleep_ok);
906 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
909 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
912 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
915 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
918 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
919 unsigned int data_reg, const u32 *vals,
920 unsigned int nregs, unsigned int start_idx);
921 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
922 unsigned int data_reg, u32 *vals, unsigned int nregs,
923 unsigned int start_idx);
927 void t4_intr_enable(struct adapter *adapter);
928 void t4_intr_disable(struct adapter *adapter);
929 int t4_slow_intr_handler(struct adapter *adapter);
931 int t4_wait_dev_ready(struct adapter *adap);
932 int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
933 struct link_config *lc);
934 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
935 int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
937 int t4_seeprom_wp(struct adapter *adapter, bool enable);
938 int get_vpd_params(struct adapter *adapter, struct vpd_params *p);
939 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
940 unsigned int t4_flash_cfg_addr(struct adapter *adapter);
941 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
942 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
943 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
944 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
945 const u8 *fw_data, unsigned int fw_size,
946 struct fw_hdr *card_fw, enum dev_state state, int *reset);
947 int t4_prep_adapter(struct adapter *adapter);
948 int t4_init_tp_params(struct adapter *adap);
949 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
950 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
951 void t4_fatal_err(struct adapter *adapter);
952 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
953 int start, int n, const u16 *rspq, unsigned int nrspq);
954 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
956 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
958 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
961 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
962 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
963 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
964 unsigned int mask, unsigned int val);
965 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
966 struct tp_tcp_stats *v6);
967 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
968 const unsigned short *alpha, const unsigned short *beta);
970 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
972 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
974 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
975 u64 mask0, u64 mask1, unsigned int crc, bool enable);
977 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
978 enum dev_master master, enum dev_state *state);
979 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
980 int t4_early_init(struct adapter *adap, unsigned int mbox);
981 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
982 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force);
983 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
984 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
985 const u8 *fw_data, unsigned int size, int force);
986 int t4_fw_config_file(struct adapter *adap, unsigned int mbox,
987 unsigned int mtype, unsigned int maddr,
988 u32 *finiver, u32 *finicsum, u32 *cfcsum);
989 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
990 unsigned int cache_line_size);
991 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
992 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
993 unsigned int vf, unsigned int nparams, const u32 *params,
995 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
996 unsigned int vf, unsigned int nparams, const u32 *params,
998 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
999 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1000 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1001 unsigned int vi, unsigned int cmask, unsigned int pmask,
1002 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1003 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1004 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1005 unsigned int *rss_size);
1006 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1007 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1009 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1010 unsigned int viid, bool free, unsigned int naddr,
1011 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1012 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1013 int idx, const u8 *addr, bool persist, bool add_smt);
1014 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1015 bool ucast, u64 vec, bool sleep_ok);
1016 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1017 bool rx_en, bool tx_en);
1018 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1019 unsigned int nblinks);
1020 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1021 unsigned int mmd, unsigned int reg, u16 *valp);
1022 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1023 unsigned int mmd, unsigned int reg, u16 val);
1024 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1025 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1026 unsigned int fl0id, unsigned int fl1id);
1027 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1028 unsigned int vf, unsigned int eqid);
1029 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1030 unsigned int vf, unsigned int eqid);
1031 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1032 unsigned int vf, unsigned int eqid);
1033 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
1034 void t4_db_full(struct adapter *adapter);
1035 void t4_db_dropped(struct adapter *adapter);
1036 int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len);
1037 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1039 #endif /* __CXGB4_H__ */