drivers/net/ethernet/chelsio/cxgb/sge.c

   1 /*****************************************************************************
   2  *                                                                           *
   3  * File: sge.c                                                               *
   4  * $Revision: 1.26 $                                                         *
   5  * $Date: 2005/06/21 18:29:48 $                                              *
   6  * Description:                                                              *
   7  *  DMA engine.                                                              *
   8  *  part of the Chelsio 10Gb Ethernet Driver.                                *
   9  *                                                                           *
  10  * This program is free software; you can redistribute it and/or modify      *
  11  * it under the terms of the GNU General Public License, version 2, as       *
  12  * published by the Free Software Foundation.                                *
  13  *                                                                           *
  14  * You should have received a copy of the GNU General Public License along   *
  15  * with this program; if not, see <http://www.gnu.org/licenses/>.            *
  16  *                                                                           *
  17  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
  18  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
  19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
  20  *                                                                           *
  21  * http://www.chelsio.com                                                    *
  22  *                                                                           *
  23  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
  24  * All rights reserved.                                                      *
  25  *                                                                           *
  26  * Maintainers: maintainers@chelsio.com                                      *
  27  *                                                                           *
  28  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
  29  *          Tina Yang               <tainay@chelsio.com>                     *
  30  *          Felix Marti             <felix@chelsio.com>                      *
  31  *          Scott Bardone           <sbardone@chelsio.com>                   *
  32  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
  33  *          Frank DiMambro          <frank@chelsio.com>                      *
  34  *                                                                           *
  35  * History:                                                                  *
  36  *                                                                           *
  37  ****************************************************************************/
  38
  39 #include "common.h"
  40
  41 #include <linux/types.h>
  42 #include <linux/errno.h>
  43 #include <linux/pci.h>
  44 #include <linux/ktime.h>
  45 #include <linux/netdevice.h>
  46 #include <linux/etherdevice.h>
  47 #include <linux/if_vlan.h>
  48 #include <linux/skbuff.h>
  49 #include <linux/init.h>
  50 #include <linux/mm.h>
  51 #include <linux/tcp.h>
  52 #include <linux/ip.h>
  53 #include <linux/in.h>
  54 #include <linux/if_arp.h>
  55 #include <linux/slab.h>
  56 #include <linux/prefetch.h>
  57
  58 #include "cpl5_cmd.h"
  59 #include "sge.h"
  60 #include "regs.h"
  61 #include "espi.h"
  62
  63 /* This belongs in if_ether.h */
  64 #define ETH_P_CPL5 0xf
  65
  66 #define SGE_CMDQ_N              2
  67 #define SGE_FREELQ_N            2
  68 #define SGE_CMDQ0_E_N           1024
  69 #define SGE_CMDQ1_E_N           128
  70 #define SGE_FREEL_SIZE          4096
  71 #define SGE_JUMBO_FREEL_SIZE    512
  72 #define SGE_FREEL_REFILL_THRESH 16
  73 #define SGE_RESPQ_E_N           1024
  74 #define SGE_INTRTIMER_NRES      1000
  75 #define SGE_RX_SM_BUF_SIZE      1536
  76 #define SGE_TX_DESC_MAX_PLEN    16384
  77
  78 #define SGE_RESPQ_REPLENISH_THRES (SGE_RESPQ_E_N / 4)
  79
  80 /*
  81  * Period of the TX buffer reclaim timer.  This timer does not need to run
  82  * frequently as TX buffers are usually reclaimed by new TX packets.
  83  */
  84 #define TX_RECLAIM_PERIOD (HZ / 4)
  85
  86 #define M_CMD_LEN       0x7fffffff
  87 #define V_CMD_LEN(v)    (v)
  88 #define G_CMD_LEN(v)    ((v) & M_CMD_LEN)
  89 #define V_CMD_GEN1(v)   ((v) << 31)
  90 #define V_CMD_GEN2(v)   (v)
  91 #define F_CMD_DATAVALID (1 << 1)
  92 #define F_CMD_SOP       (1 << 2)
  93 #define V_CMD_EOP(v)    ((v) << 3)
  94
  95 /*
  96  * Command queue, receive buffer list, and response queue descriptors.
  97  */
  98 #if defined(__BIG_ENDIAN_BITFIELD)
  99 struct cmdQ_e {
 100         u32 addr_lo;
 101         u32 len_gen;
 102         u32 flags;
 103         u32 addr_hi;
 104 };
 105
 106 struct freelQ_e {
 107         u32 addr_lo;
 108         u32 len_gen;
 109         u32 gen2;
 110         u32 addr_hi;
 111 };
 112
 113 struct respQ_e {
 114         u32 Qsleeping           : 4;
 115         u32 Cmdq1CreditReturn   : 5;
 116         u32 Cmdq1DmaComplete    : 5;
 117         u32 Cmdq0CreditReturn   : 5;
 118         u32 Cmdq0DmaComplete    : 5;
 119         u32 FreelistQid         : 2;
 120         u32 CreditValid         : 1;
 121         u32 DataValid           : 1;
 122         u32 Offload             : 1;
 123         u32 Eop                 : 1;
 124         u32 Sop                 : 1;
 125         u32 GenerationBit       : 1;
 126         u32 BufferLength;
 127 };
 128 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 129 struct cmdQ_e {
 130         u32 len_gen;
 131         u32 addr_lo;
 132         u32 addr_hi;
 133         u32 flags;
 134 };
 135
 136 struct freelQ_e {
 137         u32 len_gen;
 138         u32 addr_lo;
 139         u32 addr_hi;
 140         u32 gen2;
 141 };
 142
 143 struct respQ_e {
 144         u32 BufferLength;
 145         u32 GenerationBit       : 1;
 146         u32 Sop                 : 1;
 147         u32 Eop                 : 1;
 148         u32 Offload             : 1;
 149         u32 DataValid           : 1;
 150         u32 CreditValid         : 1;
 151         u32 FreelistQid         : 2;
 152         u32 Cmdq0DmaComplete    : 5;
 153         u32 Cmdq0CreditReturn   : 5;
 154         u32 Cmdq1DmaComplete    : 5;
 155         u32 Cmdq1CreditReturn   : 5;
 156         u32 Qsleeping           : 4;
 157 } ;
 158 #endif
 159
 160 /*
 161  * SW Context Command and Freelist Queue Descriptors
 162  */
 163 struct cmdQ_ce {
 164         struct sk_buff *skb;
 165         DEFINE_DMA_UNMAP_ADDR(dma_addr);
 166         DEFINE_DMA_UNMAP_LEN(dma_len);
 167 };
 168
 169 struct freelQ_ce {
 170         struct sk_buff *skb;
 171         DEFINE_DMA_UNMAP_ADDR(dma_addr);
 172         DEFINE_DMA_UNMAP_LEN(dma_len);
 173 };
 174
 175 /*
 176  * SW command, freelist and response rings
 177  */
 178 struct cmdQ {
 179         unsigned long   status;         /* HW DMA fetch status */
 180         unsigned int    in_use;         /* # of in-use command descriptors */
 181         unsigned int    size;           /* # of descriptors */
 182         unsigned int    processed;      /* total # of descs HW has processed */
 183         unsigned int    cleaned;        /* total # of descs SW has reclaimed */
 184         unsigned int    stop_thres;     /* SW TX queue suspend threshold */
 185         u16             pidx;           /* producer index (SW) */
 186         u16             cidx;           /* consumer index (HW) */
 187         u8              genbit;         /* current generation (=valid) bit */
 188         u8              sop;            /* is next entry start of packet? */
 189         struct cmdQ_e  *entries;        /* HW command descriptor Q */
 190         struct cmdQ_ce *centries;       /* SW command context descriptor Q */
 191         dma_addr_t      dma_addr;       /* DMA addr HW command descriptor Q */
 192         spinlock_t      lock;           /* Lock to protect cmdQ enqueuing */
 193 };
 194
 195 struct freelQ {
 196         unsigned int    credits;        /* # of available RX buffers */
 197         unsigned int    size;           /* free list capacity */
 198         u16             pidx;           /* producer index (SW) */
 199         u16             cidx;           /* consumer index (HW) */
 200         u16             rx_buffer_size; /* Buffer size on this free list */
 201         u16             dma_offset;     /* DMA offset to align IP headers */
 202         u16             recycleq_idx;   /* skb recycle q to use */
 203         u8              genbit;         /* current generation (=valid) bit */
 204         struct freelQ_e *entries;       /* HW freelist descriptor Q */
 205         struct freelQ_ce *centries;     /* SW freelist context descriptor Q */
 206         dma_addr_t      dma_addr;       /* DMA addr HW freelist descriptor Q */
 207 };
 208
 209 struct respQ {
 210         unsigned int    credits;        /* credits to be returned to SGE */
 211         unsigned int    size;           /* # of response Q descriptors */
 212         u16             cidx;           /* consumer index (SW) */
 213         u8              genbit;         /* current generation(=valid) bit */
 214         struct respQ_e *entries;        /* HW response descriptor Q */
 215         dma_addr_t      dma_addr;       /* DMA addr HW response descriptor Q */
 216 };
 217
 218 /* Bit flags for cmdQ.status */
 219 enum {
 220         CMDQ_STAT_RUNNING = 1,          /* fetch engine is running */
 221         CMDQ_STAT_LAST_PKT_DB = 2       /* last packet rung the doorbell */
 222 };
 223
 224 /* T204 TX SW scheduler */
 225
 226 /* Per T204 TX port */
 227 struct sched_port {
 228         unsigned int    avail;          /* available bits - quota */
 229         unsigned int    drain_bits_per_1024ns; /* drain rate */
 230         unsigned int    speed;          /* drain rate, mbps */
 231         unsigned int    mtu;            /* mtu size */
 232         struct sk_buff_head skbq;       /* pending skbs */
 233 };
 234
 235 /* Per T204 device */
 236 struct sched {
 237         ktime_t         last_updated;   /* last time quotas were computed */
 238         unsigned int    max_avail;      /* max bits to be sent to any port */
 239         unsigned int    port;           /* port index (round robin ports) */
 240         unsigned int    num;            /* num skbs in per port queues */
 241         struct sched_port p[MAX_NPORTS];
 242         struct tasklet_struct sched_tsk;/* tasklet used to run scheduler */
 243 };
 244 static void restart_sched(unsigned long);
 245
 246
 247 /*
 248  * Main SGE data structure
 249  *
 250  * Interrupts are handled by a single CPU and it is likely that on a MP system
 251  * the application is migrated to another CPU. In that scenario, we try to
 252  * separate the RX(in irq context) and TX state in order to decrease memory
 253  * contention.
 254  */
 255 struct sge {
 256         struct adapter *adapter;        /* adapter backpointer */
 257         struct net_device *netdev;      /* netdevice backpointer */
 258         struct freelQ   freelQ[SGE_FREELQ_N]; /* buffer free lists */
 259         struct respQ    respQ;          /* response Q */
 260         unsigned long   stopped_tx_queues; /* bitmap of suspended Tx queues */
 261         unsigned int    rx_pkt_pad;     /* RX padding for L2 packets */
 262         unsigned int    jumbo_fl;       /* jumbo freelist Q index */
 263         unsigned int    intrtimer_nres; /* no-resource interrupt timer */
 264         unsigned int    fixed_intrtimer;/* non-adaptive interrupt timer */
 265         struct timer_list tx_reclaim_timer; /* reclaims TX buffers */
 266         struct timer_list espibug_timer;
 267         unsigned long   espibug_timeout;
 268         struct sk_buff  *espibug_skb[MAX_NPORTS];
 269         u32             sge_control;    /* shadow value of sge control reg */
 270         struct sge_intr_counts stats;
 271         struct sge_port_stats __percpu *port_stats[MAX_NPORTS];
 272         struct sched    *tx_sched;
 273         struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp;
 274 };
 275
 276 static const u8 ch_mac_addr[ETH_ALEN] = {
 277         0x0, 0x7, 0x43, 0x0, 0x0, 0x0
 278 };
 279
 280 /*
 281  * stop tasklet and free all pending skb's
 282  */
 283 static void tx_sched_stop(struct sge *sge)
 284 {
 285         struct sched *s = sge->tx_sched;
 286         int i;
 287
 288         tasklet_kill(&s->sched_tsk);
 289
 290         for (i = 0; i < MAX_NPORTS; i++)
 291                 __skb_queue_purge(&s->p[s->port].skbq);
 292 }
 293
 294 /*
 295  * t1_sched_update_parms() is called when the MTU or link speed changes. It
 296  * re-computes scheduler parameters to scope with the change.
 297  */
 298 unsigned int t1_sched_update_parms(struct sge *sge, unsigned int port,
 299                                    unsigned int mtu, unsigned int speed)
 300 {
 301         struct sched *s = sge->tx_sched;
 302         struct sched_port *p = &s->p[port];
 303         unsigned int max_avail_segs;
 304
 305         pr_debug("t1_sched_update_params mtu=%d speed=%d\n", mtu, speed);
 306         if (speed)
 307                 p->speed = speed;
 308         if (mtu)
 309                 p->mtu = mtu;
 310
 311         if (speed || mtu) {
 312                 unsigned long long drain = 1024ULL * p->speed * (p->mtu - 40);
 313                 do_div(drain, (p->mtu + 50) * 1000);
 314                 p->drain_bits_per_1024ns = (unsigned int) drain;
 315
 316                 if (p->speed < 1000)
 317                         p->drain_bits_per_1024ns =
 318                                 90 * p->drain_bits_per_1024ns / 100;
 319         }
 320
 321         if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) {
 322                 p->drain_bits_per_1024ns -= 16;
 323                 s->max_avail = max(4096U, p->mtu + 16 + 14 + 4);
 324                 max_avail_segs = max(1U, 4096 / (p->mtu - 40));
 325         } else {
 326                 s->max_avail = 16384;
 327                 max_avail_segs = max(1U, 9000 / (p->mtu - 40));
 328         }
 329
 330         pr_debug("t1_sched_update_parms: mtu %u speed %u max_avail %u "
 331                  "max_avail_segs %u drain_bits_per_1024ns %u\n", p->mtu,
 332                  p->speed, s->max_avail, max_avail_segs,
 333                  p->drain_bits_per_1024ns);
 334
 335         return max_avail_segs * (p->mtu - 40);
 336 }
 337
 338 #if 0
 339
 340 /*
 341  * t1_sched_max_avail_bytes() tells the scheduler the maximum amount of
 342  * data that can be pushed per port.
 343  */
 344 void t1_sched_set_max_avail_bytes(struct sge *sge, unsigned int val)
 345 {
 346         struct sched *s = sge->tx_sched;
 347         unsigned int i;
 348
 349         s->max_avail = val;
 350         for (i = 0; i < MAX_NPORTS; i++)
 351                 t1_sched_update_parms(sge, i, 0, 0);
 352 }
 353
 354 /*
 355  * t1_sched_set_drain_bits_per_us() tells the scheduler at which rate a port
 356  * is draining.
 357  */
 358 void t1_sched_set_drain_bits_per_us(struct sge *sge, unsigned int port,
 359                                          unsigned int val)
 360 {
 361         struct sched *s = sge->tx_sched;
 362         struct sched_port *p = &s->p[port];
 363         p->drain_bits_per_1024ns = val * 1024 / 1000;
 364         t1_sched_update_parms(sge, port, 0, 0);
 365 }
 366
 367 #endif  /*  0  */
 368
 369 /*
 370  * tx_sched_init() allocates resources and does basic initialization.
 371  */
 372 static int tx_sched_init(struct sge *sge)
 373 {
 374         struct sched *s;
 375         int i;
 376
 377         s = kzalloc(sizeof (struct sched), GFP_KERNEL);
 378         if (!s)
 379                 return -ENOMEM;
 380
 381         pr_debug("tx_sched_init\n");
 382         tasklet_init(&s->sched_tsk, restart_sched, (unsigned long) sge);
 383         sge->tx_sched = s;
 384
 385         for (i = 0; i < MAX_NPORTS; i++) {
 386                 skb_queue_head_init(&s->p[i].skbq);
 387                 t1_sched_update_parms(sge, i, 1500, 1000);
 388         }
 389
 390         return 0;
 391 }
 392
 393 /*
 394  * sched_update_avail() computes the delta since the last time it was called
 395  * and updates the per port quota (number of bits that can be sent to the any
 396  * port).
 397  */
 398 static inline int sched_update_avail(struct sge *sge)
 399 {
 400         struct sched *s = sge->tx_sched;
 401         ktime_t now = ktime_get();
 402         unsigned int i;
 403         long long delta_time_ns;
 404
 405         delta_time_ns = ktime_to_ns(ktime_sub(now, s->last_updated));
 406
 407         pr_debug("sched_update_avail delta=%lld\n", delta_time_ns);
 408         if (delta_time_ns < 15000)
 409                 return 0;
 410
 411         for (i = 0; i < MAX_NPORTS; i++) {
 412                 struct sched_port *p = &s->p[i];
 413                 unsigned int delta_avail;
 414
 415                 delta_avail = (p->drain_bits_per_1024ns * delta_time_ns) >> 13;
 416                 p->avail = min(p->avail + delta_avail, s->max_avail);
 417         }
 418
 419         s->last_updated = now;
 420
 421         return 1;
 422 }
 423
 424 /*
 425  * sched_skb() is called from two different places. In the tx path, any
 426  * packet generating load on an output port will call sched_skb()
 427  * (skb != NULL). In addition, sched_skb() is called from the irq/soft irq
 428  * context (skb == NULL).
 429  * The scheduler only returns a skb (which will then be sent) if the
 430  * length of the skb is <= the current quota of the output port.
 431  */
 432 static struct sk_buff *sched_skb(struct sge *sge, struct sk_buff *skb,
 433                                 unsigned int credits)
 434 {
 435         struct sched *s = sge->tx_sched;
 436         struct sk_buff_head *skbq;
 437         unsigned int i, len, update = 1;
 438
 439         pr_debug("sched_skb %p\n", skb);
 440         if (!skb) {
 441                 if (!s->num)
 442                         return NULL;
 443         } else {
 444                 skbq = &s->p[skb->dev->if_port].skbq;
 445                 __skb_queue_tail(skbq, skb);
 446                 s->num++;
 447                 skb = NULL;
 448         }
 449
 450         if (credits < MAX_SKB_FRAGS + 1)
 451                 goto out;
 452
 453 again:
 454         for (i = 0; i < MAX_NPORTS; i++) {
 455                 s->port = (s->port + 1) & (MAX_NPORTS - 1);
 456                 skbq = &s->p[s->port].skbq;
 457
 458                 skb = skb_peek(skbq);
 459
 460                 if (!skb)
 461                         continue;
 462
 463                 len = skb->len;
 464                 if (len <= s->p[s->port].avail) {
 465                         s->p[s->port].avail -= len;
 466                         s->num--;
 467                         __skb_unlink(skb, skbq);
 468                         goto out;
 469                 }
 470                 skb = NULL;
 471         }
 472
 473         if (update-- && sched_update_avail(sge))
 474                 goto again;
 475
 476 out:
 477         /* If there are more pending skbs, we use the hardware to schedule us
 478          * again.
 479          */
 480         if (s->num && !skb) {
 481                 struct cmdQ *q = &sge->cmdQ[0];
 482                 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
 483                 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
 484                         set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
 485                         writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
 486                 }
 487         }
 488         pr_debug("sched_skb ret %p\n", skb);
 489
 490         return skb;
 491 }
 492
 493 /*
 494  * PIO to indicate that memory mapped Q contains valid descriptor(s).
 495  */
 496 static inline void doorbell_pio(struct adapter *adapter, u32 val)
 497 {
 498         wmb();
 499         writel(val, adapter->regs + A_SG_DOORBELL);
 500 }
 501
 502 /*
 503  * Frees all RX buffers on the freelist Q. The caller must make sure that
 504  * the SGE is turned off before calling this function.
 505  */
 506 static void free_freelQ_buffers(struct pci_dev *pdev, struct freelQ *q)
 507 {
 508         unsigned int cidx = q->cidx;
 509
 510         while (q->credits--) {
 511                 struct freelQ_ce *ce = &q->centries[cidx];
 512
 513                 pci_unmap_single(pdev, dma_unmap_addr(ce, dma_addr),
 514                                  dma_unmap_len(ce, dma_len),
 515                                  PCI_DMA_FROMDEVICE);
 516                 dev_kfree_skb(ce->skb);
 517                 ce->skb = NULL;
 518                 if (++cidx == q->size)
 519                         cidx = 0;
 520         }
 521 }
 522
 523 /*
 524  * Free RX free list and response queue resources.
 525  */
 526 static void free_rx_resources(struct sge *sge)
 527 {
 528         struct pci_dev *pdev = sge->adapter->pdev;
 529         unsigned int size, i;
 530
 531         if (sge->respQ.entries) {
 532                 size = sizeof(struct respQ_e) * sge->respQ.size;
 533                 pci_free_consistent(pdev, size, sge->respQ.entries,
 534                                     sge->respQ.dma_addr);
 535         }
 536
 537         for (i = 0; i < SGE_FREELQ_N; i++) {
 538                 struct freelQ *q = &sge->freelQ[i];
 539
 540                 if (q->centries) {
 541                         free_freelQ_buffers(pdev, q);
 542                         kfree(q->centries);
 543                 }
 544                 if (q->entries) {
 545                         size = sizeof(struct freelQ_e) * q->size;
 546                         pci_free_consistent(pdev, size, q->entries,
 547                                             q->dma_addr);
 548                 }
 549         }
 550 }
 551
 552 /*
 553  * Allocates basic RX resources, consisting of memory mapped freelist Qs and a
 554  * response queue.
 555  */
 556 static int alloc_rx_resources(struct sge *sge, struct sge_params *p)
 557 {
 558         struct pci_dev *pdev = sge->adapter->pdev;
 559         unsigned int size, i;
 560
 561         for (i = 0; i < SGE_FREELQ_N; i++) {
 562                 struct freelQ *q = &sge->freelQ[i];
 563
 564                 q->genbit = 1;
 565                 q->size = p->freelQ_size[i];
 566                 q->dma_offset = sge->rx_pkt_pad ? 0 : NET_IP_ALIGN;
 567                 size = sizeof(struct freelQ_e) * q->size;
 568                 q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr);
 569                 if (!q->entries)
 570                         goto err_no_mem;
 571
 572                 size = sizeof(struct freelQ_ce) * q->size;
 573                 q->centries = kzalloc(size, GFP_KERNEL);
 574                 if (!q->centries)
 575                         goto err_no_mem;
 576         }
 577
 578         /*
 579          * Calculate the buffer sizes for the two free lists.  FL0 accommodates
 580          * regular sized Ethernet frames, FL1 is sized not to exceed 16K,
 581          * including all the sk_buff overhead.
 582          *
 583          * Note: For T2 FL0 and FL1 are reversed.
 584          */
 585         sge->freelQ[!sge->jumbo_fl].rx_buffer_size = SGE_RX_SM_BUF_SIZE +
 586                 sizeof(struct cpl_rx_data) +
 587                 sge->freelQ[!sge->jumbo_fl].dma_offset;
 588
 589                 size = (16 * 1024) -
 590                     SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 591
 592         sge->freelQ[sge->jumbo_fl].rx_buffer_size = size;
 593
 594         /*
 595          * Setup which skb recycle Q should be used when recycling buffers from
 596          * each free list.
 597          */
 598         sge->freelQ[!sge->jumbo_fl].recycleq_idx = 0;
 599         sge->freelQ[sge->jumbo_fl].recycleq_idx = 1;
 600
 601         sge->respQ.genbit = 1;
 602         sge->respQ.size = SGE_RESPQ_E_N;
 603         sge->respQ.credits = 0;
 604         size = sizeof(struct respQ_e) * sge->respQ.size;
 605         sge->respQ.entries =
 606                 pci_alloc_consistent(pdev, size, &sge->respQ.dma_addr);
 607         if (!sge->respQ.entries)
 608                 goto err_no_mem;
 609         return 0;
 610
 611 err_no_mem:
 612         free_rx_resources(sge);
 613         return -ENOMEM;
 614 }
 615
 616 /*
 617  * Reclaims n TX descriptors and frees the buffers associated with them.
 618  */
 619 static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *q, unsigned int n)
 620 {
 621         struct cmdQ_ce *ce;
 622         struct pci_dev *pdev = sge->adapter->pdev;
 623         unsigned int cidx = q->cidx;
 624
 625         q->in_use -= n;
 626         ce = &q->centries[cidx];
 627         while (n--) {
 628                 if (likely(dma_unmap_len(ce, dma_len))) {
 629                         pci_unmap_single(pdev, dma_unmap_addr(ce, dma_addr),
 630                                          dma_unmap_len(ce, dma_len),
 631                                          PCI_DMA_TODEVICE);
 632                         if (q->sop)
 633                                 q->sop = 0;
 634                 }
 635                 if (ce->skb) {
 636                         dev_kfree_skb_any(ce->skb);
 637                         q->sop = 1;
 638                 }
 639                 ce++;
 640                 if (++cidx == q->size) {
 641                         cidx = 0;
 642                         ce = q->centries;
 643                 }
 644         }
 645         q->cidx = cidx;
 646 }
 647
 648 /*
 649  * Free TX resources.
 650  *
 651  * Assumes that SGE is stopped and all interrupts are disabled.
 652  */
 653 static void free_tx_resources(struct sge *sge)
 654 {
 655         struct pci_dev *pdev = sge->adapter->pdev;
 656         unsigned int size, i;
 657
 658         for (i = 0; i < SGE_CMDQ_N; i++) {
 659                 struct cmdQ *q = &sge->cmdQ[i];
 660
 661                 if (q->centries) {
 662                         if (q->in_use)
 663                                 free_cmdQ_buffers(sge, q, q->in_use);
 664                         kfree(q->centries);
 665                 }
 666                 if (q->entries) {
 667                         size = sizeof(struct cmdQ_e) * q->size;
 668                         pci_free_consistent(pdev, size, q->entries,
 669                                             q->dma_addr);
 670                 }
 671         }
 672 }
 673
 674 /*
 675  * Allocates basic TX resources, consisting of memory mapped command Qs.
 676  */
 677 static int alloc_tx_resources(struct sge *sge, struct sge_params *p)
 678 {
 679         struct pci_dev *pdev = sge->adapter->pdev;
 680         unsigned int size, i;
 681
 682         for (i = 0; i < SGE_CMDQ_N; i++) {
 683                 struct cmdQ *q = &sge->cmdQ[i];
 684
 685                 q->genbit = 1;
 686                 q->sop = 1;
 687                 q->size = p->cmdQ_size[i];
 688                 q->in_use = 0;
 689                 q->status = 0;
 690                 q->processed = q->cleaned = 0;
 691                 q->stop_thres = 0;
 692                 spin_lock_init(&q->lock);
 693                 size = sizeof(struct cmdQ_e) * q->size;
 694                 q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr);
 695                 if (!q->entries)
 696                         goto err_no_mem;
 697
 698                 size = sizeof(struct cmdQ_ce) * q->size;
 699                 q->centries = kzalloc(size, GFP_KERNEL);
 700                 if (!q->centries)
 701                         goto err_no_mem;
 702         }
 703
 704         /*
 705          * CommandQ 0 handles Ethernet and TOE packets, while queue 1 is TOE
 706          * only.  For queue 0 set the stop threshold so we can handle one more
 707          * packet from each port, plus reserve an additional 24 entries for
 708          * Ethernet packets only.  Queue 1 never suspends nor do we reserve
 709          * space for Ethernet packets.
 710          */
 711         sge->cmdQ[0].stop_thres = sge->adapter->params.nports *
 712                 (MAX_SKB_FRAGS + 1);
 713         return 0;
 714
 715 err_no_mem:
 716         free_tx_resources(sge);
 717         return -ENOMEM;
 718 }
 719
 720 static inline void setup_ring_params(struct adapter *adapter, u64 addr,
 721                                      u32 size, int base_reg_lo,
 722                                      int base_reg_hi, int size_reg)
 723 {
 724         writel((u32)addr, adapter->regs + base_reg_lo);
 725         writel(addr >> 32, adapter->regs + base_reg_hi);
 726         writel(size, adapter->regs + size_reg);
 727 }
 728
 729 /*
 730  * Enable/disable VLAN acceleration.
 731  */
 732 void t1_vlan_mode(struct adapter *adapter, netdev_features_t features)
 733 {
 734         struct sge *sge = adapter->sge;
 735
 736         if (features & NETIF_F_HW_VLAN_CTAG_RX)
 737                 sge->sge_control |= F_VLAN_XTRACT;
 738         else
 739                 sge->sge_control &= ~F_VLAN_XTRACT;
 740         if (adapter->open_device_map) {
 741                 writel(sge->sge_control, adapter->regs + A_SG_CONTROL);
 742                 readl(adapter->regs + A_SG_CONTROL);   /* flush */
 743         }
 744 }
 745
 746 /*
 747  * Programs the various SGE registers. However, the engine is not yet enabled,
 748  * but sge->sge_control is setup and ready to go.
 749  */
 750 static void configure_sge(struct sge *sge, struct sge_params *p)
 751 {
 752         struct adapter *ap = sge->adapter;
 753
 754         writel(0, ap->regs + A_SG_CONTROL);
 755         setup_ring_params(ap, sge->cmdQ[0].dma_addr, sge->cmdQ[0].size,
 756                           A_SG_CMD0BASELWR, A_SG_CMD0BASEUPR, A_SG_CMD0SIZE);
 757         setup_ring_params(ap, sge->cmdQ[1].dma_addr, sge->cmdQ[1].size,
 758                           A_SG_CMD1BASELWR, A_SG_CMD1BASEUPR, A_SG_CMD1SIZE);
 759         setup_ring_params(ap, sge->freelQ[0].dma_addr,
 760                           sge->freelQ[0].size, A_SG_FL0BASELWR,
 761                           A_SG_FL0BASEUPR, A_SG_FL0SIZE);
 762         setup_ring_params(ap, sge->freelQ[1].dma_addr,
 763                           sge->freelQ[1].size, A_SG_FL1BASELWR,
 764                           A_SG_FL1BASEUPR, A_SG_FL1SIZE);
 765
 766         /* The threshold comparison uses <. */
 767         writel(SGE_RX_SM_BUF_SIZE + 1, ap->regs + A_SG_FLTHRESHOLD);
 768
 769         setup_ring_params(ap, sge->respQ.dma_addr, sge->respQ.size,
 770                           A_SG_RSPBASELWR, A_SG_RSPBASEUPR, A_SG_RSPSIZE);
 771         writel((u32)sge->respQ.size - 1, ap->regs + A_SG_RSPQUEUECREDIT);
 772
 773         sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE |
 774                 F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE |
 775                 V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE |
 776                 V_RX_PKT_OFFSET(sge->rx_pkt_pad);
 777
 778 #if defined(__BIG_ENDIAN_BITFIELD)
 779         sge->sge_control |= F_ENABLE_BIG_ENDIAN;
 780 #endif
 781
 782         /* Initialize no-resource timer */
 783         sge->intrtimer_nres = SGE_INTRTIMER_NRES * core_ticks_per_usec(ap);
 784
 785         t1_sge_set_coalesce_params(sge, p);
 786 }
 787
 788 /*
 789  * Return the payload capacity of the jumbo free-list buffers.
 790  */
 791 static inline unsigned int jumbo_payload_capacity(const struct sge *sge)
 792 {
 793         return sge->freelQ[sge->jumbo_fl].rx_buffer_size -
 794                 sge->freelQ[sge->jumbo_fl].dma_offset -
 795                 sizeof(struct cpl_rx_data);
 796 }
 797
 798 /*
 799  * Frees all SGE related resources and the sge structure itself
 800  */
 801 void t1_sge_destroy(struct sge *sge)
 802 {
 803         int i;
 804
 805         for_each_port(sge->adapter, i)
 806                 free_percpu(sge->port_stats[i]);
 807
 808         kfree(sge->tx_sched);
 809         free_tx_resources(sge);
 810         free_rx_resources(sge);
 811         kfree(sge);
 812 }
 813
 814 /*
 815  * Allocates new RX buffers on the freelist Q (and tracks them on the freelist
 816  * context Q) until the Q is full or alloc_skb fails.
 817  *
 818  * It is possible that the generation bits already match, indicating that the
 819  * buffer is already valid and nothing needs to be done. This happens when we
 820  * copied a received buffer into a new sk_buff during the interrupt processing.
 821  *
 822  * If the SGE doesn't automatically align packets properly (!sge->rx_pkt_pad),
 823  * we specify a RX_OFFSET in order to make sure that the IP header is 4B
 824  * aligned.
 825  */
 826 static void refill_free_list(struct sge *sge, struct freelQ *q)
 827 {
 828         struct pci_dev *pdev = sge->adapter->pdev;
 829         struct freelQ_ce *ce = &q->centries[q->pidx];
 830         struct freelQ_e *e = &q->entries[q->pidx];
 831         unsigned int dma_len = q->rx_buffer_size - q->dma_offset;
 832
 833         while (q->credits < q->size) {
 834                 struct sk_buff *skb;
 835                 dma_addr_t mapping;
 836
 837                 skb = dev_alloc_skb(q->rx_buffer_size);
 838                 if (!skb)
 839                         break;
 840
 841                 skb_reserve(skb, q->dma_offset);
 842                 mapping = pci_map_single(pdev, skb->data, dma_len,
 843                                          PCI_DMA_FROMDEVICE);
 844                 skb_reserve(skb, sge->rx_pkt_pad);
 845
 846                 ce->skb = skb;
 847                 dma_unmap_addr_set(ce, dma_addr, mapping);
 848                 dma_unmap_len_set(ce, dma_len, dma_len);
 849                 e->addr_lo = (u32)mapping;
 850                 e->addr_hi = (u64)mapping >> 32;
 851                 e->len_gen = V_CMD_LEN(dma_len) | V_CMD_GEN1(q->genbit);
 852                 wmb();
 853                 e->gen2 = V_CMD_GEN2(q->genbit);
 854
 855                 e++;
 856                 ce++;
 857                 if (++q->pidx == q->size) {
 858                         q->pidx = 0;
 859                         q->genbit ^= 1;
 860                         ce = q->centries;
 861                         e = q->entries;
 862                 }
 863                 q->credits++;
 864         }
 865 }
 866
 867 /*
 868  * Calls refill_free_list for both free lists. If we cannot fill at least 1/4
 869  * of both rings, we go into 'few interrupt mode' in order to give the system
 870  * time to free up resources.
 871  */
 872 static void freelQs_empty(struct sge *sge)
 873 {
 874         struct adapter *adapter = sge->adapter;
 875         u32 irq_reg = readl(adapter->regs + A_SG_INT_ENABLE);
 876         u32 irqholdoff_reg;
 877
 878         refill_free_list(sge, &sge->freelQ[0]);
 879         refill_free_list(sge, &sge->freelQ[1]);
 880
 881         if (sge->freelQ[0].credits > (sge->freelQ[0].size >> 2) &&
 882             sge->freelQ[1].credits > (sge->freelQ[1].size >> 2)) {
 883                 irq_reg |= F_FL_EXHAUSTED;
 884                 irqholdoff_reg = sge->fixed_intrtimer;
 885         } else {
 886                 /* Clear the F_FL_EXHAUSTED interrupts for now */
 887                 irq_reg &= ~F_FL_EXHAUSTED;
 888                 irqholdoff_reg = sge->intrtimer_nres;
 889         }
 890         writel(irqholdoff_reg, adapter->regs + A_SG_INTRTIMER);
 891         writel(irq_reg, adapter->regs + A_SG_INT_ENABLE);
 892
 893         /* We reenable the Qs to force a freelist GTS interrupt later */
 894         doorbell_pio(adapter, F_FL0_ENABLE | F_FL1_ENABLE);
 895 }
 896
 897 #define SGE_PL_INTR_MASK (F_PL_INTR_SGE_ERR | F_PL_INTR_SGE_DATA)
 898 #define SGE_INT_FATAL (F_RESPQ_OVERFLOW | F_PACKET_TOO_BIG | F_PACKET_MISMATCH)
 899 #define SGE_INT_ENABLE (F_RESPQ_EXHAUSTED | F_RESPQ_OVERFLOW | \
 900                         F_FL_EXHAUSTED | F_PACKET_TOO_BIG | F_PACKET_MISMATCH)
 901
 902 /*
 903  * Disable SGE Interrupts
 904  */
 905 void t1_sge_intr_disable(struct sge *sge)
 906 {
 907         u32 val = readl(sge->adapter->regs + A_PL_ENABLE);
 908
 909         writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);
 910         writel(0, sge->adapter->regs + A_SG_INT_ENABLE);
 911 }
 912
 913 /*
 914  * Enable SGE interrupts.
 915  */
 916 void t1_sge_intr_enable(struct sge *sge)
 917 {
 918         u32 en = SGE_INT_ENABLE;
 919         u32 val = readl(sge->adapter->regs + A_PL_ENABLE);
 920
 921         if (sge->adapter->port[0].dev->hw_features & NETIF_F_TSO)
 922                 en &= ~F_PACKET_TOO_BIG;
 923         writel(en, sge->adapter->regs + A_SG_INT_ENABLE);
 924         writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);
 925 }
 926
 927 /*
 928  * Clear SGE interrupts.
 929  */
 930 void t1_sge_intr_clear(struct sge *sge)
 931 {
 932         writel(SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_CAUSE);
 933         writel(0xffffffff, sge->adapter->regs + A_SG_INT_CAUSE);
 934 }
 935
 936 /*
 937  * SGE 'Error' interrupt handler
 938  */
 939 int t1_sge_intr_error_handler(struct sge *sge)
 940 {
 941         struct adapter *adapter = sge->adapter;
 942         u32 cause = readl(adapter->regs + A_SG_INT_CAUSE);
 943
 944         if (adapter->port[0].dev->hw_features & NETIF_F_TSO)
 945                 cause &= ~F_PACKET_TOO_BIG;
 946         if (cause & F_RESPQ_EXHAUSTED)
 947                 sge->stats.respQ_empty++;
 948         if (cause & F_RESPQ_OVERFLOW) {
 949                 sge->stats.respQ_overflow++;
 950                 pr_alert("%s: SGE response queue overflow\n",
 951                          adapter->name);
 952         }
 953         if (cause & F_FL_EXHAUSTED) {
 954                 sge->stats.freelistQ_empty++;
 955                 freelQs_empty(sge);
 956         }
 957         if (cause & F_PACKET_TOO_BIG) {
 958                 sge->stats.pkt_too_big++;
 959                 pr_alert("%s: SGE max packet size exceeded\n",
 960                          adapter->name);
 961         }
 962         if (cause & F_PACKET_MISMATCH) {
 963                 sge->stats.pkt_mismatch++;
 964                 pr_alert("%s: SGE packet mismatch\n", adapter->name);
 965         }
 966         if (cause & SGE_INT_FATAL)
 967                 t1_fatal_err(adapter);
 968
 969         writel(cause, adapter->regs + A_SG_INT_CAUSE);
 970         return 0;
 971 }
 972
 973 const struct sge_intr_counts *t1_sge_get_intr_counts(const struct sge *sge)
 974 {
 975         return &sge->stats;
 976 }
 977
 978 void t1_sge_get_port_stats(const struct sge *sge, int port,
 979                            struct sge_port_stats *ss)
 980 {
 981         int cpu;
 982
 983         memset(ss, 0, sizeof(*ss));
 984         for_each_possible_cpu(cpu) {
 985                 struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[port], cpu);
 986
 987                 ss->rx_cso_good += st->rx_cso_good;
 988                 ss->tx_cso += st->tx_cso;
 989                 ss->tx_tso += st->tx_tso;
 990                 ss->tx_need_hdrroom += st->tx_need_hdrroom;
 991                 ss->vlan_xtract += st->vlan_xtract;
 992                 ss->vlan_insert += st->vlan_insert;
 993         }
 994 }
 995
 996 /**
 997  *      recycle_fl_buf - recycle a free list buffer
 998  *      @fl: the free list
 999  *      @idx: index of buffer to recycle
1000  *
1001  *      Recycles the specified buffer on the given free list by adding it at
1002  *      the next available slot on the list.
1003  */
1004 static void recycle_fl_buf(struct freelQ *fl, int idx)
1005 {
1006         struct freelQ_e *from = &fl->entries[idx];
1007         struct freelQ_e *to = &fl->entries[fl->pidx];
1008
1009         fl->centries[fl->pidx] = fl->centries[idx];
1010         to->addr_lo = from->addr_lo;
1011         to->addr_hi = from->addr_hi;
1012         to->len_gen = G_CMD_LEN(from->len_gen) | V_CMD_GEN1(fl->genbit);
1013         wmb();
1014         to->gen2 = V_CMD_GEN2(fl->genbit);
1015         fl->credits++;
1016
1017         if (++fl->pidx == fl->size) {
1018                 fl->pidx = 0;
1019                 fl->genbit ^= 1;
1020         }
1021 }
1022
1023 static int copybreak __read_mostly = 256;
1024 module_param(copybreak, int, 0);
1025 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
1026
1027 /**
1028  *      get_packet - return the next ingress packet buffer
1029  *      @pdev: the PCI device that received the packet
1030  *      @fl: the SGE free list holding the packet
1031  *      @len: the actual packet length, excluding any SGE padding
1032  *
1033  *      Get the next packet from a free list and complete setup of the
1034  *      sk_buff.  If the packet is small we make a copy and recycle the
1035  *      original buffer, otherwise we use the original buffer itself.  If a
1036  *      positive drop threshold is supplied packets are dropped and their
1037  *      buffers recycled if (a) the number of remaining buffers is under the
1038  *      threshold and the packet is too big to copy, or (b) the packet should
1039  *      be copied but there is no memory for the copy.
1040  */
1041 static inline struct sk_buff *get_packet(struct pci_dev *pdev,
1042                                          struct freelQ *fl, unsigned int len)
1043 {
1044         struct sk_buff *skb;
1045         const struct freelQ_ce *ce = &fl->centries[fl->cidx];
1046
1047         if (len < copybreak) {
1048                 skb = netdev_alloc_skb_ip_align(NULL, len);
1049                 if (!skb)
1050                         goto use_orig_buf;
1051
1052                 skb_put(skb, len);
1053                 pci_dma_sync_single_for_cpu(pdev,
1054                                             dma_unmap_addr(ce, dma_addr),
1055                                             dma_unmap_len(ce, dma_len),
1056                                             PCI_DMA_FROMDEVICE);
1057                 skb_copy_from_linear_data(ce->skb, skb->data, len);
1058                 pci_dma_sync_single_for_device(pdev,
1059                                                dma_unmap_addr(ce, dma_addr),
1060                                                dma_unmap_len(ce, dma_len),
1061                                                PCI_DMA_FROMDEVICE);
1062                 recycle_fl_buf(fl, fl->cidx);
1063                 return skb;
1064         }
1065
1066 use_orig_buf:
1067         if (fl->credits < 2) {
1068                 recycle_fl_buf(fl, fl->cidx);
1069                 return NULL;
1070         }
1071
1072         pci_unmap_single(pdev, dma_unmap_addr(ce, dma_addr),
1073                          dma_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE);
1074         skb = ce->skb;
1075         prefetch(skb->data);
1076
1077         skb_put(skb, len);
1078         return skb;
1079 }
1080
1081 /**
1082  *      unexpected_offload - handle an unexpected offload packet
1083  *      @adapter: the adapter
1084  *      @fl: the free list that received the packet
1085  *
1086  *      Called when we receive an unexpected offload packet (e.g., the TOE
1087  *      function is disabled or the card is a NIC).  Prints a message and
1088  *      recycles the buffer.
1089  */
1090 static void unexpected_offload(struct adapter *adapter, struct freelQ *fl)
1091 {
1092         struct freelQ_ce *ce = &fl->centries[fl->cidx];
1093         struct sk_buff *skb = ce->skb;
1094
1095         pci_dma_sync_single_for_cpu(adapter->pdev, dma_unmap_addr(ce, dma_addr),
1096                             dma_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE);
1097         pr_err("%s: unexpected offload packet, cmd %u\n",
1098                adapter->name, *skb->data);
1099         recycle_fl_buf(fl, fl->cidx);
1100 }
1101
1102 /*
1103  * T1/T2 SGE limits the maximum DMA size per TX descriptor to
1104  * SGE_TX_DESC_MAX_PLEN (16KB). If the PAGE_SIZE is larger than 16KB, the
1105  * stack might send more than SGE_TX_DESC_MAX_PLEN in a contiguous manner.
1106  * Note that the *_large_page_tx_descs stuff will be optimized out when
1107  * PAGE_SIZE <= SGE_TX_DESC_MAX_PLEN.
1108  *
1109  * compute_large_page_descs() computes how many additional descriptors are
1110  * required to break down the stack's request.
1111  */
1112 static inline unsigned int compute_large_page_tx_descs(struct sk_buff *skb)
1113 {
1114         unsigned int count = 0;
1115
1116         if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) {
1117                 unsigned int nfrags = skb_shinfo(skb)->nr_frags;
1118                 unsigned int i, len = skb_headlen(skb);
1119                 while (len > SGE_TX_DESC_MAX_PLEN) {
1120                         count++;
1121                         len -= SGE_TX_DESC_MAX_PLEN;
1122                 }
1123                 for (i = 0; nfrags--; i++) {
1124                         const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1125                         len = skb_frag_size(frag);
1126                         while (len > SGE_TX_DESC_MAX_PLEN) {
1127                                 count++;
1128                                 len -= SGE_TX_DESC_MAX_PLEN;
1129                         }
1130                 }
1131         }
1132         return count;
1133 }
1134
1135 /*
1136  * Write a cmdQ entry.
1137  *
1138  * Since this function writes the 'flags' field, it must not be used to
1139  * write the first cmdQ entry.
1140  */
1141 static inline void write_tx_desc(struct cmdQ_e *e, dma_addr_t mapping,
1142                                  unsigned int len, unsigned int gen,
1143                                  unsigned int eop)
1144 {
1145         BUG_ON(len > SGE_TX_DESC_MAX_PLEN);
1146
1147         e->addr_lo = (u32)mapping;
1148         e->addr_hi = (u64)mapping >> 32;
1149         e->len_gen = V_CMD_LEN(len) | V_CMD_GEN1(gen);
1150         e->flags = F_CMD_DATAVALID | V_CMD_EOP(eop) | V_CMD_GEN2(gen);
1151 }
1152
1153 /*
1154  * See comment for previous function.
1155  *
1156  * write_tx_descs_large_page() writes additional SGE tx descriptors if
1157  * *desc_len exceeds HW's capability.
1158  */
1159 static inline unsigned int write_large_page_tx_descs(unsigned int pidx,
1160                                                      struct cmdQ_e **e,
1161                                                      struct cmdQ_ce **ce,
1162                                                      unsigned int *gen,
1163                                                      dma_addr_t *desc_mapping,
1164                                                      unsigned int *desc_len,
1165                                                      unsigned int nfrags,
1166                                                      struct cmdQ *q)
1167 {
1168         if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) {
1169                 struct cmdQ_e *e1 = *e;
1170                 struct cmdQ_ce *ce1 = *ce;
1171
1172                 while (*desc_len > SGE_TX_DESC_MAX_PLEN) {
1173                         *desc_len -= SGE_TX_DESC_MAX_PLEN;
1174                         write_tx_desc(e1, *desc_mapping, SGE_TX_DESC_MAX_PLEN,
1175                                       *gen, nfrags == 0 && *desc_len == 0);
1176                         ce1->skb = NULL;
1177                         dma_unmap_len_set(ce1, dma_len, 0);
1178                         *desc_mapping += SGE_TX_DESC_MAX_PLEN;
1179                         if (*desc_len) {
1180                                 ce1++;
1181                                 e1++;
1182                                 if (++pidx == q->size) {
1183                                         pidx = 0;
1184                                         *gen ^= 1;
1185                                         ce1 = q->centries;
1186                                         e1 = q->entries;
1187                                 }
1188                         }
1189                 }
1190                 *e = e1;
1191                 *ce = ce1;
1192         }
1193         return pidx;
1194 }
1195
1196 /*
1197  * Write the command descriptors to transmit the given skb starting at
1198  * descriptor pidx with the given generation.
1199  */
1200 static inline void write_tx_descs(struct adapter *adapter, struct sk_buff *skb,
1201                                   unsigned int pidx, unsigned int gen,
1202                                   struct cmdQ *q)
1203 {
1204         dma_addr_t mapping, desc_mapping;
1205         struct cmdQ_e *e, *e1;
1206         struct cmdQ_ce *ce;
1207         unsigned int i, flags, first_desc_len, desc_len,
1208             nfrags = skb_shinfo(skb)->nr_frags;
1209
1210         e = e1 = &q->entries[pidx];
1211         ce = &q->centries[pidx];
1212
1213         mapping = pci_map_single(adapter->pdev, skb->data,
1214                                  skb_headlen(skb), PCI_DMA_TODEVICE);
1215
1216         desc_mapping = mapping;
1217         desc_len = skb_headlen(skb);
1218
1219         flags = F_CMD_DATAVALID | F_CMD_SOP |
1220             V_CMD_EOP(nfrags == 0 && desc_len <= SGE_TX_DESC_MAX_PLEN) |
1221             V_CMD_GEN2(gen);
1222         first_desc_len = (desc_len <= SGE_TX_DESC_MAX_PLEN) ?
1223             desc_len : SGE_TX_DESC_MAX_PLEN;
1224         e->addr_lo = (u32)desc_mapping;
1225         e->addr_hi = (u64)desc_mapping >> 32;
1226         e->len_gen = V_CMD_LEN(first_desc_len) | V_CMD_GEN1(gen);
1227         ce->skb = NULL;
1228         dma_unmap_len_set(ce, dma_len, 0);
1229
1230         if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN &&
1231             desc_len > SGE_TX_DESC_MAX_PLEN) {
1232                 desc_mapping += first_desc_len;
1233                 desc_len -= first_desc_len;
1234                 e1++;
1235                 ce++;
1236                 if (++pidx == q->size) {
1237                         pidx = 0;
1238                         gen ^= 1;
1239                         e1 = q->entries;
1240                         ce = q->centries;
1241                 }
1242                 pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen,
1243                                                  &desc_mapping, &desc_len,
1244                                                  nfrags, q);
1245
1246                 if (likely(desc_len))
1247                         write_tx_desc(e1, desc_mapping, desc_len, gen,
1248                                       nfrags == 0);
1249         }
1250
1251         ce->skb = NULL;
1252         dma_unmap_addr_set(ce, dma_addr, mapping);
1253         dma_unmap_len_set(ce, dma_len, skb_headlen(skb));
1254
1255         for (i = 0; nfrags--; i++) {
1256                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1257                 e1++;
1258                 ce++;
1259                 if (++pidx == q->size) {
1260                         pidx = 0;
1261                         gen ^= 1;
1262                         e1 = q->entries;
1263                         ce = q->centries;
1264                 }
1265
1266                 mapping = skb_frag_dma_map(&adapter->pdev->dev, frag, 0,
1267                                            skb_frag_size(frag), DMA_TO_DEVICE);
1268                 desc_mapping = mapping;
1269                 desc_len = skb_frag_size(frag);
1270
1271                 pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen,
1272                                                  &desc_mapping, &desc_len,
1273                                                  nfrags, q);
1274                 if (likely(desc_len))
1275                         write_tx_desc(e1, desc_mapping, desc_len, gen,
1276                                       nfrags == 0);
1277                 ce->skb = NULL;
1278                 dma_unmap_addr_set(ce, dma_addr, mapping);
1279                 dma_unmap_len_set(ce, dma_len, skb_frag_size(frag));
1280         }
1281         ce->skb = skb;
1282         wmb();
1283         e->flags = flags;
1284 }
1285
1286 /*
1287  * Clean up completed Tx buffers.
1288  */
1289 static inline void reclaim_completed_tx(struct sge *sge, struct cmdQ *q)
1290 {
1291         unsigned int reclaim = q->processed - q->cleaned;
1292
1293         if (reclaim) {
1294                 pr_debug("reclaim_completed_tx processed:%d cleaned:%d\n",
1295                          q->processed, q->cleaned);
1296                 free_cmdQ_buffers(sge, q, reclaim);
1297                 q->cleaned += reclaim;
1298         }
1299 }
1300
1301 /*
1302  * Called from tasklet. Checks the scheduler for any
1303  * pending skbs that can be sent.
1304  */
1305 static void restart_sched(unsigned long arg)
1306 {
1307         struct sge *sge = (struct sge *) arg;
1308         struct adapter *adapter = sge->adapter;
1309         struct cmdQ *q = &sge->cmdQ[0];
1310         struct sk_buff *skb;
1311         unsigned int credits, queued_skb = 0;
1312
1313         spin_lock(&q->lock);
1314         reclaim_completed_tx(sge, q);
1315
1316         credits = q->size - q->in_use;
1317         pr_debug("restart_sched credits=%d\n", credits);
1318         while ((skb = sched_skb(sge, NULL, credits)) != NULL) {
1319                 unsigned int genbit, pidx, count;
1320                 count = 1 + skb_shinfo(skb)->nr_frags;
1321                 count += compute_large_page_tx_descs(skb);
1322                 q->in_use += count;
1323                 genbit = q->genbit;
1324                 pidx = q->pidx;
1325                 q->pidx += count;
1326                 if (q->pidx >= q->size) {
1327                         q->pidx -= q->size;
1328                         q->genbit ^= 1;
1329                 }
1330                 write_tx_descs(adapter, skb, pidx, genbit, q);
1331                 credits = q->size - q->in_use;
1332                 queued_skb = 1;
1333         }
1334
1335         if (queued_skb) {
1336                 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1337                 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
1338                         set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1339                         writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1340                 }
1341         }
1342         spin_unlock(&q->lock);
1343 }
1344
1345 /**
1346  *      sge_rx - process an ingress ethernet packet
1347  *      @sge: the sge structure
1348  *      @fl: the free list that contains the packet buffer
1349  *      @len: the packet length
1350  *
1351  *      Process an ingress ethernet pakcet and deliver it to the stack.
1352  */
1353 static void sge_rx(struct sge *sge, struct freelQ *fl, unsigned int len)
1354 {
1355         struct sk_buff *skb;
1356         const struct cpl_rx_pkt *p;
1357         struct adapter *adapter = sge->adapter;
1358         struct sge_port_stats *st;
1359         struct net_device *dev;
1360
1361         skb = get_packet(adapter->pdev, fl, len - sge->rx_pkt_pad);
1362         if (unlikely(!skb)) {
1363                 sge->stats.rx_drops++;
1364                 return;
1365         }
1366
1367         p = (const struct cpl_rx_pkt *) skb->data;
1368         if (p->iff >= adapter->params.nports) {
1369                 kfree_skb(skb);
1370                 return;
1371         }
1372         __skb_pull(skb, sizeof(*p));
1373
1374         st = this_cpu_ptr(sge->port_stats[p->iff]);
1375         dev = adapter->port[p->iff].dev;
1376
1377         skb->protocol = eth_type_trans(skb, dev);
1378         if ((dev->features & NETIF_F_RXCSUM) && p->csum == 0xffff &&
1379             skb->protocol == htons(ETH_P_IP) &&
1380             (skb->data[9] == IPPROTO_TCP || skb->data[9] == IPPROTO_UDP)) {
1381                 ++st->rx_cso_good;
1382                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1383         } else
1384                 skb_checksum_none_assert(skb);
1385
1386         if (p->vlan_valid) {
1387                 st->vlan_xtract++;
1388                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(p->vlan));
1389         }
1390         netif_receive_skb(skb);
1391 }
1392
1393 /*
1394  * Returns true if a command queue has enough available descriptors that
1395  * we can resume Tx operation after temporarily disabling its packet queue.
1396  */
1397 static inline int enough_free_Tx_descs(const struct cmdQ *q)
1398 {
1399         unsigned int r = q->processed - q->cleaned;
1400
1401         return q->in_use - r < (q->size >> 1);
1402 }
1403
1404 /*
1405  * Called when sufficient space has become available in the SGE command queues
1406  * after the Tx packet schedulers have been suspended to restart the Tx path.
1407  */
1408 static void restart_tx_queues(struct sge *sge)
1409 {
1410         struct adapter *adap = sge->adapter;
1411         int i;
1412
1413         if (!enough_free_Tx_descs(&sge->cmdQ[0]))
1414                 return;
1415
1416         for_each_port(adap, i) {
1417                 struct net_device *nd = adap->port[i].dev;
1418
1419                 if (test_and_clear_bit(nd->if_port, &sge->stopped_tx_queues) &&
1420                     netif_running(nd)) {
1421                         sge->stats.cmdQ_restarted[2]++;
1422                         netif_wake_queue(nd);
1423                 }
1424         }
1425 }
1426
1427 /*
1428  * update_tx_info is called from the interrupt handler/NAPI to return cmdQ0
1429  * information.
1430  */
1431 static unsigned int update_tx_info(struct adapter *adapter,
1432                                           unsigned int flags,
1433                                           unsigned int pr0)
1434 {
1435         struct sge *sge = adapter->sge;
1436         struct cmdQ *cmdq = &sge->cmdQ[0];
1437
1438         cmdq->processed += pr0;
1439         if (flags & (F_FL0_ENABLE | F_FL1_ENABLE)) {
1440                 freelQs_empty(sge);
1441                 flags &= ~(F_FL0_ENABLE | F_FL1_ENABLE);
1442         }
1443         if (flags & F_CMDQ0_ENABLE) {
1444                 clear_bit(CMDQ_STAT_RUNNING, &cmdq->status);
1445
1446                 if (cmdq->cleaned + cmdq->in_use != cmdq->processed &&
1447                     !test_and_set_bit(CMDQ_STAT_LAST_PKT_DB, &cmdq->status)) {
1448                         set_bit(CMDQ_STAT_RUNNING, &cmdq->status);
1449                         writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1450                 }
1451                 if (sge->tx_sched)
1452                         tasklet_hi_schedule(&sge->tx_sched->sched_tsk);
1453
1454                 flags &= ~F_CMDQ0_ENABLE;
1455         }
1456
1457         if (unlikely(sge->stopped_tx_queues != 0))
1458                 restart_tx_queues(sge);
1459
1460         return flags;
1461 }
1462
1463 /*
1464  * Process SGE responses, up to the supplied budget.  Returns the number of
1465  * responses processed.  A negative budget is effectively unlimited.
1466  */
1467 static int process_responses(struct adapter *adapter, int budget)
1468 {
1469         struct sge *sge = adapter->sge;
1470         struct respQ *q = &sge->respQ;
1471         struct respQ_e *e = &q->entries[q->cidx];
1472         int done = 0;
1473         unsigned int flags = 0;
1474         unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0};
1475
1476         while (done < budget && e->GenerationBit == q->genbit) {
1477                 flags |= e->Qsleeping;
1478
1479                 cmdq_processed[0] += e->Cmdq0CreditReturn;
1480                 cmdq_processed[1] += e->Cmdq1CreditReturn;
1481
1482                 /* We batch updates to the TX side to avoid cacheline
1483                  * ping-pong of TX state information on MP where the sender
1484                  * might run on a different CPU than this function...
1485                  */
1486                 if (unlikely((flags & F_CMDQ0_ENABLE) || cmdq_processed[0] > 64)) {
1487                         flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1488                         cmdq_processed[0] = 0;
1489                 }
1490
1491                 if (unlikely(cmdq_processed[1] > 16)) {
1492                         sge->cmdQ[1].processed += cmdq_processed[1];
1493                         cmdq_processed[1] = 0;
1494                 }
1495
1496                 if (likely(e->DataValid)) {
1497                         struct freelQ *fl = &sge->freelQ[e->FreelistQid];
1498
1499                         BUG_ON(!e->Sop || !e->Eop);
1500                         if (unlikely(e->Offload))
1501                                 unexpected_offload(adapter, fl);
1502                         else
1503                                 sge_rx(sge, fl, e->BufferLength);
1504
1505                         ++done;
1506
1507                         /*
1508                          * Note: this depends on each packet consuming a
1509                          * single free-list buffer; cf. the BUG above.
1510                          */
1511                         if (++fl->cidx == fl->size)
1512                                 fl->cidx = 0;
1513                         prefetch(fl->centries[fl->cidx].skb);
1514
1515                         if (unlikely(--fl->credits <
1516                                      fl->size - SGE_FREEL_REFILL_THRESH))
1517                                 refill_free_list(sge, fl);
1518                 } else
1519                         sge->stats.pure_rsps++;
1520
1521                 e++;
1522                 if (unlikely(++q->cidx == q->size)) {
1523                         q->cidx = 0;
1524                         q->genbit ^= 1;
1525                         e = q->entries;
1526                 }
1527                 prefetch(e);
1528
1529                 if (++q->credits > SGE_RESPQ_REPLENISH_THRES) {
1530                         writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT);
1531                         q->credits = 0;
1532                 }
1533         }
1534
1535         flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1536         sge->cmdQ[1].processed += cmdq_processed[1];
1537
1538         return done;
1539 }
1540
1541 static inline int responses_pending(const struct adapter *adapter)
1542 {
1543         const struct respQ *Q = &adapter->sge->respQ;
1544         const struct respQ_e *e = &Q->entries[Q->cidx];
1545
1546         return e->GenerationBit == Q->genbit;
1547 }
1548
1549 /*
1550  * A simpler version of process_responses() that handles only pure (i.e.,
1551  * non data-carrying) responses.  Such respones are too light-weight to justify
1552  * calling a softirq when using NAPI, so we handle them specially in hard
1553  * interrupt context.  The function is called with a pointer to a response,
1554  * which the caller must ensure is a valid pure response.  Returns 1 if it
1555  * encounters a valid data-carrying response, 0 otherwise.
1556  */
1557 static int process_pure_responses(struct adapter *adapter)
1558 {
1559         struct sge *sge = adapter->sge;
1560         struct respQ *q = &sge->respQ;
1561         struct respQ_e *e = &q->entries[q->cidx];
1562         const struct freelQ *fl = &sge->freelQ[e->FreelistQid];
1563         unsigned int flags = 0;
1564         unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0};
1565
1566         prefetch(fl->centries[fl->cidx].skb);
1567         if (e->DataValid)
1568                 return 1;
1569
1570         do {
1571                 flags |= e->Qsleeping;
1572
1573                 cmdq_processed[0] += e->Cmdq0CreditReturn;
1574                 cmdq_processed[1] += e->Cmdq1CreditReturn;
1575
1576                 e++;
1577                 if (unlikely(++q->cidx == q->size)) {
1578                         q->cidx = 0;
1579                         q->genbit ^= 1;
1580                         e = q->entries;
1581                 }
1582                 prefetch(e);
1583
1584                 if (++q->credits > SGE_RESPQ_REPLENISH_THRES) {
1585                         writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT);
1586                         q->credits = 0;
1587                 }
1588                 sge->stats.pure_rsps++;
1589         } while (e->GenerationBit == q->genbit && !e->DataValid);
1590
1591         flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1592         sge->cmdQ[1].processed += cmdq_processed[1];
1593
1594         return e->GenerationBit == q->genbit;
1595 }
1596
1597 /*
1598  * Handler for new data events when using NAPI.  This does not need any locking
1599  * or protection from interrupts as data interrupts are off at this point and
1600  * other adapter interrupts do not interfere.
1601  */
1602 int t1_poll(struct napi_struct *napi, int budget)
1603 {
1604         struct adapter *adapter = container_of(napi, struct adapter, napi);
1605         int work_done = process_responses(adapter, budget);
1606
1607         if (likely(work_done < budget)) {
1608                 napi_complete(napi);
1609                 writel(adapter->sge->respQ.cidx,
1610                        adapter->regs + A_SG_SLEEPING);
1611         }
1612         return work_done;
1613 }
1614
1615 irqreturn_t t1_interrupt(int irq, void *data)
1616 {
1617         struct adapter *adapter = data;
1618         struct sge *sge = adapter->sge;
1619         int handled;
1620
1621         if (likely(responses_pending(adapter))) {
1622                 writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE);
1623
1624                 if (napi_schedule_prep(&adapter->napi)) {
1625                         if (process_pure_responses(adapter))
1626                                 __napi_schedule(&adapter->napi);
1627                         else {
1628                                 /* no data, no NAPI needed */
1629                                 writel(sge->respQ.cidx, adapter->regs + A_SG_SLEEPING);
1630                                 /* undo schedule_prep */
1631                                 napi_enable(&adapter->napi);
1632                         }
1633                 }
1634                 return IRQ_HANDLED;
1635         }
1636
1637         spin_lock(&adapter->async_lock);
1638         handled = t1_slow_intr_handler(adapter);
1639         spin_unlock(&adapter->async_lock);
1640
1641         if (!handled)
1642                 sge->stats.unhandled_irqs++;
1643
1644         return IRQ_RETVAL(handled != 0);
1645 }
1646
1647 /*
1648  * Enqueues the sk_buff onto the cmdQ[qid] and has hardware fetch it.
1649  *
1650  * The code figures out how many entries the sk_buff will require in the
1651  * cmdQ and updates the cmdQ data structure with the state once the enqueue
1652  * has complete. Then, it doesn't access the global structure anymore, but
1653  * uses the corresponding fields on the stack. In conjunction with a spinlock
1654  * around that code, we can make the function reentrant without holding the
1655  * lock when we actually enqueue (which might be expensive, especially on
1656  * architectures with IO MMUs).
1657  *
1658  * This runs with softirqs disabled.
1659  */
1660 static int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter,
1661                      unsigned int qid, struct net_device *dev)
1662 {
1663         struct sge *sge = adapter->sge;
1664         struct cmdQ *q = &sge->cmdQ[qid];
1665         unsigned int credits, pidx, genbit, count, use_sched_skb = 0;
1666
1667         if (!spin_trylock(&q->lock))
1668                 return NETDEV_TX_LOCKED;
1669
1670         reclaim_completed_tx(sge, q);
1671
1672         pidx = q->pidx;
1673         credits = q->size - q->in_use;
1674         count = 1 + skb_shinfo(skb)->nr_frags;
1675         count += compute_large_page_tx_descs(skb);
1676
1677         /* Ethernet packet */
1678         if (unlikely(credits < count)) {
1679                 if (!netif_queue_stopped(dev)) {
1680                         netif_stop_queue(dev);
1681                         set_bit(dev->if_port, &sge->stopped_tx_queues);
1682                         sge->stats.cmdQ_full[2]++;
1683                         pr_err("%s: Tx ring full while queue awake!\n",
1684                                adapter->name);
1685                 }
1686                 spin_unlock(&q->lock);
1687                 return NETDEV_TX_BUSY;
1688         }
1689
1690         if (unlikely(credits - count < q->stop_thres)) {
1691                 netif_stop_queue(dev);
1692                 set_bit(dev->if_port, &sge->stopped_tx_queues);
1693                 sge->stats.cmdQ_full[2]++;
1694         }
1695
1696         /* T204 cmdQ0 skbs that are destined for a certain port have to go
1697          * through the scheduler.
1698          */
1699         if (sge->tx_sched && !qid && skb->dev) {
1700 use_sched:
1701                 use_sched_skb = 1;
1702                 /* Note that the scheduler might return a different skb than
1703                  * the one passed in.
1704                  */
1705                 skb = sched_skb(sge, skb, credits);
1706                 if (!skb) {
1707                         spin_unlock(&q->lock);
1708                         return NETDEV_TX_OK;
1709                 }
1710                 pidx = q->pidx;
1711                 count = 1 + skb_shinfo(skb)->nr_frags;
1712                 count += compute_large_page_tx_descs(skb);
1713         }
1714
1715         q->in_use += count;
1716         genbit = q->genbit;
1717         pidx = q->pidx;
1718         q->pidx += count;
1719         if (q->pidx >= q->size) {
1720                 q->pidx -= q->size;
1721                 q->genbit ^= 1;
1722         }
1723         spin_unlock(&q->lock);
1724
1725         write_tx_descs(adapter, skb, pidx, genbit, q);
1726
1727         /*
1728          * We always ring the doorbell for cmdQ1.  For cmdQ0, we only ring
1729          * the doorbell if the Q is asleep. There is a natural race, where
1730          * the hardware is going to sleep just after we checked, however,
1731          * then the interrupt handler will detect the outstanding TX packet
1732          * and ring the doorbell for us.
1733          */
1734         if (qid)
1735                 doorbell_pio(adapter, F_CMDQ1_ENABLE);
1736         else {
1737                 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1738                 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
1739                         set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1740                         writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1741                 }
1742         }
1743
1744         if (use_sched_skb) {
1745                 if (spin_trylock(&q->lock)) {
1746                         credits = q->size - q->in_use;
1747                         skb = NULL;
1748                         goto use_sched;
1749                 }
1750         }
1751         return NETDEV_TX_OK;
1752 }
1753
1754 #define MK_ETH_TYPE_MSS(type, mss) (((mss) & 0x3FFF) | ((type) << 14))
1755
1756 /*
1757  *      eth_hdr_len - return the length of an Ethernet header
1758  *      @data: pointer to the start of the Ethernet header
1759  *
1760  *      Returns the length of an Ethernet header, including optional VLAN tag.
1761  */
1762 static inline int eth_hdr_len(const void *data)
1763 {
1764         const struct ethhdr *e = data;
1765
1766         return e->h_proto == htons(ETH_P_8021Q) ? VLAN_ETH_HLEN : ETH_HLEN;
1767 }
1768
1769 /*
1770  * Adds the CPL header to the sk_buff and passes it to t1_sge_tx.
1771  */
1772 netdev_tx_t t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1773 {
1774         struct adapter *adapter = dev->ml_priv;
1775         struct sge *sge = adapter->sge;
1776         struct sge_port_stats *st = this_cpu_ptr(sge->port_stats[dev->if_port]);
1777         struct cpl_tx_pkt *cpl;
1778         struct sk_buff *orig_skb = skb;
1779         int ret;
1780
1781         if (skb->protocol == htons(ETH_P_CPL5))
1782                 goto send;
1783
1784         /*
1785          * We are using a non-standard hard_header_len.
1786          * Allocate more header room in the rare cases it is not big enough.
1787          */
1788         if (unlikely(skb_headroom(skb) < dev->hard_header_len - ETH_HLEN)) {
1789                 skb = skb_realloc_headroom(skb, sizeof(struct cpl_tx_pkt_lso));
1790                 ++st->tx_need_hdrroom;
1791                 dev_kfree_skb_any(orig_skb);
1792                 if (!skb)
1793                         return NETDEV_TX_OK;
1794         }
1795
1796         if (skb_shinfo(skb)->gso_size) {
1797                 int eth_type;
1798                 struct cpl_tx_pkt_lso *hdr;
1799
1800                 ++st->tx_tso;
1801
1802                 eth_type = skb_network_offset(skb) == ETH_HLEN ?
1803                         CPL_ETH_II : CPL_ETH_II_VLAN;
1804
1805                 hdr = (struct cpl_tx_pkt_lso *)skb_push(skb, sizeof(*hdr));
1806                 hdr->opcode = CPL_TX_PKT_LSO;
1807                 hdr->ip_csum_dis = hdr->l4_csum_dis = 0;
1808                 hdr->ip_hdr_words = ip_hdr(skb)->ihl;
1809                 hdr->tcp_hdr_words = tcp_hdr(skb)->doff;
1810                 hdr->eth_type_mss = htons(MK_ETH_TYPE_MSS(eth_type,
1811                                                           skb_shinfo(skb)->gso_size));
1812                 hdr->len = htonl(skb->len - sizeof(*hdr));
1813                 cpl = (struct cpl_tx_pkt *)hdr;
1814         } else {
1815                 /*
1816                  * Packets shorter than ETH_HLEN can break the MAC, drop them
1817                  * early.  Also, we may get oversized packets because some
1818                  * parts of the kernel don't handle our unusual hard_header_len
1819                  * right, drop those too.
1820                  */
1821                 if (unlikely(skb->len < ETH_HLEN ||
1822                              skb->len > dev->mtu + eth_hdr_len(skb->data))) {
1823                         netdev_dbg(dev, "packet size %d hdr %d mtu%d\n",
1824                                    skb->len, eth_hdr_len(skb->data), dev->mtu);
1825                         dev_kfree_skb_any(skb);
1826                         return NETDEV_TX_OK;
1827                 }
1828
1829                 if (skb->ip_summed == CHECKSUM_PARTIAL &&
1830                     ip_hdr(skb)->protocol == IPPROTO_UDP) {
1831                         if (unlikely(skb_checksum_help(skb))) {
1832                                 netdev_dbg(dev, "unable to do udp checksum\n");
1833                                 dev_kfree_skb_any(skb);
1834                                 return NETDEV_TX_OK;
1835                         }
1836                 }
1837
1838                 /* Hmmm, assuming to catch the gratious arp... and we'll use
1839                  * it to flush out stuck espi packets...
1840                  */
1841                 if ((unlikely(!adapter->sge->espibug_skb[dev->if_port]))) {
1842                         if (skb->protocol == htons(ETH_P_ARP) &&
1843                             arp_hdr(skb)->ar_op == htons(ARPOP_REQUEST)) {
1844                                 adapter->sge->espibug_skb[dev->if_port] = skb;
1845                                 /* We want to re-use this skb later. We
1846                                  * simply bump the reference count and it
1847                                  * will not be freed...
1848                                  */
1849                                 skb = skb_get(skb);
1850                         }
1851                 }
1852
1853                 cpl = (struct cpl_tx_pkt *)__skb_push(skb, sizeof(*cpl));
1854                 cpl->opcode = CPL_TX_PKT;
1855                 cpl->ip_csum_dis = 1;    /* SW calculates IP csum */
1856                 cpl->l4_csum_dis = skb->ip_summed == CHECKSUM_PARTIAL ? 0 : 1;
1857                 /* the length field isn't used so don't bother setting it */
1858
1859                 st->tx_cso += (skb->ip_summed == CHECKSUM_PARTIAL);
1860         }
1861         cpl->iff = dev->if_port;
1862
1863         if (vlan_tx_tag_present(skb)) {
1864                 cpl->vlan_valid = 1;
1865                 cpl->vlan = htons(vlan_tx_tag_get(skb));
1866                 st->vlan_insert++;
1867         } else
1868                 cpl->vlan_valid = 0;
1869
1870 send:
1871         ret = t1_sge_tx(skb, adapter, 0, dev);
1872
1873         /* If transmit busy, and we reallocated skb's due to headroom limit,
1874          * then silently discard to avoid leak.
1875          */
1876         if (unlikely(ret != NETDEV_TX_OK && skb != orig_skb)) {
1877                 dev_kfree_skb_any(skb);
1878                 ret = NETDEV_TX_OK;
1879         }
1880         return ret;
1881 }
1882
1883 /*
1884  * Callback for the Tx buffer reclaim timer.  Runs with softirqs disabled.
1885  */
1886 static void sge_tx_reclaim_cb(unsigned long data)
1887 {
1888         int i;
1889         struct sge *sge = (struct sge *)data;
1890
1891         for (i = 0; i < SGE_CMDQ_N; ++i) {
1892                 struct cmdQ *q = &sge->cmdQ[i];
1893
1894                 if (!spin_trylock(&q->lock))
1895                         continue;
1896
1897                 reclaim_completed_tx(sge, q);
1898                 if (i == 0 && q->in_use) {    /* flush pending credits */
1899                         writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
1900                 }
1901                 spin_unlock(&q->lock);
1902         }
1903         mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
1904 }
1905
1906 /*
1907  * Propagate changes of the SGE coalescing parameters to the HW.
1908  */
1909 int t1_sge_set_coalesce_params(struct sge *sge, struct sge_params *p)
1910 {
1911         sge->fixed_intrtimer = p->rx_coalesce_usecs *
1912                 core_ticks_per_usec(sge->adapter);
1913         writel(sge->fixed_intrtimer, sge->adapter->regs + A_SG_INTRTIMER);
1914         return 0;
1915 }
1916
1917 /*
1918  * Allocates both RX and TX resources and configures the SGE. However,
1919  * the hardware is not enabled yet.
1920  */
1921 int t1_sge_configure(struct sge *sge, struct sge_params *p)
1922 {
1923         if (alloc_rx_resources(sge, p))
1924                 return -ENOMEM;
1925         if (alloc_tx_resources(sge, p)) {
1926                 free_rx_resources(sge);
1927                 return -ENOMEM;
1928         }
1929         configure_sge(sge, p);
1930
1931         /*
1932          * Now that we have sized the free lists calculate the payload
1933          * capacity of the large buffers.  Other parts of the driver use
1934          * this to set the max offload coalescing size so that RX packets
1935          * do not overflow our large buffers.
1936          */
1937         p->large_buf_capacity = jumbo_payload_capacity(sge);
1938         return 0;
1939 }
1940
1941 /*
1942  * Disables the DMA engine.
1943  */
1944 void t1_sge_stop(struct sge *sge)
1945 {
1946         int i;
1947         writel(0, sge->adapter->regs + A_SG_CONTROL);
1948         readl(sge->adapter->regs + A_SG_CONTROL); /* flush */
1949
1950         if (is_T2(sge->adapter))
1951                 del_timer_sync(&sge->espibug_timer);
1952
1953         del_timer_sync(&sge->tx_reclaim_timer);
1954         if (sge->tx_sched)
1955                 tx_sched_stop(sge);
1956
1957         for (i = 0; i < MAX_NPORTS; i++)
1958                 kfree_skb(sge->espibug_skb[i]);
1959 }
1960
1961 /*
1962  * Enables the DMA engine.
1963  */
1964 void t1_sge_start(struct sge *sge)
1965 {
1966         refill_free_list(sge, &sge->freelQ[0]);
1967         refill_free_list(sge, &sge->freelQ[1]);
1968
1969         writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL);
1970         doorbell_pio(sge->adapter, F_FL0_ENABLE | F_FL1_ENABLE);
1971         readl(sge->adapter->regs + A_SG_CONTROL); /* flush */
1972
1973         mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
1974
1975         if (is_T2(sge->adapter))
1976                 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
1977 }
1978
1979 /*
1980  * Callback for the T2 ESPI 'stuck packet feature' workaorund
1981  */
1982 static void espibug_workaround_t204(unsigned long data)
1983 {
1984         struct adapter *adapter = (struct adapter *)data;
1985         struct sge *sge = adapter->sge;
1986         unsigned int nports = adapter->params.nports;
1987         u32 seop[MAX_NPORTS];
1988
1989         if (adapter->open_device_map & PORT_MASK) {
1990                 int i;
1991
1992                 if (t1_espi_get_mon_t204(adapter, &(seop[0]), 0) < 0)
1993                         return;
1994
1995                 for (i = 0; i < nports; i++) {
1996                         struct sk_buff *skb = sge->espibug_skb[i];
1997
1998                         if (!netif_running(adapter->port[i].dev) ||
1999                             netif_queue_stopped(adapter->port[i].dev) ||
2000                             !seop[i] || ((seop[i] & 0xfff) != 0) || !skb)
2001                                 continue;
2002
2003                         if (!skb->cb[0]) {
2004                                 skb_copy_to_linear_data_offset(skb,
2005                                                     sizeof(struct cpl_tx_pkt),
2006                                                                ch_mac_addr,
2007                                                                ETH_ALEN);
2008                                 skb_copy_to_linear_data_offset(skb,
2009                                                                skb->len - 10,
2010                                                                ch_mac_addr,
2011                                                                ETH_ALEN);
2012                                 skb->cb[0] = 0xff;
2013                         }
2014
2015                         /* bump the reference count to avoid freeing of
2016                          * the skb once the DMA has completed.
2017                          */
2018                         skb = skb_get(skb);
2019                         t1_sge_tx(skb, adapter, 0, adapter->port[i].dev);
2020                 }
2021         }
2022         mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
2023 }
2024
2025 static void espibug_workaround(unsigned long data)
2026 {
2027         struct adapter *adapter = (struct adapter *)data;
2028         struct sge *sge = adapter->sge;
2029
2030         if (netif_running(adapter->port[0].dev)) {
2031                 struct sk_buff *skb = sge->espibug_skb[0];
2032                 u32 seop = t1_espi_get_mon(adapter, 0x930, 0);
2033
2034                 if ((seop & 0xfff0fff) == 0xfff && skb) {
2035                         if (!skb->cb[0]) {
2036                                 skb_copy_to_linear_data_offset(skb,
2037                                                      sizeof(struct cpl_tx_pkt),
2038                                                                ch_mac_addr,
2039                                                                ETH_ALEN);
2040                                 skb_copy_to_linear_data_offset(skb,
2041                                                                skb->len - 10,
2042                                                                ch_mac_addr,
2043                                                                ETH_ALEN);
2044                                 skb->cb[0] = 0xff;
2045                         }
2046
2047                         /* bump the reference count to avoid freeing of the
2048                          * skb once the DMA has completed.
2049                          */
2050                         skb = skb_get(skb);
2051                         t1_sge_tx(skb, adapter, 0, adapter->port[0].dev);
2052                 }
2053         }
2054         mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
2055 }
2056
2057 /*
2058  * Creates a t1_sge structure and returns suggested resource parameters.
2059  */
2060 struct sge *t1_sge_create(struct adapter *adapter, struct sge_params *p)
2061 {
2062         struct sge *sge = kzalloc(sizeof(*sge), GFP_KERNEL);
2063         int i;
2064
2065         if (!sge)
2066                 return NULL;
2067
2068         sge->adapter = adapter;
2069         sge->netdev = adapter->port[0].dev;
2070         sge->rx_pkt_pad = t1_is_T1B(adapter) ? 0 : 2;
2071         sge->jumbo_fl = t1_is_T1B(adapter) ? 1 : 0;
2072
2073         for_each_port(adapter, i) {
2074                 sge->port_stats[i] = alloc_percpu(struct sge_port_stats);
2075                 if (!sge->port_stats[i])
2076                         goto nomem_port;
2077         }
2078
2079         init_timer(&sge->tx_reclaim_timer);
2080         sge->tx_reclaim_timer.data = (unsigned long)sge;
2081         sge->tx_reclaim_timer.function = sge_tx_reclaim_cb;
2082
2083         if (is_T2(sge->adapter)) {
2084                 init_timer(&sge->espibug_timer);
2085
2086                 if (adapter->params.nports > 1) {
2087                         tx_sched_init(sge);
2088                         sge->espibug_timer.function = espibug_workaround_t204;
2089                 } else
2090                         sge->espibug_timer.function = espibug_workaround;
2091                 sge->espibug_timer.data = (unsigned long)sge->adapter;
2092
2093                 sge->espibug_timeout = 1;
2094                 /* for T204, every 10ms */
2095                 if (adapter->params.nports > 1)
2096                         sge->espibug_timeout = HZ/100;
2097         }
2098
2099
2100         p->cmdQ_size[0] = SGE_CMDQ0_E_N;
2101         p->cmdQ_size[1] = SGE_CMDQ1_E_N;
2102         p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE;
2103         p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE;
2104         if (sge->tx_sched) {
2105                 if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204)
2106                         p->rx_coalesce_usecs = 15;
2107                 else
2108                         p->rx_coalesce_usecs = 50;
2109         } else
2110                 p->rx_coalesce_usecs = 50;
2111
2112         p->coalesce_enable = 0;
2113         p->sample_interval_usecs = 0;
2114
2115         return sge;
2116 nomem_port:
2117         while (i >= 0) {
2118                 free_percpu(sge->port_stats[i]);
2119                 --i;
2120         }
2121         kfree(sge);
2122         return NULL;
2123
2124 }