drivers/net/ethernet/brocade/bna/bna_types.h

   1 /*
   2  * Linux network driver for QLogic BR-series Converged Network Adapter.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License (GPL) Version 2 as
   6  * published by the Free Software Foundation
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  */
  13 /*
  14  * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
  15  * Copyright (c) 2014-2015 QLogic Corporation
  16  * All rights reserved
  17  * www.qlogic.com
  18  */
  19 #ifndef __BNA_TYPES_H__
  20 #define __BNA_TYPES_H__
  21
  22 #include "cna.h"
  23 #include "bna_hw_defs.h"
  24 #include "bfa_cee.h"
  25 #include "bfa_msgq.h"
  26
  27 /* Forward declarations */
  28
  29 struct bna_mcam_handle;
  30 struct bna_txq;
  31 struct bna_tx;
  32 struct bna_rxq;
  33 struct bna_cq;
  34 struct bna_rx;
  35 struct bna_rxf;
  36 struct bna_enet;
  37 struct bna;
  38 struct bnad;
  39
  40 /* Enums, primitive data types */
  41
  42 enum bna_status {
  43         BNA_STATUS_T_DISABLED   = 0,
  44         BNA_STATUS_T_ENABLED    = 1
  45 };
  46
  47 enum bna_cleanup_type {
  48         BNA_HARD_CLEANUP        = 0,
  49         BNA_SOFT_CLEANUP        = 1
  50 };
  51
  52 enum bna_cb_status {
  53         BNA_CB_SUCCESS          = 0,
  54         BNA_CB_FAIL             = 1,
  55         BNA_CB_INTERRUPT        = 2,
  56         BNA_CB_BUSY             = 3,
  57         BNA_CB_INVALID_MAC      = 4,
  58         BNA_CB_MCAST_LIST_FULL  = 5,
  59         BNA_CB_UCAST_CAM_FULL   = 6,
  60         BNA_CB_WAITING          = 7,
  61         BNA_CB_NOT_EXEC         = 8
  62 };
  63
  64 enum bna_res_type {
  65         BNA_RES_T_MEM           = 1,
  66         BNA_RES_T_INTR          = 2
  67 };
  68
  69 enum bna_mem_type {
  70         BNA_MEM_T_KVA           = 1,
  71         BNA_MEM_T_DMA           = 2
  72 };
  73
  74 enum bna_intr_type {
  75         BNA_INTR_T_INTX         = 1,
  76         BNA_INTR_T_MSIX         = 2
  77 };
  78
  79 enum bna_res_req_type {
  80         BNA_RES_MEM_T_COM               = 0,
  81         BNA_RES_MEM_T_ATTR              = 1,
  82         BNA_RES_MEM_T_FWTRC             = 2,
  83         BNA_RES_MEM_T_STATS             = 3,
  84         BNA_RES_T_MAX
  85 };
  86
  87 enum bna_mod_res_req_type {
  88         BNA_MOD_RES_MEM_T_TX_ARRAY      = 0,
  89         BNA_MOD_RES_MEM_T_TXQ_ARRAY     = 1,
  90         BNA_MOD_RES_MEM_T_RX_ARRAY      = 2,
  91         BNA_MOD_RES_MEM_T_RXP_ARRAY     = 3,
  92         BNA_MOD_RES_MEM_T_RXQ_ARRAY     = 4,
  93         BNA_MOD_RES_MEM_T_UCMAC_ARRAY   = 5,
  94         BNA_MOD_RES_MEM_T_MCMAC_ARRAY   = 6,
  95         BNA_MOD_RES_MEM_T_MCHANDLE_ARRAY = 7,
  96         BNA_MOD_RES_T_MAX
  97 };
  98
  99 enum bna_tx_res_req_type {
 100         BNA_TX_RES_MEM_T_TCB    = 0,
 101         BNA_TX_RES_MEM_T_UNMAPQ = 1,
 102         BNA_TX_RES_MEM_T_QPT    = 2,
 103         BNA_TX_RES_MEM_T_SWQPT  = 3,
 104         BNA_TX_RES_MEM_T_PAGE   = 4,
 105         BNA_TX_RES_MEM_T_IBIDX  = 5,
 106         BNA_TX_RES_INTR_T_TXCMPL = 6,
 107         BNA_TX_RES_T_MAX,
 108 };
 109
 110 enum bna_rx_mem_type {
 111         BNA_RX_RES_MEM_T_CCB            = 0,    /* CQ context */
 112         BNA_RX_RES_MEM_T_RCB            = 1,    /* CQ context */
 113         BNA_RX_RES_MEM_T_UNMAPHQ        = 2,
 114         BNA_RX_RES_MEM_T_UNMAPDQ        = 3,
 115         BNA_RX_RES_MEM_T_CQPT           = 4,
 116         BNA_RX_RES_MEM_T_CSWQPT         = 5,
 117         BNA_RX_RES_MEM_T_CQPT_PAGE      = 6,
 118         BNA_RX_RES_MEM_T_HQPT           = 7,
 119         BNA_RX_RES_MEM_T_DQPT           = 8,
 120         BNA_RX_RES_MEM_T_HSWQPT         = 9,
 121         BNA_RX_RES_MEM_T_DSWQPT         = 10,
 122         BNA_RX_RES_MEM_T_DPAGE          = 11,
 123         BNA_RX_RES_MEM_T_HPAGE          = 12,
 124         BNA_RX_RES_MEM_T_IBIDX          = 13,
 125         BNA_RX_RES_MEM_T_RIT            = 14,
 126         BNA_RX_RES_T_INTR               = 15,
 127         BNA_RX_RES_T_MAX                = 16
 128 };
 129
 130 enum bna_tx_type {
 131         BNA_TX_T_REGULAR        = 0,
 132         BNA_TX_T_LOOPBACK       = 1,
 133 };
 134
 135 enum bna_tx_flags {
 136         BNA_TX_F_ENET_STARTED   = 1,
 137         BNA_TX_F_ENABLED        = 2,
 138         BNA_TX_F_BW_UPDATED     = 8,
 139 };
 140
 141 enum bna_tx_mod_flags {
 142         BNA_TX_MOD_F_ENET_STARTED       = 1,
 143         BNA_TX_MOD_F_ENET_LOOPBACK      = 2,
 144 };
 145
 146 enum bna_rx_type {
 147         BNA_RX_T_REGULAR        = 0,
 148         BNA_RX_T_LOOPBACK       = 1,
 149 };
 150
 151 enum bna_rxp_type {
 152         BNA_RXP_SINGLE          = 1,
 153         BNA_RXP_SLR             = 2,
 154         BNA_RXP_HDS             = 3
 155 };
 156
 157 enum bna_rxmode {
 158         BNA_RXMODE_PROMISC      = 1,
 159         BNA_RXMODE_DEFAULT      = 2,
 160         BNA_RXMODE_ALLMULTI     = 4
 161 };
 162
 163 enum bna_rx_event {
 164         RX_E_START                      = 1,
 165         RX_E_STOP                       = 2,
 166         RX_E_FAIL                       = 3,
 167         RX_E_STARTED                    = 4,
 168         RX_E_STOPPED                    = 5,
 169         RX_E_RXF_STARTED                = 6,
 170         RX_E_RXF_STOPPED                = 7,
 171         RX_E_CLEANUP_DONE               = 8,
 172 };
 173
 174 enum bna_rx_flags {
 175         BNA_RX_F_ENET_STARTED   = 1,
 176         BNA_RX_F_ENABLED        = 2,
 177 };
 178
 179 enum bna_rx_mod_flags {
 180         BNA_RX_MOD_F_ENET_STARTED       = 1,
 181         BNA_RX_MOD_F_ENET_LOOPBACK      = 2,
 182 };
 183
 184 enum bna_rxf_event {
 185         RXF_E_START                     = 1,
 186         RXF_E_STOP                      = 2,
 187         RXF_E_FAIL                      = 3,
 188         RXF_E_CONFIG                    = 4,
 189         RXF_E_FW_RESP                   = 7,
 190 };
 191
 192 enum bna_enet_type {
 193         BNA_ENET_T_REGULAR              = 0,
 194         BNA_ENET_T_LOOPBACK_INTERNAL    = 1,
 195         BNA_ENET_T_LOOPBACK_EXTERNAL    = 2,
 196 };
 197
 198 enum bna_link_status {
 199         BNA_LINK_DOWN           = 0,
 200         BNA_LINK_UP             = 1,
 201         BNA_CEE_UP              = 2
 202 };
 203
 204 enum bna_ethport_flags {
 205         BNA_ETHPORT_F_ADMIN_UP          = 1,
 206         BNA_ETHPORT_F_PORT_ENABLED      = 2,
 207         BNA_ETHPORT_F_RX_STARTED        = 4,
 208 };
 209
 210 enum bna_enet_flags {
 211         BNA_ENET_F_IOCETH_READY         = 1,
 212         BNA_ENET_F_ENABLED              = 2,
 213         BNA_ENET_F_PAUSE_CHANGED        = 4,
 214         BNA_ENET_F_MTU_CHANGED          = 8
 215 };
 216
 217 enum bna_rss_flags {
 218         BNA_RSS_F_RIT_PENDING           = 1,
 219         BNA_RSS_F_CFG_PENDING           = 2,
 220         BNA_RSS_F_STATUS_PENDING        = 4,
 221 };
 222
 223 enum bna_mod_flags {
 224         BNA_MOD_F_INIT_DONE             = 1,
 225 };
 226
 227 enum bna_pkt_rates {
 228         BNA_PKT_RATE_10K                = 10000,
 229         BNA_PKT_RATE_20K                = 20000,
 230         BNA_PKT_RATE_30K                = 30000,
 231         BNA_PKT_RATE_40K                = 40000,
 232         BNA_PKT_RATE_50K                = 50000,
 233         BNA_PKT_RATE_60K                = 60000,
 234         BNA_PKT_RATE_70K                = 70000,
 235         BNA_PKT_RATE_80K                = 80000,
 236 };
 237
 238 enum bna_dim_load_types {
 239         BNA_LOAD_T_HIGH_4               = 0, /* 80K <= r */
 240         BNA_LOAD_T_HIGH_3               = 1, /* 60K <= r < 80K */
 241         BNA_LOAD_T_HIGH_2               = 2, /* 50K <= r < 60K */
 242         BNA_LOAD_T_HIGH_1               = 3, /* 40K <= r < 50K */
 243         BNA_LOAD_T_LOW_1                = 4, /* 30K <= r < 40K */
 244         BNA_LOAD_T_LOW_2                = 5, /* 20K <= r < 30K */
 245         BNA_LOAD_T_LOW_3                = 6, /* 10K <= r < 20K */
 246         BNA_LOAD_T_LOW_4                = 7, /* r < 10K */
 247         BNA_LOAD_T_MAX                  = 8
 248 };
 249
 250 enum bna_dim_bias_types {
 251         BNA_BIAS_T_SMALL                = 0, /* small pkts > (large pkts * 2) */
 252         BNA_BIAS_T_LARGE                = 1, /* Not BNA_BIAS_T_SMALL */
 253         BNA_BIAS_T_MAX                  = 2
 254 };
 255
 256 #define BNA_MAX_NAME_SIZE       64
 257 struct bna_ident {
 258         int                     id;
 259         char                    name[BNA_MAX_NAME_SIZE];
 260 };
 261
 262 struct bna_mac {
 263         /* This should be the first one */
 264         struct list_head                        qe;
 265         u8                      addr[ETH_ALEN];
 266         struct bna_mcam_handle *handle;
 267 };
 268
 269 struct bna_mem_descr {
 270         u32             len;
 271         void            *kva;
 272         struct bna_dma_addr dma;
 273 };
 274
 275 struct bna_mem_info {
 276         enum bna_mem_type mem_type;
 277         u32             len;
 278         u32             num;
 279         u32             align_sz; /* 0/1 = no alignment */
 280         struct bna_mem_descr *mdl;
 281         void                    *cookie; /* For bnad to unmap dma later */
 282 };
 283
 284 struct bna_intr_descr {
 285         int                     vector;
 286 };
 287
 288 struct bna_intr_info {
 289         enum bna_intr_type intr_type;
 290         int                     num;
 291         struct bna_intr_descr *idl;
 292 };
 293
 294 union bna_res_u {
 295         struct bna_mem_info mem_info;
 296         struct bna_intr_info intr_info;
 297 };
 298
 299 struct bna_res_info {
 300         enum bna_res_type res_type;
 301         union bna_res_u         res_u;
 302 };
 303
 304 /* HW QPT */
 305 struct bna_qpt {
 306         struct bna_dma_addr hw_qpt_ptr;
 307         void            *kv_qpt_ptr;
 308         u32             page_count;
 309         u32             page_size;
 310 };
 311
 312 struct bna_attr {
 313         bool                    fw_query_complete;
 314         int                     num_txq;
 315         int                     num_rxp;
 316         int                     num_ucmac;
 317         int                     num_mcmac;
 318         int                     max_rit_size;
 319 };
 320
 321 /* IOCEth */
 322
 323 struct bna_ioceth {
 324         bfa_fsm_t               fsm;
 325         struct bfa_ioc ioc;
 326
 327         struct bna_attr attr;
 328         struct bfa_msgq_cmd_entry msgq_cmd;
 329         struct bfi_enet_attr_req attr_req;
 330
 331         void (*stop_cbfn)(struct bnad *bnad);
 332         struct bnad *stop_cbarg;
 333
 334         struct bna *bna;
 335 };
 336
 337 /* Enet */
 338
 339 /* Pause configuration */
 340 struct bna_pause_config {
 341         enum bna_status tx_pause;
 342         enum bna_status rx_pause;
 343 };
 344
 345 struct bna_enet {
 346         bfa_fsm_t               fsm;
 347         enum bna_enet_flags flags;
 348
 349         enum bna_enet_type type;
 350
 351         struct bna_pause_config pause_config;
 352         int                     mtu;
 353
 354         /* Callback for bna_enet_disable(), enet_stop() */
 355         void (*stop_cbfn)(void *);
 356         void                    *stop_cbarg;
 357
 358         /* Callback for bna_enet_mtu_set() */
 359         void (*mtu_cbfn)(struct bnad *);
 360
 361         struct bfa_wc           chld_stop_wc;
 362
 363         struct bfa_msgq_cmd_entry msgq_cmd;
 364         struct bfi_enet_set_pause_req pause_req;
 365
 366         struct bna *bna;
 367 };
 368
 369 /* Ethport */
 370
 371 struct bna_ethport {
 372         bfa_fsm_t               fsm;
 373         enum bna_ethport_flags flags;
 374
 375         enum bna_link_status link_status;
 376
 377         int                     rx_started_count;
 378
 379         void (*stop_cbfn)(struct bna_enet *);
 380
 381         void (*adminup_cbfn)(struct bnad *, enum bna_cb_status);
 382
 383         void (*link_cbfn)(struct bnad *, enum bna_link_status);
 384
 385         struct bfa_msgq_cmd_entry msgq_cmd;
 386         union {
 387                 struct bfi_enet_enable_req admin_req;
 388                 struct bfi_enet_diag_lb_req lpbk_req;
 389         } bfi_enet_cmd;
 390
 391         struct bna *bna;
 392 };
 393
 394 /* Interrupt Block */
 395
 396 /* Doorbell structure */
 397 struct bna_ib_dbell {
 398         void __iomem   *doorbell_addr;
 399         u32             doorbell_ack;
 400 };
 401
 402 /* IB structure */
 403 struct bna_ib {
 404         struct bna_dma_addr ib_seg_host_addr;
 405         void            *ib_seg_host_addr_kva;
 406
 407         struct bna_ib_dbell door_bell;
 408
 409         enum bna_intr_type      intr_type;
 410         int                     intr_vector;
 411
 412         u8                      coalescing_timeo;    /* Unit is 5usec. */
 413
 414         int                     interpkt_count;
 415         int                     interpkt_timeo;
 416 };
 417
 418 /* Tx object */
 419
 420 /* Tx datapath control structure */
 421 #define BNA_Q_NAME_SIZE         16
 422 struct bna_tcb {
 423         /* Fast path */
 424         void                    **sw_qpt;
 425         void                    *sw_q;
 426         void                    *unmap_q;
 427         u32             producer_index;
 428         u32             consumer_index;
 429         volatile u32    *hw_consumer_index;
 430         u32             q_depth;
 431         void __iomem   *q_dbell;
 432         struct bna_ib_dbell *i_dbell;
 433         /* Control path */
 434         struct bna_txq *txq;
 435         struct bnad *bnad;
 436         void                    *priv; /* BNAD's cookie */
 437         enum bna_intr_type intr_type;
 438         int                     intr_vector;
 439         u8                      priority; /* Current priority */
 440         unsigned long           flags; /* Used by bnad as required */
 441         int                     id;
 442         char                    name[BNA_Q_NAME_SIZE];
 443 };
 444
 445 /* TxQ QPT and configuration */
 446 struct bna_txq {
 447         /* This should be the first one */
 448         struct list_head                        qe;
 449
 450         u8                      priority;
 451
 452         struct bna_qpt qpt;
 453         struct bna_tcb *tcb;
 454         struct bna_ib ib;
 455
 456         struct bna_tx *tx;
 457
 458         int                     hw_id;
 459
 460         u64             tx_packets;
 461         u64             tx_bytes;
 462 };
 463
 464 /* Tx object */
 465 struct bna_tx {
 466         /* This should be the first one */
 467         struct list_head                        qe;
 468         int                     rid;
 469         int                     hw_id;
 470
 471         bfa_fsm_t               fsm;
 472         enum bna_tx_flags flags;
 473
 474         enum bna_tx_type type;
 475         int                     num_txq;
 476
 477         struct list_head                        txq_q;
 478         u16                     txf_vlan_id;
 479
 480         /* Tx event handlers */
 481         void (*tcb_setup_cbfn)(struct bnad *, struct bna_tcb *);
 482         void (*tcb_destroy_cbfn)(struct bnad *, struct bna_tcb *);
 483         void (*tx_stall_cbfn)(struct bnad *, struct bna_tx *);
 484         void (*tx_resume_cbfn)(struct bnad *, struct bna_tx *);
 485         void (*tx_cleanup_cbfn)(struct bnad *, struct bna_tx *);
 486
 487         /* callback for bna_tx_disable(), bna_tx_stop() */
 488         void (*stop_cbfn)(void *arg, struct bna_tx *tx);
 489         void                    *stop_cbarg;
 490
 491         struct bfa_msgq_cmd_entry msgq_cmd;
 492         union {
 493                 struct bfi_enet_tx_cfg_req      cfg_req;
 494                 struct bfi_enet_req             req;
 495                 struct bfi_enet_tx_cfg_rsp      cfg_rsp;
 496         } bfi_enet_cmd;
 497
 498         struct bna *bna;
 499         void                    *priv;  /* bnad's cookie */
 500 };
 501
 502 /* Tx object configuration used during creation */
 503 struct bna_tx_config {
 504         int                     num_txq;
 505         int                     txq_depth;
 506         int                     coalescing_timeo;
 507         enum bna_tx_type tx_type;
 508 };
 509
 510 struct bna_tx_event_cbfn {
 511         /* Optional */
 512         void (*tcb_setup_cbfn)(struct bnad *, struct bna_tcb *);
 513         void (*tcb_destroy_cbfn)(struct bnad *, struct bna_tcb *);
 514         /* Mandatory */
 515         void (*tx_stall_cbfn)(struct bnad *, struct bna_tx *);
 516         void (*tx_resume_cbfn)(struct bnad *, struct bna_tx *);
 517         void (*tx_cleanup_cbfn)(struct bnad *, struct bna_tx *);
 518 };
 519
 520 /* Tx module - keeps track of free, active tx objects */
 521 struct bna_tx_mod {
 522         struct bna_tx *tx;              /* BFI_MAX_TXQ entries */
 523         struct bna_txq *txq;            /* BFI_MAX_TXQ entries */
 524
 525         struct list_head                        tx_free_q;
 526         struct list_head                        tx_active_q;
 527
 528         struct list_head                        txq_free_q;
 529
 530         /* callback for bna_tx_mod_stop() */
 531         void (*stop_cbfn)(struct bna_enet *enet);
 532
 533         struct bfa_wc           tx_stop_wc;
 534
 535         enum bna_tx_mod_flags flags;
 536
 537         u8                      prio_map;
 538         int                     default_prio;
 539         int                     iscsi_over_cee;
 540         int                     iscsi_prio;
 541         int                     prio_reconfigured;
 542
 543         u32                     rid_mask;
 544
 545         struct bna *bna;
 546 };
 547
 548 /* Rx object */
 549
 550 /* Rx datapath control structure */
 551 struct bna_rcb {
 552         /* Fast path */
 553         void                    **sw_qpt;
 554         void                    *sw_q;
 555         void                    *unmap_q;
 556         u32             producer_index;
 557         u32             consumer_index;
 558         u32             q_depth;
 559         void __iomem   *q_dbell;
 560         /* Control path */
 561         struct bna_rxq *rxq;
 562         struct bna_ccb *ccb;
 563         struct bnad *bnad;
 564         void                    *priv; /* BNAD's cookie */
 565         unsigned long           flags;
 566         int                     id;
 567 };
 568
 569 /* RxQ structure - QPT, configuration */
 570 struct bna_rxq {
 571         struct list_head                        qe;
 572
 573         int                     buffer_size;
 574         int                     q_depth;
 575         u32                     num_vecs;
 576         enum bna_status         multi_buffer;
 577
 578         struct bna_qpt qpt;
 579         struct bna_rcb *rcb;
 580
 581         struct bna_rxp *rxp;
 582         struct bna_rx *rx;
 583
 584         int                     hw_id;
 585
 586         u64             rx_packets;
 587         u64             rx_bytes;
 588         u64             rx_packets_with_error;
 589         u64             rxbuf_alloc_failed;
 590         u64             rxbuf_map_failed;
 591 };
 592
 593 /* RxQ pair */
 594 union bna_rxq_u {
 595         struct {
 596                 struct bna_rxq *hdr;
 597                 struct bna_rxq *data;
 598         } hds;
 599         struct {
 600                 struct bna_rxq *small;
 601                 struct bna_rxq *large;
 602         } slr;
 603         struct {
 604                 struct bna_rxq *only;
 605                 struct bna_rxq *reserved;
 606         } single;
 607 };
 608
 609 /* Packet rate for Dynamic Interrupt Moderation */
 610 struct bna_pkt_rate {
 611         u32             small_pkt_cnt;
 612         u32             large_pkt_cnt;
 613 };
 614
 615 /* Completion control structure */
 616 struct bna_ccb {
 617         /* Fast path */
 618         void                    **sw_qpt;
 619         void                    *sw_q;
 620         u32             producer_index;
 621         volatile u32    *hw_producer_index;
 622         u32             q_depth;
 623         struct bna_ib_dbell *i_dbell;
 624         struct bna_rcb *rcb[2];
 625         void                    *ctrl; /* For bnad */
 626         struct bna_pkt_rate pkt_rate;
 627         u32                     pkts_una;
 628         u32                     bytes_per_intr;
 629
 630         /* Control path */
 631         struct bna_cq *cq;
 632         struct bnad *bnad;
 633         void                    *priv; /* BNAD's cookie */
 634         enum bna_intr_type intr_type;
 635         int                     intr_vector;
 636         u8                      rx_coalescing_timeo; /* For NAPI */
 637         int                     id;
 638         char                    name[BNA_Q_NAME_SIZE];
 639 };
 640
 641 /* CQ QPT, configuration  */
 642 struct bna_cq {
 643         struct bna_qpt qpt;
 644         struct bna_ccb *ccb;
 645
 646         struct bna_ib ib;
 647
 648         struct bna_rx *rx;
 649 };
 650
 651 struct bna_rss_config {
 652         enum bfi_enet_rss_type  hash_type;
 653         u8                      hash_mask;
 654         u32             toeplitz_hash_key[BFI_ENET_RSS_KEY_LEN];
 655 };
 656
 657 struct bna_hds_config {
 658         enum bfi_enet_hds_type  hdr_type;
 659         int                     forced_offset;
 660 };
 661
 662 /* Rx object configuration used during creation */
 663 struct bna_rx_config {
 664         enum bna_rx_type rx_type;
 665         int                     num_paths;
 666         enum bna_rxp_type rxp_type;
 667         int                     coalescing_timeo;
 668         /*
 669          * Small/Large (or Header/Data) buffer size to be configured
 670          * for SLR and HDS queue type.
 671          */
 672         u32                     frame_size;
 673
 674         /* header or small queue */
 675         u32                     q1_depth;
 676         u32                     q1_buf_size;
 677
 678         /* data or large queue */
 679         u32                     q0_depth;
 680         u32                     q0_buf_size;
 681         u32                     q0_num_vecs;
 682         enum bna_status         q0_multi_buf;
 683
 684         enum bna_status rss_status;
 685         struct bna_rss_config rss_config;
 686
 687         struct bna_hds_config hds_config;
 688
 689         enum bna_status vlan_strip_status;
 690 };
 691
 692 /* Rx Path structure - one per MSIX vector/CPU */
 693 struct bna_rxp {
 694         /* This should be the first one */
 695         struct list_head                        qe;
 696
 697         enum bna_rxp_type type;
 698         union   bna_rxq_u       rxq;
 699         struct bna_cq cq;
 700
 701         struct bna_rx *rx;
 702
 703         /* MSI-x vector number for configuring RSS */
 704         int                     vector;
 705         int                     hw_id;
 706 };
 707
 708 /* RxF structure (hardware Rx Function) */
 709 struct bna_rxf {
 710         bfa_fsm_t               fsm;
 711
 712         struct bfa_msgq_cmd_entry msgq_cmd;
 713         union {
 714                 struct bfi_enet_enable_req req;
 715                 struct bfi_enet_rss_cfg_req rss_req;
 716                 struct bfi_enet_rit_req rit_req;
 717                 struct bfi_enet_rx_vlan_req vlan_req;
 718                 struct bfi_enet_mcast_add_req mcast_add_req;
 719                 struct bfi_enet_mcast_del_req mcast_del_req;
 720                 struct bfi_enet_ucast_req ucast_req;
 721         } bfi_enet_cmd;
 722
 723         /* callback for bna_rxf_start() */
 724         void (*start_cbfn) (struct bna_rx *rx);
 725         struct bna_rx *start_cbarg;
 726
 727         /* callback for bna_rxf_stop() */
 728         void (*stop_cbfn) (struct bna_rx *rx);
 729         struct bna_rx *stop_cbarg;
 730
 731         /**
 732          * callback for:
 733          *      bna_rxf_ucast_set()
 734          *      bna_rxf_{ucast/mcast}_add(),
 735          *      bna_rxf_{ucast/mcast}_del(),
 736          *      bna_rxf_mode_set()
 737          */
 738         void (*cam_fltr_cbfn)(struct bnad *bnad, struct bna_rx *rx);
 739         struct bnad *cam_fltr_cbarg;
 740
 741         /* List of unicast addresses yet to be applied to h/w */
 742         struct list_head                        ucast_pending_add_q;
 743         struct list_head                        ucast_pending_del_q;
 744         struct bna_mac *ucast_pending_mac;
 745         int                     ucast_pending_set;
 746         /* ucast addresses applied to the h/w */
 747         struct list_head                        ucast_active_q;
 748         struct bna_mac ucast_active_mac;
 749         int                     ucast_active_set;
 750
 751         /* List of multicast addresses yet to be applied to h/w */
 752         struct list_head                        mcast_pending_add_q;
 753         struct list_head                        mcast_pending_del_q;
 754         /* multicast addresses applied to the h/w */
 755         struct list_head                        mcast_active_q;
 756         struct list_head                        mcast_handle_q;
 757
 758         /* Rx modes yet to be applied to h/w */
 759         enum bna_rxmode rxmode_pending;
 760         enum bna_rxmode rxmode_pending_bitmask;
 761         /* Rx modes applied to h/w */
 762         enum bna_rxmode rxmode_active;
 763
 764         u8                      vlan_pending_bitmask;
 765         enum bna_status vlan_filter_status;
 766         u32     vlan_filter_table[(BFI_ENET_VLAN_ID_MAX) / 32];
 767         bool                    vlan_strip_pending;
 768         enum bna_status         vlan_strip_status;
 769
 770         enum bna_rss_flags      rss_pending;
 771         enum bna_status         rss_status;
 772         struct bna_rss_config   rss_cfg;
 773         u8                      *rit;
 774         int                     rit_size;
 775
 776         struct bna_rx           *rx;
 777 };
 778
 779 /* Rx object */
 780 struct bna_rx {
 781         /* This should be the first one */
 782         struct list_head                        qe;
 783         int                     rid;
 784         int                     hw_id;
 785
 786         bfa_fsm_t               fsm;
 787
 788         enum bna_rx_type type;
 789
 790         int                     num_paths;
 791         struct list_head                        rxp_q;
 792
 793         struct bna_hds_config   hds_cfg;
 794
 795         struct bna_rxf rxf;
 796
 797         enum bna_rx_flags rx_flags;
 798
 799         struct bfa_msgq_cmd_entry msgq_cmd;
 800         union {
 801                 struct bfi_enet_rx_cfg_req      cfg_req;
 802                 struct bfi_enet_req             req;
 803                 struct bfi_enet_rx_cfg_rsp      cfg_rsp;
 804         } bfi_enet_cmd;
 805
 806         /* Rx event handlers */
 807         void (*rcb_setup_cbfn)(struct bnad *, struct bna_rcb *);
 808         void (*rcb_destroy_cbfn)(struct bnad *, struct bna_rcb *);
 809         void (*ccb_setup_cbfn)(struct bnad *, struct bna_ccb *);
 810         void (*ccb_destroy_cbfn)(struct bnad *, struct bna_ccb *);
 811         void (*rx_stall_cbfn)(struct bnad *, struct bna_rx *);
 812         void (*rx_cleanup_cbfn)(struct bnad *, struct bna_rx *);
 813         void (*rx_post_cbfn)(struct bnad *, struct bna_rx *);
 814
 815         /* callback for bna_rx_disable(), bna_rx_stop() */
 816         void (*stop_cbfn)(void *arg, struct bna_rx *rx);
 817         void                    *stop_cbarg;
 818
 819         struct bna *bna;
 820         void                    *priv; /* bnad's cookie */
 821 };
 822
 823 struct bna_rx_event_cbfn {
 824         /* Optional */
 825         void (*rcb_setup_cbfn)(struct bnad *, struct bna_rcb *);
 826         void (*rcb_destroy_cbfn)(struct bnad *, struct bna_rcb *);
 827         void (*ccb_setup_cbfn)(struct bnad *, struct bna_ccb *);
 828         void (*ccb_destroy_cbfn)(struct bnad *, struct bna_ccb *);
 829         void (*rx_stall_cbfn)(struct bnad *, struct bna_rx *);
 830         /* Mandatory */
 831         void (*rx_cleanup_cbfn)(struct bnad *, struct bna_rx *);
 832         void (*rx_post_cbfn)(struct bnad *, struct bna_rx *);
 833 };
 834
 835 /* Rx module - keeps track of free, active rx objects */
 836 struct bna_rx_mod {
 837         struct bna *bna;                /* back pointer to parent */
 838         struct bna_rx *rx;              /* BFI_MAX_RXQ entries */
 839         struct bna_rxp *rxp;            /* BFI_MAX_RXQ entries */
 840         struct bna_rxq *rxq;            /* BFI_MAX_RXQ entries */
 841
 842         struct list_head                        rx_free_q;
 843         struct list_head                        rx_active_q;
 844         int                     rx_free_count;
 845
 846         struct list_head                        rxp_free_q;
 847         int                     rxp_free_count;
 848
 849         struct list_head                        rxq_free_q;
 850         int                     rxq_free_count;
 851
 852         enum bna_rx_mod_flags flags;
 853
 854         /* callback for bna_rx_mod_stop() */
 855         void (*stop_cbfn)(struct bna_enet *enet);
 856
 857         struct bfa_wc           rx_stop_wc;
 858         u32             dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX];
 859         u32             rid_mask;
 860 };
 861
 862 /* CAM */
 863
 864 struct bna_ucam_mod {
 865         struct bna_mac *ucmac;          /* num_ucmac * 2 entries */
 866         struct list_head                        free_q;
 867         struct list_head                        del_q;
 868
 869         struct bna *bna;
 870 };
 871
 872 struct bna_mcam_handle {
 873         /* This should be the first one */
 874         struct list_head                        qe;
 875         int                     handle;
 876         int                     refcnt;
 877 };
 878
 879 struct bna_mcam_mod {
 880         struct bna_mac *mcmac;          /* num_mcmac * 2 entries */
 881         struct bna_mcam_handle *mchandle;       /* num_mcmac entries */
 882         struct list_head                        free_q;
 883         struct list_head                        del_q;
 884         struct list_head                        free_handle_q;
 885
 886         struct bna *bna;
 887 };
 888
 889 /* Statistics */
 890
 891 struct bna_stats {
 892         struct bna_dma_addr     hw_stats_dma;
 893         struct bfi_enet_stats   *hw_stats_kva;
 894         struct bfi_enet_stats   hw_stats;
 895 };
 896
 897 struct bna_stats_mod {
 898         bool            ioc_ready;
 899         bool            stats_get_busy;
 900         bool            stats_clr_busy;
 901         struct bfa_msgq_cmd_entry stats_get_cmd;
 902         struct bfa_msgq_cmd_entry stats_clr_cmd;
 903         struct bfi_enet_stats_req stats_get;
 904         struct bfi_enet_stats_req stats_clr;
 905 };
 906
 907 /* BNA */
 908
 909 struct bna {
 910         struct bna_ident ident;
 911         struct bfa_pcidev pcidev;
 912
 913         struct bna_reg regs;
 914         struct bna_bit_defn bits;
 915
 916         struct bna_stats stats;
 917
 918         struct bna_ioceth ioceth;
 919         struct bfa_cee cee;
 920         struct bfa_flash flash;
 921         struct bfa_msgq msgq;
 922
 923         struct bna_ethport ethport;
 924         struct bna_enet enet;
 925         struct bna_stats_mod stats_mod;
 926
 927         struct bna_tx_mod tx_mod;
 928         struct bna_rx_mod rx_mod;
 929         struct bna_ucam_mod ucam_mod;
 930         struct bna_mcam_mod mcam_mod;
 931
 932         enum bna_mod_flags mod_flags;
 933
 934         int                     default_mode_rid;
 935         int                     promisc_rid;
 936
 937         struct bnad *bnad;
 938 };
 939 #endif  /* __BNA_TYPES_H__ */