2 * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation
3 * Copyright (c) 2006, 2007 Maciej W. Rozycki
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 * This driver is designed for the Broadcom SiByte SOC built-in
20 * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
22 * Updated to the driver model and the PHY abstraction layer
23 * by Maciej W. Rozycki.
26 #include <linux/bug.h>
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/string.h>
30 #include <linux/timer.h>
31 #include <linux/errno.h>
32 #include <linux/ioport.h>
33 #include <linux/slab.h>
34 #include <linux/interrupt.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/init.h>
39 #include <linux/bitops.h>
40 #include <linux/err.h>
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/phy.h>
44 #include <linux/platform_device.h>
45 #include <linux/prefetch.h>
47 #include <asm/cache.h>
49 #include <asm/processor.h> /* Processor type for cache alignment. */
51 /* Operational parameters that usually are not changed. */
53 #define CONFIG_SBMAC_COALESCE
55 /* Time in jiffies before concluding the transmitter is hung. */
56 #define TX_TIMEOUT (2*HZ)
59 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
60 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
62 /* A few user-configurable values which may be modified when a driver
65 /* 1 normal messages, 0 quiet .. 7 verbose. */
67 module_param(debug, int, S_IRUGO);
68 MODULE_PARM_DESC(debug, "Debug messages");
70 #ifdef CONFIG_SBMAC_COALESCE
71 static int int_pktcnt_tx = 255;
72 module_param(int_pktcnt_tx, int, S_IRUGO);
73 MODULE_PARM_DESC(int_pktcnt_tx, "TX packet count");
75 static int int_timeout_tx = 255;
76 module_param(int_timeout_tx, int, S_IRUGO);
77 MODULE_PARM_DESC(int_timeout_tx, "TX timeout value");
79 static int int_pktcnt_rx = 64;
80 module_param(int_pktcnt_rx, int, S_IRUGO);
81 MODULE_PARM_DESC(int_pktcnt_rx, "RX packet count");
83 static int int_timeout_rx = 64;
84 module_param(int_timeout_rx, int, S_IRUGO);
85 MODULE_PARM_DESC(int_timeout_rx, "RX timeout value");
88 #include <asm/sibyte/board.h>
89 #include <asm/sibyte/sb1250.h>
90 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
91 #include <asm/sibyte/bcm1480_regs.h>
92 #include <asm/sibyte/bcm1480_int.h>
93 #define R_MAC_DMA_OODPKTLOST_RX R_MAC_DMA_OODPKTLOST
94 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
95 #include <asm/sibyte/sb1250_regs.h>
96 #include <asm/sibyte/sb1250_int.h>
98 #error invalid SiByte MAC configuration
100 #include <asm/sibyte/sb1250_scd.h>
101 #include <asm/sibyte/sb1250_mac.h>
102 #include <asm/sibyte/sb1250_dma.h>
104 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
105 #define UNIT_INT(n) (K_BCM1480_INT_MAC_0 + ((n) * 2))
106 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
107 #define UNIT_INT(n) (K_INT_MAC_0 + (n))
109 #error invalid SiByte MAC configuration
113 #define SBMAC_PHY_INT K_INT_PHY
115 #define SBMAC_PHY_INT PHY_POLL
118 /**********************************************************************
120 ********************************************************************* */
123 sbmac_speed_none = 0,
124 sbmac_speed_10 = SPEED_10,
125 sbmac_speed_100 = SPEED_100,
126 sbmac_speed_1000 = SPEED_1000,
130 sbmac_duplex_none = -1,
131 sbmac_duplex_half = DUPLEX_HALF,
132 sbmac_duplex_full = DUPLEX_FULL,
151 /**********************************************************************
153 ********************************************************************* */
156 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
157 (d)->sbdma_dscrtable : (d)->f+1)
160 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
162 #define SBMAC_MAX_TXDESCR 256
163 #define SBMAC_MAX_RXDESCR 256
165 #define ENET_PACKET_SIZE 1518
166 /*#define ENET_PACKET_SIZE 9216 */
168 /**********************************************************************
169 * DMA Descriptor structure
170 ********************************************************************* */
177 /**********************************************************************
178 * DMA Controller structure
179 ********************************************************************* */
184 * This stuff is used to identify the channel and the registers
185 * associated with it.
187 struct sbmac_softc *sbdma_eth; /* back pointer to associated
189 int sbdma_channel; /* channel number */
190 int sbdma_txdir; /* direction (1=transmit) */
191 int sbdma_maxdescr; /* total # of descriptors
193 #ifdef CONFIG_SBMAC_COALESCE
194 int sbdma_int_pktcnt;
195 /* # descriptors rx/tx
197 int sbdma_int_timeout;
198 /* # usec rx/tx interrupt */
200 void __iomem *sbdma_config0; /* DMA config register 0 */
201 void __iomem *sbdma_config1; /* DMA config register 1 */
202 void __iomem *sbdma_dscrbase;
203 /* descriptor base address */
204 void __iomem *sbdma_dscrcnt; /* descriptor count register */
205 void __iomem *sbdma_curdscr; /* current descriptor
207 void __iomem *sbdma_oodpktlost;
208 /* pkt drop (rx only) */
211 * This stuff is for maintenance of the ring
213 void *sbdma_dscrtable_unaligned;
214 struct sbdmadscr *sbdma_dscrtable;
215 /* base of descriptor table */
216 struct sbdmadscr *sbdma_dscrtable_end;
217 /* end of descriptor table */
218 struct sk_buff **sbdma_ctxtable;
219 /* context table, one
221 dma_addr_t sbdma_dscrtable_phys;
222 /* and also the phys addr */
223 struct sbdmadscr *sbdma_addptr; /* next dscr for sw to add */
224 struct sbdmadscr *sbdma_remptr; /* next dscr for sw
229 /**********************************************************************
230 * Ethernet softc structure
231 ********************************************************************* */
236 * Linux-specific things
238 struct net_device *sbm_dev; /* pointer to linux device */
239 struct napi_struct napi;
240 struct phy_device *phy_dev; /* the associated PHY device */
241 struct mii_bus *mii_bus; /* the MII bus */
242 int phy_irq[PHY_MAX_ADDR];
243 spinlock_t sbm_lock; /* spin lock */
244 int sbm_devflags; /* current device flags */
247 * Controller-specific things
249 void __iomem *sbm_base; /* MAC's base address */
250 enum sbmac_state sbm_state; /* current state */
252 void __iomem *sbm_macenable; /* MAC Enable Register */
253 void __iomem *sbm_maccfg; /* MAC Config Register */
254 void __iomem *sbm_fifocfg; /* FIFO Config Register */
255 void __iomem *sbm_framecfg; /* Frame Config Register */
256 void __iomem *sbm_rxfilter; /* Receive Filter Register */
257 void __iomem *sbm_isr; /* Interrupt Status Register */
258 void __iomem *sbm_imr; /* Interrupt Mask Register */
259 void __iomem *sbm_mdio; /* MDIO Register */
261 enum sbmac_speed sbm_speed; /* current speed */
262 enum sbmac_duplex sbm_duplex; /* current duplex */
263 enum sbmac_fc sbm_fc; /* cur. flow control setting */
264 int sbm_pause; /* current pause setting */
265 int sbm_link; /* current link state */
267 unsigned char sbm_hwaddr[ETH_ALEN];
269 struct sbmacdma sbm_txdma; /* only channel 0 for now */
270 struct sbmacdma sbm_rxdma;
276 /**********************************************************************
278 ********************************************************************* */
280 /**********************************************************************
282 ********************************************************************* */
284 static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan,
285 int txrx, int maxdescr);
286 static void sbdma_channel_start(struct sbmacdma *d, int rxtx);
287 static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d,
289 static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *m);
290 static void sbdma_emptyring(struct sbmacdma *d);
291 static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d);
292 static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d,
293 int work_to_do, int poll);
294 static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d,
296 static int sbmac_initctx(struct sbmac_softc *s);
297 static void sbmac_channel_start(struct sbmac_softc *s);
298 static void sbmac_channel_stop(struct sbmac_softc *s);
299 static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *,
301 static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff);
302 static uint64_t sbmac_addr2reg(unsigned char *ptr);
303 static irqreturn_t sbmac_intr(int irq, void *dev_instance);
304 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
305 static void sbmac_setmulti(struct sbmac_softc *sc);
306 static int sbmac_init(struct platform_device *pldev, long long base);
307 static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed);
308 static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
311 static int sbmac_open(struct net_device *dev);
312 static void sbmac_tx_timeout (struct net_device *dev);
313 static void sbmac_set_rx_mode(struct net_device *dev);
314 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
315 static int sbmac_close(struct net_device *dev);
316 static int sbmac_poll(struct napi_struct *napi, int budget);
318 static void sbmac_mii_poll(struct net_device *dev);
319 static int sbmac_mii_probe(struct net_device *dev);
321 static void sbmac_mii_sync(void __iomem *sbm_mdio);
322 static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data,
324 static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx);
325 static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
329 /**********************************************************************
331 ********************************************************************* */
333 static char sbmac_string[] = "sb1250-mac";
335 static char sbmac_mdio_string[] = "sb1250-mac-mdio";
338 /**********************************************************************
340 ********************************************************************* */
342 #define MII_COMMAND_START 0x01
343 #define MII_COMMAND_READ 0x02
344 #define MII_COMMAND_WRITE 0x01
345 #define MII_COMMAND_ACK 0x02
347 #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */
352 /**********************************************************************
353 * SBMAC_MII_SYNC(sbm_mdio)
355 * Synchronize with the MII - send a pattern of bits to the MII
356 * that will guarantee that it is ready to accept a command.
359 * sbm_mdio - address of the MAC's MDIO register
363 ********************************************************************* */
365 static void sbmac_mii_sync(void __iomem *sbm_mdio)
371 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
373 bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
375 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
377 for (cnt = 0; cnt < 32; cnt++) {
378 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio);
379 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
383 /**********************************************************************
384 * SBMAC_MII_SENDDATA(sbm_mdio, data, bitcnt)
386 * Send some bits to the MII. The bits to be sent are right-
387 * justified in the 'data' parameter.
390 * sbm_mdio - address of the MAC's MDIO register
391 * data - data to send
392 * bitcnt - number of bits to send
393 ********************************************************************* */
395 static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data,
400 unsigned int curmask;
403 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
405 bits = M_MAC_MDIO_DIR_OUTPUT;
406 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
408 curmask = 1 << (bitcnt - 1);
410 for (i = 0; i < bitcnt; i++) {
412 bits |= M_MAC_MDIO_OUT;
413 else bits &= ~M_MAC_MDIO_OUT;
414 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
415 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio);
416 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
423 /**********************************************************************
424 * SBMAC_MII_READ(bus, phyaddr, regidx)
425 * Read a PHY register.
428 * bus - MDIO bus handle
429 * phyaddr - PHY's address
430 * regnum - index of register to read
433 * value read, or 0xffff if an error occurred.
434 ********************************************************************* */
436 static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
438 struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv;
439 void __iomem *sbm_mdio = sc->sbm_mdio;
446 * Synchronize ourselves so that the PHY knows the next
447 * thing coming down is a command
449 sbmac_mii_sync(sbm_mdio);
452 * Send the data to the PHY. The sequence is
453 * a "start" command (2 bits)
454 * a "read" command (2 bits)
455 * the PHY addr (5 bits)
456 * the register index (5 bits)
458 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2);
459 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_READ, 2);
460 sbmac_mii_senddata(sbm_mdio, phyaddr, 5);
461 sbmac_mii_senddata(sbm_mdio, regidx, 5);
463 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
466 * Switch the port around without a clock transition.
468 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
471 * Send out a clock pulse to signal we want the status
473 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
475 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
478 * If an error occurred, the PHY will signal '1' back
480 error = __raw_readq(sbm_mdio) & M_MAC_MDIO_IN;
483 * Issue an 'idle' clock pulse, but keep the direction
486 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
488 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
492 for (idx = 0; idx < 16; idx++) {
496 if (__raw_readq(sbm_mdio) & M_MAC_MDIO_IN)
500 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
502 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
505 /* Switch back to output */
506 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio);
514 /**********************************************************************
515 * SBMAC_MII_WRITE(bus, phyaddr, regidx, regval)
517 * Write a value to a PHY register.
520 * bus - MDIO bus handle
521 * phyaddr - PHY to use
522 * regidx - register within the PHY
523 * regval - data to write to register
527 ********************************************************************* */
529 static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
532 struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv;
533 void __iomem *sbm_mdio = sc->sbm_mdio;
536 sbmac_mii_sync(sbm_mdio);
538 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2);
539 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_WRITE, 2);
540 sbmac_mii_senddata(sbm_mdio, phyaddr, 5);
541 sbmac_mii_senddata(sbm_mdio, regidx, 5);
542 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_ACK, 2);
543 sbmac_mii_senddata(sbm_mdio, regval, 16);
545 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
547 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio);
554 /**********************************************************************
555 * SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
557 * Initialize a DMA channel context. Since there are potentially
558 * eight DMA channels per MAC, it's nice to do this in a standard
562 * d - struct sbmacdma (DMA channel context)
563 * s - struct sbmac_softc (pointer to a MAC)
564 * chan - channel number (0..1 right now)
565 * txrx - Identifies DMA_TX or DMA_RX for channel direction
566 * maxdescr - number of descriptors
570 ********************************************************************* */
572 static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan,
573 int txrx, int maxdescr)
575 #ifdef CONFIG_SBMAC_COALESCE
576 int int_pktcnt, int_timeout;
580 * Save away interesting stuff in the structure
584 d->sbdma_channel = chan;
585 d->sbdma_txdir = txrx;
589 s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
592 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BYTES);
593 __raw_writeq(0, s->sbm_base + R_MAC_RMON_COLLISIONS);
594 __raw_writeq(0, s->sbm_base + R_MAC_RMON_LATE_COL);
595 __raw_writeq(0, s->sbm_base + R_MAC_RMON_EX_COL);
596 __raw_writeq(0, s->sbm_base + R_MAC_RMON_FCS_ERROR);
597 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_ABORT);
598 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BAD);
599 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_GOOD);
600 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_RUNT);
601 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_OVERSIZE);
602 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BYTES);
603 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_MCAST);
604 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BCAST);
605 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BAD);
606 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_GOOD);
607 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_RUNT);
608 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_OVERSIZE);
609 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_FCS_ERROR);
610 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_LENGTH_ERROR);
611 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_CODE_ERROR);
612 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_ALIGN_ERROR);
615 * initialize register pointers
619 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
621 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
623 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
625 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
627 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
629 d->sbdma_oodpktlost = NULL;
631 d->sbdma_oodpktlost =
632 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_OODPKTLOST_RX);
635 * Allocate memory for the ring
638 d->sbdma_maxdescr = maxdescr;
640 d->sbdma_dscrtable_unaligned = kcalloc(d->sbdma_maxdescr + 1,
641 sizeof(*d->sbdma_dscrtable),
645 * The descriptor table must be aligned to at least 16 bytes or the
646 * MAC will corrupt it.
648 d->sbdma_dscrtable = (struct sbdmadscr *)
649 ALIGN((unsigned long)d->sbdma_dscrtable_unaligned,
650 sizeof(*d->sbdma_dscrtable));
652 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
654 d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
660 d->sbdma_ctxtable = kcalloc(d->sbdma_maxdescr,
661 sizeof(*d->sbdma_ctxtable), GFP_KERNEL);
663 #ifdef CONFIG_SBMAC_COALESCE
665 * Setup Rx/Tx DMA coalescing defaults
668 int_pktcnt = (txrx == DMA_TX) ? int_pktcnt_tx : int_pktcnt_rx;
670 d->sbdma_int_pktcnt = int_pktcnt;
672 d->sbdma_int_pktcnt = 1;
675 int_timeout = (txrx == DMA_TX) ? int_timeout_tx : int_timeout_rx;
677 d->sbdma_int_timeout = int_timeout;
679 d->sbdma_int_timeout = 0;
685 /**********************************************************************
686 * SBDMA_CHANNEL_START(d)
688 * Initialize the hardware registers for a DMA channel.
691 * d - DMA channel to init (context must be previously init'd
692 * rxtx - DMA_RX or DMA_TX depending on what type of channel
696 ********************************************************************* */
698 static void sbdma_channel_start(struct sbmacdma *d, int rxtx)
701 * Turn on the DMA channel
704 #ifdef CONFIG_SBMAC_COALESCE
705 __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
706 0, d->sbdma_config1);
707 __raw_writeq(M_DMA_EOP_INT_EN |
708 V_DMA_RINGSZ(d->sbdma_maxdescr) |
709 V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
710 0, d->sbdma_config0);
712 __raw_writeq(0, d->sbdma_config1);
713 __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) |
714 0, d->sbdma_config0);
717 __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase);
720 * Initialize ring pointers
723 d->sbdma_addptr = d->sbdma_dscrtable;
724 d->sbdma_remptr = d->sbdma_dscrtable;
727 /**********************************************************************
728 * SBDMA_CHANNEL_STOP(d)
730 * Initialize the hardware registers for a DMA channel.
733 * d - DMA channel to init (context must be previously init'd
737 ********************************************************************* */
739 static void sbdma_channel_stop(struct sbmacdma *d)
742 * Turn off the DMA channel
745 __raw_writeq(0, d->sbdma_config1);
747 __raw_writeq(0, d->sbdma_dscrbase);
749 __raw_writeq(0, d->sbdma_config0);
755 d->sbdma_addptr = NULL;
756 d->sbdma_remptr = NULL;
759 static inline void sbdma_align_skb(struct sk_buff *skb,
760 unsigned int power2, unsigned int offset)
762 unsigned char *addr = skb->data;
763 unsigned char *newaddr = PTR_ALIGN(addr, power2);
765 skb_reserve(skb, newaddr - addr + offset);
769 /**********************************************************************
770 * SBDMA_ADD_RCVBUFFER(d,sb)
772 * Add a buffer to the specified DMA channel. For receive channels,
773 * this queues a buffer for inbound packets.
776 * sc - softc structure
777 * d - DMA channel descriptor
778 * sb - sk_buff to add, or NULL if we should allocate one
781 * 0 if buffer could not be added (ring is full)
782 * 1 if buffer added successfully
783 ********************************************************************* */
786 static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d,
789 struct net_device *dev = sc->sbm_dev;
790 struct sbdmadscr *dsc;
791 struct sbdmadscr *nextdsc;
792 struct sk_buff *sb_new = NULL;
793 int pktsize = ENET_PACKET_SIZE;
795 /* get pointer to our current place in the ring */
797 dsc = d->sbdma_addptr;
798 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
801 * figure out if the ring is full - if the next descriptor
802 * is the same as the one that we're going to remove from
803 * the ring, the ring is full
806 if (nextdsc == d->sbdma_remptr) {
811 * Allocate a sk_buff if we don't already have one.
812 * If we do have an sk_buff, reset it so that it's empty.
814 * Note: sk_buffs don't seem to be guaranteed to have any sort
815 * of alignment when they are allocated. Therefore, allocate enough
816 * extra space to make sure that:
818 * 1. the data does not start in the middle of a cache line.
819 * 2. The data does not end in the middle of a cache line
820 * 3. The buffer can be aligned such that the IP addresses are
823 * Remember, the SOCs MAC writes whole cache lines at a time,
824 * without reading the old contents first. So, if the sk_buff's
825 * data portion starts in the middle of a cache line, the SOC
826 * DMA will trash the beginning (and ending) portions.
830 sb_new = netdev_alloc_skb(dev, ENET_PACKET_SIZE +
831 SMP_CACHE_BYTES * 2 +
836 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, NET_IP_ALIGN);
841 * nothing special to reinit buffer, it's already aligned
842 * and sb->data already points to a good place.
847 * fill in the descriptor
850 #ifdef CONFIG_SBMAC_COALESCE
852 * Do not interrupt per DMA transfer.
854 dsc->dscr_a = virt_to_phys(sb_new->data) |
855 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) | 0;
857 dsc->dscr_a = virt_to_phys(sb_new->data) |
858 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) |
859 M_DMA_DSCRA_INTERRUPT;
862 /* receiving: no options */
866 * fill in the context
869 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
872 * point at next packet
875 d->sbdma_addptr = nextdsc;
878 * Give the buffer to the DMA engine.
881 __raw_writeq(1, d->sbdma_dscrcnt);
883 return 0; /* we did it */
886 /**********************************************************************
887 * SBDMA_ADD_TXBUFFER(d,sb)
889 * Add a transmit buffer to the specified DMA channel, causing a
893 * d - DMA channel descriptor
894 * sb - sk_buff to add
897 * 0 transmit queued successfully
898 * otherwise error code
899 ********************************************************************* */
902 static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *sb)
904 struct sbdmadscr *dsc;
905 struct sbdmadscr *nextdsc;
910 /* get pointer to our current place in the ring */
912 dsc = d->sbdma_addptr;
913 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
916 * figure out if the ring is full - if the next descriptor
917 * is the same as the one that we're going to remove from
918 * the ring, the ring is full
921 if (nextdsc == d->sbdma_remptr) {
926 * Under Linux, it's not necessary to copy/coalesce buffers
927 * like it is on NetBSD. We think they're all contiguous,
928 * but that may not be true for GBE.
934 * fill in the descriptor. Note that the number of cache
935 * blocks in the descriptor is the number of blocks
936 * *spanned*, so we need to add in the offset (if any)
937 * while doing the calculation.
940 phys = virt_to_phys(sb->data);
941 ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
944 V_DMA_DSCRA_A_SIZE(ncb) |
945 #ifndef CONFIG_SBMAC_COALESCE
946 M_DMA_DSCRA_INTERRUPT |
950 /* transmitting: set outbound options and length */
952 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
953 V_DMA_DSCRB_PKT_SIZE(length);
956 * fill in the context
959 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
962 * point at next packet
965 d->sbdma_addptr = nextdsc;
968 * Give the buffer to the DMA engine.
971 __raw_writeq(1, d->sbdma_dscrcnt);
973 return 0; /* we did it */
979 /**********************************************************************
982 * Free all allocated sk_buffs on the specified DMA channel;
989 ********************************************************************* */
991 static void sbdma_emptyring(struct sbmacdma *d)
996 for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
997 sb = d->sbdma_ctxtable[idx];
1000 d->sbdma_ctxtable[idx] = NULL;
1006 /**********************************************************************
1009 * Fill the specified DMA channel (must be receive channel)
1013 * sc - softc structure
1018 ********************************************************************* */
1020 static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d)
1024 for (idx = 0; idx < SBMAC_MAX_RXDESCR - 1; idx++) {
1025 if (sbdma_add_rcvbuffer(sc, d, NULL) != 0)
1030 #ifdef CONFIG_NET_POLL_CONTROLLER
1031 static void sbmac_netpoll(struct net_device *netdev)
1033 struct sbmac_softc *sc = netdev_priv(netdev);
1034 int irq = sc->sbm_dev->irq;
1036 __raw_writeq(0, sc->sbm_imr);
1038 sbmac_intr(irq, netdev);
1040 #ifdef CONFIG_SBMAC_COALESCE
1041 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1042 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
1045 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1046 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
1051 /**********************************************************************
1052 * SBDMA_RX_PROCESS(sc,d,work_to_do,poll)
1054 * Process "completed" receive buffers on the specified DMA channel.
1057 * sc - softc structure
1058 * d - DMA channel context
1059 * work_to_do - no. of packets to process before enabling interrupt
1061 * poll - 1: using polling (for NAPI)
1065 ********************************************************************* */
1067 static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d,
1068 int work_to_do, int poll)
1070 struct net_device *dev = sc->sbm_dev;
1073 struct sbdmadscr *dsc;
1082 /* Check if the HW dropped any frames */
1083 dev->stats.rx_fifo_errors
1084 += __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff;
1085 __raw_writeq(0, sc->sbm_rxdma.sbdma_oodpktlost);
1087 while (work_to_do-- > 0) {
1089 * figure out where we are (as an index) and where
1090 * the hardware is (also as an index)
1092 * This could be done faster if (for example) the
1093 * descriptor table was page-aligned and contiguous in
1094 * both virtual and physical memory -- you could then
1095 * just compare the low-order bits of the virtual address
1096 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1099 dsc = d->sbdma_remptr;
1100 curidx = dsc - d->sbdma_dscrtable;
1103 prefetch(&d->sbdma_ctxtable[curidx]);
1105 hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1106 d->sbdma_dscrtable_phys) /
1107 sizeof(*d->sbdma_dscrtable);
1110 * If they're the same, that means we've processed all
1111 * of the descriptors up to (but not including) the one that
1112 * the hardware is working on right now.
1115 if (curidx == hwidx)
1119 * Otherwise, get the packet's sk_buff ptr back
1122 sb = d->sbdma_ctxtable[curidx];
1123 d->sbdma_ctxtable[curidx] = NULL;
1125 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1128 * Check packet status. If good, process it.
1129 * If not, silently drop it and put it back on the
1133 if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) {
1136 * Add a new buffer to replace the old one. If we fail
1137 * to allocate a buffer, we're going to drop this
1138 * packet and put it right back on the receive ring.
1141 if (unlikely(sbdma_add_rcvbuffer(sc, d, NULL) ==
1143 dev->stats.rx_dropped++;
1144 /* Re-add old buffer */
1145 sbdma_add_rcvbuffer(sc, d, sb);
1146 /* No point in continuing at the moment */
1147 printk(KERN_ERR "dropped packet (1)\n");
1148 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1152 * Set length into the packet
1157 * Buffer has been replaced on the
1158 * receive ring. Pass the buffer to
1161 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1162 /* Check hw IPv4/TCP checksum if supported */
1163 if (sc->rx_hw_checksum == ENABLE) {
1164 if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1165 !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1166 sb->ip_summed = CHECKSUM_UNNECESSARY;
1167 /* don't need to set sb->csum */
1169 skb_checksum_none_assert(sb);
1173 prefetch((const void *)(((char *)sb->data)+32));
1175 dropped = netif_receive_skb(sb);
1177 dropped = netif_rx(sb);
1179 if (dropped == NET_RX_DROP) {
1180 dev->stats.rx_dropped++;
1181 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1185 dev->stats.rx_bytes += len;
1186 dev->stats.rx_packets++;
1191 * Packet was mangled somehow. Just drop it and
1192 * put it back on the receive ring.
1194 dev->stats.rx_errors++;
1195 sbdma_add_rcvbuffer(sc, d, sb);
1200 * .. and advance to the next buffer.
1203 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1208 goto again; /* collect fifo drop statistics again */
1214 /**********************************************************************
1215 * SBDMA_TX_PROCESS(sc,d)
1217 * Process "completed" transmit buffers on the specified DMA channel.
1218 * This is normally called within the interrupt service routine.
1219 * Note that this isn't really ideal for priority channels, since
1220 * it processes all of the packets on a given channel before
1224 * sc - softc structure
1225 * d - DMA channel context
1226 * poll - 1: using polling (for NAPI)
1230 ********************************************************************* */
1232 static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d,
1235 struct net_device *dev = sc->sbm_dev;
1238 struct sbdmadscr *dsc;
1240 unsigned long flags;
1241 int packets_handled = 0;
1243 spin_lock_irqsave(&(sc->sbm_lock), flags);
1245 if (d->sbdma_remptr == d->sbdma_addptr)
1248 hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1249 d->sbdma_dscrtable_phys) / sizeof(*d->sbdma_dscrtable);
1253 * figure out where we are (as an index) and where
1254 * the hardware is (also as an index)
1256 * This could be done faster if (for example) the
1257 * descriptor table was page-aligned and contiguous in
1258 * both virtual and physical memory -- you could then
1259 * just compare the low-order bits of the virtual address
1260 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1263 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1266 * If they're the same, that means we've processed all
1267 * of the descriptors up to (but not including) the one that
1268 * the hardware is working on right now.
1271 if (curidx == hwidx)
1275 * Otherwise, get the packet's sk_buff ptr back
1278 dsc = &(d->sbdma_dscrtable[curidx]);
1279 sb = d->sbdma_ctxtable[curidx];
1280 d->sbdma_ctxtable[curidx] = NULL;
1286 dev->stats.tx_bytes += sb->len;
1287 dev->stats.tx_packets++;
1290 * for transmits, we just free buffers.
1293 dev_kfree_skb_irq(sb);
1296 * .. and advance to the next buffer.
1299 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1306 * Decide if we should wake up the protocol or not.
1307 * Other drivers seem to do this when we reach a low
1308 * watermark on the transmit queue.
1311 if (packets_handled)
1312 netif_wake_queue(d->sbdma_eth->sbm_dev);
1315 spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1321 /**********************************************************************
1324 * Initialize an Ethernet context structure - this is called
1325 * once per MAC on the 1250. Memory is allocated here, so don't
1326 * call it again from inside the ioctl routines that bring the
1330 * s - sbmac context structure
1334 ********************************************************************* */
1336 static int sbmac_initctx(struct sbmac_softc *s)
1340 * figure out the addresses of some ports
1343 s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1344 s->sbm_maccfg = s->sbm_base + R_MAC_CFG;
1345 s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG;
1346 s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG;
1347 s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG;
1348 s->sbm_isr = s->sbm_base + R_MAC_STATUS;
1349 s->sbm_imr = s->sbm_base + R_MAC_INT_MASK;
1350 s->sbm_mdio = s->sbm_base + R_MAC_MDIO;
1353 * Initialize the DMA channels. Right now, only one per MAC is used
1354 * Note: Only do this _once_, as it allocates memory from the kernel!
1357 sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1358 sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1361 * initial state is OFF
1364 s->sbm_state = sbmac_state_off;
1370 static void sbdma_uninitctx(struct sbmacdma *d)
1372 if (d->sbdma_dscrtable_unaligned) {
1373 kfree(d->sbdma_dscrtable_unaligned);
1374 d->sbdma_dscrtable_unaligned = d->sbdma_dscrtable = NULL;
1377 if (d->sbdma_ctxtable) {
1378 kfree(d->sbdma_ctxtable);
1379 d->sbdma_ctxtable = NULL;
1384 static void sbmac_uninitctx(struct sbmac_softc *sc)
1386 sbdma_uninitctx(&(sc->sbm_txdma));
1387 sbdma_uninitctx(&(sc->sbm_rxdma));
1391 /**********************************************************************
1392 * SBMAC_CHANNEL_START(s)
1394 * Start packet processing on this MAC.
1397 * s - sbmac structure
1401 ********************************************************************* */
1403 static void sbmac_channel_start(struct sbmac_softc *s)
1407 uint64_t cfg,fifo,framecfg;
1411 * Don't do this if running
1414 if (s->sbm_state == sbmac_state_on)
1418 * Bring the controller out of reset, but leave it off.
1421 __raw_writeq(0, s->sbm_macenable);
1424 * Ignore all received packets
1427 __raw_writeq(0, s->sbm_rxfilter);
1430 * Calculate values for various control registers.
1433 cfg = M_MAC_RETRY_EN |
1434 M_MAC_TX_HOLD_SOP_EN |
1435 V_MAC_TX_PAUSE_CNT_16K |
1442 * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1443 * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1444 * Use a larger RD_THRSH for gigabit
1446 if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2)
1451 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */
1452 ((s->sbm_speed == sbmac_speed_1000)
1453 ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1454 V_MAC_TX_RL_THRSH(4) |
1455 V_MAC_RX_PL_THRSH(4) |
1456 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */
1457 V_MAC_RX_RL_THRSH(8) |
1460 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1461 V_MAC_MAX_FRAMESZ_DEFAULT |
1462 V_MAC_BACKOFF_SEL(1);
1465 * Clear out the hash address map
1468 port = s->sbm_base + R_MAC_HASH_BASE;
1469 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1470 __raw_writeq(0, port);
1471 port += sizeof(uint64_t);
1475 * Clear out the exact-match table
1478 port = s->sbm_base + R_MAC_ADDR_BASE;
1479 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1480 __raw_writeq(0, port);
1481 port += sizeof(uint64_t);
1485 * Clear out the DMA Channel mapping table registers
1488 port = s->sbm_base + R_MAC_CHUP0_BASE;
1489 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1490 __raw_writeq(0, port);
1491 port += sizeof(uint64_t);
1495 port = s->sbm_base + R_MAC_CHLO0_BASE;
1496 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1497 __raw_writeq(0, port);
1498 port += sizeof(uint64_t);
1502 * Program the hardware address. It goes into the hardware-address
1503 * register as well as the first filter register.
1506 reg = sbmac_addr2reg(s->sbm_hwaddr);
1508 port = s->sbm_base + R_MAC_ADDR_BASE;
1509 __raw_writeq(reg, port);
1510 port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1512 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1514 * Pass1 SOCs do not receive packets addressed to the
1515 * destination address in the R_MAC_ETHERNET_ADDR register.
1516 * Set the value to zero.
1518 __raw_writeq(0, port);
1520 __raw_writeq(reg, port);
1524 * Set the receive filter for no packets, and write values
1525 * to the various config registers
1528 __raw_writeq(0, s->sbm_rxfilter);
1529 __raw_writeq(0, s->sbm_imr);
1530 __raw_writeq(framecfg, s->sbm_framecfg);
1531 __raw_writeq(fifo, s->sbm_fifocfg);
1532 __raw_writeq(cfg, s->sbm_maccfg);
1535 * Initialize DMA channels (rings should be ok now)
1538 sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1539 sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1542 * Configure the speed, duplex, and flow control
1545 sbmac_set_speed(s,s->sbm_speed);
1546 sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1549 * Fill the receive ring
1552 sbdma_fillring(s, &(s->sbm_rxdma));
1555 * Turn on the rest of the bits in the enable register
1558 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
1559 __raw_writeq(M_MAC_RXDMA_EN0 |
1560 M_MAC_TXDMA_EN0, s->sbm_macenable);
1561 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
1562 __raw_writeq(M_MAC_RXDMA_EN0 |
1565 M_MAC_TX_ENABLE, s->sbm_macenable);
1567 #error invalid SiByte MAC configuration
1570 #ifdef CONFIG_SBMAC_COALESCE
1571 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1572 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr);
1574 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1575 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr);
1579 * Enable receiving unicasts and broadcasts
1582 __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter);
1585 * we're running now.
1588 s->sbm_state = sbmac_state_on;
1591 * Program multicast addresses
1597 * If channel was in promiscuous mode before, turn that on
1600 if (s->sbm_devflags & IFF_PROMISC) {
1601 sbmac_promiscuous_mode(s,1);
1607 /**********************************************************************
1608 * SBMAC_CHANNEL_STOP(s)
1610 * Stop packet processing on this MAC.
1613 * s - sbmac structure
1617 ********************************************************************* */
1619 static void sbmac_channel_stop(struct sbmac_softc *s)
1621 /* don't do this if already stopped */
1623 if (s->sbm_state == sbmac_state_off)
1626 /* don't accept any packets, disable all interrupts */
1628 __raw_writeq(0, s->sbm_rxfilter);
1629 __raw_writeq(0, s->sbm_imr);
1631 /* Turn off ticker */
1635 /* turn off receiver and transmitter */
1637 __raw_writeq(0, s->sbm_macenable);
1639 /* We're stopped now. */
1641 s->sbm_state = sbmac_state_off;
1644 * Stop DMA channels (rings should be ok now)
1647 sbdma_channel_stop(&(s->sbm_rxdma));
1648 sbdma_channel_stop(&(s->sbm_txdma));
1650 /* Empty the receive and transmit rings */
1652 sbdma_emptyring(&(s->sbm_rxdma));
1653 sbdma_emptyring(&(s->sbm_txdma));
1657 /**********************************************************************
1658 * SBMAC_SET_CHANNEL_STATE(state)
1660 * Set the channel's state ON or OFF
1667 ********************************************************************* */
1668 static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *sc,
1669 enum sbmac_state state)
1671 enum sbmac_state oldstate = sc->sbm_state;
1674 * If same as previous state, return
1677 if (state == oldstate) {
1682 * If new state is ON, turn channel on
1685 if (state == sbmac_state_on) {
1686 sbmac_channel_start(sc);
1689 sbmac_channel_stop(sc);
1693 * Return previous state
1700 /**********************************************************************
1701 * SBMAC_PROMISCUOUS_MODE(sc,onoff)
1703 * Turn on or off promiscuous mode
1707 * onoff - 1 to turn on, 0 to turn off
1711 ********************************************************************* */
1713 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1717 if (sc->sbm_state != sbmac_state_on)
1721 reg = __raw_readq(sc->sbm_rxfilter);
1722 reg |= M_MAC_ALLPKT_EN;
1723 __raw_writeq(reg, sc->sbm_rxfilter);
1726 reg = __raw_readq(sc->sbm_rxfilter);
1727 reg &= ~M_MAC_ALLPKT_EN;
1728 __raw_writeq(reg, sc->sbm_rxfilter);
1732 /**********************************************************************
1733 * SBMAC_SETIPHDR_OFFSET(sc,onoff)
1735 * Set the iphdr offset as 15 assuming ethernet encapsulation
1742 ********************************************************************* */
1744 static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1748 /* Hard code the off set to 15 for now */
1749 reg = __raw_readq(sc->sbm_rxfilter);
1750 reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1751 __raw_writeq(reg, sc->sbm_rxfilter);
1753 /* BCM1250 pass1 didn't have hardware checksum. Everything
1755 if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) {
1756 sc->rx_hw_checksum = DISABLE;
1758 sc->rx_hw_checksum = ENABLE;
1763 /**********************************************************************
1764 * SBMAC_ADDR2REG(ptr)
1766 * Convert six bytes into the 64-bit register value that
1767 * we typically write into the SBMAC's address/mcast registers
1770 * ptr - pointer to 6 bytes
1774 ********************************************************************* */
1776 static uint64_t sbmac_addr2reg(unsigned char *ptr)
1782 reg |= (uint64_t) *(--ptr);
1784 reg |= (uint64_t) *(--ptr);
1786 reg |= (uint64_t) *(--ptr);
1788 reg |= (uint64_t) *(--ptr);
1790 reg |= (uint64_t) *(--ptr);
1792 reg |= (uint64_t) *(--ptr);
1798 /**********************************************************************
1799 * SBMAC_SET_SPEED(s,speed)
1801 * Configure LAN speed for the specified MAC.
1802 * Warning: must be called when MAC is off!
1805 * s - sbmac structure
1806 * speed - speed to set MAC to (see enum sbmac_speed)
1810 * 0 indicates invalid parameters
1811 ********************************************************************* */
1813 static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed)
1819 * Save new current values
1822 s->sbm_speed = speed;
1824 if (s->sbm_state == sbmac_state_on)
1825 return 0; /* save for next restart */
1828 * Read current register values
1831 cfg = __raw_readq(s->sbm_maccfg);
1832 framecfg = __raw_readq(s->sbm_framecfg);
1835 * Mask out the stuff we want to change
1838 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1839 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1843 * Now add in the new bits
1847 case sbmac_speed_10:
1848 framecfg |= V_MAC_IFG_RX_10 |
1850 K_MAC_IFG_THRSH_10 |
1852 cfg |= V_MAC_SPEED_SEL_10MBPS;
1855 case sbmac_speed_100:
1856 framecfg |= V_MAC_IFG_RX_100 |
1858 V_MAC_IFG_THRSH_100 |
1859 V_MAC_SLOT_SIZE_100;
1860 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1863 case sbmac_speed_1000:
1864 framecfg |= V_MAC_IFG_RX_1000 |
1866 V_MAC_IFG_THRSH_1000 |
1867 V_MAC_SLOT_SIZE_1000;
1868 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
1876 * Send the bits back to the hardware
1879 __raw_writeq(framecfg, s->sbm_framecfg);
1880 __raw_writeq(cfg, s->sbm_maccfg);
1885 /**********************************************************************
1886 * SBMAC_SET_DUPLEX(s,duplex,fc)
1888 * Set Ethernet duplex and flow control options for this MAC
1889 * Warning: must be called when MAC is off!
1892 * s - sbmac structure
1893 * duplex - duplex setting (see enum sbmac_duplex)
1894 * fc - flow control setting (see enum sbmac_fc)
1898 * 0 if an invalid parameter combination was specified
1899 ********************************************************************* */
1901 static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
1907 * Save new current values
1910 s->sbm_duplex = duplex;
1913 if (s->sbm_state == sbmac_state_on)
1914 return 0; /* save for next restart */
1917 * Read current register values
1920 cfg = __raw_readq(s->sbm_maccfg);
1923 * Mask off the stuff we're about to change
1926 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
1930 case sbmac_duplex_half:
1932 case sbmac_fc_disabled:
1933 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
1936 case sbmac_fc_collision:
1937 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
1940 case sbmac_fc_carrier:
1941 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
1944 case sbmac_fc_frame: /* not valid in half duplex */
1945 default: /* invalid selection */
1950 case sbmac_duplex_full:
1952 case sbmac_fc_disabled:
1953 cfg |= V_MAC_FC_CMD_DISABLED;
1956 case sbmac_fc_frame:
1957 cfg |= V_MAC_FC_CMD_ENABLED;
1960 case sbmac_fc_collision: /* not valid in full duplex */
1961 case sbmac_fc_carrier: /* not valid in full duplex */
1971 * Send the bits back to the hardware
1974 __raw_writeq(cfg, s->sbm_maccfg);
1982 /**********************************************************************
1985 * Interrupt handler for MAC interrupts
1992 ********************************************************************* */
1993 static irqreturn_t sbmac_intr(int irq,void *dev_instance)
1995 struct net_device *dev = (struct net_device *) dev_instance;
1996 struct sbmac_softc *sc = netdev_priv(dev);
2001 * Read the ISR (this clears the bits in the real
2002 * register, except for counter addr)
2005 isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2008 return IRQ_RETVAL(0);
2012 * Transmits on channel 0
2015 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0))
2016 sbdma_tx_process(sc,&(sc->sbm_txdma), 0);
2018 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2019 if (napi_schedule_prep(&sc->napi)) {
2020 __raw_writeq(0, sc->sbm_imr);
2021 __napi_schedule(&sc->napi);
2022 /* Depend on the exit from poll to reenable intr */
2025 /* may leave some packets behind */
2026 sbdma_rx_process(sc,&(sc->sbm_rxdma),
2027 SBMAC_MAX_RXDESCR * 2, 0);
2030 return IRQ_RETVAL(handled);
2033 /**********************************************************************
2034 * SBMAC_START_TX(skb,dev)
2036 * Start output on the specified interface. Basically, we
2037 * queue as many buffers as we can until the ring fills up, or
2038 * we run off the end of the queue, whichever comes first.
2045 ********************************************************************* */
2046 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2048 struct sbmac_softc *sc = netdev_priv(dev);
2049 unsigned long flags;
2052 spin_lock_irqsave(&sc->sbm_lock, flags);
2055 * Put the buffer on the transmit ring. If we
2056 * don't have room, stop the queue.
2059 if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2060 /* XXX save skb that we could not send */
2061 netif_stop_queue(dev);
2062 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2064 return NETDEV_TX_BUSY;
2067 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2069 return NETDEV_TX_OK;
2072 /**********************************************************************
2073 * SBMAC_SETMULTI(sc)
2075 * Reprogram the multicast table into the hardware, given
2076 * the list of multicasts associated with the interface
2084 ********************************************************************* */
2086 static void sbmac_setmulti(struct sbmac_softc *sc)
2091 struct netdev_hw_addr *ha;
2092 struct net_device *dev = sc->sbm_dev;
2095 * Clear out entire multicast table. We do this by nuking
2096 * the entire hash table and all the direct matches except
2097 * the first one, which is used for our station address
2100 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2101 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2102 __raw_writeq(0, port);
2105 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2106 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2107 __raw_writeq(0, port);
2111 * Clear the filter to say we don't want any multicasts.
2114 reg = __raw_readq(sc->sbm_rxfilter);
2115 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2116 __raw_writeq(reg, sc->sbm_rxfilter);
2118 if (dev->flags & IFF_ALLMULTI) {
2120 * Enable ALL multicasts. Do this by inverting the
2121 * multicast enable bit.
2123 reg = __raw_readq(sc->sbm_rxfilter);
2124 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2125 __raw_writeq(reg, sc->sbm_rxfilter);
2131 * Progam new multicast entries. For now, only use the
2132 * perfect filter. In the future we'll need to use the
2133 * hash filter if the perfect filter overflows
2136 /* XXX only using perfect filter for now, need to use hash
2137 * XXX if the table overflows */
2139 idx = 1; /* skip station address */
2140 netdev_for_each_mc_addr(ha, dev) {
2141 if (idx == MAC_ADDR_COUNT)
2143 reg = sbmac_addr2reg(ha->addr);
2144 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2145 __raw_writeq(reg, port);
2150 * Enable the "accept multicast bits" if we programmed at least one
2155 reg = __raw_readq(sc->sbm_rxfilter);
2156 reg |= M_MAC_MCAST_EN;
2157 __raw_writeq(reg, sc->sbm_rxfilter);
2161 static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2163 if (new_mtu > ENET_PACKET_SIZE)
2165 _dev->mtu = new_mtu;
2166 pr_info("changing the mtu to %d\n", new_mtu);
2170 static const struct net_device_ops sbmac_netdev_ops = {
2171 .ndo_open = sbmac_open,
2172 .ndo_stop = sbmac_close,
2173 .ndo_start_xmit = sbmac_start_tx,
2174 .ndo_set_rx_mode = sbmac_set_rx_mode,
2175 .ndo_tx_timeout = sbmac_tx_timeout,
2176 .ndo_do_ioctl = sbmac_mii_ioctl,
2177 .ndo_change_mtu = sb1250_change_mtu,
2178 .ndo_validate_addr = eth_validate_addr,
2179 .ndo_set_mac_address = eth_mac_addr,
2180 #ifdef CONFIG_NET_POLL_CONTROLLER
2181 .ndo_poll_controller = sbmac_netpoll,
2185 /**********************************************************************
2188 * Attach routine - init hardware and hook ourselves into linux
2191 * dev - net_device structure
2195 ********************************************************************* */
2197 static int sbmac_init(struct platform_device *pldev, long long base)
2199 struct net_device *dev = platform_get_drvdata(pldev);
2200 int idx = pldev->id;
2201 struct sbmac_softc *sc = netdev_priv(dev);
2202 unsigned char *eaddr;
2210 eaddr = sc->sbm_hwaddr;
2213 * Read the ethernet address. The firmware left this programmed
2214 * for us in the ethernet address register for each mac.
2217 ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2218 __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR);
2219 for (i = 0; i < 6; i++) {
2220 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2224 for (i = 0; i < 6; i++) {
2225 dev->dev_addr[i] = eaddr[i];
2229 * Initialize context (get pointers to registers and stuff), then
2230 * allocate the memory for the descriptor tables.
2236 * Set up Linux device callins
2239 spin_lock_init(&(sc->sbm_lock));
2241 dev->netdev_ops = &sbmac_netdev_ops;
2242 dev->watchdog_timeo = TX_TIMEOUT;
2244 netif_napi_add(dev, &sc->napi, sbmac_poll, 16);
2246 dev->irq = UNIT_INT(idx);
2248 /* This is needed for PASS2 for Rx H/W checksum feature */
2249 sbmac_set_iphdr_offset(sc);
2251 sc->mii_bus = mdiobus_alloc();
2252 if (sc->mii_bus == NULL) {
2257 sc->mii_bus->name = sbmac_mdio_string;
2258 snprintf(sc->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2260 sc->mii_bus->priv = sc;
2261 sc->mii_bus->read = sbmac_mii_read;
2262 sc->mii_bus->write = sbmac_mii_write;
2263 sc->mii_bus->irq = sc->phy_irq;
2264 for (i = 0; i < PHY_MAX_ADDR; ++i)
2265 sc->mii_bus->irq[i] = SBMAC_PHY_INT;
2267 sc->mii_bus->parent = &pldev->dev;
2271 err = mdiobus_register(sc->mii_bus);
2273 printk(KERN_ERR "%s: unable to register MDIO bus\n",
2277 platform_set_drvdata(pldev, sc->mii_bus);
2279 err = register_netdev(dev);
2281 printk(KERN_ERR "%s.%d: unable to register netdev\n",
2286 pr_info("%s.%d: registered as %s\n", sbmac_string, idx, dev->name);
2288 if (sc->rx_hw_checksum == ENABLE)
2289 pr_info("%s: enabling TCP rcv checksum\n", dev->name);
2292 * Display Ethernet address (this is called during the config
2293 * process so we need to finish off the config message that
2294 * was being displayed)
2296 pr_info("%s: SiByte Ethernet at 0x%08Lx, address: %pM\n",
2297 dev->name, base, eaddr);
2301 mdiobus_unregister(sc->mii_bus);
2303 mdiobus_free(sc->mii_bus);
2305 sbmac_uninitctx(sc);
2310 static int sbmac_open(struct net_device *dev)
2312 struct sbmac_softc *sc = netdev_priv(dev);
2316 pr_debug("%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2319 * map/route interrupt (clear status first, in case something
2320 * weird is pending; we haven't initialized the mac registers
2324 __raw_readq(sc->sbm_isr);
2325 err = request_irq(dev->irq, sbmac_intr, IRQF_SHARED, dev->name, dev);
2327 printk(KERN_ERR "%s: unable to get IRQ %d\n", dev->name,
2332 sc->sbm_speed = sbmac_speed_none;
2333 sc->sbm_duplex = sbmac_duplex_none;
2334 sc->sbm_fc = sbmac_fc_none;
2341 err = sbmac_mii_probe(dev);
2343 goto out_unregister;
2346 * Turn on the channel
2349 sbmac_set_channel_state(sc,sbmac_state_on);
2351 netif_start_queue(dev);
2353 sbmac_set_rx_mode(dev);
2355 phy_start(sc->phy_dev);
2357 napi_enable(&sc->napi);
2362 free_irq(dev->irq, dev);
2367 static int sbmac_mii_probe(struct net_device *dev)
2369 struct sbmac_softc *sc = netdev_priv(dev);
2370 struct phy_device *phy_dev;
2373 for (i = 0; i < PHY_MAX_ADDR; i++) {
2374 phy_dev = sc->mii_bus->phy_map[i];
2379 printk(KERN_ERR "%s: no PHY found\n", dev->name);
2383 phy_dev = phy_connect(dev, dev_name(&phy_dev->dev), &sbmac_mii_poll,
2384 PHY_INTERFACE_MODE_GMII);
2385 if (IS_ERR(phy_dev)) {
2386 printk(KERN_ERR "%s: could not attach to PHY\n", dev->name);
2387 return PTR_ERR(phy_dev);
2390 /* Remove any features not supported by the controller */
2391 phy_dev->supported &= SUPPORTED_10baseT_Half |
2392 SUPPORTED_10baseT_Full |
2393 SUPPORTED_100baseT_Half |
2394 SUPPORTED_100baseT_Full |
2395 SUPPORTED_1000baseT_Half |
2396 SUPPORTED_1000baseT_Full |
2400 SUPPORTED_Asym_Pause;
2401 phy_dev->advertising = phy_dev->supported;
2403 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2404 dev->name, phy_dev->drv->name,
2405 dev_name(&phy_dev->dev), phy_dev->irq);
2407 sc->phy_dev = phy_dev;
2413 static void sbmac_mii_poll(struct net_device *dev)
2415 struct sbmac_softc *sc = netdev_priv(dev);
2416 struct phy_device *phy_dev = sc->phy_dev;
2417 unsigned long flags;
2419 int link_chg, speed_chg, duplex_chg, pause_chg, fc_chg;
2421 link_chg = (sc->sbm_link != phy_dev->link);
2422 speed_chg = (sc->sbm_speed != phy_dev->speed);
2423 duplex_chg = (sc->sbm_duplex != phy_dev->duplex);
2424 pause_chg = (sc->sbm_pause != phy_dev->pause);
2426 if (!link_chg && !speed_chg && !duplex_chg && !pause_chg)
2427 return; /* Hmmm... */
2429 if (!phy_dev->link) {
2431 sc->sbm_link = phy_dev->link;
2432 sc->sbm_speed = sbmac_speed_none;
2433 sc->sbm_duplex = sbmac_duplex_none;
2434 sc->sbm_fc = sbmac_fc_disabled;
2436 pr_info("%s: link unavailable\n", dev->name);
2441 if (phy_dev->duplex == DUPLEX_FULL) {
2443 fc = sbmac_fc_frame;
2445 fc = sbmac_fc_disabled;
2447 fc = sbmac_fc_collision;
2448 fc_chg = (sc->sbm_fc != fc);
2450 pr_info("%s: link available: %dbase-%cD\n", dev->name, phy_dev->speed,
2451 phy_dev->duplex == DUPLEX_FULL ? 'F' : 'H');
2453 spin_lock_irqsave(&sc->sbm_lock, flags);
2455 sc->sbm_speed = phy_dev->speed;
2456 sc->sbm_duplex = phy_dev->duplex;
2458 sc->sbm_pause = phy_dev->pause;
2459 sc->sbm_link = phy_dev->link;
2461 if ((speed_chg || duplex_chg || fc_chg) &&
2462 sc->sbm_state != sbmac_state_off) {
2464 * something changed, restart the channel
2467 pr_debug("%s: restarting channel "
2468 "because PHY state changed\n", dev->name);
2469 sbmac_channel_stop(sc);
2470 sbmac_channel_start(sc);
2473 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2477 static void sbmac_tx_timeout (struct net_device *dev)
2479 struct sbmac_softc *sc = netdev_priv(dev);
2480 unsigned long flags;
2482 spin_lock_irqsave(&sc->sbm_lock, flags);
2485 dev->trans_start = jiffies; /* prevent tx timeout */
2486 dev->stats.tx_errors++;
2488 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2490 printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2496 static void sbmac_set_rx_mode(struct net_device *dev)
2498 unsigned long flags;
2499 struct sbmac_softc *sc = netdev_priv(dev);
2501 spin_lock_irqsave(&sc->sbm_lock, flags);
2502 if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2504 * Promiscuous changed.
2507 if (dev->flags & IFF_PROMISC) {
2508 sbmac_promiscuous_mode(sc,1);
2511 sbmac_promiscuous_mode(sc,0);
2514 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2517 * Program the multicasts. Do this every time.
2524 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2526 struct sbmac_softc *sc = netdev_priv(dev);
2528 if (!netif_running(dev) || !sc->phy_dev)
2531 return phy_mii_ioctl(sc->phy_dev, rq, cmd);
2534 static int sbmac_close(struct net_device *dev)
2536 struct sbmac_softc *sc = netdev_priv(dev);
2538 napi_disable(&sc->napi);
2540 phy_stop(sc->phy_dev);
2542 sbmac_set_channel_state(sc, sbmac_state_off);
2544 netif_stop_queue(dev);
2547 pr_debug("%s: Shutting down ethercard\n", dev->name);
2549 phy_disconnect(sc->phy_dev);
2551 free_irq(dev->irq, dev);
2553 sbdma_emptyring(&(sc->sbm_txdma));
2554 sbdma_emptyring(&(sc->sbm_rxdma));
2559 static int sbmac_poll(struct napi_struct *napi, int budget)
2561 struct sbmac_softc *sc = container_of(napi, struct sbmac_softc, napi);
2564 work_done = sbdma_rx_process(sc, &(sc->sbm_rxdma), budget, 1);
2565 sbdma_tx_process(sc, &(sc->sbm_txdma), 1);
2567 if (work_done < budget) {
2568 napi_complete(napi);
2570 #ifdef CONFIG_SBMAC_COALESCE
2571 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
2572 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
2575 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
2576 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
2584 static int sbmac_probe(struct platform_device *pldev)
2586 struct net_device *dev;
2587 struct sbmac_softc *sc;
2588 void __iomem *sbm_base;
2589 struct resource *res;
2590 u64 sbmac_orig_hwaddr;
2593 res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
2595 sbm_base = ioremap_nocache(res->start, resource_size(res));
2597 printk(KERN_ERR "%s: unable to map device registers\n",
2598 dev_name(&pldev->dev));
2604 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2605 * value for us by the firmware if we're going to use this MAC.
2606 * If we find a zero, skip this MAC.
2608 sbmac_orig_hwaddr = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR);
2609 pr_debug("%s: %sconfiguring MAC at 0x%08Lx\n", dev_name(&pldev->dev),
2610 sbmac_orig_hwaddr ? "" : "not ", (long long)res->start);
2611 if (sbmac_orig_hwaddr == 0) {
2617 * Okay, cool. Initialize this MAC.
2619 dev = alloc_etherdev(sizeof(struct sbmac_softc));
2625 platform_set_drvdata(pldev, dev);
2626 SET_NETDEV_DEV(dev, &pldev->dev);
2628 sc = netdev_priv(dev);
2629 sc->sbm_base = sbm_base;
2631 err = sbmac_init(pldev, res->start);
2639 __raw_writeq(sbmac_orig_hwaddr, sbm_base + R_MAC_ETHERNET_ADDR);
2648 static int __exit sbmac_remove(struct platform_device *pldev)
2650 struct net_device *dev = platform_get_drvdata(pldev);
2651 struct sbmac_softc *sc = netdev_priv(dev);
2653 unregister_netdev(dev);
2654 sbmac_uninitctx(sc);
2655 mdiobus_unregister(sc->mii_bus);
2656 mdiobus_free(sc->mii_bus);
2657 iounmap(sc->sbm_base);
2663 static struct platform_driver sbmac_driver = {
2664 .probe = sbmac_probe,
2665 .remove = __exit_p(sbmac_remove),
2667 .name = sbmac_string,
2668 .owner = THIS_MODULE,
2672 module_platform_driver(sbmac_driver);