2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
6 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/phy.h>
17 #include <linux/interrupt.h>
18 #include <linux/dma-mapping.h>
19 #include <bcm47xx_nvram.h>
21 static const struct bcma_device_id bgmac_bcma_tbl[] = {
22 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
23 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
26 MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl);
28 static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask,
29 u32 value, int timeout)
34 for (i = 0; i < timeout / 10; i++) {
35 val = bcma_read32(core, reg);
36 if ((val & mask) == value)
40 pr_err("Timeout waiting for reg 0x%X\n", reg);
44 /**************************************************
46 **************************************************/
48 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
56 /* Suspend DMA TX ring first.
57 * bgmac_wait_value doesn't support waiting for any of few values, so
58 * implement whole loop here.
60 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
61 BGMAC_DMA_TX_SUSPEND);
62 for (i = 0; i < 10000 / 10; i++) {
63 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
64 val &= BGMAC_DMA_TX_STAT;
65 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
66 val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
67 val == BGMAC_DMA_TX_STAT_STOPPED) {
74 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
75 ring->mmio_base, val);
77 /* Remove SUSPEND bit */
78 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
79 if (!bgmac_wait_value(bgmac->core,
80 ring->mmio_base + BGMAC_DMA_TX_STATUS,
81 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
83 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
86 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
87 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
88 bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n",
93 static void bgmac_dma_tx_enable(struct bgmac *bgmac,
94 struct bgmac_dma_ring *ring)
98 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
99 ctl |= BGMAC_DMA_TX_ENABLE;
100 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
101 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
104 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
105 struct bgmac_dma_ring *ring,
108 struct device *dma_dev = bgmac->core->dma_dev;
109 struct net_device *net_dev = bgmac->net_dev;
110 struct bgmac_dma_desc *dma_desc;
111 struct bgmac_slot_info *slot;
115 if (skb->len > BGMAC_DESC_CTL1_LEN) {
116 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len);
120 if (ring->start <= ring->end)
121 free_slots = ring->start - ring->end + BGMAC_TX_RING_SLOTS;
123 free_slots = ring->start - ring->end;
124 if (free_slots == 1) {
125 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n");
126 netif_stop_queue(net_dev);
127 return NETDEV_TX_BUSY;
130 slot = &ring->slots[ring->end];
132 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb->len,
134 if (dma_mapping_error(dma_dev, slot->dma_addr)) {
135 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n",
140 ctl0 = BGMAC_DESC_CTL0_IOC | BGMAC_DESC_CTL0_SOF | BGMAC_DESC_CTL0_EOF;
141 if (ring->end == ring->num_slots - 1)
142 ctl0 |= BGMAC_DESC_CTL0_EOT;
143 ctl1 = skb->len & BGMAC_DESC_CTL1_LEN;
145 dma_desc = ring->cpu_base;
146 dma_desc += ring->end;
147 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
148 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
149 dma_desc->ctl0 = cpu_to_le32(ctl0);
150 dma_desc->ctl1 = cpu_to_le32(ctl1);
152 netdev_sent_queue(net_dev, skb->len);
156 /* Increase ring->end to point empty slot. We tell hardware the first
157 * slot it should *not* read.
159 if (++ring->end >= BGMAC_TX_RING_SLOTS)
161 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
163 ring->end * sizeof(struct bgmac_dma_desc));
165 /* Always keep one slot free to allow detecting bugged calls. */
166 if (--free_slots == 1)
167 netif_stop_queue(net_dev);
172 netif_stop_queue(net_dev);
177 /* Free transmitted packets */
178 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
180 struct device *dma_dev = bgmac->core->dma_dev;
183 unsigned bytes_compl = 0, pkts_compl = 0;
185 /* The last slot that hardware didn't consume yet */
186 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
187 empty_slot &= BGMAC_DMA_TX_STATDPTR;
188 empty_slot -= ring->index_base;
189 empty_slot &= BGMAC_DMA_TX_STATDPTR;
190 empty_slot /= sizeof(struct bgmac_dma_desc);
192 while (ring->start != empty_slot) {
193 struct bgmac_slot_info *slot = &ring->slots[ring->start];
196 /* Unmap no longer used buffer */
197 dma_unmap_single(dma_dev, slot->dma_addr,
198 slot->skb->len, DMA_TO_DEVICE);
201 bytes_compl += slot->skb->len;
204 /* Free memory! :) */
205 dev_kfree_skb(slot->skb);
208 bgmac_err(bgmac, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d\n",
209 ring->start, ring->end);
212 if (++ring->start >= BGMAC_TX_RING_SLOTS)
217 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
219 if (freed && netif_queue_stopped(bgmac->net_dev))
220 netif_wake_queue(bgmac->net_dev);
223 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
225 if (!ring->mmio_base)
228 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
229 if (!bgmac_wait_value(bgmac->core,
230 ring->mmio_base + BGMAC_DMA_RX_STATUS,
231 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
233 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n",
237 static void bgmac_dma_rx_enable(struct bgmac *bgmac,
238 struct bgmac_dma_ring *ring)
242 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
243 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
244 ctl |= BGMAC_DMA_RX_ENABLE;
245 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
246 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
247 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
248 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
251 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
252 struct bgmac_slot_info *slot)
254 struct device *dma_dev = bgmac->core->dma_dev;
257 struct bgmac_rx_header *rx;
260 skb = netdev_alloc_skb(bgmac->net_dev, BGMAC_RX_BUF_SIZE);
264 /* Poison - if everything goes fine, hardware will overwrite it */
265 rx = (struct bgmac_rx_header *)skb->data;
266 rx->len = cpu_to_le16(0xdead);
267 rx->flags = cpu_to_le16(0xbeef);
269 /* Map skb for the DMA */
270 dma_addr = dma_map_single(dma_dev, skb->data,
271 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
272 if (dma_mapping_error(dma_dev, dma_addr)) {
273 bgmac_err(bgmac, "DMA mapping error\n");
278 /* Update the slot */
280 slot->dma_addr = dma_addr;
282 if (slot->dma_addr & 0xC0000000)
283 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
288 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
289 struct bgmac_dma_ring *ring, int desc_idx)
291 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
292 u32 ctl0 = 0, ctl1 = 0;
294 if (desc_idx == ring->num_slots - 1)
295 ctl0 |= BGMAC_DESC_CTL0_EOT;
296 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
297 /* Is there any BGMAC device that requires extension? */
298 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
299 * B43_DMA64_DCTL1_ADDREXT_MASK;
302 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
303 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
304 dma_desc->ctl0 = cpu_to_le32(ctl0);
305 dma_desc->ctl1 = cpu_to_le32(ctl1);
308 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
314 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
315 end_slot &= BGMAC_DMA_RX_STATDPTR;
316 end_slot -= ring->index_base;
317 end_slot &= BGMAC_DMA_RX_STATDPTR;
318 end_slot /= sizeof(struct bgmac_dma_desc);
320 ring->end = end_slot;
322 while (ring->start != ring->end) {
323 struct device *dma_dev = bgmac->core->dma_dev;
324 struct bgmac_slot_info *slot = &ring->slots[ring->start];
325 struct sk_buff *skb = slot->skb;
326 struct bgmac_rx_header *rx;
329 /* Unmap buffer to make it accessible to the CPU */
330 dma_sync_single_for_cpu(dma_dev, slot->dma_addr,
331 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
333 /* Get info from the header */
334 rx = (struct bgmac_rx_header *)skb->data;
335 len = le16_to_cpu(rx->len);
336 flags = le16_to_cpu(rx->flags);
339 dma_addr_t old_dma_addr = slot->dma_addr;
342 /* Check for poison and drop or pass the packet */
343 if (len == 0xdead && flags == 0xbeef) {
344 bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n",
346 dma_sync_single_for_device(dma_dev,
356 /* Prepare new skb as replacement */
357 err = bgmac_dma_rx_skb_for_slot(bgmac, slot);
359 /* Poison the old skb */
360 rx->len = cpu_to_le16(0xdead);
361 rx->flags = cpu_to_le16(0xbeef);
363 dma_sync_single_for_device(dma_dev,
369 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
371 /* Unmap old skb, we'll pass it to the netfif */
372 dma_unmap_single(dma_dev, old_dma_addr,
373 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
375 skb_put(skb, BGMAC_RX_FRAME_OFFSET + len);
376 skb_pull(skb, BGMAC_RX_FRAME_OFFSET);
378 skb_checksum_none_assert(skb);
379 skb->protocol = eth_type_trans(skb, bgmac->net_dev);
380 netif_receive_skb(skb);
384 if (++ring->start >= BGMAC_RX_RING_SLOTS)
387 if (handled >= weight) /* Should never be greater */
394 /* Does ring support unaligned addressing? */
395 static bool bgmac_dma_unaligned(struct bgmac *bgmac,
396 struct bgmac_dma_ring *ring,
397 enum bgmac_dma_ring_type ring_type)
400 case BGMAC_DMA_RING_TX:
401 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
403 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
406 case BGMAC_DMA_RING_RX:
407 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
409 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
416 static void bgmac_dma_ring_free(struct bgmac *bgmac,
417 struct bgmac_dma_ring *ring)
419 struct device *dma_dev = bgmac->core->dma_dev;
420 struct bgmac_slot_info *slot;
424 for (i = 0; i < ring->num_slots; i++) {
425 slot = &ring->slots[i];
428 dma_unmap_single(dma_dev, slot->dma_addr,
429 slot->skb->len, DMA_TO_DEVICE);
430 dev_kfree_skb(slot->skb);
434 if (ring->cpu_base) {
435 /* Free ring of descriptors */
436 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
437 dma_free_coherent(dma_dev, size, ring->cpu_base,
442 static void bgmac_dma_free(struct bgmac *bgmac)
446 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
447 bgmac_dma_ring_free(bgmac, &bgmac->tx_ring[i]);
448 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
449 bgmac_dma_ring_free(bgmac, &bgmac->rx_ring[i]);
452 static int bgmac_dma_alloc(struct bgmac *bgmac)
454 struct device *dma_dev = bgmac->core->dma_dev;
455 struct bgmac_dma_ring *ring;
456 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
457 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
458 int size; /* ring size: different for Tx and Rx */
462 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
463 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
465 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) {
466 bgmac_err(bgmac, "Core does not report 64-bit DMA\n");
470 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
471 ring = &bgmac->tx_ring[i];
472 ring->num_slots = BGMAC_TX_RING_SLOTS;
473 ring->mmio_base = ring_base[i];
475 /* Alloc ring of descriptors */
476 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
477 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
480 if (!ring->cpu_base) {
481 bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n",
485 if (ring->dma_base & 0xC0000000)
486 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
488 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
491 ring->index_base = lower_32_bits(ring->dma_base);
493 ring->index_base = 0;
495 /* No need to alloc TX slots yet */
498 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
501 ring = &bgmac->rx_ring[i];
502 ring->num_slots = BGMAC_RX_RING_SLOTS;
503 ring->mmio_base = ring_base[i];
505 /* Alloc ring of descriptors */
506 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
507 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
510 if (!ring->cpu_base) {
511 bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n",
516 if (ring->dma_base & 0xC0000000)
517 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
519 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
522 ring->index_base = lower_32_bits(ring->dma_base);
524 ring->index_base = 0;
527 for (j = 0; j < ring->num_slots; j++) {
528 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
530 bgmac_err(bgmac, "Can't allocate skb for slot in RX ring\n");
539 bgmac_dma_free(bgmac);
543 static void bgmac_dma_init(struct bgmac *bgmac)
545 struct bgmac_dma_ring *ring;
548 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
549 ring = &bgmac->tx_ring[i];
551 if (!ring->unaligned)
552 bgmac_dma_tx_enable(bgmac, ring);
553 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
554 lower_32_bits(ring->dma_base));
555 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
556 upper_32_bits(ring->dma_base));
558 bgmac_dma_tx_enable(bgmac, ring);
561 ring->end = 0; /* Points the slot that should *not* be read */
564 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
567 ring = &bgmac->rx_ring[i];
569 if (!ring->unaligned)
570 bgmac_dma_rx_enable(bgmac, ring);
571 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
572 lower_32_bits(ring->dma_base));
573 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
574 upper_32_bits(ring->dma_base));
576 bgmac_dma_rx_enable(bgmac, ring);
578 for (j = 0; j < ring->num_slots; j++)
579 bgmac_dma_rx_setup_desc(bgmac, ring, j);
581 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
583 ring->num_slots * sizeof(struct bgmac_dma_desc));
590 /**************************************************
592 **************************************************/
594 static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
596 struct bcma_device *core;
601 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK);
602 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK);
603 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT);
604 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK);
605 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT);
606 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE);
607 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START);
608 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK);
609 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK);
610 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT);
611 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE);
613 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
614 core = bgmac->core->bus->drv_gmac_cmn.core;
615 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
616 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
619 phy_access_addr = BGMAC_PHY_ACCESS;
620 phy_ctl_addr = BGMAC_PHY_CNTL;
623 tmp = bcma_read32(core, phy_ctl_addr);
624 tmp &= ~BGMAC_PC_EPA_MASK;
626 bcma_write32(core, phy_ctl_addr, tmp);
628 tmp = BGMAC_PA_START;
629 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
630 tmp |= reg << BGMAC_PA_REG_SHIFT;
631 bcma_write32(core, phy_access_addr, tmp);
633 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
634 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n",
639 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK;
642 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
643 static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value)
645 struct bcma_device *core;
650 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
651 core = bgmac->core->bus->drv_gmac_cmn.core;
652 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
653 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
656 phy_access_addr = BGMAC_PHY_ACCESS;
657 phy_ctl_addr = BGMAC_PHY_CNTL;
660 tmp = bcma_read32(core, phy_ctl_addr);
661 tmp &= ~BGMAC_PC_EPA_MASK;
663 bcma_write32(core, phy_ctl_addr, tmp);
665 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO);
666 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)
667 bgmac_warn(bgmac, "Error setting MDIO int\n");
669 tmp = BGMAC_PA_START;
670 tmp |= BGMAC_PA_WRITE;
671 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
672 tmp |= reg << BGMAC_PA_REG_SHIFT;
674 bcma_write32(core, phy_access_addr, tmp);
676 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
677 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n",
685 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
686 static void bgmac_phy_init(struct bgmac *bgmac)
688 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
689 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
692 if (ci->id == BCMA_CHIP_ID_BCM5356) {
693 for (i = 0; i < 5; i++) {
694 bgmac_phy_write(bgmac, i, 0x1f, 0x008b);
695 bgmac_phy_write(bgmac, i, 0x15, 0x0100);
696 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
697 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa);
698 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
701 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) ||
702 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) ||
703 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) {
704 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0);
705 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0);
706 for (i = 0; i < 5; i++) {
707 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
708 bgmac_phy_write(bgmac, i, 0x16, 0x5284);
709 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
710 bgmac_phy_write(bgmac, i, 0x17, 0x0010);
711 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
712 bgmac_phy_write(bgmac, i, 0x16, 0x5296);
713 bgmac_phy_write(bgmac, i, 0x17, 0x1073);
714 bgmac_phy_write(bgmac, i, 0x17, 0x9073);
715 bgmac_phy_write(bgmac, i, 0x16, 0x52b6);
716 bgmac_phy_write(bgmac, i, 0x17, 0x9273);
717 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
722 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
723 static void bgmac_phy_reset(struct bgmac *bgmac)
725 if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
728 bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
729 BGMAC_PHY_CTL_RESET);
731 if (bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) &
733 bgmac_err(bgmac, "PHY reset failed\n");
734 bgmac_phy_init(bgmac);
737 /**************************************************
739 **************************************************/
741 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is
742 * nothing to change? Try if after stabilizng driver.
744 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
747 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
748 u32 new_val = (cmdcfg & mask) | set;
750 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
753 if (new_val != cmdcfg || force)
754 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
756 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
760 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
764 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
765 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
766 tmp = (addr[4] << 8) | addr[5];
767 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
770 static void bgmac_set_rx_mode(struct net_device *net_dev)
772 struct bgmac *bgmac = netdev_priv(net_dev);
774 if (net_dev->flags & IFF_PROMISC)
775 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
777 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
780 #if 0 /* We don't use that regs yet */
781 static void bgmac_chip_stats_update(struct bgmac *bgmac)
785 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) {
786 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
787 bgmac->mib_tx_regs[i] =
789 BGMAC_TX_GOOD_OCTETS + (i * 4));
790 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
791 bgmac->mib_rx_regs[i] =
793 BGMAC_RX_GOOD_OCTETS + (i * 4));
796 /* TODO: what else? how to handle BCM4706? Specs are needed */
800 static void bgmac_clear_mib(struct bgmac *bgmac)
804 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT)
807 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
808 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
809 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
810 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
811 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
814 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
815 static void bgmac_mac_speed(struct bgmac *bgmac)
817 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
820 switch (bgmac->mac_speed) {
822 set |= BGMAC_CMDCFG_ES_10;
825 set |= BGMAC_CMDCFG_ES_100;
828 set |= BGMAC_CMDCFG_ES_1000;
831 bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed);
834 if (bgmac->mac_duplex == DUPLEX_HALF)
835 set |= BGMAC_CMDCFG_HD;
837 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
840 static void bgmac_miiconfig(struct bgmac *bgmac)
842 u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
844 if (imode == 0 || imode == 1) {
845 bgmac->mac_speed = SPEED_100;
846 bgmac->mac_duplex = DUPLEX_FULL;
847 bgmac_mac_speed(bgmac);
851 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
852 static void bgmac_chip_reset(struct bgmac *bgmac)
854 struct bcma_device *core = bgmac->core;
855 struct bcma_bus *bus = core->bus;
856 struct bcma_chipinfo *ci = &bus->chipinfo;
861 if (bcma_core_is_enabled(core)) {
862 if (!bgmac->stats_grabbed) {
863 /* bgmac_chip_stats_update(bgmac); */
864 bgmac->stats_grabbed = true;
867 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
868 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
870 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
873 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
874 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
876 /* TODO: Clear software multicast filter list */
879 iost = bcma_aread32(core, BCMA_IOST);
880 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
881 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
882 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188))
883 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
885 if (iost & BGMAC_BCMA_IOST_ATTACHED) {
886 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
887 if (!bgmac->has_robosw)
888 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
891 bcma_core_enable(core, flags);
893 if (core->id.rev > 2) {
894 bgmac_set(bgmac, BCMA_CLKCTLST,
895 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
896 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST,
897 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
898 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
902 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
903 ci->id == BCMA_CHIP_ID_BCM4749 ||
904 ci->id == BCMA_CHIP_ID_BCM53572) {
905 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
907 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
908 BGMAC_CHIPCTL_1_IF_TYPE_MII;
911 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
912 if (kstrtou8(buf, 0, &et_swtype))
913 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n",
918 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) {
919 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
920 } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
921 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
922 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) {
923 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
924 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
926 bcma_chipco_chipctl_maskset(cc, 1,
927 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
928 BGMAC_CHIPCTL_1_SW_TYPE_MASK),
932 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
933 bcma_awrite32(core, BCMA_IOCTL,
934 bcma_aread32(core, BCMA_IOCTL) &
935 ~BGMAC_BCMA_IOCTL_SW_RESET);
937 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
938 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
939 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
940 * be keps until taking MAC out of the reset.
942 bgmac_cmdcfg_maskset(bgmac,
954 BGMAC_CMDCFG_PAD_EN |
961 bgmac->mac_speed = SPEED_UNKNOWN;
962 bgmac->mac_duplex = DUPLEX_UNKNOWN;
964 bgmac_clear_mib(bgmac);
965 if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
966 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0,
967 BCMA_GMAC_CMN_PC_MTE);
969 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
970 bgmac_miiconfig(bgmac);
971 bgmac_phy_init(bgmac);
973 netdev_reset_queue(bgmac->net_dev);
975 bgmac->int_status = 0;
978 static void bgmac_chip_intrs_on(struct bgmac *bgmac)
980 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
983 static void bgmac_chip_intrs_off(struct bgmac *bgmac)
985 bgmac_write(bgmac, BGMAC_INT_MASK, 0);
986 bgmac_read(bgmac, BGMAC_INT_MASK);
989 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
990 static void bgmac_enable(struct bgmac *bgmac)
992 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
1000 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
1001 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
1002 BGMAC_CMDCFG_SR, true);
1004 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1005 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1007 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1009 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0)
1010 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1011 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2)
1012 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0,
1013 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1016 case BCMA_CHIP_ID_BCM5357:
1017 case BCMA_CHIP_ID_BCM4749:
1018 case BCMA_CHIP_ID_BCM53572:
1019 case BCMA_CHIP_ID_BCM4716:
1020 case BCMA_CHIP_ID_BCM47162:
1021 fl_ctl = 0x03cb04cb;
1022 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1023 ci->id == BCMA_CHIP_ID_BCM4749 ||
1024 ci->id == BCMA_CHIP_ID_BCM53572)
1026 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1027 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
1031 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1032 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1033 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
1034 mdp = (bp_clk * 128 / 1000) - 3;
1035 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1036 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1039 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
1040 static void bgmac_chip_init(struct bgmac *bgmac, bool full_init)
1042 struct bgmac_dma_ring *ring;
1045 /* 1 interrupt per received frame */
1046 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1048 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1049 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1051 bgmac_set_rx_mode(bgmac->net_dev);
1053 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
1055 if (bgmac->loopback)
1056 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1058 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
1060 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1063 bgmac_dma_init(bgmac);
1064 if (1) /* FIXME: is there any case we don't want IRQs? */
1065 bgmac_chip_intrs_on(bgmac);
1067 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
1068 ring = &bgmac->rx_ring[i];
1069 bgmac_dma_rx_enable(bgmac, ring);
1073 bgmac_enable(bgmac);
1076 static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1078 struct bgmac *bgmac = netdev_priv(dev_id);
1080 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1081 int_status &= bgmac->int_mask;
1087 bgmac_write(bgmac, BGMAC_INT_STATUS, int_status);
1089 /* Disable new interrupts until handling existing ones */
1090 bgmac_chip_intrs_off(bgmac);
1092 bgmac->int_status = int_status;
1094 napi_schedule(&bgmac->napi);
1099 static int bgmac_poll(struct napi_struct *napi, int weight)
1101 struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
1102 struct bgmac_dma_ring *ring;
1105 if (bgmac->int_status & BGMAC_IS_TX0) {
1106 ring = &bgmac->tx_ring[0];
1107 bgmac_dma_tx_free(bgmac, ring);
1108 bgmac->int_status &= ~BGMAC_IS_TX0;
1111 if (bgmac->int_status & BGMAC_IS_RX) {
1112 ring = &bgmac->rx_ring[0];
1113 handled += bgmac_dma_rx_read(bgmac, ring, weight);
1114 bgmac->int_status &= ~BGMAC_IS_RX;
1117 if (bgmac->int_status) {
1118 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", bgmac->int_status);
1119 bgmac->int_status = 0;
1122 if (handled < weight)
1123 napi_complete(napi);
1125 bgmac_chip_intrs_on(bgmac);
1130 /**************************************************
1132 **************************************************/
1134 static int bgmac_open(struct net_device *net_dev)
1136 struct bgmac *bgmac = netdev_priv(net_dev);
1139 bgmac_chip_reset(bgmac);
1140 /* Specs say about reclaiming rings here, but we do that in DMA init */
1141 bgmac_chip_init(bgmac, true);
1143 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED,
1144 KBUILD_MODNAME, net_dev);
1146 bgmac_err(bgmac, "IRQ request error: %d!\n", err);
1149 napi_enable(&bgmac->napi);
1151 phy_start(bgmac->phy_dev);
1153 netif_carrier_on(net_dev);
1159 static int bgmac_stop(struct net_device *net_dev)
1161 struct bgmac *bgmac = netdev_priv(net_dev);
1163 netif_carrier_off(net_dev);
1165 phy_stop(bgmac->phy_dev);
1167 napi_disable(&bgmac->napi);
1168 bgmac_chip_intrs_off(bgmac);
1169 free_irq(bgmac->core->irq, net_dev);
1171 bgmac_chip_reset(bgmac);
1176 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1177 struct net_device *net_dev)
1179 struct bgmac *bgmac = netdev_priv(net_dev);
1180 struct bgmac_dma_ring *ring;
1182 /* No QOS support yet */
1183 ring = &bgmac->tx_ring[0];
1184 return bgmac_dma_tx_add(bgmac, ring, skb);
1187 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1189 struct bgmac *bgmac = netdev_priv(net_dev);
1192 ret = eth_prepare_mac_addr_change(net_dev, addr);
1195 bgmac_write_mac_address(bgmac, (u8 *)addr);
1196 eth_commit_mac_addr_change(net_dev, addr);
1200 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1202 struct bgmac *bgmac = netdev_priv(net_dev);
1203 struct mii_ioctl_data *data = if_mii(ifr);
1207 data->phy_id = bgmac->phyaddr;
1210 if (!netif_running(net_dev))
1212 data->val_out = bgmac_phy_read(bgmac, data->phy_id,
1213 data->reg_num & 0x1f);
1216 if (!netif_running(net_dev))
1218 bgmac_phy_write(bgmac, data->phy_id, data->reg_num & 0x1f,
1226 static const struct net_device_ops bgmac_netdev_ops = {
1227 .ndo_open = bgmac_open,
1228 .ndo_stop = bgmac_stop,
1229 .ndo_start_xmit = bgmac_start_xmit,
1230 .ndo_set_rx_mode = bgmac_set_rx_mode,
1231 .ndo_set_mac_address = bgmac_set_mac_address,
1232 .ndo_validate_addr = eth_validate_addr,
1233 .ndo_do_ioctl = bgmac_ioctl,
1236 /**************************************************
1238 **************************************************/
1240 static int bgmac_get_settings(struct net_device *net_dev,
1241 struct ethtool_cmd *cmd)
1243 struct bgmac *bgmac = netdev_priv(net_dev);
1245 return phy_ethtool_gset(bgmac->phy_dev, cmd);
1248 static int bgmac_set_settings(struct net_device *net_dev,
1249 struct ethtool_cmd *cmd)
1251 struct bgmac *bgmac = netdev_priv(net_dev);
1253 return phy_ethtool_sset(bgmac->phy_dev, cmd);
1256 static void bgmac_get_drvinfo(struct net_device *net_dev,
1257 struct ethtool_drvinfo *info)
1259 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1260 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info));
1263 static const struct ethtool_ops bgmac_ethtool_ops = {
1264 .get_settings = bgmac_get_settings,
1265 .set_settings = bgmac_set_settings,
1266 .get_drvinfo = bgmac_get_drvinfo,
1269 /**************************************************
1271 **************************************************/
1273 static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum)
1275 return bgmac_phy_read(bus->priv, mii_id, regnum);
1278 static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum,
1281 return bgmac_phy_write(bus->priv, mii_id, regnum, value);
1284 static void bgmac_adjust_link(struct net_device *net_dev)
1286 struct bgmac *bgmac = netdev_priv(net_dev);
1287 struct phy_device *phy_dev = bgmac->phy_dev;
1288 bool update = false;
1290 if (phy_dev->link) {
1291 if (phy_dev->speed != bgmac->mac_speed) {
1292 bgmac->mac_speed = phy_dev->speed;
1296 if (phy_dev->duplex != bgmac->mac_duplex) {
1297 bgmac->mac_duplex = phy_dev->duplex;
1303 bgmac_mac_speed(bgmac);
1304 phy_print_status(phy_dev);
1308 static int bgmac_mii_register(struct bgmac *bgmac)
1310 struct mii_bus *mii_bus;
1311 struct phy_device *phy_dev;
1312 char bus_id[MII_BUS_ID_SIZE + 3];
1315 mii_bus = mdiobus_alloc();
1319 mii_bus->name = "bgmac mii bus";
1320 sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num,
1321 bgmac->core->core_unit);
1322 mii_bus->priv = bgmac;
1323 mii_bus->read = bgmac_mii_read;
1324 mii_bus->write = bgmac_mii_write;
1325 mii_bus->parent = &bgmac->core->dev;
1326 mii_bus->phy_mask = ~(1 << bgmac->phyaddr);
1328 mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
1329 if (!mii_bus->irq) {
1333 for (i = 0; i < PHY_MAX_ADDR; i++)
1334 mii_bus->irq[i] = PHY_POLL;
1336 err = mdiobus_register(mii_bus);
1338 bgmac_err(bgmac, "Registration of mii bus failed\n");
1342 bgmac->mii_bus = mii_bus;
1344 /* Connect to the PHY */
1345 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id,
1347 phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link,
1348 PHY_INTERFACE_MODE_MII);
1349 if (IS_ERR(phy_dev)) {
1350 bgmac_err(bgmac, "PHY connecton failed\n");
1351 err = PTR_ERR(phy_dev);
1352 goto err_unregister_bus;
1354 bgmac->phy_dev = phy_dev;
1359 mdiobus_unregister(mii_bus);
1361 kfree(mii_bus->irq);
1363 mdiobus_free(mii_bus);
1367 static void bgmac_mii_unregister(struct bgmac *bgmac)
1369 struct mii_bus *mii_bus = bgmac->mii_bus;
1371 mdiobus_unregister(mii_bus);
1372 kfree(mii_bus->irq);
1373 mdiobus_free(mii_bus);
1376 /**************************************************
1378 **************************************************/
1380 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */
1381 static int bgmac_probe(struct bcma_device *core)
1383 struct net_device *net_dev;
1384 struct bgmac *bgmac;
1385 struct ssb_sprom *sprom = &core->bus->sprom;
1386 u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac;
1389 /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */
1390 if (core->core_unit > 1) {
1391 pr_err("Unsupported core_unit %d\n", core->core_unit);
1395 if (!is_valid_ether_addr(mac)) {
1396 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac);
1397 eth_random_addr(mac);
1398 dev_warn(&core->dev, "Using random MAC: %pM\n", mac);
1401 /* Allocation and references */
1402 net_dev = alloc_etherdev(sizeof(*bgmac));
1405 net_dev->netdev_ops = &bgmac_netdev_ops;
1406 net_dev->irq = core->irq;
1407 SET_ETHTOOL_OPS(net_dev, &bgmac_ethtool_ops);
1408 bgmac = netdev_priv(net_dev);
1409 bgmac->net_dev = net_dev;
1411 bcma_set_drvdata(core, bgmac);
1414 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN);
1416 /* On BCM4706 we need common core to access PHY */
1417 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1418 !core->bus->drv_gmac_cmn.core) {
1419 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n");
1421 goto err_netdev_free;
1423 bgmac->cmn = core->bus->drv_gmac_cmn.core;
1425 bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr :
1427 bgmac->phyaddr &= BGMAC_PHY_MASK;
1428 if (bgmac->phyaddr == BGMAC_PHY_MASK) {
1429 bgmac_err(bgmac, "No PHY found\n");
1431 goto err_netdev_free;
1433 bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr,
1434 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : "");
1436 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
1437 bgmac_err(bgmac, "PCI setup not implemented\n");
1439 goto err_netdev_free;
1442 bgmac_chip_reset(bgmac);
1444 err = bgmac_dma_alloc(bgmac);
1446 bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
1447 goto err_netdev_free;
1450 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
1451 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
1452 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1454 /* TODO: reset the external phy. Specs are needed */
1455 bgmac_phy_reset(bgmac);
1457 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo &
1458 BGMAC_BFL_ENETROBO);
1459 if (bgmac->has_robosw)
1460 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n");
1462 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM)
1463 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n");
1465 err = bgmac_mii_register(bgmac);
1467 bgmac_err(bgmac, "Cannot register MDIO\n");
1472 err = register_netdev(bgmac->net_dev);
1474 bgmac_err(bgmac, "Cannot register net device\n");
1476 goto err_mii_unregister;
1479 netif_carrier_off(net_dev);
1481 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1486 bgmac_mii_unregister(bgmac);
1488 bgmac_dma_free(bgmac);
1491 bcma_set_drvdata(core, NULL);
1492 free_netdev(net_dev);
1497 static void bgmac_remove(struct bcma_device *core)
1499 struct bgmac *bgmac = bcma_get_drvdata(core);
1501 netif_napi_del(&bgmac->napi);
1502 unregister_netdev(bgmac->net_dev);
1503 bgmac_mii_unregister(bgmac);
1504 bgmac_dma_free(bgmac);
1505 bcma_set_drvdata(core, NULL);
1506 free_netdev(bgmac->net_dev);
1509 static struct bcma_driver bgmac_bcma_driver = {
1510 .name = KBUILD_MODNAME,
1511 .id_table = bgmac_bcma_tbl,
1512 .probe = bgmac_probe,
1513 .remove = bgmac_remove,
1516 static int __init bgmac_init(void)
1520 err = bcma_driver_register(&bgmac_bcma_driver);
1523 pr_info("Broadcom 47xx GBit MAC driver loaded\n");
1528 static void __exit bgmac_exit(void)
1530 bcma_driver_unregister(&bgmac_bcma_driver);
1533 module_init(bgmac_init)
1534 module_exit(bgmac_exit)
1536 MODULE_AUTHOR("Rafał Miłecki");
1537 MODULE_LICENSE("GPL");