drivers/net/ethernet/amd/xgbe/xgbe-drv.c

   1 /*
   2  * AMD 10Gb Ethernet driver
   3  *
   4  * This file is available to you under your choice of the following two
   5  * licenses:
   6  *
   7  * License 1: GPLv2
   8  *
   9  * Copyright (c) 2014 Advanced Micro Devices, Inc.
  10  *
  11  * This file is free software; you may copy, redistribute and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation, either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This file is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  *
  24  * This file incorporates work covered by the following copyright and
  25  * permission notice:
  26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  29  *     and you.
  30  *
  31  *     The Software IS NOT an item of Licensed Software or Licensed Product
  32  *     under any End User Software License Agreement or Agreement for Licensed
  33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  34  *     granted, free of charge, to any person obtaining a copy of this software
  35  *     annotated with this license and the Software, to deal in the Software
  36  *     without restriction, including without limitation the rights to use,
  37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38  *     of the Software, and to permit persons to whom the Software is furnished
  39  *     to do so, subject to the following conditions:
  40  *
  41  *     The above copyright notice and this permission notice shall be included
  42  *     in all copies or substantial portions of the Software.
  43  *
  44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54  *     THE POSSIBILITY OF SUCH DAMAGE.
  55  *
  56  *
  57  * License 2: Modified BSD
  58  *
  59  * Copyright (c) 2014 Advanced Micro Devices, Inc.
  60  * All rights reserved.
  61  *
  62  * Redistribution and use in source and binary forms, with or without
  63  * modification, are permitted provided that the following conditions are met:
  64  *     * Redistributions of source code must retain the above copyright
  65  *       notice, this list of conditions and the following disclaimer.
  66  *     * Redistributions in binary form must reproduce the above copyright
  67  *       notice, this list of conditions and the following disclaimer in the
  68  *       documentation and/or other materials provided with the distribution.
  69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
  70  *       names of its contributors may be used to endorse or promote products
  71  *       derived from this software without specific prior written permission.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83  *
  84  * This file incorporates work covered by the following copyright and
  85  * permission notice:
  86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  89  *     and you.
  90  *
  91  *     The Software IS NOT an item of Licensed Software or Licensed Product
  92  *     under any End User Software License Agreement or Agreement for Licensed
  93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  94  *     granted, free of charge, to any person obtaining a copy of this software
  95  *     annotated with this license and the Software, to deal in the Software
  96  *     without restriction, including without limitation the rights to use,
  97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98  *     of the Software, and to permit persons to whom the Software is furnished
  99  *     to do so, subject to the following conditions:
 100  *
 101  *     The above copyright notice and this permission notice shall be included
 102  *     in all copies or substantial portions of the Software.
 103  *
 104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
 105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
 108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 114  *     THE POSSIBILITY OF SUCH DAMAGE.
 115  */
 116
 117 #include <linux/platform_device.h>
 118 #include <linux/spinlock.h>
 119 #include <linux/tcp.h>
 120 #include <linux/if_vlan.h>
 121 #include <net/busy_poll.h>
 122 #include <linux/clk.h>
 123 #include <linux/if_ether.h>
 124 #include <linux/net_tstamp.h>
 125 #include <linux/phy.h>
 126
 127 #include "xgbe.h"
 128 #include "xgbe-common.h"
 129
 130 static int xgbe_one_poll(struct napi_struct *, int);
 131 static int xgbe_all_poll(struct napi_struct *, int);
 132 static void xgbe_set_rx_mode(struct net_device *);
 133
 134 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
 135 {
 136         struct xgbe_channel *channel_mem, *channel;
 137         struct xgbe_ring *tx_ring, *rx_ring;
 138         unsigned int count, i;
 139         int ret = -ENOMEM;
 140
 141         count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
 142
 143         channel_mem = kcalloc(count, sizeof(struct xgbe_channel), GFP_KERNEL);
 144         if (!channel_mem)
 145                 goto err_channel;
 146
 147         tx_ring = kcalloc(pdata->tx_ring_count, sizeof(struct xgbe_ring),
 148                           GFP_KERNEL);
 149         if (!tx_ring)
 150                 goto err_tx_ring;
 151
 152         rx_ring = kcalloc(pdata->rx_ring_count, sizeof(struct xgbe_ring),
 153                           GFP_KERNEL);
 154         if (!rx_ring)
 155                 goto err_rx_ring;
 156
 157         for (i = 0, channel = channel_mem; i < count; i++, channel++) {
 158                 snprintf(channel->name, sizeof(channel->name), "channel-%d", i);
 159                 channel->pdata = pdata;
 160                 channel->queue_index = i;
 161                 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
 162                                     (DMA_CH_INC * i);
 163
 164                 if (pdata->per_channel_irq) {
 165                         /* Get the DMA interrupt (offset 1) */
 166                         ret = platform_get_irq(pdata->pdev, i + 1);
 167                         if (ret < 0) {
 168                                 netdev_err(pdata->netdev,
 169                                            "platform_get_irq %u failed\n",
 170                                            i + 1);
 171                                 goto err_irq;
 172                         }
 173
 174                         channel->dma_irq = ret;
 175                 }
 176
 177                 if (i < pdata->tx_ring_count) {
 178                         spin_lock_init(&tx_ring->lock);
 179                         channel->tx_ring = tx_ring++;
 180                 }
 181
 182                 if (i < pdata->rx_ring_count) {
 183                         spin_lock_init(&rx_ring->lock);
 184                         channel->rx_ring = rx_ring++;
 185                 }
 186
 187                 DBGPR("  %s: queue=%u, dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
 188                       channel->name, channel->queue_index, channel->dma_regs,
 189                       channel->dma_irq, channel->tx_ring, channel->rx_ring);
 190         }
 191
 192         pdata->channel = channel_mem;
 193         pdata->channel_count = count;
 194
 195         return 0;
 196
 197 err_irq:
 198         kfree(rx_ring);
 199
 200 err_rx_ring:
 201         kfree(tx_ring);
 202
 203 err_tx_ring:
 204         kfree(channel_mem);
 205
 206 err_channel:
 207         return ret;
 208 }
 209
 210 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
 211 {
 212         if (!pdata->channel)
 213                 return;
 214
 215         kfree(pdata->channel->rx_ring);
 216         kfree(pdata->channel->tx_ring);
 217         kfree(pdata->channel);
 218
 219         pdata->channel = NULL;
 220         pdata->channel_count = 0;
 221 }
 222
 223 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
 224 {
 225         return (ring->rdesc_count - (ring->cur - ring->dirty));
 226 }
 227
 228 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
 229                                     struct xgbe_ring *ring, unsigned int count)
 230 {
 231         struct xgbe_prv_data *pdata = channel->pdata;
 232
 233         if (count > xgbe_tx_avail_desc(ring)) {
 234                 DBGPR("  Tx queue stopped, not enough descriptors available\n");
 235                 netif_stop_subqueue(pdata->netdev, channel->queue_index);
 236                 ring->tx.queue_stopped = 1;
 237
 238                 /* If we haven't notified the hardware because of xmit_more
 239                  * support, tell it now
 240                  */
 241                 if (ring->tx.xmit_more)
 242                         pdata->hw_if.tx_start_xmit(channel, ring);
 243
 244                 return NETDEV_TX_BUSY;
 245         }
 246
 247         return 0;
 248 }
 249
 250 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
 251 {
 252         unsigned int rx_buf_size;
 253
 254         if (mtu > XGMAC_JUMBO_PACKET_MTU) {
 255                 netdev_alert(netdev, "MTU exceeds maximum supported value\n");
 256                 return -EINVAL;
 257         }
 258
 259         rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
 260         rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
 261
 262         rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
 263                       ~(XGBE_RX_BUF_ALIGN - 1);
 264
 265         return rx_buf_size;
 266 }
 267
 268 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
 269 {
 270         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 271         struct xgbe_channel *channel;
 272         enum xgbe_int int_id;
 273         unsigned int i;
 274
 275         channel = pdata->channel;
 276         for (i = 0; i < pdata->channel_count; i++, channel++) {
 277                 if (channel->tx_ring && channel->rx_ring)
 278                         int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
 279                 else if (channel->tx_ring)
 280                         int_id = XGMAC_INT_DMA_CH_SR_TI;
 281                 else if (channel->rx_ring)
 282                         int_id = XGMAC_INT_DMA_CH_SR_RI;
 283                 else
 284                         continue;
 285
 286                 hw_if->enable_int(channel, int_id);
 287         }
 288 }
 289
 290 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
 291 {
 292         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 293         struct xgbe_channel *channel;
 294         enum xgbe_int int_id;
 295         unsigned int i;
 296
 297         channel = pdata->channel;
 298         for (i = 0; i < pdata->channel_count; i++, channel++) {
 299                 if (channel->tx_ring && channel->rx_ring)
 300                         int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
 301                 else if (channel->tx_ring)
 302                         int_id = XGMAC_INT_DMA_CH_SR_TI;
 303                 else if (channel->rx_ring)
 304                         int_id = XGMAC_INT_DMA_CH_SR_RI;
 305                 else
 306                         continue;
 307
 308                 hw_if->disable_int(channel, int_id);
 309         }
 310 }
 311
 312 static irqreturn_t xgbe_isr(int irq, void *data)
 313 {
 314         struct xgbe_prv_data *pdata = data;
 315         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 316         struct xgbe_channel *channel;
 317         unsigned int dma_isr, dma_ch_isr;
 318         unsigned int mac_isr, mac_tssr;
 319         unsigned int i;
 320
 321         /* The DMA interrupt status register also reports MAC and MTL
 322          * interrupts. So for polling mode, we just need to check for
 323          * this register to be non-zero
 324          */
 325         dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
 326         if (!dma_isr)
 327                 goto isr_done;
 328
 329         DBGPR("  DMA_ISR = %08x\n", dma_isr);
 330
 331         for (i = 0; i < pdata->channel_count; i++) {
 332                 if (!(dma_isr & (1 << i)))
 333                         continue;
 334
 335                 channel = pdata->channel + i;
 336
 337                 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
 338                 DBGPR("  DMA_CH%u_ISR = %08x\n", i, dma_ch_isr);
 339
 340                 /* If we get a TI or RI interrupt that means per channel DMA
 341                  * interrupts are not enabled, so we use the private data napi
 342                  * structure, not the per channel napi structure
 343                  */
 344                 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
 345                     XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI)) {
 346                         if (napi_schedule_prep(&pdata->napi)) {
 347                                 /* Disable Tx and Rx interrupts */
 348                                 xgbe_disable_rx_tx_ints(pdata);
 349
 350                                 /* Turn on polling */
 351                                 __napi_schedule(&pdata->napi);
 352                         }
 353                 }
 354
 355                 /* Restart the device on a Fatal Bus Error */
 356                 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
 357                         schedule_work(&pdata->restart_work);
 358
 359                 /* Clear all interrupt signals */
 360                 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
 361         }
 362
 363         if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
 364                 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
 365
 366                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
 367                         hw_if->tx_mmc_int(pdata);
 368
 369                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
 370                         hw_if->rx_mmc_int(pdata);
 371
 372                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
 373                         mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
 374
 375                         if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
 376                                 /* Read Tx Timestamp to clear interrupt */
 377                                 pdata->tx_tstamp =
 378                                         hw_if->get_tx_tstamp(pdata);
 379                                 schedule_work(&pdata->tx_tstamp_work);
 380                         }
 381                 }
 382         }
 383
 384         DBGPR("  DMA_ISR = %08x\n", XGMAC_IOREAD(pdata, DMA_ISR));
 385
 386 isr_done:
 387         return IRQ_HANDLED;
 388 }
 389
 390 static irqreturn_t xgbe_dma_isr(int irq, void *data)
 391 {
 392         struct xgbe_channel *channel = data;
 393
 394         /* Per channel DMA interrupts are enabled, so we use the per
 395          * channel napi structure and not the private data napi structure
 396          */
 397         if (napi_schedule_prep(&channel->napi)) {
 398                 /* Disable Tx and Rx interrupts */
 399                 disable_irq_nosync(channel->dma_irq);
 400
 401                 /* Turn on polling */
 402                 __napi_schedule(&channel->napi);
 403         }
 404
 405         return IRQ_HANDLED;
 406 }
 407
 408 static enum hrtimer_restart xgbe_tx_timer(struct hrtimer *timer)
 409 {
 410         struct xgbe_channel *channel = container_of(timer,
 411                                                     struct xgbe_channel,
 412                                                     tx_timer);
 413         struct xgbe_ring *ring = channel->tx_ring;
 414         struct xgbe_prv_data *pdata = channel->pdata;
 415         struct napi_struct *napi;
 416         unsigned long flags;
 417
 418         DBGPR("-->xgbe_tx_timer\n");
 419
 420         napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
 421
 422         spin_lock_irqsave(&ring->lock, flags);
 423
 424         if (napi_schedule_prep(napi)) {
 425                 /* Disable Tx and Rx interrupts */
 426                 if (pdata->per_channel_irq)
 427                         disable_irq(channel->dma_irq);
 428                 else
 429                         xgbe_disable_rx_tx_ints(pdata);
 430
 431                 /* Turn on polling */
 432                 __napi_schedule(napi);
 433         }
 434
 435         channel->tx_timer_active = 0;
 436
 437         spin_unlock_irqrestore(&ring->lock, flags);
 438
 439         DBGPR("<--xgbe_tx_timer\n");
 440
 441         return HRTIMER_NORESTART;
 442 }
 443
 444 static void xgbe_init_tx_timers(struct xgbe_prv_data *pdata)
 445 {
 446         struct xgbe_channel *channel;
 447         unsigned int i;
 448
 449         DBGPR("-->xgbe_init_tx_timers\n");
 450
 451         channel = pdata->channel;
 452         for (i = 0; i < pdata->channel_count; i++, channel++) {
 453                 if (!channel->tx_ring)
 454                         break;
 455
 456                 DBGPR("  %s adding tx timer\n", channel->name);
 457                 hrtimer_init(&channel->tx_timer, CLOCK_MONOTONIC,
 458                              HRTIMER_MODE_REL);
 459                 channel->tx_timer.function = xgbe_tx_timer;
 460         }
 461
 462         DBGPR("<--xgbe_init_tx_timers\n");
 463 }
 464
 465 static void xgbe_stop_tx_timers(struct xgbe_prv_data *pdata)
 466 {
 467         struct xgbe_channel *channel;
 468         unsigned int i;
 469
 470         DBGPR("-->xgbe_stop_tx_timers\n");
 471
 472         channel = pdata->channel;
 473         for (i = 0; i < pdata->channel_count; i++, channel++) {
 474                 if (!channel->tx_ring)
 475                         break;
 476
 477                 DBGPR("  %s deleting tx timer\n", channel->name);
 478                 channel->tx_timer_active = 0;
 479                 hrtimer_cancel(&channel->tx_timer);
 480         }
 481
 482         DBGPR("<--xgbe_stop_tx_timers\n");
 483 }
 484
 485 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
 486 {
 487         unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
 488         struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
 489
 490         DBGPR("-->xgbe_get_all_hw_features\n");
 491
 492         mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
 493         mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
 494         mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
 495
 496         memset(hw_feat, 0, sizeof(*hw_feat));
 497
 498         hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
 499
 500         /* Hardware feature register 0 */
 501         hw_feat->gmii        = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
 502         hw_feat->vlhash      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
 503         hw_feat->sma         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
 504         hw_feat->rwk         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
 505         hw_feat->mgk         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
 506         hw_feat->mmc         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
 507         hw_feat->aoe         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
 508         hw_feat->ts          = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
 509         hw_feat->eee         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
 510         hw_feat->tx_coe      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
 511         hw_feat->rx_coe      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
 512         hw_feat->addn_mac    = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
 513                                               ADDMACADRSEL);
 514         hw_feat->ts_src      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
 515         hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
 516
 517         /* Hardware feature register 1 */
 518         hw_feat->rx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 519                                                 RXFIFOSIZE);
 520         hw_feat->tx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 521                                                 TXFIFOSIZE);
 522         hw_feat->dcb           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
 523         hw_feat->sph           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
 524         hw_feat->tso           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
 525         hw_feat->dma_debug     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
 526         hw_feat->rss           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
 527         hw_feat->tc_cnt        = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
 528         hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 529                                                   HASHTBLSZ);
 530         hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 531                                                   L3L4FNUM);
 532
 533         /* Hardware feature register 2 */
 534         hw_feat->rx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
 535         hw_feat->tx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
 536         hw_feat->rx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
 537         hw_feat->tx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
 538         hw_feat->pps_out_num  = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
 539         hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
 540
 541         /* Translate the Hash Table size into actual number */
 542         switch (hw_feat->hash_table_size) {
 543         case 0:
 544                 break;
 545         case 1:
 546                 hw_feat->hash_table_size = 64;
 547                 break;
 548         case 2:
 549                 hw_feat->hash_table_size = 128;
 550                 break;
 551         case 3:
 552                 hw_feat->hash_table_size = 256;
 553                 break;
 554         }
 555
 556         /* The Queue, Channel and TC counts are zero based so increment them
 557          * to get the actual number
 558          */
 559         hw_feat->rx_q_cnt++;
 560         hw_feat->tx_q_cnt++;
 561         hw_feat->rx_ch_cnt++;
 562         hw_feat->tx_ch_cnt++;
 563         hw_feat->tc_cnt++;
 564
 565         DBGPR("<--xgbe_get_all_hw_features\n");
 566 }
 567
 568 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
 569 {
 570         struct xgbe_channel *channel;
 571         unsigned int i;
 572
 573         if (pdata->per_channel_irq) {
 574                 channel = pdata->channel;
 575                 for (i = 0; i < pdata->channel_count; i++, channel++) {
 576                         if (add)
 577                                 netif_napi_add(pdata->netdev, &channel->napi,
 578                                                xgbe_one_poll, NAPI_POLL_WEIGHT);
 579
 580                         napi_enable(&channel->napi);
 581                 }
 582         } else {
 583                 if (add)
 584                         netif_napi_add(pdata->netdev, &pdata->napi,
 585                                        xgbe_all_poll, NAPI_POLL_WEIGHT);
 586
 587                 napi_enable(&pdata->napi);
 588         }
 589 }
 590
 591 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
 592 {
 593         struct xgbe_channel *channel;
 594         unsigned int i;
 595
 596         if (pdata->per_channel_irq) {
 597                 channel = pdata->channel;
 598                 for (i = 0; i < pdata->channel_count; i++, channel++) {
 599                         napi_disable(&channel->napi);
 600
 601                         if (del)
 602                                 netif_napi_del(&channel->napi);
 603                 }
 604         } else {
 605                 napi_disable(&pdata->napi);
 606
 607                 if (del)
 608                         netif_napi_del(&pdata->napi);
 609         }
 610 }
 611
 612 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
 613 {
 614         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 615
 616         DBGPR("-->xgbe_init_tx_coalesce\n");
 617
 618         pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
 619         pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
 620
 621         hw_if->config_tx_coalesce(pdata);
 622
 623         DBGPR("<--xgbe_init_tx_coalesce\n");
 624 }
 625
 626 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
 627 {
 628         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 629
 630         DBGPR("-->xgbe_init_rx_coalesce\n");
 631
 632         pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
 633         pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
 634
 635         hw_if->config_rx_coalesce(pdata);
 636
 637         DBGPR("<--xgbe_init_rx_coalesce\n");
 638 }
 639
 640 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
 641 {
 642         struct xgbe_desc_if *desc_if = &pdata->desc_if;
 643         struct xgbe_channel *channel;
 644         struct xgbe_ring *ring;
 645         struct xgbe_ring_data *rdata;
 646         unsigned int i, j;
 647
 648         DBGPR("-->xgbe_free_tx_data\n");
 649
 650         channel = pdata->channel;
 651         for (i = 0; i < pdata->channel_count; i++, channel++) {
 652                 ring = channel->tx_ring;
 653                 if (!ring)
 654                         break;
 655
 656                 for (j = 0; j < ring->rdesc_count; j++) {
 657                         rdata = XGBE_GET_DESC_DATA(ring, j);
 658                         desc_if->unmap_rdata(pdata, rdata);
 659                 }
 660         }
 661
 662         DBGPR("<--xgbe_free_tx_data\n");
 663 }
 664
 665 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
 666 {
 667         struct xgbe_desc_if *desc_if = &pdata->desc_if;
 668         struct xgbe_channel *channel;
 669         struct xgbe_ring *ring;
 670         struct xgbe_ring_data *rdata;
 671         unsigned int i, j;
 672
 673         DBGPR("-->xgbe_free_rx_data\n");
 674
 675         channel = pdata->channel;
 676         for (i = 0; i < pdata->channel_count; i++, channel++) {
 677                 ring = channel->rx_ring;
 678                 if (!ring)
 679                         break;
 680
 681                 for (j = 0; j < ring->rdesc_count; j++) {
 682                         rdata = XGBE_GET_DESC_DATA(ring, j);
 683                         desc_if->unmap_rdata(pdata, rdata);
 684                 }
 685         }
 686
 687         DBGPR("<--xgbe_free_rx_data\n");
 688 }
 689
 690 static void xgbe_adjust_link(struct net_device *netdev)
 691 {
 692         struct xgbe_prv_data *pdata = netdev_priv(netdev);
 693         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 694         struct phy_device *phydev = pdata->phydev;
 695         int new_state = 0;
 696
 697         if (phydev == NULL)
 698                 return;
 699
 700         if (phydev->link) {
 701                 /* Flow control support */
 702                 if (pdata->pause_autoneg) {
 703                         if (phydev->pause || phydev->asym_pause) {
 704                                 pdata->tx_pause = 1;
 705                                 pdata->rx_pause = 1;
 706                         } else {
 707                                 pdata->tx_pause = 0;
 708                                 pdata->rx_pause = 0;
 709                         }
 710                 }
 711
 712                 if (pdata->tx_pause != pdata->phy_tx_pause) {
 713                         hw_if->config_tx_flow_control(pdata);
 714                         pdata->phy_tx_pause = pdata->tx_pause;
 715                 }
 716
 717                 if (pdata->rx_pause != pdata->phy_rx_pause) {
 718                         hw_if->config_rx_flow_control(pdata);
 719                         pdata->phy_rx_pause = pdata->rx_pause;
 720                 }
 721
 722                 /* Speed support */
 723                 if (phydev->speed != pdata->phy_speed) {
 724                         new_state = 1;
 725
 726                         switch (phydev->speed) {
 727                         case SPEED_10000:
 728                                 hw_if->set_xgmii_speed(pdata);
 729                                 break;
 730
 731                         case SPEED_2500:
 732                                 hw_if->set_gmii_2500_speed(pdata);
 733                                 break;
 734
 735                         case SPEED_1000:
 736                                 hw_if->set_gmii_speed(pdata);
 737                                 break;
 738                         }
 739                         pdata->phy_speed = phydev->speed;
 740                 }
 741
 742                 if (phydev->link != pdata->phy_link) {
 743                         new_state = 1;
 744                         pdata->phy_link = 1;
 745                 }
 746         } else if (pdata->phy_link) {
 747                 new_state = 1;
 748                 pdata->phy_link = 0;
 749                 pdata->phy_speed = SPEED_UNKNOWN;
 750         }
 751
 752         if (new_state)
 753                 phy_print_status(phydev);
 754 }
 755
 756 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
 757 {
 758         struct net_device *netdev = pdata->netdev;
 759         struct phy_device *phydev = pdata->phydev;
 760         int ret;
 761
 762         pdata->phy_link = -1;
 763         pdata->phy_speed = SPEED_UNKNOWN;
 764         pdata->phy_tx_pause = pdata->tx_pause;
 765         pdata->phy_rx_pause = pdata->rx_pause;
 766
 767         ret = phy_connect_direct(netdev, phydev, &xgbe_adjust_link,
 768                                  pdata->phy_mode);
 769         if (ret) {
 770                 netdev_err(netdev, "phy_connect_direct failed\n");
 771                 return ret;
 772         }
 773
 774         if (!phydev->drv || (phydev->drv->phy_id == 0)) {
 775                 netdev_err(netdev, "phy_id not valid\n");
 776                 ret = -ENODEV;
 777                 goto err_phy_connect;
 778         }
 779         DBGPR("  phy_connect_direct succeeded for PHY %s, link=%d\n",
 780               dev_name(&phydev->dev), phydev->link);
 781
 782         return 0;
 783
 784 err_phy_connect:
 785         phy_disconnect(phydev);
 786
 787         return ret;
 788 }
 789
 790 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
 791 {
 792         if (!pdata->phydev)
 793                 return;
 794
 795         phy_disconnect(pdata->phydev);
 796 }
 797
 798 int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
 799 {
 800         struct xgbe_prv_data *pdata = netdev_priv(netdev);
 801         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 802         unsigned long flags;
 803
 804         DBGPR("-->xgbe_powerdown\n");
 805
 806         if (!netif_running(netdev) ||
 807             (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
 808                 netdev_alert(netdev, "Device is already powered down\n");
 809                 DBGPR("<--xgbe_powerdown\n");
 810                 return -EINVAL;
 811         }
 812
 813         phy_stop(pdata->phydev);
 814
 815         spin_lock_irqsave(&pdata->lock, flags);
 816
 817         if (caller == XGMAC_DRIVER_CONTEXT)
 818                 netif_device_detach(netdev);
 819
 820         netif_tx_stop_all_queues(netdev);
 821         xgbe_napi_disable(pdata, 0);
 822
 823         /* Powerdown Tx/Rx */
 824         hw_if->powerdown_tx(pdata);
 825         hw_if->powerdown_rx(pdata);
 826
 827         pdata->power_down = 1;
 828
 829         spin_unlock_irqrestore(&pdata->lock, flags);
 830
 831         DBGPR("<--xgbe_powerdown\n");
 832
 833         return 0;
 834 }
 835
 836 int xgbe_powerup(struct net_device *netdev, unsigned int caller)
 837 {
 838         struct xgbe_prv_data *pdata = netdev_priv(netdev);
 839         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 840         unsigned long flags;
 841
 842         DBGPR("-->xgbe_powerup\n");
 843
 844         if (!netif_running(netdev) ||
 845             (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
 846                 netdev_alert(netdev, "Device is already powered up\n");
 847                 DBGPR("<--xgbe_powerup\n");
 848                 return -EINVAL;
 849         }
 850
 851         spin_lock_irqsave(&pdata->lock, flags);
 852
 853         pdata->power_down = 0;
 854
 855         phy_start(pdata->phydev);
 856
 857         /* Enable Tx/Rx */
 858         hw_if->powerup_tx(pdata);
 859         hw_if->powerup_rx(pdata);
 860
 861         if (caller == XGMAC_DRIVER_CONTEXT)
 862                 netif_device_attach(netdev);
 863
 864         xgbe_napi_enable(pdata, 0);
 865         netif_tx_start_all_queues(netdev);
 866
 867         spin_unlock_irqrestore(&pdata->lock, flags);
 868
 869         DBGPR("<--xgbe_powerup\n");
 870
 871         return 0;
 872 }
 873
 874 static int xgbe_start(struct xgbe_prv_data *pdata)
 875 {
 876         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 877         struct net_device *netdev = pdata->netdev;
 878
 879         DBGPR("-->xgbe_start\n");
 880
 881         xgbe_set_rx_mode(netdev);
 882
 883         hw_if->init(pdata);
 884
 885         phy_start(pdata->phydev);
 886
 887         hw_if->enable_tx(pdata);
 888         hw_if->enable_rx(pdata);
 889
 890         xgbe_init_tx_timers(pdata);
 891
 892         xgbe_napi_enable(pdata, 1);
 893         netif_tx_start_all_queues(netdev);
 894
 895         DBGPR("<--xgbe_start\n");
 896
 897         return 0;
 898 }
 899
 900 static void xgbe_stop(struct xgbe_prv_data *pdata)
 901 {
 902         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 903         struct xgbe_channel *channel;
 904         struct net_device *netdev = pdata->netdev;
 905         struct netdev_queue *txq;
 906         unsigned int i;
 907
 908         DBGPR("-->xgbe_stop\n");
 909
 910         phy_stop(pdata->phydev);
 911
 912         netif_tx_stop_all_queues(netdev);
 913         xgbe_napi_disable(pdata, 1);
 914
 915         xgbe_stop_tx_timers(pdata);
 916
 917         hw_if->disable_tx(pdata);
 918         hw_if->disable_rx(pdata);
 919
 920         channel = pdata->channel;
 921         for (i = 0; i < pdata->channel_count; i++, channel++) {
 922                 if (!channel->tx_ring)
 923                         continue;
 924
 925                 txq = netdev_get_tx_queue(netdev, channel->queue_index);
 926                 netdev_tx_reset_queue(txq);
 927         }
 928
 929         DBGPR("<--xgbe_stop\n");
 930 }
 931
 932 static void xgbe_restart_dev(struct xgbe_prv_data *pdata, unsigned int reset)
 933 {
 934         struct xgbe_channel *channel;
 935         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 936         unsigned int i;
 937
 938         DBGPR("-->xgbe_restart_dev\n");
 939
 940         /* If not running, "restart" will happen on open */
 941         if (!netif_running(pdata->netdev))
 942                 return;
 943
 944         xgbe_stop(pdata);
 945         synchronize_irq(pdata->dev_irq);
 946         if (pdata->per_channel_irq) {
 947                 channel = pdata->channel;
 948                 for (i = 0; i < pdata->channel_count; i++, channel++)
 949                         synchronize_irq(channel->dma_irq);
 950         }
 951
 952         xgbe_free_tx_data(pdata);
 953         xgbe_free_rx_data(pdata);
 954
 955         /* Issue software reset to device if requested */
 956         if (reset)
 957                 hw_if->exit(pdata);
 958
 959         xgbe_start(pdata);
 960
 961         DBGPR("<--xgbe_restart_dev\n");
 962 }
 963
 964 static void xgbe_restart(struct work_struct *work)
 965 {
 966         struct xgbe_prv_data *pdata = container_of(work,
 967                                                    struct xgbe_prv_data,
 968                                                    restart_work);
 969
 970         rtnl_lock();
 971
 972         xgbe_restart_dev(pdata, 1);
 973
 974         rtnl_unlock();
 975 }
 976
 977 static void xgbe_tx_tstamp(struct work_struct *work)
 978 {
 979         struct xgbe_prv_data *pdata = container_of(work,
 980                                                    struct xgbe_prv_data,
 981                                                    tx_tstamp_work);
 982         struct skb_shared_hwtstamps hwtstamps;
 983         u64 nsec;
 984         unsigned long flags;
 985
 986         if (pdata->tx_tstamp) {
 987                 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
 988                                             pdata->tx_tstamp);
 989
 990                 memset(&hwtstamps, 0, sizeof(hwtstamps));
 991                 hwtstamps.hwtstamp = ns_to_ktime(nsec);
 992                 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
 993         }
 994
 995         dev_kfree_skb_any(pdata->tx_tstamp_skb);
 996
 997         spin_lock_irqsave(&pdata->tstamp_lock, flags);
 998         pdata->tx_tstamp_skb = NULL;
 999         spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1000 }
1001
1002 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1003                                       struct ifreq *ifreq)
1004 {
1005         if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
1006                          sizeof(pdata->tstamp_config)))
1007                 return -EFAULT;
1008
1009         return 0;
1010 }
1011
1012 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1013                                       struct ifreq *ifreq)
1014 {
1015         struct hwtstamp_config config;
1016         unsigned int mac_tscr;
1017
1018         if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
1019                 return -EFAULT;
1020
1021         if (config.flags)
1022                 return -EINVAL;
1023
1024         mac_tscr = 0;
1025
1026         switch (config.tx_type) {
1027         case HWTSTAMP_TX_OFF:
1028                 break;
1029
1030         case HWTSTAMP_TX_ON:
1031                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1032                 break;
1033
1034         default:
1035                 return -ERANGE;
1036         }
1037
1038         switch (config.rx_filter) {
1039         case HWTSTAMP_FILTER_NONE:
1040                 break;
1041
1042         case HWTSTAMP_FILTER_ALL:
1043                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1044                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1045                 break;
1046
1047         /* PTP v2, UDP, any kind of event packet */
1048         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1049                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1050         /* PTP v1, UDP, any kind of event packet */
1051         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1052                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1053                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1054                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1055                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1056                 break;
1057
1058         /* PTP v2, UDP, Sync packet */
1059         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1060                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1061         /* PTP v1, UDP, Sync packet */
1062         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1063                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1064                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1065                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1066                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1067                 break;
1068
1069         /* PTP v2, UDP, Delay_req packet */
1070         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1071                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1072         /* PTP v1, UDP, Delay_req packet */
1073         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1074                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1075                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1076                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1077                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1078                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1079                 break;
1080
1081         /* 802.AS1, Ethernet, any kind of event packet */
1082         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1083                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1084                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1085                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1086                 break;
1087
1088         /* 802.AS1, Ethernet, Sync packet */
1089         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1090                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1091                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1092                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1093                 break;
1094
1095         /* 802.AS1, Ethernet, Delay_req packet */
1096         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1097                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1098                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1099                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1100                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1101                 break;
1102
1103         /* PTP v2/802.AS1, any layer, any kind of event packet */
1104         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1105                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1106                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1107                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1108                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1109                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1110                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1111                 break;
1112
1113         /* PTP v2/802.AS1, any layer, Sync packet */
1114         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1115                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1116                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1117                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1118                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1119                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1120                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1121                 break;
1122
1123         /* PTP v2/802.AS1, any layer, Delay_req packet */
1124         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1125                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1126                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1127                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1128                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1129                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1130                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1131                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1132                 break;
1133
1134         default:
1135                 return -ERANGE;
1136         }
1137
1138         pdata->hw_if.config_tstamp(pdata, mac_tscr);
1139
1140         memcpy(&pdata->tstamp_config, &config, sizeof(config));
1141
1142         return 0;
1143 }
1144
1145 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1146                                 struct sk_buff *skb,
1147                                 struct xgbe_packet_data *packet)
1148 {
1149         unsigned long flags;
1150
1151         if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1152                 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1153                 if (pdata->tx_tstamp_skb) {
1154                         /* Another timestamp in progress, ignore this one */
1155                         XGMAC_SET_BITS(packet->attributes,
1156                                        TX_PACKET_ATTRIBUTES, PTP, 0);
1157                 } else {
1158                         pdata->tx_tstamp_skb = skb_get(skb);
1159                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1160                 }
1161                 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1162         }
1163
1164         if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1165                 skb_tx_timestamp(skb);
1166 }
1167
1168 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1169 {
1170         if (vlan_tx_tag_present(skb))
1171                 packet->vlan_ctag = vlan_tx_tag_get(skb);
1172 }
1173
1174 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1175 {
1176         int ret;
1177
1178         if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1179                             TSO_ENABLE))
1180                 return 0;
1181
1182         ret = skb_cow_head(skb, 0);
1183         if (ret)
1184                 return ret;
1185
1186         packet->header_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1187         packet->tcp_header_len = tcp_hdrlen(skb);
1188         packet->tcp_payload_len = skb->len - packet->header_len;
1189         packet->mss = skb_shinfo(skb)->gso_size;
1190         DBGPR("  packet->header_len=%u\n", packet->header_len);
1191         DBGPR("  packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1192               packet->tcp_header_len, packet->tcp_payload_len);
1193         DBGPR("  packet->mss=%u\n", packet->mss);
1194
1195         /* Update the number of packets that will ultimately be transmitted
1196          * along with the extra bytes for each extra packet
1197          */
1198         packet->tx_packets = skb_shinfo(skb)->gso_segs;
1199         packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1200
1201         return 0;
1202 }
1203
1204 static int xgbe_is_tso(struct sk_buff *skb)
1205 {
1206         if (skb->ip_summed != CHECKSUM_PARTIAL)
1207                 return 0;
1208
1209         if (!skb_is_gso(skb))
1210                 return 0;
1211
1212         DBGPR("  TSO packet to be processed\n");
1213
1214         return 1;
1215 }
1216
1217 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1218                              struct xgbe_ring *ring, struct sk_buff *skb,
1219                              struct xgbe_packet_data *packet)
1220 {
1221         struct skb_frag_struct *frag;
1222         unsigned int context_desc;
1223         unsigned int len;
1224         unsigned int i;
1225
1226         packet->skb = skb;
1227
1228         context_desc = 0;
1229         packet->rdesc_count = 0;
1230
1231         packet->tx_packets = 1;
1232         packet->tx_bytes = skb->len;
1233
1234         if (xgbe_is_tso(skb)) {
1235                 /* TSO requires an extra descriptor if mss is different */
1236                 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1237                         context_desc = 1;
1238                         packet->rdesc_count++;
1239                 }
1240
1241                 /* TSO requires an extra descriptor for TSO header */
1242                 packet->rdesc_count++;
1243
1244                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1245                                TSO_ENABLE, 1);
1246                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1247                                CSUM_ENABLE, 1);
1248         } else if (skb->ip_summed == CHECKSUM_PARTIAL)
1249                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1250                                CSUM_ENABLE, 1);
1251
1252         if (vlan_tx_tag_present(skb)) {
1253                 /* VLAN requires an extra descriptor if tag is different */
1254                 if (vlan_tx_tag_get(skb) != ring->tx.cur_vlan_ctag)
1255                         /* We can share with the TSO context descriptor */
1256                         if (!context_desc) {
1257                                 context_desc = 1;
1258                                 packet->rdesc_count++;
1259                         }
1260
1261                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1262                                VLAN_CTAG, 1);
1263         }
1264
1265         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1266             (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1267                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1268                                PTP, 1);
1269
1270         for (len = skb_headlen(skb); len;) {
1271                 packet->rdesc_count++;
1272                 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1273         }
1274
1275         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1276                 frag = &skb_shinfo(skb)->frags[i];
1277                 for (len = skb_frag_size(frag); len; ) {
1278                         packet->rdesc_count++;
1279                         len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1280                 }
1281         }
1282 }
1283
1284 static int xgbe_open(struct net_device *netdev)
1285 {
1286         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1287         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1288         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1289         struct xgbe_channel *channel = NULL;
1290         unsigned int i = 0;
1291         int ret;
1292
1293         DBGPR("-->xgbe_open\n");
1294
1295         /* Initialize the phy */
1296         ret = xgbe_phy_init(pdata);
1297         if (ret)
1298                 return ret;
1299
1300         /* Enable the clocks */
1301         ret = clk_prepare_enable(pdata->sysclk);
1302         if (ret) {
1303                 netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1304                 goto err_phy_init;
1305         }
1306
1307         ret = clk_prepare_enable(pdata->ptpclk);
1308         if (ret) {
1309                 netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1310                 goto err_sysclk;
1311         }
1312
1313         /* Calculate the Rx buffer size before allocating rings */
1314         ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1315         if (ret < 0)
1316                 goto err_ptpclk;
1317         pdata->rx_buf_size = ret;
1318
1319         /* Allocate the channel and ring structures */
1320         ret = xgbe_alloc_channels(pdata);
1321         if (ret)
1322                 goto err_ptpclk;
1323
1324         /* Allocate the ring descriptors and buffers */
1325         ret = desc_if->alloc_ring_resources(pdata);
1326         if (ret)
1327                 goto err_channels;
1328
1329         /* Initialize the device restart and Tx timestamp work struct */
1330         INIT_WORK(&pdata->restart_work, xgbe_restart);
1331         INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1332
1333         /* Request interrupts */
1334         ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
1335                                netdev->name, pdata);
1336         if (ret) {
1337                 netdev_alert(netdev, "error requesting irq %d\n",
1338                              pdata->dev_irq);
1339                 goto err_rings;
1340         }
1341
1342         if (pdata->per_channel_irq) {
1343                 channel = pdata->channel;
1344                 for (i = 0; i < pdata->channel_count; i++, channel++) {
1345                         snprintf(channel->dma_irq_name,
1346                                  sizeof(channel->dma_irq_name) - 1,
1347                                  "%s-TxRx-%u", netdev_name(netdev),
1348                                  channel->queue_index);
1349
1350                         ret = devm_request_irq(pdata->dev, channel->dma_irq,
1351                                                xgbe_dma_isr, 0,
1352                                                channel->dma_irq_name, channel);
1353                         if (ret) {
1354                                 netdev_alert(netdev,
1355                                              "error requesting irq %d\n",
1356                                              channel->dma_irq);
1357                                 goto err_irq;
1358                         }
1359                 }
1360         }
1361
1362         ret = xgbe_start(pdata);
1363         if (ret)
1364                 goto err_start;
1365
1366         DBGPR("<--xgbe_open\n");
1367
1368         return 0;
1369
1370 err_start:
1371         hw_if->exit(pdata);
1372
1373 err_irq:
1374         if (pdata->per_channel_irq) {
1375                 /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
1376                 for (i--, channel--; i < pdata->channel_count; i--, channel--)
1377                         devm_free_irq(pdata->dev, channel->dma_irq, channel);
1378         }
1379
1380         devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1381
1382 err_rings:
1383         desc_if->free_ring_resources(pdata);
1384
1385 err_channels:
1386         xgbe_free_channels(pdata);
1387
1388 err_ptpclk:
1389         clk_disable_unprepare(pdata->ptpclk);
1390
1391 err_sysclk:
1392         clk_disable_unprepare(pdata->sysclk);
1393
1394 err_phy_init:
1395         xgbe_phy_exit(pdata);
1396
1397         return ret;
1398 }
1399
1400 static int xgbe_close(struct net_device *netdev)
1401 {
1402         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1403         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1404         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1405         struct xgbe_channel *channel;
1406         unsigned int i;
1407
1408         DBGPR("-->xgbe_close\n");
1409
1410         /* Stop the device */
1411         xgbe_stop(pdata);
1412
1413         /* Issue software reset to device */
1414         hw_if->exit(pdata);
1415
1416         /* Free the ring descriptors and buffers */
1417         desc_if->free_ring_resources(pdata);
1418
1419         /* Release the interrupts */
1420         devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1421         if (pdata->per_channel_irq) {
1422                 channel = pdata->channel;
1423                 for (i = 0; i < pdata->channel_count; i++, channel++)
1424                         devm_free_irq(pdata->dev, channel->dma_irq, channel);
1425         }
1426
1427         /* Free the channel and ring structures */
1428         xgbe_free_channels(pdata);
1429
1430         /* Disable the clocks */
1431         clk_disable_unprepare(pdata->ptpclk);
1432         clk_disable_unprepare(pdata->sysclk);
1433
1434         /* Release the phy */
1435         xgbe_phy_exit(pdata);
1436
1437         DBGPR("<--xgbe_close\n");
1438
1439         return 0;
1440 }
1441
1442 static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
1443 {
1444         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1445         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1446         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1447         struct xgbe_channel *channel;
1448         struct xgbe_ring *ring;
1449         struct xgbe_packet_data *packet;
1450         struct netdev_queue *txq;
1451         unsigned long flags;
1452         int ret;
1453
1454         DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
1455
1456         channel = pdata->channel + skb->queue_mapping;
1457         txq = netdev_get_tx_queue(netdev, channel->queue_index);
1458         ring = channel->tx_ring;
1459         packet = &ring->packet_data;
1460
1461         ret = NETDEV_TX_OK;
1462
1463         spin_lock_irqsave(&ring->lock, flags);
1464
1465         if (skb->len == 0) {
1466                 netdev_err(netdev, "empty skb received from stack\n");
1467                 dev_kfree_skb_any(skb);
1468                 goto tx_netdev_return;
1469         }
1470
1471         /* Calculate preliminary packet info */
1472         memset(packet, 0, sizeof(*packet));
1473         xgbe_packet_info(pdata, ring, skb, packet);
1474
1475         /* Check that there are enough descriptors available */
1476         ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
1477         if (ret)
1478                 goto tx_netdev_return;
1479
1480         ret = xgbe_prep_tso(skb, packet);
1481         if (ret) {
1482                 netdev_err(netdev, "error processing TSO packet\n");
1483                 dev_kfree_skb_any(skb);
1484                 goto tx_netdev_return;
1485         }
1486         xgbe_prep_vlan(skb, packet);
1487
1488         if (!desc_if->map_tx_skb(channel, skb)) {
1489                 dev_kfree_skb_any(skb);
1490                 goto tx_netdev_return;
1491         }
1492
1493         xgbe_prep_tx_tstamp(pdata, skb, packet);
1494
1495         /* Report on the actual number of bytes (to be) sent */
1496         netdev_tx_sent_queue(txq, packet->tx_bytes);
1497
1498         /* Configure required descriptor fields for transmission */
1499         hw_if->dev_xmit(channel);
1500
1501 #ifdef XGMAC_ENABLE_TX_PKT_DUMP
1502         xgbe_print_pkt(netdev, skb, true);
1503 #endif
1504
1505         /* Stop the queue in advance if there may not be enough descriptors */
1506         xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
1507
1508         ret = NETDEV_TX_OK;
1509
1510 tx_netdev_return:
1511         spin_unlock_irqrestore(&ring->lock, flags);
1512
1513         DBGPR("<--xgbe_xmit\n");
1514
1515         return ret;
1516 }
1517
1518 static void xgbe_set_rx_mode(struct net_device *netdev)
1519 {
1520         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1521         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1522         unsigned int pr_mode, am_mode;
1523
1524         DBGPR("-->xgbe_set_rx_mode\n");
1525
1526         pr_mode = ((netdev->flags & IFF_PROMISC) != 0);
1527         am_mode = ((netdev->flags & IFF_ALLMULTI) != 0);
1528
1529         hw_if->set_promiscuous_mode(pdata, pr_mode);
1530         hw_if->set_all_multicast_mode(pdata, am_mode);
1531
1532         hw_if->add_mac_addresses(pdata);
1533
1534         DBGPR("<--xgbe_set_rx_mode\n");
1535 }
1536
1537 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
1538 {
1539         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1540         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1541         struct sockaddr *saddr = addr;
1542
1543         DBGPR("-->xgbe_set_mac_address\n");
1544
1545         if (!is_valid_ether_addr(saddr->sa_data))
1546                 return -EADDRNOTAVAIL;
1547
1548         memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len);
1549
1550         hw_if->set_mac_address(pdata, netdev->dev_addr);
1551
1552         DBGPR("<--xgbe_set_mac_address\n");
1553
1554         return 0;
1555 }
1556
1557 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
1558 {
1559         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1560         int ret;
1561
1562         switch (cmd) {
1563         case SIOCGHWTSTAMP:
1564                 ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
1565                 break;
1566
1567         case SIOCSHWTSTAMP:
1568                 ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
1569                 break;
1570
1571         default:
1572                 ret = -EOPNOTSUPP;
1573         }
1574
1575         return ret;
1576 }
1577
1578 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
1579 {
1580         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1581         int ret;
1582
1583         DBGPR("-->xgbe_change_mtu\n");
1584
1585         ret = xgbe_calc_rx_buf_size(netdev, mtu);
1586         if (ret < 0)
1587                 return ret;
1588
1589         pdata->rx_buf_size = ret;
1590         netdev->mtu = mtu;
1591
1592         xgbe_restart_dev(pdata, 0);
1593
1594         DBGPR("<--xgbe_change_mtu\n");
1595
1596         return 0;
1597 }
1598
1599 static struct rtnl_link_stats64 *xgbe_get_stats64(struct net_device *netdev,
1600                                                   struct rtnl_link_stats64 *s)
1601 {
1602         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1603         struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
1604
1605         DBGPR("-->%s\n", __func__);
1606
1607         pdata->hw_if.read_mmc_stats(pdata);
1608
1609         s->rx_packets = pstats->rxframecount_gb;
1610         s->rx_bytes = pstats->rxoctetcount_gb;
1611         s->rx_errors = pstats->rxframecount_gb -
1612                        pstats->rxbroadcastframes_g -
1613                        pstats->rxmulticastframes_g -
1614                        pstats->rxunicastframes_g;
1615         s->multicast = pstats->rxmulticastframes_g;
1616         s->rx_length_errors = pstats->rxlengtherror;
1617         s->rx_crc_errors = pstats->rxcrcerror;
1618         s->rx_fifo_errors = pstats->rxfifooverflow;
1619
1620         s->tx_packets = pstats->txframecount_gb;
1621         s->tx_bytes = pstats->txoctetcount_gb;
1622         s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
1623         s->tx_dropped = netdev->stats.tx_dropped;
1624
1625         DBGPR("<--%s\n", __func__);
1626
1627         return s;
1628 }
1629
1630 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
1631                                 u16 vid)
1632 {
1633         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1634         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1635
1636         DBGPR("-->%s\n", __func__);
1637
1638         set_bit(vid, pdata->active_vlans);
1639         hw_if->update_vlan_hash_table(pdata);
1640
1641         DBGPR("<--%s\n", __func__);
1642
1643         return 0;
1644 }
1645
1646 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
1647                                  u16 vid)
1648 {
1649         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1650         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1651
1652         DBGPR("-->%s\n", __func__);
1653
1654         clear_bit(vid, pdata->active_vlans);
1655         hw_if->update_vlan_hash_table(pdata);
1656
1657         DBGPR("<--%s\n", __func__);
1658
1659         return 0;
1660 }
1661
1662 #ifdef CONFIG_NET_POLL_CONTROLLER
1663 static void xgbe_poll_controller(struct net_device *netdev)
1664 {
1665         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1666         struct xgbe_channel *channel;
1667         unsigned int i;
1668
1669         DBGPR("-->xgbe_poll_controller\n");
1670
1671         if (pdata->per_channel_irq) {
1672                 channel = pdata->channel;
1673                 for (i = 0; i < pdata->channel_count; i++, channel++)
1674                         xgbe_dma_isr(channel->dma_irq, channel);
1675         } else {
1676                 disable_irq(pdata->dev_irq);
1677                 xgbe_isr(pdata->dev_irq, pdata);
1678                 enable_irq(pdata->dev_irq);
1679         }
1680
1681         DBGPR("<--xgbe_poll_controller\n");
1682 }
1683 #endif /* End CONFIG_NET_POLL_CONTROLLER */
1684
1685 static int xgbe_setup_tc(struct net_device *netdev, u8 tc)
1686 {
1687         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1688         unsigned int offset, queue;
1689         u8 i;
1690
1691         if (tc && (tc != pdata->hw_feat.tc_cnt))
1692                 return -EINVAL;
1693
1694         if (tc) {
1695                 netdev_set_num_tc(netdev, tc);
1696                 for (i = 0, queue = 0, offset = 0; i < tc; i++) {
1697                         while ((queue < pdata->tx_q_count) &&
1698                                (pdata->q2tc_map[queue] == i))
1699                                 queue++;
1700
1701                         DBGPR("  TC%u using TXq%u-%u\n", i, offset, queue - 1);
1702                         netdev_set_tc_queue(netdev, i, queue - offset, offset);
1703                         offset = queue;
1704                 }
1705         } else {
1706                 netdev_reset_tc(netdev);
1707         }
1708
1709         return 0;
1710 }
1711
1712 static int xgbe_set_features(struct net_device *netdev,
1713                              netdev_features_t features)
1714 {
1715         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1716         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1717         netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
1718         int ret = 0;
1719
1720         rxhash = pdata->netdev_features & NETIF_F_RXHASH;
1721         rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
1722         rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
1723         rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
1724
1725         if ((features & NETIF_F_RXHASH) && !rxhash)
1726                 ret = hw_if->enable_rss(pdata);
1727         else if (!(features & NETIF_F_RXHASH) && rxhash)
1728                 ret = hw_if->disable_rss(pdata);
1729         if (ret)
1730                 return ret;
1731
1732         if ((features & NETIF_F_RXCSUM) && !rxcsum)
1733                 hw_if->enable_rx_csum(pdata);
1734         else if (!(features & NETIF_F_RXCSUM) && rxcsum)
1735                 hw_if->disable_rx_csum(pdata);
1736
1737         if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
1738                 hw_if->enable_rx_vlan_stripping(pdata);
1739         else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
1740                 hw_if->disable_rx_vlan_stripping(pdata);
1741
1742         if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
1743                 hw_if->enable_rx_vlan_filtering(pdata);
1744         else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
1745                 hw_if->disable_rx_vlan_filtering(pdata);
1746
1747         pdata->netdev_features = features;
1748
1749         DBGPR("<--xgbe_set_features\n");
1750
1751         return 0;
1752 }
1753
1754 static const struct net_device_ops xgbe_netdev_ops = {
1755         .ndo_open               = xgbe_open,
1756         .ndo_stop               = xgbe_close,
1757         .ndo_start_xmit         = xgbe_xmit,
1758         .ndo_set_rx_mode        = xgbe_set_rx_mode,
1759         .ndo_set_mac_address    = xgbe_set_mac_address,
1760         .ndo_validate_addr      = eth_validate_addr,
1761         .ndo_do_ioctl           = xgbe_ioctl,
1762         .ndo_change_mtu         = xgbe_change_mtu,
1763         .ndo_get_stats64        = xgbe_get_stats64,
1764         .ndo_vlan_rx_add_vid    = xgbe_vlan_rx_add_vid,
1765         .ndo_vlan_rx_kill_vid   = xgbe_vlan_rx_kill_vid,
1766 #ifdef CONFIG_NET_POLL_CONTROLLER
1767         .ndo_poll_controller    = xgbe_poll_controller,
1768 #endif
1769         .ndo_setup_tc           = xgbe_setup_tc,
1770         .ndo_set_features       = xgbe_set_features,
1771 };
1772
1773 struct net_device_ops *xgbe_get_netdev_ops(void)
1774 {
1775         return (struct net_device_ops *)&xgbe_netdev_ops;
1776 }
1777
1778 static void xgbe_rx_refresh(struct xgbe_channel *channel)
1779 {
1780         struct xgbe_prv_data *pdata = channel->pdata;
1781         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1782         struct xgbe_ring *ring = channel->rx_ring;
1783         struct xgbe_ring_data *rdata;
1784
1785         desc_if->realloc_rx_buffer(channel);
1786
1787         /* Update the Rx Tail Pointer Register with address of
1788          * the last cleaned entry */
1789         rdata = XGBE_GET_DESC_DATA(ring, ring->rx.realloc_index - 1);
1790         XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1791                           lower_32_bits(rdata->rdesc_dma));
1792 }
1793
1794 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
1795                                        struct xgbe_ring_data *rdata,
1796                                        unsigned int *len)
1797 {
1798         struct net_device *netdev = pdata->netdev;
1799         struct sk_buff *skb;
1800         u8 *packet;
1801         unsigned int copy_len;
1802
1803         skb = netdev_alloc_skb_ip_align(netdev, rdata->rx.hdr.dma_len);
1804         if (!skb)
1805                 return NULL;
1806
1807         packet = page_address(rdata->rx.hdr.pa.pages) +
1808                  rdata->rx.hdr.pa.pages_offset;
1809         copy_len = (rdata->rx.hdr_len) ? rdata->rx.hdr_len : *len;
1810         copy_len = min(rdata->rx.hdr.dma_len, copy_len);
1811         skb_copy_to_linear_data(skb, packet, copy_len);
1812         skb_put(skb, copy_len);
1813
1814         *len -= copy_len;
1815
1816         return skb;
1817 }
1818
1819 static int xgbe_tx_poll(struct xgbe_channel *channel)
1820 {
1821         struct xgbe_prv_data *pdata = channel->pdata;
1822         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1823         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1824         struct xgbe_ring *ring = channel->tx_ring;
1825         struct xgbe_ring_data *rdata;
1826         struct xgbe_ring_desc *rdesc;
1827         struct net_device *netdev = pdata->netdev;
1828         struct netdev_queue *txq;
1829         unsigned long flags;
1830         int processed = 0;
1831         unsigned int tx_packets = 0, tx_bytes = 0;
1832
1833         DBGPR("-->xgbe_tx_poll\n");
1834
1835         /* Nothing to do if there isn't a Tx ring for this channel */
1836         if (!ring)
1837                 return 0;
1838
1839         txq = netdev_get_tx_queue(netdev, channel->queue_index);
1840
1841         spin_lock_irqsave(&ring->lock, flags);
1842
1843         while ((processed < XGBE_TX_DESC_MAX_PROC) &&
1844                (ring->dirty != ring->cur)) {
1845                 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
1846                 rdesc = rdata->rdesc;
1847
1848                 if (!hw_if->tx_complete(rdesc))
1849                         break;
1850
1851                 /* Make sure descriptor fields are read after reading the OWN
1852                  * bit */
1853                 rmb();
1854
1855 #ifdef XGMAC_ENABLE_TX_DESC_DUMP
1856                 xgbe_dump_tx_desc(ring, ring->dirty, 1, 0);
1857 #endif
1858
1859                 if (hw_if->is_last_desc(rdesc)) {
1860                         tx_packets += rdata->tx.packets;
1861                         tx_bytes += rdata->tx.bytes;
1862                 }
1863
1864                 /* Free the SKB and reset the descriptor for re-use */
1865                 desc_if->unmap_rdata(pdata, rdata);
1866                 hw_if->tx_desc_reset(rdata);
1867
1868                 processed++;
1869                 ring->dirty++;
1870         }
1871
1872         if (!processed)
1873                 goto unlock;
1874
1875         netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
1876
1877         if ((ring->tx.queue_stopped == 1) &&
1878             (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
1879                 ring->tx.queue_stopped = 0;
1880                 netif_tx_wake_queue(txq);
1881         }
1882
1883         DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
1884
1885 unlock:
1886         spin_unlock_irqrestore(&ring->lock, flags);
1887
1888         return processed;
1889 }
1890
1891 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
1892 {
1893         struct xgbe_prv_data *pdata = channel->pdata;
1894         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1895         struct xgbe_ring *ring = channel->rx_ring;
1896         struct xgbe_ring_data *rdata;
1897         struct xgbe_packet_data *packet;
1898         struct net_device *netdev = pdata->netdev;
1899         struct napi_struct *napi;
1900         struct sk_buff *skb;
1901         struct skb_shared_hwtstamps *hwtstamps;
1902         unsigned int incomplete, error, context_next, context;
1903         unsigned int len, put_len, max_len;
1904         unsigned int received = 0;
1905         int packet_count = 0;
1906
1907         DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
1908
1909         /* Nothing to do if there isn't a Rx ring for this channel */
1910         if (!ring)
1911                 return 0;
1912
1913         napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
1914
1915         rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1916         packet = &ring->packet_data;
1917         while (packet_count < budget) {
1918                 DBGPR("  cur = %d\n", ring->cur);
1919
1920                 /* First time in loop see if we need to restore state */
1921                 if (!received && rdata->state_saved) {
1922                         incomplete = rdata->state.incomplete;
1923                         context_next = rdata->state.context_next;
1924                         skb = rdata->state.skb;
1925                         error = rdata->state.error;
1926                         len = rdata->state.len;
1927                 } else {
1928                         memset(packet, 0, sizeof(*packet));
1929                         incomplete = 0;
1930                         context_next = 0;
1931                         skb = NULL;
1932                         error = 0;
1933                         len = 0;
1934                 }
1935
1936 read_again:
1937                 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1938
1939                 if (ring->dirty > (XGBE_RX_DESC_CNT >> 3))
1940                         xgbe_rx_refresh(channel);
1941
1942                 if (hw_if->dev_read(channel))
1943                         break;
1944
1945                 received++;
1946                 ring->cur++;
1947                 ring->dirty++;
1948
1949                 incomplete = XGMAC_GET_BITS(packet->attributes,
1950                                             RX_PACKET_ATTRIBUTES,
1951                                             INCOMPLETE);
1952                 context_next = XGMAC_GET_BITS(packet->attributes,
1953                                               RX_PACKET_ATTRIBUTES,
1954                                               CONTEXT_NEXT);
1955                 context = XGMAC_GET_BITS(packet->attributes,
1956                                          RX_PACKET_ATTRIBUTES,
1957                                          CONTEXT);
1958
1959                 /* Earlier error, just drain the remaining data */
1960                 if ((incomplete || context_next) && error)
1961                         goto read_again;
1962
1963                 if (error || packet->errors) {
1964                         if (packet->errors)
1965                                 DBGPR("Error in received packet\n");
1966                         dev_kfree_skb(skb);
1967                         goto next_packet;
1968                 }
1969
1970                 if (!context) {
1971                         put_len = rdata->rx.len - len;
1972                         len += put_len;
1973
1974                         if (!skb) {
1975                                 dma_sync_single_for_cpu(pdata->dev,
1976                                                         rdata->rx.hdr.dma,
1977                                                         rdata->rx.hdr.dma_len,
1978                                                         DMA_FROM_DEVICE);
1979
1980                                 skb = xgbe_create_skb(pdata, rdata, &put_len);
1981                                 if (!skb) {
1982                                         error = 1;
1983                                         goto skip_data;
1984                                 }
1985                         }
1986
1987                         if (put_len) {
1988                                 dma_sync_single_for_cpu(pdata->dev,
1989                                                         rdata->rx.buf.dma,
1990                                                         rdata->rx.buf.dma_len,
1991                                                         DMA_FROM_DEVICE);
1992
1993                                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1994                                                 rdata->rx.buf.pa.pages,
1995                                                 rdata->rx.buf.pa.pages_offset,
1996                                                 put_len, rdata->rx.buf.dma_len);
1997                                 rdata->rx.buf.pa.pages = NULL;
1998                         }
1999                 }
2000
2001 skip_data:
2002                 if (incomplete || context_next)
2003                         goto read_again;
2004
2005                 if (!skb)
2006                         goto next_packet;
2007
2008                 /* Be sure we don't exceed the configured MTU */
2009                 max_len = netdev->mtu + ETH_HLEN;
2010                 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2011                     (skb->protocol == htons(ETH_P_8021Q)))
2012                         max_len += VLAN_HLEN;
2013
2014                 if (skb->len > max_len) {
2015                         DBGPR("packet length exceeds configured MTU\n");
2016                         dev_kfree_skb(skb);
2017                         goto next_packet;
2018                 }
2019
2020 #ifdef XGMAC_ENABLE_RX_PKT_DUMP
2021                 xgbe_print_pkt(netdev, skb, false);
2022 #endif
2023
2024                 skb_checksum_none_assert(skb);
2025                 if (XGMAC_GET_BITS(packet->attributes,
2026                                    RX_PACKET_ATTRIBUTES, CSUM_DONE))
2027                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2028
2029                 if (XGMAC_GET_BITS(packet->attributes,
2030                                    RX_PACKET_ATTRIBUTES, VLAN_CTAG))
2031                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2032                                                packet->vlan_ctag);
2033
2034                 if (XGMAC_GET_BITS(packet->attributes,
2035                                    RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
2036                         u64 nsec;
2037
2038                         nsec = timecounter_cyc2time(&pdata->tstamp_tc,
2039                                                     packet->rx_tstamp);
2040                         hwtstamps = skb_hwtstamps(skb);
2041                         hwtstamps->hwtstamp = ns_to_ktime(nsec);
2042                 }
2043
2044                 if (XGMAC_GET_BITS(packet->attributes,
2045                                    RX_PACKET_ATTRIBUTES, RSS_HASH))
2046                         skb_set_hash(skb, packet->rss_hash,
2047                                      packet->rss_hash_type);
2048
2049                 skb->dev = netdev;
2050                 skb->protocol = eth_type_trans(skb, netdev);
2051                 skb_record_rx_queue(skb, channel->queue_index);
2052                 skb_mark_napi_id(skb, napi);
2053
2054                 netdev->last_rx = jiffies;
2055                 napi_gro_receive(napi, skb);
2056
2057 next_packet:
2058                 packet_count++;
2059         }
2060
2061         /* Check if we need to save state before leaving */
2062         if (received && (incomplete || context_next)) {
2063                 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2064                 rdata->state_saved = 1;
2065                 rdata->state.incomplete = incomplete;
2066                 rdata->state.context_next = context_next;
2067                 rdata->state.skb = skb;
2068                 rdata->state.len = len;
2069                 rdata->state.error = error;
2070         }
2071
2072         DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2073
2074         return packet_count;
2075 }
2076
2077 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2078 {
2079         struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2080                                                     napi);
2081         int processed = 0;
2082
2083         DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2084
2085         /* Cleanup Tx ring first */
2086         xgbe_tx_poll(channel);
2087
2088         /* Process Rx ring next */
2089         processed = xgbe_rx_poll(channel, budget);
2090
2091         /* If we processed everything, we are done */
2092         if (processed < budget) {
2093                 /* Turn off polling */
2094                 napi_complete(napi);
2095
2096                 /* Enable Tx and Rx interrupts */
2097                 enable_irq(channel->dma_irq);
2098         }
2099
2100         DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2101
2102         return processed;
2103 }
2104
2105 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2106 {
2107         struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2108                                                    napi);
2109         struct xgbe_channel *channel;
2110         int ring_budget;
2111         int processed, last_processed;
2112         unsigned int i;
2113
2114         DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2115
2116         processed = 0;
2117         ring_budget = budget / pdata->rx_ring_count;
2118         do {
2119                 last_processed = processed;
2120
2121                 channel = pdata->channel;
2122                 for (i = 0; i < pdata->channel_count; i++, channel++) {
2123                         /* Cleanup Tx ring first */
2124                         xgbe_tx_poll(channel);
2125
2126                         /* Process Rx ring next */
2127                         if (ring_budget > (budget - processed))
2128                                 ring_budget = budget - processed;
2129                         processed += xgbe_rx_poll(channel, ring_budget);
2130                 }
2131         } while ((processed < budget) && (processed != last_processed));
2132
2133         /* If we processed everything, we are done */
2134         if (processed < budget) {
2135                 /* Turn off polling */
2136                 napi_complete(napi);
2137
2138                 /* Enable Tx and Rx interrupts */
2139                 xgbe_enable_rx_tx_ints(pdata);
2140         }
2141
2142         DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2143
2144         return processed;
2145 }
2146
2147 void xgbe_dump_tx_desc(struct xgbe_ring *ring, unsigned int idx,
2148                        unsigned int count, unsigned int flag)
2149 {
2150         struct xgbe_ring_data *rdata;
2151         struct xgbe_ring_desc *rdesc;
2152
2153         while (count--) {
2154                 rdata = XGBE_GET_DESC_DATA(ring, idx);
2155                 rdesc = rdata->rdesc;
2156                 pr_alert("TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2157                          (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2158                          le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2159                          le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2160                 idx++;
2161         }
2162 }
2163
2164 void xgbe_dump_rx_desc(struct xgbe_ring *ring, struct xgbe_ring_desc *desc,
2165                        unsigned int idx)
2166 {
2167         pr_alert("RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n", idx,
2168                  le32_to_cpu(desc->desc0), le32_to_cpu(desc->desc1),
2169                  le32_to_cpu(desc->desc2), le32_to_cpu(desc->desc3));
2170 }
2171
2172 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2173 {
2174         struct ethhdr *eth = (struct ethhdr *)skb->data;
2175         unsigned char *buf = skb->data;
2176         unsigned char buffer[128];
2177         unsigned int i, j;
2178
2179         netdev_alert(netdev, "\n************** SKB dump ****************\n");
2180
2181         netdev_alert(netdev, "%s packet of %d bytes\n",
2182                      (tx_rx ? "TX" : "RX"), skb->len);
2183
2184         netdev_alert(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
2185         netdev_alert(netdev, "Src MAC addr: %pM\n", eth->h_source);
2186         netdev_alert(netdev, "Protocol: 0x%04hx\n", ntohs(eth->h_proto));
2187
2188         for (i = 0, j = 0; i < skb->len;) {
2189                 j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx",
2190                               buf[i++]);
2191
2192                 if ((i % 32) == 0) {
2193                         netdev_alert(netdev, "  0x%04x: %s\n", i - 32, buffer);
2194                         j = 0;
2195                 } else if ((i % 16) == 0) {
2196                         buffer[j++] = ' ';
2197                         buffer[j++] = ' ';
2198                 } else if ((i % 4) == 0) {
2199                         buffer[j++] = ' ';
2200                 }
2201         }
2202         if (i % 32)
2203                 netdev_alert(netdev, "  0x%04x: %s\n", i - (i % 32), buffer);
2204
2205         netdev_alert(netdev, "\n************** SKB dump ****************\n");
2206 }