2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 * There are a lot of defines in here that are unused and/or have cryptic
24 * names. Please leave them alone, as they're the closest thing we have
25 * to a spec from Attansic at present. *ahem* -- CHS
31 #include <linux/types.h>
32 #include <linux/mii.h>
37 /* function prototypes needed by multiple files */
38 s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw);
39 s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data);
40 s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
41 s32 atl1_read_mac_addr(struct atl1_hw *hw);
42 s32 atl1_init_hw(struct atl1_hw *hw);
43 s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
44 s32 atl1_set_speed_and_duplex(struct atl1_hw *hw, u16 speed, u16 duplex);
45 u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
46 void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
47 s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data);
48 void atl1_set_mac_addr(struct atl1_hw *hw);
49 s32 atl1_phy_enter_power_saving(struct atl1_hw *hw);
50 s32 atl1_reset_hw(struct atl1_hw *hw);
51 void atl1_check_options(struct atl1_adapter *adapter);
53 /* register definitions */
54 #define REG_PCIE_CAP_LIST 0x58
56 #define REG_VPD_CAP 0x6C
57 #define VPD_CAP_ID_MASK 0xff
58 #define VPD_CAP_ID_SHIFT 0
59 #define VPD_CAP_NEXT_PTR_MASK 0xFF
60 #define VPD_CAP_NEXT_PTR_SHIFT 8
61 #define VPD_CAP_VPD_ADDR_MASK 0x7FFF
62 #define VPD_CAP_VPD_ADDR_SHIFT 16
63 #define VPD_CAP_VPD_FLAG 0x80000000
65 #define REG_VPD_DATA 0x70
67 #define REG_SPI_FLASH_CTRL 0x200
68 #define SPI_FLASH_CTRL_STS_NON_RDY 0x1
69 #define SPI_FLASH_CTRL_STS_WEN 0x2
70 #define SPI_FLASH_CTRL_STS_WPEN 0x80
71 #define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
72 #define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
73 #define SPI_FLASH_CTRL_INS_MASK 0x7
74 #define SPI_FLASH_CTRL_INS_SHIFT 8
75 #define SPI_FLASH_CTRL_START 0x800
76 #define SPI_FLASH_CTRL_EN_VPD 0x2000
77 #define SPI_FLASH_CTRL_LDSTART 0x8000
78 #define SPI_FLASH_CTRL_CS_HI_MASK 0x3
79 #define SPI_FLASH_CTRL_CS_HI_SHIFT 16
80 #define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
81 #define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
82 #define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
83 #define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
84 #define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
85 #define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
86 #define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
87 #define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
88 #define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
89 #define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
90 #define SPI_FLASH_CTRL_WAIT_READY 0x10000000
92 #define REG_SPI_ADDR 0x204
94 #define REG_SPI_DATA 0x208
96 #define REG_SPI_FLASH_CONFIG 0x20C
97 #define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
98 #define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
99 #define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
100 #define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
101 #define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
103 #define REG_SPI_FLASH_OP_PROGRAM 0x210
104 #define REG_SPI_FLASH_OP_SC_ERASE 0x211
105 #define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
106 #define REG_SPI_FLASH_OP_RDID 0x213
107 #define REG_SPI_FLASH_OP_WREN 0x214
108 #define REG_SPI_FLASH_OP_RDSR 0x215
109 #define REG_SPI_FLASH_OP_WRSR 0x216
110 #define REG_SPI_FLASH_OP_READ 0x217
112 #define REG_TWSI_CTRL 0x218
113 #define TWSI_CTRL_LD_OFFSET_MASK 0xFF
114 #define TWSI_CTRL_LD_OFFSET_SHIFT 0
115 #define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
116 #define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
117 #define TWSI_CTRL_SW_LDSTART 0x800
118 #define TWSI_CTRL_HW_LDSTART 0x1000
119 #define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
120 #define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
121 #define TWSI_CTRL_LD_EXIST 0x400000
122 #define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
123 #define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
124 #define TWSI_CTRL_FREQ_SEL_100K 0
125 #define TWSI_CTRL_FREQ_SEL_200K 1
126 #define TWSI_CTRL_FREQ_SEL_300K 2
127 #define TWSI_CTRL_FREQ_SEL_400K 3
128 #define TWSI_CTRL_SMB_SLV_ADDR
129 #define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
130 #define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
132 #define REG_PCIE_DEV_MISC_CTRL 0x21C
133 #define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
134 #define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
135 #define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
136 #define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
137 #define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
139 /* Selene Master Control Register */
140 #define REG_MASTER_CTRL 0x1400
141 #define MASTER_CTRL_SOFT_RST 0x1
142 #define MASTER_CTRL_MTIMER_EN 0x2
143 #define MASTER_CTRL_ITIMER_EN 0x4
144 #define MASTER_CTRL_MANUAL_INT 0x8
145 #define MASTER_CTRL_REV_NUM_SHIFT 16
146 #define MASTER_CTRL_REV_NUM_MASK 0xff
147 #define MASTER_CTRL_DEV_ID_SHIFT 24
148 #define MASTER_CTRL_DEV_ID_MASK 0xff
150 /* Timer Initial Value Register */
151 #define REG_MANUAL_TIMER_INIT 0x1404
153 /* IRQ ModeratorTimer Initial Value Register */
154 #define REG_IRQ_MODU_TIMER_INIT 0x1408
156 #define REG_GPHY_ENABLE 0x140C
158 /* IRQ Anti-Lost Timer Initial Value Register */
159 #define REG_CMBDISDMA_TIMER 0x140E
161 /* Block IDLE Status Register */
162 #define REG_IDLE_STATUS 0x1410
163 #define IDLE_STATUS_RXMAC 1
164 #define IDLE_STATUS_TXMAC 2
165 #define IDLE_STATUS_RXQ 4
166 #define IDLE_STATUS_TXQ 8
167 #define IDLE_STATUS_DMAR 0x10
168 #define IDLE_STATUS_DMAW 0x20
169 #define IDLE_STATUS_SMB 0x40
170 #define IDLE_STATUS_CMB 0x80
172 /* MDIO Control Register */
173 #define REG_MDIO_CTRL 0x1414
174 #define MDIO_DATA_MASK 0xffff
175 #define MDIO_DATA_SHIFT 0
176 #define MDIO_REG_ADDR_MASK 0x1f
177 #define MDIO_REG_ADDR_SHIFT 16
178 #define MDIO_RW 0x200000
179 #define MDIO_SUP_PREAMBLE 0x400000
180 #define MDIO_START 0x800000
181 #define MDIO_CLK_SEL_SHIFT 24
182 #define MDIO_CLK_25_4 0
183 #define MDIO_CLK_25_6 2
184 #define MDIO_CLK_25_8 3
185 #define MDIO_CLK_25_10 4
186 #define MDIO_CLK_25_14 5
187 #define MDIO_CLK_25_20 6
188 #define MDIO_CLK_25_28 7
189 #define MDIO_BUSY 0x8000000
190 #define MDIO_WAIT_TIMES 30
192 /* MII PHY Status Register */
193 #define REG_PHY_STATUS 0x1418
195 /* BIST Control and Status Register0 (for the Packet Memory) */
196 #define REG_BIST0_CTRL 0x141c
197 #define BIST0_NOW 0x1
198 #define BIST0_SRAM_FAIL 0x2
199 #define BIST0_FUSE_FLAG 0x4
200 #define REG_BIST1_CTRL 0x1420
201 #define BIST1_NOW 0x1
202 #define BIST1_SRAM_FAIL 0x2
203 #define BIST1_FUSE_FLAG 0x4
205 /* MAC Control Register */
206 #define REG_MAC_CTRL 0x1480
207 #define MAC_CTRL_TX_EN 1
208 #define MAC_CTRL_RX_EN 2
209 #define MAC_CTRL_TX_FLOW 4
210 #define MAC_CTRL_RX_FLOW 8
211 #define MAC_CTRL_LOOPBACK 0x10
212 #define MAC_CTRL_DUPLX 0x20
213 #define MAC_CTRL_ADD_CRC 0x40
214 #define MAC_CTRL_PAD 0x80
215 #define MAC_CTRL_LENCHK 0x100
216 #define MAC_CTRL_HUGE_EN 0x200
217 #define MAC_CTRL_PRMLEN_SHIFT 10
218 #define MAC_CTRL_PRMLEN_MASK 0xf
219 #define MAC_CTRL_RMV_VLAN 0x4000
220 #define MAC_CTRL_PROMIS_EN 0x8000
221 #define MAC_CTRL_TX_PAUSE 0x10000
222 #define MAC_CTRL_SCNT 0x20000
223 #define MAC_CTRL_SRST_TX 0x40000
224 #define MAC_CTRL_TX_SIMURST 0x80000
225 #define MAC_CTRL_SPEED_SHIFT 20
226 #define MAC_CTRL_SPEED_MASK 0x300000
227 #define MAC_CTRL_SPEED_1000 2
228 #define MAC_CTRL_SPEED_10_100 1
229 #define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
230 #define MAC_CTRL_TX_HUGE 0x800000
231 #define MAC_CTRL_RX_CHKSUM_EN 0x1000000
232 #define MAC_CTRL_MC_ALL_EN 0x2000000
233 #define MAC_CTRL_BC_EN 0x4000000
234 #define MAC_CTRL_DBG 0x8000000
236 /* MAC IPG/IFG Control Register */
237 #define REG_MAC_IPG_IFG 0x1484
238 #define MAC_IPG_IFG_IPGT_SHIFT 0
239 #define MAC_IPG_IFG_IPGT_MASK 0x7f
240 #define MAC_IPG_IFG_MIFG_SHIFT 8
241 #define MAC_IPG_IFG_MIFG_MASK 0xff
242 #define MAC_IPG_IFG_IPGR1_SHIFT 16
243 #define MAC_IPG_IFG_IPGR1_MASK 0x7f
244 #define MAC_IPG_IFG_IPGR2_SHIFT 24
245 #define MAC_IPG_IFG_IPGR2_MASK 0x7f
247 /* MAC STATION ADDRESS */
248 #define REG_MAC_STA_ADDR 0x1488
250 /* Hash table for multicast address */
251 #define REG_RX_HASH_TABLE 0x1490
253 /* MAC Half-Duplex Control Register */
254 #define REG_MAC_HALF_DUPLX_CTRL 0x1498
255 #define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0
256 #define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
257 #define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
258 #define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
259 #define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
260 #define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
261 #define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000
262 #define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000
263 #define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20
264 #define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
265 #define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24
266 #define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf
268 /* Maximum Frame Length Control Register */
269 #define REG_MTU 0x149c
271 /* Wake-On-Lan control register */
272 #define REG_WOL_CTRL 0x14a0
273 #define WOL_PATTERN_EN 0x00000001
274 #define WOL_PATTERN_PME_EN 0x00000002
275 #define WOL_MAGIC_EN 0x00000004
276 #define WOL_MAGIC_PME_EN 0x00000008
277 #define WOL_LINK_CHG_EN 0x00000010
278 #define WOL_LINK_CHG_PME_EN 0x00000020
279 #define WOL_PATTERN_ST 0x00000100
280 #define WOL_MAGIC_ST 0x00000200
281 #define WOL_LINKCHG_ST 0x00000400
282 #define WOL_CLK_SWITCH_EN 0x00008000
283 #define WOL_PT0_EN 0x00010000
284 #define WOL_PT1_EN 0x00020000
285 #define WOL_PT2_EN 0x00040000
286 #define WOL_PT3_EN 0x00080000
287 #define WOL_PT4_EN 0x00100000
288 #define WOL_PT5_EN 0x00200000
289 #define WOL_PT6_EN 0x00400000
291 /* WOL Length ( 2 DWORD ) */
292 #define REG_WOL_PATTERN_LEN 0x14a4
293 #define WOL_PT_LEN_MASK 0x7f
294 #define WOL_PT0_LEN_SHIFT 0
295 #define WOL_PT1_LEN_SHIFT 8
296 #define WOL_PT2_LEN_SHIFT 16
297 #define WOL_PT3_LEN_SHIFT 24
298 #define WOL_PT4_LEN_SHIFT 0
299 #define WOL_PT5_LEN_SHIFT 8
300 #define WOL_PT6_LEN_SHIFT 16
302 /* Internal SRAM Partition Register */
303 #define REG_SRAM_RFD_ADDR 0x1500
304 #define REG_SRAM_RFD_LEN (REG_SRAM_RFD_ADDR+ 4)
305 #define REG_SRAM_RRD_ADDR (REG_SRAM_RFD_ADDR+ 8)
306 #define REG_SRAM_RRD_LEN (REG_SRAM_RFD_ADDR+12)
307 #define REG_SRAM_TPD_ADDR (REG_SRAM_RFD_ADDR+16)
308 #define REG_SRAM_TPD_LEN (REG_SRAM_RFD_ADDR+20)
309 #define REG_SRAM_TRD_ADDR (REG_SRAM_RFD_ADDR+24)
310 #define REG_SRAM_TRD_LEN (REG_SRAM_RFD_ADDR+28)
311 #define REG_SRAM_RXF_ADDR (REG_SRAM_RFD_ADDR+32)
312 #define REG_SRAM_RXF_LEN (REG_SRAM_RFD_ADDR+36)
313 #define REG_SRAM_TXF_ADDR (REG_SRAM_RFD_ADDR+40)
314 #define REG_SRAM_TXF_LEN (REG_SRAM_RFD_ADDR+44)
315 #define REG_SRAM_TCPH_PATH_ADDR (REG_SRAM_RFD_ADDR+48)
316 #define SRAM_TCPH_ADDR_MASK 0x0fff
317 #define SRAM_TCPH_ADDR_SHIFT 0
318 #define SRAM_PATH_ADDR_MASK 0x0fff
319 #define SRAM_PATH_ADDR_SHIFT 16
321 /* Load Ptr Register */
322 #define REG_LOAD_PTR (REG_SRAM_RFD_ADDR+52)
324 /* Descriptor Control register */
325 #define REG_DESC_BASE_ADDR_HI 0x1540
326 #define REG_DESC_RFD_ADDR_LO (REG_DESC_BASE_ADDR_HI+4)
327 #define REG_DESC_RRD_ADDR_LO (REG_DESC_BASE_ADDR_HI+8)
328 #define REG_DESC_TPD_ADDR_LO (REG_DESC_BASE_ADDR_HI+12)
329 #define REG_DESC_CMB_ADDR_LO (REG_DESC_BASE_ADDR_HI+16)
330 #define REG_DESC_SMB_ADDR_LO (REG_DESC_BASE_ADDR_HI+20)
331 #define REG_DESC_RFD_RRD_RING_SIZE (REG_DESC_BASE_ADDR_HI+24)
332 #define DESC_RFD_RING_SIZE_MASK 0x7ff
333 #define DESC_RFD_RING_SIZE_SHIFT 0
334 #define DESC_RRD_RING_SIZE_MASK 0x7ff
335 #define DESC_RRD_RING_SIZE_SHIFT 16
336 #define REG_DESC_TPD_RING_SIZE (REG_DESC_BASE_ADDR_HI+28)
337 #define DESC_TPD_RING_SIZE_MASK 0x3ff
338 #define DESC_TPD_RING_SIZE_SHIFT 0
340 /* TXQ Control Register */
341 #define REG_TXQ_CTRL 0x1580
342 #define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0
343 #define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1f
344 #define TXQ_CTRL_EN 0x20
345 #define TXQ_CTRL_ENH_MODE 0x40
346 #define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8
347 #define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3f
348 #define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16
349 #define TXQ_CTRL_TXF_BURST_NUM_MASK 0xffff
351 /* Jumbo packet Threshold for task offload */
352 #define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584
353 #define TX_JUMBO_TASK_TH_MASK 0x7ff
354 #define TX_JUMBO_TASK_TH_SHIFT 0
355 #define TX_TPD_MIN_IPG_MASK 0x1f
356 #define TX_TPD_MIN_IPG_SHIFT 16
358 /* RXQ Control Register */
359 #define REG_RXQ_CTRL 0x15a0
360 #define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0
361 #define RXQ_CTRL_RFD_BURST_NUM_MASK 0xff
362 #define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8
363 #define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xff
364 #define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16
365 #define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1f
366 #define RXQ_CTRL_CUT_THRU_EN 0x40000000
367 #define RXQ_CTRL_EN 0x80000000
369 /* Rx jumbo packet threshold and rrd retirement timer */
370 #define REG_RXQ_JMBOSZ_RRDTIM (REG_RXQ_CTRL+ 4)
371 #define RXQ_JMBOSZ_TH_MASK 0x7ff
372 #define RXQ_JMBOSZ_TH_SHIFT 0
373 #define RXQ_JMBO_LKAH_MASK 0xf
374 #define RXQ_JMBO_LKAH_SHIFT 11
375 #define RXQ_RRD_TIMER_MASK 0xffff
376 #define RXQ_RRD_TIMER_SHIFT 16
378 /* RFD flow control register */
379 #define REG_RXQ_RXF_PAUSE_THRESH (REG_RXQ_CTRL+ 8)
380 #define RXQ_RXF_PAUSE_TH_HI_SHIFT 16
381 #define RXQ_RXF_PAUSE_TH_HI_MASK 0xfff
382 #define RXQ_RXF_PAUSE_TH_LO_SHIFT 0
383 #define RXQ_RXF_PAUSE_TH_LO_MASK 0xfff
385 /* RRD flow control register */
386 #define REG_RXQ_RRD_PAUSE_THRESH (REG_RXQ_CTRL+12)
387 #define RXQ_RRD_PAUSE_TH_HI_SHIFT 0
388 #define RXQ_RRD_PAUSE_TH_HI_MASK 0xfff
389 #define RXQ_RRD_PAUSE_TH_LO_SHIFT 16
390 #define RXQ_RRD_PAUSE_TH_LO_MASK 0xfff
392 /* DMA Engine Control Register */
393 #define REG_DMA_CTRL 0x15c0
394 #define DMA_CTRL_DMAR_IN_ORDER 0x1
395 #define DMA_CTRL_DMAR_ENH_ORDER 0x2
396 #define DMA_CTRL_DMAR_OUT_ORDER 0x4
397 #define DMA_CTRL_RCB_VALUE 0x8
398 #define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
399 #define DMA_CTRL_DMAR_BURST_LEN_MASK 7
400 #define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
401 #define DMA_CTRL_DMAW_BURST_LEN_MASK 7
402 #define DMA_CTRL_DMAR_EN 0x400
403 #define DMA_CTRL_DMAW_EN 0x800
405 /* CMB/SMB Control Register */
406 #define REG_CSMB_CTRL 0x15d0
407 #define CSMB_CTRL_CMB_NOW 1
408 #define CSMB_CTRL_SMB_NOW 2
409 #define CSMB_CTRL_CMB_EN 4
410 #define CSMB_CTRL_SMB_EN 8
412 /* CMB DMA Write Threshold Register */
413 #define REG_CMB_WRITE_TH (REG_CSMB_CTRL+ 4)
414 #define CMB_RRD_TH_SHIFT 0
415 #define CMB_RRD_TH_MASK 0x7ff
416 #define CMB_TPD_TH_SHIFT 16
417 #define CMB_TPD_TH_MASK 0x7ff
419 /* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
420 #define REG_CMB_WRITE_TIMER (REG_CSMB_CTRL+ 8)
421 #define CMB_RX_TM_SHIFT 0
422 #define CMB_RX_TM_MASK 0xffff
423 #define CMB_TX_TM_SHIFT 16
424 #define CMB_TX_TM_MASK 0xffff
426 /* Number of packet received since last CMB write */
427 #define REG_CMB_RX_PKT_CNT (REG_CSMB_CTRL+12)
429 /* Number of packet transmitted since last CMB write */
430 #define REG_CMB_TX_PKT_CNT (REG_CSMB_CTRL+16)
432 /* SMB auto DMA timer register */
433 #define REG_SMB_TIMER (REG_CSMB_CTRL+20)
435 /* Mailbox Register */
436 #define REG_MAILBOX 0x15f0
437 #define MB_RFD_PROD_INDX_SHIFT 0
438 #define MB_RFD_PROD_INDX_MASK 0x7ff
439 #define MB_RRD_CONS_INDX_SHIFT 11
440 #define MB_RRD_CONS_INDX_MASK 0x7ff
441 #define MB_TPD_PROD_INDX_SHIFT 22
442 #define MB_TPD_PROD_INDX_MASK 0x3ff
444 /* Interrupt Status Register */
445 #define REG_ISR 0x1600
450 #define ISR_RFD_UNRUN 0x10
451 #define ISR_RRD_OV 0x20
452 #define ISR_TXF_UNRUN 0x40
453 #define ISR_LINK 0x80
454 #define ISR_HOST_RFD_UNRUN 0x100
455 #define ISR_HOST_RRD_OV 0x200
456 #define ISR_DMAR_TO_RST 0x400
457 #define ISR_DMAW_TO_RST 0x800
458 #define ISR_GPHY 0x1000
459 #define ISR_RX_PKT 0x10000
460 #define ISR_TX_PKT 0x20000
461 #define ISR_TX_DMA 0x40000
462 #define ISR_RX_DMA 0x80000
463 #define ISR_CMB_RX 0x100000
464 #define ISR_CMB_TX 0x200000
465 #define ISR_MAC_RX 0x400000
466 #define ISR_MAC_TX 0x800000
467 #define ISR_UR_DETECTED 0x1000000
468 #define ISR_FERR_DETECTED 0x2000000
469 #define ISR_NFERR_DETECTED 0x4000000
470 #define ISR_CERR_DETECTED 0x8000000
471 #define ISR_PHY_LINKDOWN 0x10000000
472 #define ISR_DIS_SMB 0x20000000
473 #define ISR_DIS_DMA 0x40000000
474 #define ISR_DIS_INT 0x80000000
476 /* Interrupt Mask Register */
477 #define REG_IMR 0x1604
479 /* Normal Interrupt mask */
480 #define IMR_NORMAL_MASK (\
489 /* Debug Interrupt Mask (enable all interrupt) */
490 #define IMR_DEBUG_MASK (\
506 /* Interrupt Status Register */
507 #define REG_RFD_RRD_IDX 0x1800
508 #define REG_TPD_IDX 0x1804
511 /* PHY Common Register */
512 #define MII_AT001_CR 0x09
513 #define MII_AT001_SR 0x0A
514 #define MII_AT001_ESR 0x0F
515 #define MII_AT001_PSCR 0x10
516 #define MII_AT001_PSSR 0x11
518 /* PHY Control Register */
519 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
520 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
521 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
522 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
523 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
524 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
525 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
526 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
527 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
528 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
529 #define MII_CR_SPEED_MASK 0x2040
530 #define MII_CR_SPEED_1000 0x0040
531 #define MII_CR_SPEED_100 0x2000
532 #define MII_CR_SPEED_10 0x0000
534 /* PHY Status Register */
535 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
536 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
537 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
538 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
539 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
540 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
541 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
542 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
543 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
544 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
545 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
546 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
547 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
548 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
549 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
551 /* Link partner ability register. */
552 #define MII_LPA_SLCT 0x001f /* Same as advertise selector */
553 #define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
554 #define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
555 #define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
556 #define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
557 #define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
558 #define MII_LPA_PAUSE 0x0400 /* PAUSE */
559 #define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */
560 #define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
561 #define MII_LPA_LPACK 0x4000 /* Link partner acked us */
562 #define MII_LPA_NPAGE 0x8000 /* Next page bit */
564 /* Autoneg Advertisement Register */
565 #define MII_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
566 #define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
567 #define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
568 #define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
569 #define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
570 #define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
571 #define MII_AR_PAUSE 0x0400 /* Pause operation desired */
572 #define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
573 #define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
574 #define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
575 #define MII_AR_SPEED_MASK 0x01E0
576 #define MII_AR_DEFAULT_CAP_MASK 0x0DE0
578 /* 1000BASE-T Control Register */
579 #define MII_AT001_CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
580 #define MII_AT001_CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
581 #define MII_AT001_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port, 0=DTE device */
582 #define MII_AT001_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master, 0=Configure PHY as Slave */
583 #define MII_AT001_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value, 0=Automatic Master/Slave config */
584 #define MII_AT001_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
585 #define MII_AT001_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
586 #define MII_AT001_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
587 #define MII_AT001_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
588 #define MII_AT001_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
589 #define MII_AT001_CR_1000T_SPEED_MASK 0x0300
590 #define MII_AT001_CR_1000T_DEFAULT_CAP_MASK 0x0300
592 /* 1000BASE-T Status Register */
593 #define MII_AT001_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
594 #define MII_AT001_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
595 #define MII_AT001_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
596 #define MII_AT001_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
597 #define MII_AT001_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
598 #define MII_AT001_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
599 #define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT 12
600 #define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT 13
602 /* Extended Status Register */
603 #define MII_AT001_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
604 #define MII_AT001_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
605 #define MII_AT001_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
606 #define MII_AT001_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
608 /* AT001 PHY Specific Control Register */
609 #define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
610 #define MII_AT001_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
611 #define MII_AT001_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
612 #define MII_AT001_PSCR_MAC_POWERDOWN 0x0008
613 #define MII_AT001_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 0=CLK125 toggling */
614 #define MII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5, Manual MDI configuration */
615 #define MII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
616 #define MII_AT001_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
617 #define MII_AT001_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled all speeds. */
618 #define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T RX Threshold), 0=Normal 10BASE-T RX Threshold */
619 #define MII_AT001_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
620 #define MII_AT001_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
621 #define MII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
622 #define MII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
623 #define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT 1
624 #define MII_AT001_PSCR_AUTO_X_MODE_SHIFT 5
625 #define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
627 /* AT001 PHY Specific Status Register */
628 #define MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
629 #define MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
630 #define MII_AT001_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
631 #define MII_AT001_PSSR_10MBS 0x0000 /* 00=10Mbs */
632 #define MII_AT001_PSSR_100MBS 0x4000 /* 01=100Mbs */
633 #define MII_AT001_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
635 /* PCI Command Register Bit Definitions */
636 #define PCI_REG_COMMAND 0x04 /* PCI Command Register */
637 #define CMD_IO_SPACE 0x0001
638 #define CMD_MEMORY_SPACE 0x0002
639 #define CMD_BUS_MASTER 0x0004
641 /* Wake Up Filter Control */
642 #define ATL1_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
643 #define ATL1_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
644 #define ATL1_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
645 #define ATL1_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
646 #define ATL1_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
649 #define ATL1_SUCCESS 0
650 #define ATL1_ERR_EEPROM 1
651 #define ATL1_ERR_PHY 2
652 #define ATL1_ERR_CONFIG 3
653 #define ATL1_ERR_PARAM 4
654 #define ATL1_ERR_MAC_TYPE 5
655 #define ATL1_ERR_PHY_TYPE 6
656 #define ATL1_ERR_PHY_SPEED 7
657 #define ATL1_ERR_PHY_RES 8
659 #define SPEED_0 0xffff
661 #define SPEED_100 100
662 #define SPEED_1000 1000
663 #define HALF_DUPLEX 1
664 #define FULL_DUPLEX 2
666 #define MEDIA_TYPE_AUTO_SENSOR 0
667 #define MEDIA_TYPE_1000M_FULL 1
668 #define MEDIA_TYPE_100M_FULL 2
669 #define MEDIA_TYPE_100M_HALF 3
670 #define MEDIA_TYPE_10M_FULL 4
671 #define MEDIA_TYPE_10M_HALF 5
673 #define ADVERTISE_10_HALF 0x0001
674 #define ADVERTISE_10_FULL 0x0002
675 #define ADVERTISE_100_HALF 0x0004
676 #define ADVERTISE_100_FULL 0x0008
677 #define ADVERTISE_1000_HALF 0x0010
678 #define ADVERTISE_1000_FULL 0x0020
679 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
680 #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
681 #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
683 /* The size (in bytes) of a ethernet packet */
684 #define ENET_HEADER_SIZE 14
685 #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* with FCS */
686 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* with FCS */
687 #define ETHERNET_FCS_SIZE 4
688 #define MAX_JUMBO_FRAME_SIZE 0x2800
690 #define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
691 #define PHY_FORCE_TIME 20 /* 2.0 Seconds */
693 /* For checksumming , the sum of all words in the EEPROM should equal 0xBABA */
694 #define EEPROM_SUM 0xBABA
696 #define ATL1_EEDUMP_LEN 48
698 /* Statistics counters collected by the MAC */
699 struct stats_msg_block {
701 u32 rx_ok; /* The number of good packet received. */
702 u32 rx_bcast; /* The number of good broadcast packet received. */
703 u32 rx_mcast; /* The number of good multicast packet received. */
704 u32 rx_pause; /* The number of Pause packet received. */
705 u32 rx_ctrl; /* The number of Control packet received other than Pause frame. */
706 u32 rx_fcs_err; /* The number of packets with bad FCS. */
707 u32 rx_len_err; /* The number of packets with mismatch of length field and actual size. */
708 u32 rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */
709 u32 rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */
710 u32 rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */
711 u32 rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */
712 u32 rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */
713 u32 rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */
714 u32 rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */
715 u32 rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
716 u32 rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
717 u32 rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */
718 u32 rx_sz_ov; /* The number of good and bad packets received that are more than MTU size šC truncated by Selene. */
719 u32 rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */
720 u32 rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */
721 u32 rx_align_err; /* Alignment Error */
722 u32 rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */
723 u32 rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */
724 u32 rx_err_addr; /* The number of packets dropped due to address filtering. */
727 u32 tx_ok; /* The number of good packet transmitted. */
728 u32 tx_bcast; /* The number of good broadcast packet transmitted. */
729 u32 tx_mcast; /* The number of good multicast packet transmitted. */
730 u32 tx_pause; /* The number of Pause packet transmitted. */
731 u32 tx_exc_defer; /* The number of packets transmitted with excessive deferral. */
732 u32 tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */
733 u32 tx_defer; /* The number of packets transmitted that is deferred. */
734 u32 tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */
735 u32 tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */
736 u32 tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
737 u32 tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
738 u32 tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
739 u32 tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
740 u32 tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
741 u32 tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
742 u32 tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */
743 u32 tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
744 u32 tx_late_col; /* The number of packets transmitted with late collisions. */
745 u32 tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */
746 u32 tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
747 u32 tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
748 u32 tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */
749 u32 tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */
750 u32 tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */
751 u32 tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */
752 u32 smb_updated; /* 1: SMB Updated. This is used by software as the indication of the statistics update.
753 * Software should clear this bit as soon as retrieving the statistics information. */
756 /* Coalescing Message Block */
757 struct coals_msg_block {
758 u32 int_stats; /* interrupt status */
759 u16 rrd_prod_idx; /* TRD Producer Index. */
760 u16 rfd_cons_idx; /* RFD Consumer Index. */
761 u16 update; /* Selene sets this bit every time it DMA the CMB to host memory.
762 * Software supposes to clear this bit when CMB information is processed. */
763 u16 tpd_cons_idx; /* TPD Consumer Index. */
767 struct rx_return_desc {
768 u8 num_buf; /* Number of RFD buffers used by the received packet */
770 u16 buf_indx; /* RFD Index of the first buffer */
779 u16 pkt_flg; /* Packet flags */
780 u16 err_flg; /* Error flags */
782 u16 vlan_tag; /* VLAN TAG */
785 #define PACKET_FLAG_ETH_TYPE 0x0080
786 #define PACKET_FLAG_VLAN_INS 0x0100
787 #define PACKET_FLAG_ERR 0x0200
788 #define PACKET_FLAG_IPV4 0x0400
789 #define PACKET_FLAG_UDP 0x0800
790 #define PACKET_FLAG_TCP 0x1000
791 #define PACKET_FLAG_BCAST 0x2000
792 #define PACKET_FLAG_MCAST 0x4000
793 #define PACKET_FLAG_PAUSE 0x8000
795 #define ERR_FLAG_CRC 0x0001
796 #define ERR_FLAG_CODE 0x0002
797 #define ERR_FLAG_DRIBBLE 0x0004
798 #define ERR_FLAG_RUNT 0x0008
799 #define ERR_FLAG_OV 0x0010
800 #define ERR_FLAG_TRUNC 0x0020
801 #define ERR_FLAG_IP_CHKSUM 0x0040
802 #define ERR_FLAG_L4_CHKSUM 0x0080
803 #define ERR_FLAG_LEN 0x0100
804 #define ERR_FLAG_DES_ADDR 0x0200
807 struct rx_free_desc {
808 __le64 buffer_addr; /* Address of the descriptor's data buffer */
809 __le16 buf_len; /* Size of the receive buffer in host memory, in byte */
810 u16 coalese; /* Update consumer index to host after the reception of this frame */
811 /* __attribute__ ((packed)) is required */
812 } __attribute__ ((packed));
815 #define TSO_PARAM_BUFLEN_MASK 0x3FFF
816 #define TSO_PARAM_BUFLEN_SHIFT 0
817 #define TSO_PARAM_DMAINT_MASK 0x0001
818 #define TSO_PARAM_DMAINT_SHIFT 14
819 #define TSO_PARAM_PKTNT_MASK 0x0001
820 #define TSO_PARAM_PKTINT_SHIFT 15
821 #define TSO_PARAM_VLANTAG_MASK 0xFFFF
822 #define TSO_PARAM_VLAN_SHIFT 16
825 #define TSO_PARAM_EOP_MASK 0x0001
826 #define TSO_PARAM_EOP_SHIFT 0
827 #define TSO_PARAM_COALESCE_MASK 0x0001
828 #define TSO_PARAM_COALESCE_SHIFT 1
829 #define TSO_PARAM_INSVLAG_MASK 0x0001
830 #define TSO_PARAM_INSVLAG_SHIFT 2
831 #define TSO_PARAM_CUSTOMCKSUM_MASK 0x0001
832 #define TSO_PARAM_CUSTOMCKSUM_SHIFT 3
833 #define TSO_PARAM_SEGMENT_MASK 0x0001
834 #define TSO_PARAM_SEGMENT_SHIFT 4
835 #define TSO_PARAM_IPCKSUM_MASK 0x0001
836 #define TSO_PARAM_IPCKSUM_SHIFT 5
837 #define TSO_PARAM_TCPCKSUM_MASK 0x0001
838 #define TSO_PARAM_TCPCKSUM_SHIFT 6
839 #define TSO_PARAM_UDPCKSUM_MASK 0x0001
840 #define TSO_PARAM_UDPCKSUM_SHIFT 7
841 #define TSO_PARAM_VLANTAGGED_MASK 0x0001
842 #define TSO_PARAM_VLANTAGGED_SHIFT 8
843 #define TSO_PARAM_ETHTYPE_MASK 0x0001
844 #define TSO_PARAM_ETHTYPE_SHIFT 9
845 #define TSO_PARAM_IPHL_MASK 0x000F
846 #define TSO_PARAM_IPHL_SHIFT 10
847 #define TSO_PARAM_TCPHDRLEN_MASK 0x000F
848 #define TSO_PARAM_TCPHDRLEN_SHIFT 14
849 #define TSO_PARAM_HDRFLAG_MASK 0x0001
850 #define TSO_PARAM_HDRFLAG_SHIFT 18
851 #define TSO_PARAM_MSS_MASK 0x1FFF
852 #define TSO_PARAM_MSS_SHIFT 19
855 #define CSUM_PARAM_BUFLEN_MASK 0x3FFF
856 #define CSUM_PARAM_BUFLEN_SHIFT 0
857 #define CSUM_PARAM_DMAINT_MASK 0x0001
858 #define CSUM_PARAM_DMAINT_SHIFT 14
859 #define CSUM_PARAM_PKTINT_MASK 0x0001
860 #define CSUM_PARAM_PKTINT_SHIFT 15
861 #define CSUM_PARAM_VALANTAG_MASK 0xFFFF
862 #define CSUM_PARAM_VALAN_SHIFT 16
865 #define CSUM_PARAM_EOP_MASK 0x0001
866 #define CSUM_PARAM_EOP_SHIFT 0
867 #define CSUM_PARAM_COALESCE_MASK 0x0001
868 #define CSUM_PARAM_COALESCE_SHIFT 1
869 #define CSUM_PARAM_INSVLAG_MASK 0x0001
870 #define CSUM_PARAM_INSVLAG_SHIFT 2
871 #define CSUM_PARAM_CUSTOMCKSUM_MASK 0x0001
872 #define CSUM_PARAM_CUSTOMCKSUM_SHIFT 3
873 #define CSUM_PARAM_SEGMENT_MASK 0x0001
874 #define CSUM_PARAM_SEGMENT_SHIFT 4
875 #define CSUM_PARAM_IPCKSUM_MASK 0x0001
876 #define CSUM_PARAM_IPCKSUM_SHIFT 5
877 #define CSUM_PARAM_TCPCKSUM_MASK 0x0001
878 #define CSUM_PARAM_TCPCKSUM_SHIFT 6
879 #define CSUM_PARAM_UDPCKSUM_MASK 0x0001
880 #define CSUM_PARAM_UDPCKSUM_SHIFT 7
881 #define CSUM_PARAM_VLANTAGGED_MASK 0x0001
882 #define CSUM_PARAM_VLANTAGGED_SHIFT 8
883 #define CSUM_PARAM_ETHTYPE_MASK 0x0001
884 #define CSUM_PARAM_ETHTYPE_SHIFT 9
885 #define CSUM_PARAM_IPHL_MASK 0x000F
886 #define CSUM_PARAM_IPHL_SHIFT 10
887 #define CSUM_PARAM_PLOADOFFSET_MASK 0x00FF
888 #define CSUM_PARAM_PLOADOFFSET_SHIFT 16
889 #define CSUM_PARAM_XSUMOFFSET_MASK 0x00FF
890 #define CSUM_PARAM_XSUMOFFSET_SHIFT 24
894 /* The order of these declarations is important -- don't change it */
895 u32 tsopu; /* tso_param upper word */
896 u32 tsopl; /* tso_param lower word */
900 /* The order of these declarations is important -- don't change it */
901 u32 csumpu; /* csum_param upper word */
902 u32 csumpl; /* csum_param lower word */
907 struct csum_param csum;
908 struct tso_param tso;
911 struct tx_packet_desc {
913 union tpd_descr desc;
916 /* DMA Order Settings */
917 enum atl1_dma_order {
919 atl1_dma_ord_enh = 2,
928 enum atl1_dma_req_block {
929 atl1_dma_req_128 = 0,
930 atl1_dma_req_256 = 1,
931 atl1_dma_req_512 = 2,
932 atl1_dam_req_1024 = 3,
933 atl1_dam_req_2048 = 4,
934 atl1_dma_req_4096 = 5
937 struct atl1_spi_flash_dev {
938 const char *manu_name; /* manufacturer id */
951 #endif /* _ATL1_HW_H_ */
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