2 * ARM GIC v2m MSI(-X) support
3 * Support for Message Signaled Interrupts for systems that
4 * implement ARM Generic Interrupt Controller: GICv2m.
6 * Copyright (C) 2014 Advanced Micro Devices, Inc.
7 * Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
8 * Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
9 * Brandon Anderson <brandon.anderson@amd.com>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #define pr_fmt(fmt) "GICv2m: " fmt
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/kernel.h>
21 #include <linux/of_address.h>
22 #include <linux/of_pci.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
29 * [25:16] lowest SPI assigned to MSI
31 * [9:0] Numer of SPIs assigned to MSI
33 #define V2M_MSI_TYPER 0x008
34 #define V2M_MSI_TYPER_BASE_SHIFT 16
35 #define V2M_MSI_TYPER_BASE_MASK 0x3FF
36 #define V2M_MSI_TYPER_NUM_MASK 0x3FF
37 #define V2M_MSI_SETSPI_NS 0x040
38 #define V2M_MIN_SPI 32
39 #define V2M_MAX_SPI 1019
40 #define V2M_MSI_IIDR 0xFCC
42 #define V2M_MSI_TYPER_BASE_SPI(x) \
43 (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)
45 #define V2M_MSI_TYPER_NUM_SPI(x) ((x) & V2M_MSI_TYPER_NUM_MASK)
47 /* APM X-Gene with GICv2m MSI_IIDR register value */
48 #define XGENE_GICV2M_MSI_IIDR 0x06000170
50 /* List of flags for specific v2m implementation */
51 #define GICV2M_NEEDS_SPI_OFFSET 0x00000001
54 spinlock_t msi_cnt_lock;
55 struct resource res; /* GICv2m resource */
56 void __iomem *base; /* GICv2m virt address */
57 u32 spi_start; /* The SPI number that MSIs start */
58 u32 nr_spis; /* The number of SPIs for MSIs */
59 unsigned long *bm; /* MSI vector bitmap */
60 u32 flags; /* v2m flags for specific implementation */
63 static void gicv2m_mask_msi_irq(struct irq_data *d)
66 irq_chip_mask_parent(d);
69 static void gicv2m_unmask_msi_irq(struct irq_data *d)
71 pci_msi_unmask_irq(d);
72 irq_chip_unmask_parent(d);
75 static struct irq_chip gicv2m_msi_irq_chip = {
77 .irq_mask = gicv2m_mask_msi_irq,
78 .irq_unmask = gicv2m_unmask_msi_irq,
79 .irq_eoi = irq_chip_eoi_parent,
80 .irq_write_msi_msg = pci_msi_domain_write_msg,
83 static struct msi_domain_info gicv2m_msi_domain_info = {
84 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
86 .chip = &gicv2m_msi_irq_chip,
89 static int gicv2m_set_affinity(struct irq_data *irq_data,
90 const struct cpumask *mask, bool force)
94 ret = irq_chip_set_affinity_parent(irq_data, mask, force);
95 if (ret == IRQ_SET_MASK_OK)
96 ret = IRQ_SET_MASK_OK_DONE;
101 static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
103 struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
104 phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS;
106 msg->address_hi = upper_32_bits(addr);
107 msg->address_lo = lower_32_bits(addr);
108 msg->data = data->hwirq;
110 if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
111 msg->data -= v2m->spi_start;
114 static struct irq_chip gicv2m_irq_chip = {
116 .irq_mask = irq_chip_mask_parent,
117 .irq_unmask = irq_chip_unmask_parent,
118 .irq_eoi = irq_chip_eoi_parent,
119 .irq_set_affinity = gicv2m_set_affinity,
120 .irq_compose_msi_msg = gicv2m_compose_msi_msg,
123 static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
125 irq_hw_number_t hwirq)
127 struct of_phandle_args args;
131 args.np = domain->parent->of_node;
134 args.args[1] = hwirq - 32;
135 args.args[2] = IRQ_TYPE_EDGE_RISING;
137 err = irq_domain_alloc_irqs_parent(domain, virq, 1, &args);
141 /* Configure the interrupt line to be edge */
142 d = irq_domain_get_irq_data(domain->parent, virq);
143 d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
147 static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq)
151 pos = hwirq - v2m->spi_start;
152 if (pos < 0 || pos >= v2m->nr_spis) {
153 pr_err("Failed to teardown msi. Invalid hwirq %d\n", hwirq);
157 spin_lock(&v2m->msi_cnt_lock);
158 __clear_bit(pos, v2m->bm);
159 spin_unlock(&v2m->msi_cnt_lock);
162 static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
163 unsigned int nr_irqs, void *args)
165 struct v2m_data *v2m = domain->host_data;
166 int hwirq, offset, err = 0;
168 spin_lock(&v2m->msi_cnt_lock);
169 offset = find_first_zero_bit(v2m->bm, v2m->nr_spis);
170 if (offset < v2m->nr_spis)
171 __set_bit(offset, v2m->bm);
174 spin_unlock(&v2m->msi_cnt_lock);
179 hwirq = v2m->spi_start + offset;
181 err = gicv2m_irq_gic_domain_alloc(domain, virq, hwirq);
183 gicv2m_unalloc_msi(v2m, hwirq);
187 irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
188 &gicv2m_irq_chip, v2m);
193 static void gicv2m_irq_domain_free(struct irq_domain *domain,
194 unsigned int virq, unsigned int nr_irqs)
196 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
197 struct v2m_data *v2m = irq_data_get_irq_chip_data(d);
199 BUG_ON(nr_irqs != 1);
200 gicv2m_unalloc_msi(v2m, d->hwirq);
201 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
204 static const struct irq_domain_ops gicv2m_domain_ops = {
205 .alloc = gicv2m_irq_domain_alloc,
206 .free = gicv2m_irq_domain_free,
209 static bool is_msi_spi_valid(u32 base, u32 num)
211 if (base < V2M_MIN_SPI) {
212 pr_err("Invalid MSI base SPI (base:%u)\n", base);
216 if ((num == 0) || (base + num > V2M_MAX_SPI)) {
217 pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
218 num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
225 static struct irq_chip gicv2m_pmsi_irq_chip = {
229 static struct msi_domain_ops gicv2m_pmsi_ops = {
232 static struct msi_domain_info gicv2m_pmsi_domain_info = {
233 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
234 .ops = &gicv2m_pmsi_ops,
235 .chip = &gicv2m_pmsi_irq_chip,
238 static int __init gicv2m_init_one(struct device_node *node,
239 struct irq_domain *parent)
242 struct v2m_data *v2m;
243 struct irq_domain *inner_domain, *pci_domain, *plat_domain;
245 v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
247 pr_err("Failed to allocate struct v2m_data.\n");
251 ret = of_address_to_resource(node, 0, &v2m->res);
253 pr_err("Failed to allocate v2m resource.\n");
257 v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
259 pr_err("Failed to map GICv2m resource\n");
264 if (!of_property_read_u32(node, "arm,msi-base-spi", &v2m->spi_start) &&
265 !of_property_read_u32(node, "arm,msi-num-spis", &v2m->nr_spis)) {
266 pr_info("Overriding V2M MSI_TYPER (base:%u, num:%u)\n",
267 v2m->spi_start, v2m->nr_spis);
269 u32 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
271 v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
272 v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
275 if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
281 * APM X-Gene GICv2m implementation has an erratum where
282 * the MSI data needs to be the offset from the spi_start
283 * in order to trigger the correct MSI interrupt. This is
284 * different from the standard GICv2m implementation where
285 * the MSI data is the absolute value within the range from
286 * spi_start to (spi_start + num_spis).
288 if (readl_relaxed(v2m->base + V2M_MSI_IIDR) == XGENE_GICV2M_MSI_IIDR)
289 v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
291 v2m->bm = kzalloc(sizeof(long) * BITS_TO_LONGS(v2m->nr_spis),
298 inner_domain = irq_domain_add_tree(node, &gicv2m_domain_ops, v2m);
300 pr_err("Failed to create GICv2m domain\n");
305 inner_domain->bus_token = DOMAIN_BUS_NEXUS;
306 inner_domain->parent = parent;
307 pci_domain = pci_msi_create_irq_domain(node, &gicv2m_msi_domain_info,
309 plat_domain = platform_msi_create_irq_domain(node,
310 &gicv2m_pmsi_domain_info,
312 if (!pci_domain || !plat_domain) {
313 pr_err("Failed to create MSI domains\n");
315 goto err_free_domains;
318 spin_lock_init(&v2m->msi_cnt_lock);
320 pr_info("Node %s: range[%#lx:%#lx], SPI[%d:%d]\n", node->name,
321 (unsigned long)v2m->res.start, (unsigned long)v2m->res.end,
322 v2m->spi_start, (v2m->spi_start + v2m->nr_spis));
328 irq_domain_remove(plat_domain);
330 irq_domain_remove(pci_domain);
332 irq_domain_remove(inner_domain);
342 static struct of_device_id gicv2m_device_id[] = {
343 { .compatible = "arm,gic-v2m-frame", },
347 int __init gicv2m_of_init(struct device_node *node, struct irq_domain *parent)
350 struct device_node *child;
352 for (child = of_find_matching_node(node, gicv2m_device_id); child;
353 child = of_find_matching_node(child, gicv2m_device_id)) {
354 if (!of_find_property(child, "msi-controller", NULL))
357 ret = gicv2m_init_one(child, parent);