drivers/gpu/drm/radeon/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "radeon.h"
  26 #include "radeon_asic.h"
  27 #include "sid.h"
  28 #include "r600_dpm.h"
  29 #include "si_dpm.h"
  30 #include "atom.h"
  31 #include <linux/math64.h>
  32 #include <linux/seq_file.h>
  33
  34 #define MC_CG_ARB_FREQ_F0           0x0a
  35 #define MC_CG_ARB_FREQ_F1           0x0b
  36 #define MC_CG_ARB_FREQ_F2           0x0c
  37 #define MC_CG_ARB_FREQ_F3           0x0d
  38
  39 #define SMC_RAM_END                 0x20000
  40
  41 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  42
  43 static const struct si_cac_config_reg cac_weights_tahiti[] =
  44 {
  45         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
  46         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  47         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
  48         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
  49         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  50         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  51         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  52         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  53         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  54         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
  55         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  56         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
  57         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
  58         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
  59         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
  60         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  61         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  62         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
  63         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  64         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
  65         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
  66         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
  67         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  68         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  69         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  70         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  71         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  72         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  73         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  74         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  75         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
  76         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  77         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  78         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  79         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
  80         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  81         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  82         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
  83         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  84         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
  85         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  86         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  87         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  88         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  89         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  90         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  91         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  92         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  93         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  94         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  95         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  96         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  97         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  98         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  99         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 100         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 101         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 102         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 103         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 104         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 105         { 0xFFFFFFFF }
 106 };
 107
 108 static const struct si_cac_config_reg lcac_tahiti[] =
 109 {
 110         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 111         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 112         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 113         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 114         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 115         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 116         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 117         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 118         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 119         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 120         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 121         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 122         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 123         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 124         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 125         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 126         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 127         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 128         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 129         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 130         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 131         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 132         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 133         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 134         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 135         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 136         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 137         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 138         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 139         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 140         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 141         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 142         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 143         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 144         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 145         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 146         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 147         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 148         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 149         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 150         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 151         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 152         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 153         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 154         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 155         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 156         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 157         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 158         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 159         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 160         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 161         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 162         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 163         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 164         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 165         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 166         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 167         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 168         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 169         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 170         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 171         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 172         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 173         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 174         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 175         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 176         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 177         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 178         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 179         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 180         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 181         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 182         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 183         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 184         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 185         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 186         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 187         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 188         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 189         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 190         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 191         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 192         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 193         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 194         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 195         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 196         { 0xFFFFFFFF }
 197
 198 };
 199
 200 static const struct si_cac_config_reg cac_override_tahiti[] =
 201 {
 202         { 0xFFFFFFFF }
 203 };
 204
 205 static const struct si_powertune_data powertune_data_tahiti =
 206 {
 207         ((1 << 16) | 27027),
 208         6,
 209         0,
 210         4,
 211         95,
 212         {
 213                 0UL,
 214                 0UL,
 215                 4521550UL,
 216                 309631529UL,
 217                 -1270850L,
 218                 4513710L,
 219                 40
 220         },
 221         595000000UL,
 222         12,
 223         {
 224                 0,
 225                 0,
 226                 0,
 227                 0,
 228                 0,
 229                 0,
 230                 0,
 231                 0
 232         },
 233         true
 234 };
 235
 236 static const struct si_dte_data dte_data_tahiti =
 237 {
 238         { 1159409, 0, 0, 0, 0 },
 239         { 777, 0, 0, 0, 0 },
 240         2,
 241         54000,
 242         127000,
 243         25,
 244         2,
 245         10,
 246         13,
 247         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 248         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 249         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 250         85,
 251         false
 252 };
 253
 254 static const struct si_dte_data dte_data_tahiti_le =
 255 {
 256         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 257         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 258         0x5,
 259         0xAFC8,
 260         0x64,
 261         0x32,
 262         1,
 263         0,
 264         0x10,
 265         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 266         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 267         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 268         85,
 269         true
 270 };
 271
 272 static const struct si_dte_data dte_data_tahiti_pro =
 273 {
 274         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 275         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 276         5,
 277         45000,
 278         100,
 279         0xA,
 280         1,
 281         0,
 282         0x10,
 283         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 284         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 285         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 286         90,
 287         true
 288 };
 289
 290 static const struct si_dte_data dte_data_new_zealand =
 291 {
 292         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 293         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 294         0x5,
 295         0xAFC8,
 296         0x69,
 297         0x32,
 298         1,
 299         0,
 300         0x10,
 301         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 302         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 303         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 304         85,
 305         true
 306 };
 307
 308 static const struct si_dte_data dte_data_aruba_pro =
 309 {
 310         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 311         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 312         5,
 313         45000,
 314         100,
 315         0xA,
 316         1,
 317         0,
 318         0x10,
 319         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 320         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 321         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 322         90,
 323         true
 324 };
 325
 326 static const struct si_dte_data dte_data_malta =
 327 {
 328         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 329         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 330         5,
 331         45000,
 332         100,
 333         0xA,
 334         1,
 335         0,
 336         0x10,
 337         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 338         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 339         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 340         90,
 341         true
 342 };
 343
 344 struct si_cac_config_reg cac_weights_pitcairn[] =
 345 {
 346         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 347         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 348         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 349         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 350         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 351         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 352         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 353         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 354         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 355         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 356         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 357         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 358         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 359         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 360         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 361         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 362         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 363         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 364         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 365         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 366         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 367         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 368         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 369         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 370         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 371         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 372         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 373         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 374         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 375         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 376         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 377         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 378         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 379         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 380         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 381         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 382         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 383         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 384         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 385         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 386         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 387         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 388         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 389         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 390         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 391         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 392         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 393         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 394         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 395         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 396         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 397         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 398         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 399         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 400         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 401         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 402         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 403         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 404         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 405         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 406         { 0xFFFFFFFF }
 407 };
 408
 409 static const struct si_cac_config_reg lcac_pitcairn[] =
 410 {
 411         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 412         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 413         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 414         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 415         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 416         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 417         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 418         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 419         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 420         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 421         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 422         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 423         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 424         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 425         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 426         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 427         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 428         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 429         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 430         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 431         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 432         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 433         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 434         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 435         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 436         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 437         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 438         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 439         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 440         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 441         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 442         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 443         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 444         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 445         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 446         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 447         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 448         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 449         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 450         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 451         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 452         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 453         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 454         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 455         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 456         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 457         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 458         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 459         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 460         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 461         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 462         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 463         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 464         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 465         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 466         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 467         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 468         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 469         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 470         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 471         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 472         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 473         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 474         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 475         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 476         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 477         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 478         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 479         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 480         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 481         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 482         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 483         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 484         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 485         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 486         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 487         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 488         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 489         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 490         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 491         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 492         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 493         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 494         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 495         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 496         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 497         { 0xFFFFFFFF }
 498 };
 499
 500 static const struct si_cac_config_reg cac_override_pitcairn[] =
 501 {
 502     { 0xFFFFFFFF }
 503 };
 504
 505 static const struct si_powertune_data powertune_data_pitcairn =
 506 {
 507         ((1 << 16) | 27027),
 508         5,
 509         0,
 510         6,
 511         100,
 512         {
 513                 51600000UL,
 514                 1800000UL,
 515                 7194395UL,
 516                 309631529UL,
 517                 -1270850L,
 518                 4513710L,
 519                 100
 520         },
 521         117830498UL,
 522         12,
 523         {
 524                 0,
 525                 0,
 526                 0,
 527                 0,
 528                 0,
 529                 0,
 530                 0,
 531                 0
 532         },
 533         true
 534 };
 535
 536 static const struct si_dte_data dte_data_pitcairn =
 537 {
 538         { 0, 0, 0, 0, 0 },
 539         { 0, 0, 0, 0, 0 },
 540         0,
 541         0,
 542         0,
 543         0,
 544         0,
 545         0,
 546         0,
 547         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 548         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 549         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 550         0,
 551         false
 552 };
 553
 554 static const struct si_dte_data dte_data_curacao_xt =
 555 {
 556         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 557         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 558         5,
 559         45000,
 560         100,
 561         0xA,
 562         1,
 563         0,
 564         0x10,
 565         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 566         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 567         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 568         90,
 569         true
 570 };
 571
 572 static const struct si_dte_data dte_data_curacao_pro =
 573 {
 574         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 575         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 576         5,
 577         45000,
 578         100,
 579         0xA,
 580         1,
 581         0,
 582         0x10,
 583         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 584         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 585         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 586         90,
 587         true
 588 };
 589
 590 static const struct si_dte_data dte_data_neptune_xt =
 591 {
 592         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 593         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 594         5,
 595         45000,
 596         100,
 597         0xA,
 598         1,
 599         0,
 600         0x10,
 601         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 602         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 603         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 604         90,
 605         true
 606 };
 607
 608 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 609 {
 610         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 611         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 612         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 613         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 614         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 615         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 616         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 617         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 618         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 619         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 620         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 621         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 622         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 623         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 624         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 625         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 626         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 627         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 628         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 629         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 630         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 631         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 632         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 633         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 634         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 635         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 636         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 637         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 638         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 639         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 640         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 641         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 642         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 643         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 644         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 645         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 646         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 647         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 648         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 649         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 650         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 651         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 652         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 653         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 654         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 655         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 656         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 657         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 658         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 659         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 660         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 661         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 662         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 663         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 664         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 665         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 666         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 667         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 668         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 669         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 670         { 0xFFFFFFFF }
 671 };
 672
 673 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 674 {
 675         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 676         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 677         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 678         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 679         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 680         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 681         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 682         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 683         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 684         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 685         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 686         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 687         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 688         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 689         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 690         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 691         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 692         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 693         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 694         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 695         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 696         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 697         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 698         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 699         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 700         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 701         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 702         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 703         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 704         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 705         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 706         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 707         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 708         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 709         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 710         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 711         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 712         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 713         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 714         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 715         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 716         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 717         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 718         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 719         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 720         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 721         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 722         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 723         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 724         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 725         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 726         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 727         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 728         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 729         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 730         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 731         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 732         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 733         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 734         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 735         { 0xFFFFFFFF }
 736 };
 737
 738 static const struct si_cac_config_reg cac_weights_heathrow[] =
 739 {
 740         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 741         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 742         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 743         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 744         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 745         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 746         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 747         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 748         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 749         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 750         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 751         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 752         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 753         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 754         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 755         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 756         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 757         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 758         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 759         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 760         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 761         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 762         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 763         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 764         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 765         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 766         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 767         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 768         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 769         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 770         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 771         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 772         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 773         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 774         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 775         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 776         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 777         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 778         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 779         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 780         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 781         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 782         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 783         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 784         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 785         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 786         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 787         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 788         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 789         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 790         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 791         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 792         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 793         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 794         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 795         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 796         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 797         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 798         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 799         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 800         { 0xFFFFFFFF }
 801 };
 802
 803 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 804 {
 805         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 806         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 807         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 808         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 809         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 810         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 811         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 812         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 813         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 814         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 815         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 816         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 817         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 818         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 819         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 820         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 821         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 822         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 823         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 824         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 825         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 826         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 827         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 828         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 829         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 830         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 831         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 832         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 833         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 834         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 835         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 836         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 837         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 838         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 839         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 840         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 841         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 842         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 843         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 844         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 845         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 846         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 847         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 848         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 849         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 850         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 851         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 852         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 853         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 854         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 855         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 856         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 857         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 858         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 859         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 860         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 861         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 862         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 863         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 864         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 865         { 0xFFFFFFFF }
 866 };
 867
 868 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 869 {
 870         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 871         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 872         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 873         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 874         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 875         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 876         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 877         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 878         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 879         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 880         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 881         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 882         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 883         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 884         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 885         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 886         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 887         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 888         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 889         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 890         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 891         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 892         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 893         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 894         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 895         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 896         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 897         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 898         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 899         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 900         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 901         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 902         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 903         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 904         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 905         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 906         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 907         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 908         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 909         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 910         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 911         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 912         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 913         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 914         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 915         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 916         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 917         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 918         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 919         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 920         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 921         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 922         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 923         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 924         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 925         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 926         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 927         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 928         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 929         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 930         { 0xFFFFFFFF }
 931 };
 932
 933 static const struct si_cac_config_reg lcac_cape_verde[] =
 934 {
 935         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 936         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 937         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 938         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 939         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 940         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 941         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 942         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 943         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 944         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 945         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 946         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 947         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 948         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 949         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 950         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 951         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 952         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 953         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 954         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 955         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 956         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 957         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 958         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 959         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 960         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 961         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 962         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 963         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 964         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 965         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 966         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 967         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 968         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 969         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 970         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 971         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 972         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 973         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 974         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 975         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 976         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 977         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 978         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 979         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 980         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 981         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 982         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 983         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 984         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 985         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 986         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 987         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 988         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 989         { 0xFFFFFFFF }
 990 };
 991
 992 static const struct si_cac_config_reg cac_override_cape_verde[] =
 993 {
 994     { 0xFFFFFFFF }
 995 };
 996
 997 static const struct si_powertune_data powertune_data_cape_verde =
 998 {
 999         ((1 << 16) | 0x6993),
1000         5,
1001         0,
1002         7,
1003         105,
1004         {
1005                 0UL,
1006                 0UL,
1007                 7194395UL,
1008                 309631529UL,
1009                 -1270850L,
1010                 4513710L,
1011                 100
1012         },
1013         117830498UL,
1014         12,
1015         {
1016                 0,
1017                 0,
1018                 0,
1019                 0,
1020                 0,
1021                 0,
1022                 0,
1023                 0
1024         },
1025         true
1026 };
1027
1028 static const struct si_dte_data dte_data_cape_verde =
1029 {
1030         { 0, 0, 0, 0, 0 },
1031         { 0, 0, 0, 0, 0 },
1032         0,
1033         0,
1034         0,
1035         0,
1036         0,
1037         0,
1038         0,
1039         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1042         0,
1043         false
1044 };
1045
1046 static const struct si_dte_data dte_data_venus_xtx =
1047 {
1048         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1049         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1050         5,
1051         55000,
1052         0x69,
1053         0xA,
1054         1,
1055         0,
1056         0x3,
1057         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1060         90,
1061         true
1062 };
1063
1064 static const struct si_dte_data dte_data_venus_xt =
1065 {
1066         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1067         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1068         5,
1069         55000,
1070         0x69,
1071         0xA,
1072         1,
1073         0,
1074         0x3,
1075         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1078         90,
1079         true
1080 };
1081
1082 static const struct si_dte_data dte_data_venus_pro =
1083 {
1084         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1085         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1086         5,
1087         55000,
1088         0x69,
1089         0xA,
1090         1,
1091         0,
1092         0x3,
1093         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1096         90,
1097         true
1098 };
1099
1100 struct si_cac_config_reg cac_weights_oland[] =
1101 {
1102         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1103         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1104         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1105         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1106         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1107         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1108         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1109         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1110         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1111         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1112         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1113         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1114         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1115         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1116         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1117         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1118         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1119         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1120         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1121         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1122         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1123         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1124         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1125         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1126         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1127         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1128         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1129         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1130         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1131         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1132         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1133         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1134         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1135         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1136         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1137         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1138         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1139         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1140         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1141         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1142         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1143         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1145         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1146         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1147         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1148         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1149         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1150         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1160         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1161         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1162         { 0xFFFFFFFF }
1163 };
1164
1165 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1166 {
1167         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1168         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1169         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1170         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1171         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1172         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1173         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1174         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1175         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1176         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1177         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1178         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1179         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1180         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1181         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1182         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1183         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1184         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1185         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1186         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1187         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1188         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1189         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1190         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1191         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1192         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1193         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1194         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1195         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1196         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1197         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1198         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1199         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1200         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1201         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1202         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1203         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1204         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1205         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1206         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1207         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1208         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1210         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1211         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1212         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1214         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1215         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1216         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1217         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1218         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1219         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1220         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1222         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1223         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1225         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1226         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1227         { 0xFFFFFFFF }
1228 };
1229
1230 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1231 {
1232         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1233         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1234         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1235         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1236         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1238         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1239         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1240         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1241         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1242         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1243         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1244         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1245         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1246         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1247         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1248         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1249         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1250         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1251         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1252         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1253         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1254         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1255         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1256         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1257         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1258         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1259         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1260         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1261         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1262         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1263         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1264         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1265         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1266         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1267         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1268         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1269         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1270         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1271         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1272         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1273         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1275         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1276         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1277         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1278         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1279         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1280         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1281         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1282         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1283         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1284         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1285         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1286         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1287         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1288         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1290         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1291         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1292         { 0xFFFFFFFF }
1293 };
1294
1295 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1296 {
1297         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1298         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1299         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1300         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1301         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1303         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1304         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1305         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1306         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1307         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1308         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1309         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1310         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1311         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1312         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1313         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1314         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1315         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1316         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1317         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1318         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1319         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1320         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1321         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1322         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1323         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1324         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1325         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1326         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1327         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1328         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1329         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1330         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1331         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1332         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1333         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1334         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1335         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1336         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1337         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1338         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1340         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1341         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1342         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1343         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1344         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1345         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1346         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1347         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1348         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1349         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1350         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1351         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1352         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1353         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1355         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1356         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1357         { 0xFFFFFFFF }
1358 };
1359
1360 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1361 {
1362         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1363         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1364         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1365         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1366         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1368         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1369         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1370         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1371         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1372         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1373         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1374         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1375         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1376         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1377         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1378         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1379         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1380         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1381         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1382         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1383         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1384         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1385         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1386         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1387         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1388         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1389         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1390         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1391         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1392         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1393         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1394         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1395         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1396         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1397         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1398         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1399         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1400         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1401         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1402         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1403         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1405         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1406         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1407         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1408         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1409         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1410         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1411         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1412         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1413         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1414         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1415         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1416         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1417         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1418         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1420         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1421         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1422         { 0xFFFFFFFF }
1423 };
1424
1425 static const struct si_cac_config_reg lcac_oland[] =
1426 {
1427         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1428         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1429         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1430         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1432         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1436         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1438         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1440         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1442         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1444         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1454         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1456         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1458         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1468         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1469         { 0xFFFFFFFF }
1470 };
1471
1472 static const struct si_cac_config_reg lcac_mars_pro[] =
1473 {
1474         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1475         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1476         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1477         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1479         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1483         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1485         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1489         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1491         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1501         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1503         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1505         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1515         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516         { 0xFFFFFFFF }
1517 };
1518
1519 static const struct si_cac_config_reg cac_override_oland[] =
1520 {
1521         { 0xFFFFFFFF }
1522 };
1523
1524 static const struct si_powertune_data powertune_data_oland =
1525 {
1526         ((1 << 16) | 0x6993),
1527         5,
1528         0,
1529         7,
1530         105,
1531         {
1532                 0UL,
1533                 0UL,
1534                 7194395UL,
1535                 309631529UL,
1536                 -1270850L,
1537                 4513710L,
1538                 100
1539         },
1540         117830498UL,
1541         12,
1542         {
1543                 0,
1544                 0,
1545                 0,
1546                 0,
1547                 0,
1548                 0,
1549                 0,
1550                 0
1551         },
1552         true
1553 };
1554
1555 static const struct si_powertune_data powertune_data_mars_pro =
1556 {
1557         ((1 << 16) | 0x6993),
1558         5,
1559         0,
1560         7,
1561         105,
1562         {
1563                 0UL,
1564                 0UL,
1565                 7194395UL,
1566                 309631529UL,
1567                 -1270850L,
1568                 4513710L,
1569                 100
1570         },
1571         117830498UL,
1572         12,
1573         {
1574                 0,
1575                 0,
1576                 0,
1577                 0,
1578                 0,
1579                 0,
1580                 0,
1581                 0
1582         },
1583         true
1584 };
1585
1586 static const struct si_dte_data dte_data_oland =
1587 {
1588         { 0, 0, 0, 0, 0 },
1589         { 0, 0, 0, 0, 0 },
1590         0,
1591         0,
1592         0,
1593         0,
1594         0,
1595         0,
1596         0,
1597         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1600         0,
1601         false
1602 };
1603
1604 static const struct si_dte_data dte_data_mars_pro =
1605 {
1606         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1607         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1608         5,
1609         55000,
1610         105,
1611         0xA,
1612         1,
1613         0,
1614         0x10,
1615         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1616         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1617         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1618         90,
1619         true
1620 };
1621
1622 static const struct si_dte_data dte_data_sun_xt =
1623 {
1624         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1625         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1626         5,
1627         55000,
1628         105,
1629         0xA,
1630         1,
1631         0,
1632         0x10,
1633         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1634         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1635         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1636         90,
1637         true
1638 };
1639
1640
1641 static const struct si_cac_config_reg cac_weights_hainan[] =
1642 {
1643         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1644         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1645         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1646         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1647         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1648         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1649         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1650         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1651         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1652         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1653         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1654         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1655         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1656         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1657         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1658         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1659         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1660         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1661         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1662         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1663         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1664         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1665         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1666         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1667         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1668         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1669         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1670         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1671         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1672         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1674         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1675         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1677         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1678         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1679         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1680         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1681         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1682         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1683         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1684         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1685         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1686         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1687         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1688         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1689         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1690         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1691         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1701         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1702         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1703         { 0xFFFFFFFF }
1704 };
1705
1706 static const struct si_powertune_data powertune_data_hainan =
1707 {
1708         ((1 << 16) | 0x6993),
1709         5,
1710         0,
1711         9,
1712         105,
1713         {
1714                 0UL,
1715                 0UL,
1716                 7194395UL,
1717                 309631529UL,
1718                 -1270850L,
1719                 4513710L,
1720                 100
1721         },
1722         117830498UL,
1723         12,
1724         {
1725                 0,
1726                 0,
1727                 0,
1728                 0,
1729                 0,
1730                 0,
1731                 0,
1732                 0
1733         },
1734         true
1735 };
1736
1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1741
1742 extern int si_mc_load_microcode(struct radeon_device *rdev);
1743
1744 static int si_populate_voltage_value(struct radeon_device *rdev,
1745                                      const struct atom_voltage_table *table,
1746                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1747 static int si_get_std_voltage_value(struct radeon_device *rdev,
1748                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1749                                     u16 *std_voltage);
1750 static int si_write_smc_soft_register(struct radeon_device *rdev,
1751                                       u16 reg_offset, u32 value);
1752 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1753                                          struct rv7xx_pl *pl,
1754                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1755 static int si_calculate_sclk_params(struct radeon_device *rdev,
1756                                     u32 engine_clock,
1757                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1758
1759 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1760 {
1761         struct si_power_info *pi = rdev->pm.dpm.priv;
1762
1763         return pi;
1764 }
1765
1766 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1767                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1768 {
1769         s64 kt, kv, leakage_w, i_leakage, vddc;
1770         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1771         s64 tmp;
1772
1773         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1774         vddc = div64_s64(drm_int2fixp(v), 1000);
1775         temperature = div64_s64(drm_int2fixp(t), 1000);
1776
1777         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1778         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1779         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1780         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1781         t_ref = drm_int2fixp(coeff->t_ref);
1782
1783         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1784         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1785         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1786         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1787
1788         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1789
1790         *leakage = drm_fixp2int(leakage_w * 1000);
1791 }
1792
1793 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1794                                              const struct ni_leakage_coeffients *coeff,
1795                                              u16 v,
1796                                              s32 t,
1797                                              u32 i_leakage,
1798                                              u32 *leakage)
1799 {
1800         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1801 }
1802
1803 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1804                                                const u32 fixed_kt, u16 v,
1805                                                u32 ileakage, u32 *leakage)
1806 {
1807         s64 kt, kv, leakage_w, i_leakage, vddc;
1808
1809         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1810         vddc = div64_s64(drm_int2fixp(v), 1000);
1811
1812         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1813         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1814                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1815
1816         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1817
1818         *leakage = drm_fixp2int(leakage_w * 1000);
1819 }
1820
1821 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1822                                        const struct ni_leakage_coeffients *coeff,
1823                                        const u32 fixed_kt,
1824                                        u16 v,
1825                                        u32 i_leakage,
1826                                        u32 *leakage)
1827 {
1828         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1829 }
1830
1831
1832 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1833                                    struct si_dte_data *dte_data)
1834 {
1835         u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1836         u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1837         u32 k = dte_data->k;
1838         u32 t_max = dte_data->max_t;
1839         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1840         u32 t_0 = dte_data->t0;
1841         u32 i;
1842
1843         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1844                 dte_data->tdep_count = 3;
1845
1846                 for (i = 0; i < k; i++) {
1847                         dte_data->r[i] =
1848                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1849                                 (p_limit2  * (u32)100);
1850                 }
1851
1852                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1853
1854                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1855                         dte_data->tdep_r[i] = dte_data->r[4];
1856                 }
1857         } else {
1858                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1859         }
1860 }
1861
1862 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1863 {
1864         struct ni_power_info *ni_pi = ni_get_pi(rdev);
1865         struct si_power_info *si_pi = si_get_pi(rdev);
1866         bool update_dte_from_pl2 = false;
1867
1868         if (rdev->family == CHIP_TAHITI) {
1869                 si_pi->cac_weights = cac_weights_tahiti;
1870                 si_pi->lcac_config = lcac_tahiti;
1871                 si_pi->cac_override = cac_override_tahiti;
1872                 si_pi->powertune_data = &powertune_data_tahiti;
1873                 si_pi->dte_data = dte_data_tahiti;
1874
1875                 switch (rdev->pdev->device) {
1876                 case 0x6798:
1877                         si_pi->dte_data.enable_dte_by_default = true;
1878                         break;
1879                 case 0x6799:
1880                         si_pi->dte_data = dte_data_new_zealand;
1881                         break;
1882                 case 0x6790:
1883                 case 0x6791:
1884                 case 0x6792:
1885                 case 0x679E:
1886                         si_pi->dte_data = dte_data_aruba_pro;
1887                         update_dte_from_pl2 = true;
1888                         break;
1889                 case 0x679B:
1890                         si_pi->dte_data = dte_data_malta;
1891                         update_dte_from_pl2 = true;
1892                         break;
1893                 case 0x679A:
1894                         si_pi->dte_data = dte_data_tahiti_pro;
1895                         update_dte_from_pl2 = true;
1896                         break;
1897                 default:
1898                         if (si_pi->dte_data.enable_dte_by_default == true)
1899                                 DRM_ERROR("DTE is not enabled!\n");
1900                         break;
1901                 }
1902         } else if (rdev->family == CHIP_PITCAIRN) {
1903                 switch (rdev->pdev->device) {
1904                 case 0x6810:
1905                 case 0x6818:
1906                         si_pi->cac_weights = cac_weights_pitcairn;
1907                         si_pi->lcac_config = lcac_pitcairn;
1908                         si_pi->cac_override = cac_override_pitcairn;
1909                         si_pi->powertune_data = &powertune_data_pitcairn;
1910                         si_pi->dte_data = dte_data_curacao_xt;
1911                         update_dte_from_pl2 = true;
1912                         break;
1913                 case 0x6819:
1914                 case 0x6811:
1915                         si_pi->cac_weights = cac_weights_pitcairn;
1916                         si_pi->lcac_config = lcac_pitcairn;
1917                         si_pi->cac_override = cac_override_pitcairn;
1918                         si_pi->powertune_data = &powertune_data_pitcairn;
1919                         si_pi->dte_data = dte_data_curacao_pro;
1920                         update_dte_from_pl2 = true;
1921                         break;
1922                 case 0x6800:
1923                 case 0x6806:
1924                         si_pi->cac_weights = cac_weights_pitcairn;
1925                         si_pi->lcac_config = lcac_pitcairn;
1926                         si_pi->cac_override = cac_override_pitcairn;
1927                         si_pi->powertune_data = &powertune_data_pitcairn;
1928                         si_pi->dte_data = dte_data_neptune_xt;
1929                         update_dte_from_pl2 = true;
1930                         break;
1931                 default:
1932                         si_pi->cac_weights = cac_weights_pitcairn;
1933                         si_pi->lcac_config = lcac_pitcairn;
1934                         si_pi->cac_override = cac_override_pitcairn;
1935                         si_pi->powertune_data = &powertune_data_pitcairn;
1936                         si_pi->dte_data = dte_data_pitcairn;
1937                         break;
1938                 }
1939         } else if (rdev->family == CHIP_VERDE) {
1940                 si_pi->lcac_config = lcac_cape_verde;
1941                 si_pi->cac_override = cac_override_cape_verde;
1942                 si_pi->powertune_data = &powertune_data_cape_verde;
1943
1944                 switch (rdev->pdev->device) {
1945                 case 0x683B:
1946                 case 0x683F:
1947                 case 0x6829:
1948                 case 0x6835:
1949                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1950                         si_pi->dte_data = dte_data_cape_verde;
1951                         break;
1952                 case 0x682C:
1953                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1954                         si_pi->dte_data = dte_data_sun_xt;
1955                         break;
1956                 case 0x6825:
1957                 case 0x6827:
1958                         si_pi->cac_weights = cac_weights_heathrow;
1959                         si_pi->dte_data = dte_data_cape_verde;
1960                         break;
1961                 case 0x6824:
1962                 case 0x682D:
1963                         si_pi->cac_weights = cac_weights_chelsea_xt;
1964                         si_pi->dte_data = dte_data_cape_verde;
1965                         break;
1966                 case 0x682F:
1967                         si_pi->cac_weights = cac_weights_chelsea_pro;
1968                         si_pi->dte_data = dte_data_cape_verde;
1969                         break;
1970                 case 0x6820:
1971                         si_pi->cac_weights = cac_weights_heathrow;
1972                         si_pi->dte_data = dte_data_venus_xtx;
1973                         break;
1974                 case 0x6821:
1975                         si_pi->cac_weights = cac_weights_heathrow;
1976                         si_pi->dte_data = dte_data_venus_xt;
1977                         break;
1978                 case 0x6823:
1979                 case 0x682B:
1980                 case 0x6822:
1981                 case 0x682A:
1982                         si_pi->cac_weights = cac_weights_chelsea_pro;
1983                         si_pi->dte_data = dte_data_venus_pro;
1984                         break;
1985                 default:
1986                         si_pi->cac_weights = cac_weights_cape_verde;
1987                         si_pi->dte_data = dte_data_cape_verde;
1988                         break;
1989                 }
1990         } else if (rdev->family == CHIP_OLAND) {
1991                 switch (rdev->pdev->device) {
1992                 case 0x6601:
1993                 case 0x6621:
1994                 case 0x6603:
1995                 case 0x6605:
1996                         si_pi->cac_weights = cac_weights_mars_pro;
1997                         si_pi->lcac_config = lcac_mars_pro;
1998                         si_pi->cac_override = cac_override_oland;
1999                         si_pi->powertune_data = &powertune_data_mars_pro;
2000                         si_pi->dte_data = dte_data_mars_pro;
2001                         update_dte_from_pl2 = true;
2002                         break;
2003                 case 0x6600:
2004                 case 0x6606:
2005                 case 0x6620:
2006                 case 0x6604:
2007                         si_pi->cac_weights = cac_weights_mars_xt;
2008                         si_pi->lcac_config = lcac_mars_pro;
2009                         si_pi->cac_override = cac_override_oland;
2010                         si_pi->powertune_data = &powertune_data_mars_pro;
2011                         si_pi->dte_data = dte_data_mars_pro;
2012                         update_dte_from_pl2 = true;
2013                         break;
2014                 case 0x6611:
2015                 case 0x6613:
2016                 case 0x6608:
2017                         si_pi->cac_weights = cac_weights_oland_pro;
2018                         si_pi->lcac_config = lcac_mars_pro;
2019                         si_pi->cac_override = cac_override_oland;
2020                         si_pi->powertune_data = &powertune_data_mars_pro;
2021                         si_pi->dte_data = dte_data_mars_pro;
2022                         update_dte_from_pl2 = true;
2023                         break;
2024                 case 0x6610:
2025                         si_pi->cac_weights = cac_weights_oland_xt;
2026                         si_pi->lcac_config = lcac_mars_pro;
2027                         si_pi->cac_override = cac_override_oland;
2028                         si_pi->powertune_data = &powertune_data_mars_pro;
2029                         si_pi->dte_data = dte_data_mars_pro;
2030                         update_dte_from_pl2 = true;
2031                         break;
2032                 default:
2033                         si_pi->cac_weights = cac_weights_oland;
2034                         si_pi->lcac_config = lcac_oland;
2035                         si_pi->cac_override = cac_override_oland;
2036                         si_pi->powertune_data = &powertune_data_oland;
2037                         si_pi->dte_data = dte_data_oland;
2038                         break;
2039                 }
2040         } else if (rdev->family == CHIP_HAINAN) {
2041                 si_pi->cac_weights = cac_weights_hainan;
2042                 si_pi->lcac_config = lcac_oland;
2043                 si_pi->cac_override = cac_override_oland;
2044                 si_pi->powertune_data = &powertune_data_hainan;
2045                 si_pi->dte_data = dte_data_sun_xt;
2046                 update_dte_from_pl2 = true;
2047         } else {
2048                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2049                 return;
2050         }
2051
2052         ni_pi->enable_power_containment = false;
2053         ni_pi->enable_cac = false;
2054         ni_pi->enable_sq_ramping = false;
2055         si_pi->enable_dte = false;
2056
2057         if (si_pi->powertune_data->enable_powertune_by_default) {
2058                 ni_pi->enable_power_containment= true;
2059                 ni_pi->enable_cac = true;
2060                 if (si_pi->dte_data.enable_dte_by_default) {
2061                         si_pi->enable_dte = true;
2062                         if (update_dte_from_pl2)
2063                                 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2064
2065                 }
2066                 ni_pi->enable_sq_ramping = true;
2067         }
2068
2069         ni_pi->driver_calculate_cac_leakage = true;
2070         ni_pi->cac_configuration_required = true;
2071
2072         if (ni_pi->cac_configuration_required) {
2073                 ni_pi->support_cac_long_term_average = true;
2074                 si_pi->dyn_powertune_data.l2_lta_window_size =
2075                         si_pi->powertune_data->l2_lta_window_size_default;
2076                 si_pi->dyn_powertune_data.lts_truncate =
2077                         si_pi->powertune_data->lts_truncate_default;
2078         } else {
2079                 ni_pi->support_cac_long_term_average = false;
2080                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2081                 si_pi->dyn_powertune_data.lts_truncate = 0;
2082         }
2083
2084         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2085 }
2086
2087 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2088 {
2089         return 1;
2090 }
2091
2092 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2093 {
2094         u32 xclk;
2095         u32 wintime;
2096         u32 cac_window;
2097         u32 cac_window_size;
2098
2099         xclk = radeon_get_xclk(rdev);
2100
2101         if (xclk == 0)
2102                 return 0;
2103
2104         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2105         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2106
2107         wintime = (cac_window_size * 100) / xclk;
2108
2109         return wintime;
2110 }
2111
2112 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2113 {
2114         return power_in_watts;
2115 }
2116
2117 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2118                                             bool adjust_polarity,
2119                                             u32 tdp_adjustment,
2120                                             u32 *tdp_limit,
2121                                             u32 *near_tdp_limit)
2122 {
2123         u32 adjustment_delta, max_tdp_limit;
2124
2125         if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2126                 return -EINVAL;
2127
2128         max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2129
2130         if (adjust_polarity) {
2131                 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2132                 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2133         } else {
2134                 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2135                 adjustment_delta  = rdev->pm.dpm.tdp_limit - *tdp_limit;
2136                 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2137                         *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2138                 else
2139                         *near_tdp_limit = 0;
2140         }
2141
2142         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2143                 return -EINVAL;
2144         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2145                 return -EINVAL;
2146
2147         return 0;
2148 }
2149
2150 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2151                                       struct radeon_ps *radeon_state)
2152 {
2153         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2154         struct si_power_info *si_pi = si_get_pi(rdev);
2155
2156         if (ni_pi->enable_power_containment) {
2157                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2158                 PP_SIslands_PAPMParameters *papm_parm;
2159                 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2160                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2161                 u32 tdp_limit;
2162                 u32 near_tdp_limit;
2163                 int ret;
2164
2165                 if (scaling_factor == 0)
2166                         return -EINVAL;
2167
2168                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2169
2170                 ret = si_calculate_adjusted_tdp_limits(rdev,
2171                                                        false, /* ??? */
2172                                                        rdev->pm.dpm.tdp_adjustment,
2173                                                        &tdp_limit,
2174                                                        &near_tdp_limit);
2175                 if (ret)
2176                         return ret;
2177
2178                 smc_table->dpm2Params.TDPLimit =
2179                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2180                 smc_table->dpm2Params.NearTDPLimit =
2181                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2182                 smc_table->dpm2Params.SafePowerLimit =
2183                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2184
2185                 ret = si_copy_bytes_to_smc(rdev,
2186                                            (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2187                                                  offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2188                                            (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2189                                            sizeof(u32) * 3,
2190                                            si_pi->sram_end);
2191                 if (ret)
2192                         return ret;
2193
2194                 if (si_pi->enable_ppm) {
2195                         papm_parm = &si_pi->papm_parm;
2196                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2197                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2198                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2199                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2200                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2201                         papm_parm->PlatformPowerLimit = 0xffffffff;
2202                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2203
2204                         ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2205                                                    (u8 *)papm_parm,
2206                                                    sizeof(PP_SIslands_PAPMParameters),
2207                                                    si_pi->sram_end);
2208                         if (ret)
2209                                 return ret;
2210                 }
2211         }
2212         return 0;
2213 }
2214
2215 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2216                                         struct radeon_ps *radeon_state)
2217 {
2218         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2219         struct si_power_info *si_pi = si_get_pi(rdev);
2220
2221         if (ni_pi->enable_power_containment) {
2222                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2223                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2224                 int ret;
2225
2226                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2227
2228                 smc_table->dpm2Params.NearTDPLimit =
2229                         cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2230                 smc_table->dpm2Params.SafePowerLimit =
2231                         cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2232
2233                 ret = si_copy_bytes_to_smc(rdev,
2234                                            (si_pi->state_table_start +
2235                                             offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2236                                             offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2237                                            (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2238                                            sizeof(u32) * 2,
2239                                            si_pi->sram_end);
2240                 if (ret)
2241                         return ret;
2242         }
2243
2244         return 0;
2245 }
2246
2247 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2248                                                const u16 prev_std_vddc,
2249                                                const u16 curr_std_vddc)
2250 {
2251         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2252         u64 prev_vddc = (u64)prev_std_vddc;
2253         u64 curr_vddc = (u64)curr_std_vddc;
2254         u64 pwr_efficiency_ratio, n, d;
2255
2256         if ((prev_vddc == 0) || (curr_vddc == 0))
2257                 return 0;
2258
2259         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2260         d = prev_vddc * prev_vddc;
2261         pwr_efficiency_ratio = div64_u64(n, d);
2262
2263         if (pwr_efficiency_ratio > (u64)0xFFFF)
2264                 return 0;
2265
2266         return (u16)pwr_efficiency_ratio;
2267 }
2268
2269 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2270                                             struct radeon_ps *radeon_state)
2271 {
2272         struct si_power_info *si_pi = si_get_pi(rdev);
2273
2274         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2275             radeon_state->vclk && radeon_state->dclk)
2276                 return true;
2277
2278         return false;
2279 }
2280
2281 static int si_populate_power_containment_values(struct radeon_device *rdev,
2282                                                 struct radeon_ps *radeon_state,
2283                                                 SISLANDS_SMC_SWSTATE *smc_state)
2284 {
2285         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2286         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2287         struct ni_ps *state = ni_get_ps(radeon_state);
2288         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2289         u32 prev_sclk;
2290         u32 max_sclk;
2291         u32 min_sclk;
2292         u16 prev_std_vddc;
2293         u16 curr_std_vddc;
2294         int i;
2295         u16 pwr_efficiency_ratio;
2296         u8 max_ps_percent;
2297         bool disable_uvd_power_tune;
2298         int ret;
2299
2300         if (ni_pi->enable_power_containment == false)
2301                 return 0;
2302
2303         if (state->performance_level_count == 0)
2304                 return -EINVAL;
2305
2306         if (smc_state->levelCount != state->performance_level_count)
2307                 return -EINVAL;
2308
2309         disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2310
2311         smc_state->levels[0].dpm2.MaxPS = 0;
2312         smc_state->levels[0].dpm2.NearTDPDec = 0;
2313         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2314         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2315         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2316
2317         for (i = 1; i < state->performance_level_count; i++) {
2318                 prev_sclk = state->performance_levels[i-1].sclk;
2319                 max_sclk  = state->performance_levels[i].sclk;
2320                 if (i == 1)
2321                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2322                 else
2323                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2324
2325                 if (prev_sclk > max_sclk)
2326                         return -EINVAL;
2327
2328                 if ((max_ps_percent == 0) ||
2329                     (prev_sclk == max_sclk) ||
2330                     disable_uvd_power_tune) {
2331                         min_sclk = max_sclk;
2332                 } else if (i == 1) {
2333                         min_sclk = prev_sclk;
2334                 } else {
2335                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2336                 }
2337
2338                 if (min_sclk < state->performance_levels[0].sclk)
2339                         min_sclk = state->performance_levels[0].sclk;
2340
2341                 if (min_sclk == 0)
2342                         return -EINVAL;
2343
2344                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2345                                                 state->performance_levels[i-1].vddc, &vddc);
2346                 if (ret)
2347                         return ret;
2348
2349                 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2350                 if (ret)
2351                         return ret;
2352
2353                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2354                                                 state->performance_levels[i].vddc, &vddc);
2355                 if (ret)
2356                         return ret;
2357
2358                 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2359                 if (ret)
2360                         return ret;
2361
2362                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2363                                                                            prev_std_vddc, curr_std_vddc);
2364
2365                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2366                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2367                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2368                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2369                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2370         }
2371
2372         return 0;
2373 }
2374
2375 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2376                                          struct radeon_ps *radeon_state,
2377                                          SISLANDS_SMC_SWSTATE *smc_state)
2378 {
2379         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2380         struct ni_ps *state = ni_get_ps(radeon_state);
2381         u32 sq_power_throttle, sq_power_throttle2;
2382         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2383         int i;
2384
2385         if (state->performance_level_count == 0)
2386                 return -EINVAL;
2387
2388         if (smc_state->levelCount != state->performance_level_count)
2389                 return -EINVAL;
2390
2391         if (rdev->pm.dpm.sq_ramping_threshold == 0)
2392                 return -EINVAL;
2393
2394         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2395                 enable_sq_ramping = false;
2396
2397         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2398                 enable_sq_ramping = false;
2399
2400         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2401                 enable_sq_ramping = false;
2402
2403         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2404                 enable_sq_ramping = false;
2405
2406         if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2407                 enable_sq_ramping = false;
2408
2409         for (i = 0; i < state->performance_level_count; i++) {
2410                 sq_power_throttle = 0;
2411                 sq_power_throttle2 = 0;
2412
2413                 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2414                     enable_sq_ramping) {
2415                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2416                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2417                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2418                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2419                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2420                 } else {
2421                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2422                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2423                 }
2424
2425                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2426                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2427         }
2428
2429         return 0;
2430 }
2431
2432 static int si_enable_power_containment(struct radeon_device *rdev,
2433                                        struct radeon_ps *radeon_new_state,
2434                                        bool enable)
2435 {
2436         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2437         PPSMC_Result smc_result;
2438         int ret = 0;
2439
2440         if (ni_pi->enable_power_containment) {
2441                 if (enable) {
2442                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2443                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2444                                 if (smc_result != PPSMC_Result_OK) {
2445                                         ret = -EINVAL;
2446                                         ni_pi->pc_enabled = false;
2447                                 } else {
2448                                         ni_pi->pc_enabled = true;
2449                                 }
2450                         }
2451                 } else {
2452                         smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2453                         if (smc_result != PPSMC_Result_OK)
2454                                 ret = -EINVAL;
2455                         ni_pi->pc_enabled = false;
2456                 }
2457         }
2458
2459         return ret;
2460 }
2461
2462 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2463 {
2464         struct si_power_info *si_pi = si_get_pi(rdev);
2465         int ret = 0;
2466         struct si_dte_data *dte_data = &si_pi->dte_data;
2467         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2468         u32 table_size;
2469         u8 tdep_count;
2470         u32 i;
2471
2472         if (dte_data == NULL)
2473                 si_pi->enable_dte = false;
2474
2475         if (si_pi->enable_dte == false)
2476                 return 0;
2477
2478         if (dte_data->k <= 0)
2479                 return -EINVAL;
2480
2481         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2482         if (dte_tables == NULL) {
2483                 si_pi->enable_dte = false;
2484                 return -ENOMEM;
2485         }
2486
2487         table_size = dte_data->k;
2488
2489         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2490                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2491
2492         tdep_count = dte_data->tdep_count;
2493         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2494                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2495
2496         dte_tables->K = cpu_to_be32(table_size);
2497         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2498         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2499         dte_tables->WindowSize = dte_data->window_size;
2500         dte_tables->temp_select = dte_data->temp_select;
2501         dte_tables->DTE_mode = dte_data->dte_mode;
2502         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2503
2504         if (tdep_count > 0)
2505                 table_size--;
2506
2507         for (i = 0; i < table_size; i++) {
2508                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2509                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2510         }
2511
2512         dte_tables->Tdep_count = tdep_count;
2513
2514         for (i = 0; i < (u32)tdep_count; i++) {
2515                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2516                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2517                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2518         }
2519
2520         ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2521                                    sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2522         kfree(dte_tables);
2523
2524         return ret;
2525 }
2526
2527 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2528                                           u16 *max, u16 *min)
2529 {
2530         struct si_power_info *si_pi = si_get_pi(rdev);
2531         struct radeon_cac_leakage_table *table =
2532                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2533         u32 i;
2534         u32 v0_loadline;
2535
2536
2537         if (table == NULL)
2538                 return -EINVAL;
2539
2540         *max = 0;
2541         *min = 0xFFFF;
2542
2543         for (i = 0; i < table->count; i++) {
2544                 if (table->entries[i].vddc > *max)
2545                         *max = table->entries[i].vddc;
2546                 if (table->entries[i].vddc < *min)
2547                         *min = table->entries[i].vddc;
2548         }
2549
2550         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2551                 return -EINVAL;
2552
2553         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2554
2555         if (v0_loadline > 0xFFFFUL)
2556                 return -EINVAL;
2557
2558         *min = (u16)v0_loadline;
2559
2560         if ((*min > *max) || (*max == 0) || (*min == 0))
2561                 return -EINVAL;
2562
2563         return 0;
2564 }
2565
2566 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2567 {
2568         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2569                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2570 }
2571
2572 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2573                                      PP_SIslands_CacConfig *cac_tables,
2574                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2575                                      u16 t0, u16 t_step)
2576 {
2577         struct si_power_info *si_pi = si_get_pi(rdev);
2578         u32 leakage;
2579         unsigned int i, j;
2580         s32 t;
2581         u32 smc_leakage;
2582         u32 scaling_factor;
2583         u16 voltage;
2584
2585         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2586
2587         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2588                 t = (1000 * (i * t_step + t0));
2589
2590                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2591                         voltage = vddc_max - (vddc_step * j);
2592
2593                         si_calculate_leakage_for_v_and_t(rdev,
2594                                                          &si_pi->powertune_data->leakage_coefficients,
2595                                                          voltage,
2596                                                          t,
2597                                                          si_pi->dyn_powertune_data.cac_leakage,
2598                                                          &leakage);
2599
2600                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2601
2602                         if (smc_leakage > 0xFFFF)
2603                                 smc_leakage = 0xFFFF;
2604
2605                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2606                                 cpu_to_be16((u16)smc_leakage);
2607                 }
2608         }
2609         return 0;
2610 }
2611
2612 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2613                                             PP_SIslands_CacConfig *cac_tables,
2614                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2615 {
2616         struct si_power_info *si_pi = si_get_pi(rdev);
2617         u32 leakage;
2618         unsigned int i, j;
2619         u32 smc_leakage;
2620         u32 scaling_factor;
2621         u16 voltage;
2622
2623         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2624
2625         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2626                 voltage = vddc_max - (vddc_step * j);
2627
2628                 si_calculate_leakage_for_v(rdev,
2629                                            &si_pi->powertune_data->leakage_coefficients,
2630                                            si_pi->powertune_data->fixed_kt,
2631                                            voltage,
2632                                            si_pi->dyn_powertune_data.cac_leakage,
2633                                            &leakage);
2634
2635                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2636
2637                 if (smc_leakage > 0xFFFF)
2638                         smc_leakage = 0xFFFF;
2639
2640                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2641                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2642                                 cpu_to_be16((u16)smc_leakage);
2643         }
2644         return 0;
2645 }
2646
2647 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2648 {
2649         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2650         struct si_power_info *si_pi = si_get_pi(rdev);
2651         PP_SIslands_CacConfig *cac_tables = NULL;
2652         u16 vddc_max, vddc_min, vddc_step;
2653         u16 t0, t_step;
2654         u32 load_line_slope, reg;
2655         int ret = 0;
2656         u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2657
2658         if (ni_pi->enable_cac == false)
2659                 return 0;
2660
2661         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2662         if (!cac_tables)
2663                 return -ENOMEM;
2664
2665         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2666         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2667         WREG32(CG_CAC_CTRL, reg);
2668
2669         si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2670         si_pi->dyn_powertune_data.dc_pwr_value =
2671                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2672         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2673         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2674
2675         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2676
2677         ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2678         if (ret)
2679                 goto done_free;
2680
2681         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2682         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2683         t_step = 4;
2684         t0 = 60;
2685
2686         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2687                 ret = si_init_dte_leakage_table(rdev, cac_tables,
2688                                                 vddc_max, vddc_min, vddc_step,
2689                                                 t0, t_step);
2690         else
2691                 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2692                                                        vddc_max, vddc_min, vddc_step);
2693         if (ret)
2694                 goto done_free;
2695
2696         load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2697
2698         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2699         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2700         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2701         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2702         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2703         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2704         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2705         cac_tables->calculation_repeats = cpu_to_be32(2);
2706         cac_tables->dc_cac = cpu_to_be32(0);
2707         cac_tables->log2_PG_LKG_SCALE = 12;
2708         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2709         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2710         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2711
2712         ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2713                                    sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2714
2715         if (ret)
2716                 goto done_free;
2717
2718         ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2719
2720 done_free:
2721         if (ret) {
2722                 ni_pi->enable_cac = false;
2723                 ni_pi->enable_power_containment = false;
2724         }
2725
2726         kfree(cac_tables);
2727
2728         return 0;
2729 }
2730
2731 static int si_program_cac_config_registers(struct radeon_device *rdev,
2732                                            const struct si_cac_config_reg *cac_config_regs)
2733 {
2734         const struct si_cac_config_reg *config_regs = cac_config_regs;
2735         u32 data = 0, offset;
2736
2737         if (!config_regs)
2738                 return -EINVAL;
2739
2740         while (config_regs->offset != 0xFFFFFFFF) {
2741                 switch (config_regs->type) {
2742                 case SISLANDS_CACCONFIG_CGIND:
2743                         offset = SMC_CG_IND_START + config_regs->offset;
2744                         if (offset < SMC_CG_IND_END)
2745                                 data = RREG32_SMC(offset);
2746                         break;
2747                 default:
2748                         data = RREG32(config_regs->offset << 2);
2749                         break;
2750                 }
2751
2752                 data &= ~config_regs->mask;
2753                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2754
2755                 switch (config_regs->type) {
2756                 case SISLANDS_CACCONFIG_CGIND:
2757                         offset = SMC_CG_IND_START + config_regs->offset;
2758                         if (offset < SMC_CG_IND_END)
2759                                 WREG32_SMC(offset, data);
2760                         break;
2761                 default:
2762                         WREG32(config_regs->offset << 2, data);
2763                         break;
2764                 }
2765                 config_regs++;
2766         }
2767         return 0;
2768 }
2769
2770 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2771 {
2772         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2773         struct si_power_info *si_pi = si_get_pi(rdev);
2774         int ret;
2775
2776         if ((ni_pi->enable_cac == false) ||
2777             (ni_pi->cac_configuration_required == false))
2778                 return 0;
2779
2780         ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2781         if (ret)
2782                 return ret;
2783         ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2784         if (ret)
2785                 return ret;
2786         ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2787         if (ret)
2788                 return ret;
2789
2790         return 0;
2791 }
2792
2793 static int si_enable_smc_cac(struct radeon_device *rdev,
2794                              struct radeon_ps *radeon_new_state,
2795                              bool enable)
2796 {
2797         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2798         struct si_power_info *si_pi = si_get_pi(rdev);
2799         PPSMC_Result smc_result;
2800         int ret = 0;
2801
2802         if (ni_pi->enable_cac) {
2803                 if (enable) {
2804                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2805                                 if (ni_pi->support_cac_long_term_average) {
2806                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2807                                         if (smc_result != PPSMC_Result_OK)
2808                                                 ni_pi->support_cac_long_term_average = false;
2809                                 }
2810
2811                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2812                                 if (smc_result != PPSMC_Result_OK) {
2813                                         ret = -EINVAL;
2814                                         ni_pi->cac_enabled = false;
2815                                 } else {
2816                                         ni_pi->cac_enabled = true;
2817                                 }
2818
2819                                 if (si_pi->enable_dte) {
2820                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2821                                         if (smc_result != PPSMC_Result_OK)
2822                                                 ret = -EINVAL;
2823                                 }
2824                         }
2825                 } else if (ni_pi->cac_enabled) {
2826                         if (si_pi->enable_dte)
2827                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2828
2829                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2830
2831                         ni_pi->cac_enabled = false;
2832
2833                         if (ni_pi->support_cac_long_term_average)
2834                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2835                 }
2836         }
2837         return ret;
2838 }
2839
2840 static int si_init_smc_spll_table(struct radeon_device *rdev)
2841 {
2842         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2843         struct si_power_info *si_pi = si_get_pi(rdev);
2844         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2845         SISLANDS_SMC_SCLK_VALUE sclk_params;
2846         u32 fb_div, p_div;
2847         u32 clk_s, clk_v;
2848         u32 sclk = 0;
2849         int ret = 0;
2850         u32 tmp;
2851         int i;
2852
2853         if (si_pi->spll_table_start == 0)
2854                 return -EINVAL;
2855
2856         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2857         if (spll_table == NULL)
2858                 return -ENOMEM;
2859
2860         for (i = 0; i < 256; i++) {
2861                 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2862                 if (ret)
2863                         break;
2864
2865                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2866                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2867                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2868                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2869
2870                 fb_div &= ~0x00001FFF;
2871                 fb_div >>= 1;
2872                 clk_v >>= 6;
2873
2874                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2875                         ret = -EINVAL;
2876                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2877                         ret = -EINVAL;
2878                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2879                         ret = -EINVAL;
2880                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2881                         ret = -EINVAL;
2882
2883                 if (ret)
2884                         break;
2885
2886                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2887                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2888                 spll_table->freq[i] = cpu_to_be32(tmp);
2889
2890                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2891                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2892                 spll_table->ss[i] = cpu_to_be32(tmp);
2893
2894                 sclk += 512;
2895         }
2896
2897
2898         if (!ret)
2899                 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2900                                            (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2901                                            si_pi->sram_end);
2902
2903         if (ret)
2904                 ni_pi->enable_power_containment = false;
2905
2906         kfree(spll_table);
2907
2908         return ret;
2909 }
2910
2911 struct si_dpm_quirk {
2912         u32 chip_vendor;
2913         u32 chip_device;
2914         u32 subsys_vendor;
2915         u32 subsys_device;
2916         u32 max_sclk;
2917         u32 max_mclk;
2918 };
2919
2920 /* cards with dpm stability problems */
2921 static struct si_dpm_quirk si_dpm_quirk_list[] = {
2922         /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
2923         { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
2924         { 0, 0, 0, 0 },
2925 };
2926
2927 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2928                                         struct radeon_ps *rps)
2929 {
2930         struct ni_ps *ps = ni_get_ps(rps);
2931         struct radeon_clock_and_voltage_limits *max_limits;
2932         bool disable_mclk_switching = false;
2933         bool disable_sclk_switching = false;
2934         u32 mclk, sclk;
2935         u16 vddc, vddci;
2936         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2937         u32 max_sclk = 0, max_mclk = 0;
2938         int i;
2939         struct si_dpm_quirk *p = si_dpm_quirk_list;
2940
2941         /* Apply dpm quirks */
2942         while (p && p->chip_device != 0) {
2943                 if (rdev->pdev->vendor == p->chip_vendor &&
2944                     rdev->pdev->device == p->chip_device &&
2945                     rdev->pdev->subsystem_vendor == p->subsys_vendor &&
2946                     rdev->pdev->subsystem_device == p->subsys_device) {
2947                         max_sclk = p->max_sclk;
2948                         max_mclk = p->max_mclk;
2949                         break;
2950                 }
2951                 ++p;
2952         }
2953
2954         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2955             ni_dpm_vblank_too_short(rdev))
2956                 disable_mclk_switching = true;
2957
2958         if (rps->vclk || rps->dclk) {
2959                 disable_mclk_switching = true;
2960                 disable_sclk_switching = true;
2961         }
2962
2963         if (rdev->pm.dpm.ac_power)
2964                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2965         else
2966                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2967
2968         for (i = ps->performance_level_count - 2; i >= 0; i--) {
2969                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
2970                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
2971         }
2972         if (rdev->pm.dpm.ac_power == false) {
2973                 for (i = 0; i < ps->performance_level_count; i++) {
2974                         if (ps->performance_levels[i].mclk > max_limits->mclk)
2975                                 ps->performance_levels[i].mclk = max_limits->mclk;
2976                         if (ps->performance_levels[i].sclk > max_limits->sclk)
2977                                 ps->performance_levels[i].sclk = max_limits->sclk;
2978                         if (ps->performance_levels[i].vddc > max_limits->vddc)
2979                                 ps->performance_levels[i].vddc = max_limits->vddc;
2980                         if (ps->performance_levels[i].vddci > max_limits->vddci)
2981                                 ps->performance_levels[i].vddci = max_limits->vddci;
2982                 }
2983         }
2984
2985         /* limit clocks to max supported clocks based on voltage dependency tables */
2986         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2987                                                         &max_sclk_vddc);
2988         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2989                                                         &max_mclk_vddci);
2990         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2991                                                         &max_mclk_vddc);
2992
2993         for (i = 0; i < ps->performance_level_count; i++) {
2994                 if (max_sclk_vddc) {
2995                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
2996                                 ps->performance_levels[i].sclk = max_sclk_vddc;
2997                 }
2998                 if (max_mclk_vddci) {
2999                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
3000                                 ps->performance_levels[i].mclk = max_mclk_vddci;
3001                 }
3002                 if (max_mclk_vddc) {
3003                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
3004                                 ps->performance_levels[i].mclk = max_mclk_vddc;
3005                 }
3006                 if (max_mclk) {
3007                         if (ps->performance_levels[i].mclk > max_mclk)
3008                                 ps->performance_levels[i].mclk = max_mclk;
3009                 }
3010                 if (max_sclk) {
3011                         if (ps->performance_levels[i].sclk > max_sclk)
3012                                 ps->performance_levels[i].sclk = max_sclk;
3013                 }
3014         }
3015
3016         /* XXX validate the min clocks required for display */
3017
3018         if (disable_mclk_switching) {
3019                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3020                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3021         } else {
3022                 mclk = ps->performance_levels[0].mclk;
3023                 vddci = ps->performance_levels[0].vddci;
3024         }
3025
3026         if (disable_sclk_switching) {
3027                 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3028                 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3029         } else {
3030                 sclk = ps->performance_levels[0].sclk;
3031                 vddc = ps->performance_levels[0].vddc;
3032         }
3033
3034         /* adjusted low state */
3035         ps->performance_levels[0].sclk = sclk;
3036         ps->performance_levels[0].mclk = mclk;
3037         ps->performance_levels[0].vddc = vddc;
3038         ps->performance_levels[0].vddci = vddci;
3039
3040         if (disable_sclk_switching) {
3041                 sclk = ps->performance_levels[0].sclk;
3042                 for (i = 1; i < ps->performance_level_count; i++) {
3043                         if (sclk < ps->performance_levels[i].sclk)
3044                                 sclk = ps->performance_levels[i].sclk;
3045                 }
3046                 for (i = 0; i < ps->performance_level_count; i++) {
3047                         ps->performance_levels[i].sclk = sclk;
3048                         ps->performance_levels[i].vddc = vddc;
3049                 }
3050         } else {
3051                 for (i = 1; i < ps->performance_level_count; i++) {
3052                         if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3053                                 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3054                         if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3055                                 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3056                 }
3057         }
3058
3059         if (disable_mclk_switching) {
3060                 mclk = ps->performance_levels[0].mclk;
3061                 for (i = 1; i < ps->performance_level_count; i++) {
3062                         if (mclk < ps->performance_levels[i].mclk)
3063                                 mclk = ps->performance_levels[i].mclk;
3064                 }
3065                 for (i = 0; i < ps->performance_level_count; i++) {
3066                         ps->performance_levels[i].mclk = mclk;
3067                         ps->performance_levels[i].vddci = vddci;
3068                 }
3069         } else {
3070                 for (i = 1; i < ps->performance_level_count; i++) {
3071                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3072                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3073                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3074                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3075                 }
3076         }
3077
3078         for (i = 0; i < ps->performance_level_count; i++)
3079                 btc_adjust_clock_combinations(rdev, max_limits,
3080                                               &ps->performance_levels[i]);
3081
3082         for (i = 0; i < ps->performance_level_count; i++) {
3083                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3084                                                    ps->performance_levels[i].sclk,
3085                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3086                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3087                                                    ps->performance_levels[i].mclk,
3088                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
3089                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3090                                                    ps->performance_levels[i].mclk,
3091                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3092                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3093                                                    rdev->clock.current_dispclk,
3094                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3095         }
3096
3097         for (i = 0; i < ps->performance_level_count; i++) {
3098                 btc_apply_voltage_delta_rules(rdev,
3099                                               max_limits->vddc, max_limits->vddci,
3100                                               &ps->performance_levels[i].vddc,
3101                                               &ps->performance_levels[i].vddci);
3102         }
3103
3104         ps->dc_compatible = true;
3105         for (i = 0; i < ps->performance_level_count; i++) {
3106                 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3107                         ps->dc_compatible = false;
3108         }
3109
3110 }
3111
3112 #if 0
3113 static int si_read_smc_soft_register(struct radeon_device *rdev,
3114                                      u16 reg_offset, u32 *value)
3115 {
3116         struct si_power_info *si_pi = si_get_pi(rdev);
3117
3118         return si_read_smc_sram_dword(rdev,
3119                                       si_pi->soft_regs_start + reg_offset, value,
3120                                       si_pi->sram_end);
3121 }
3122 #endif
3123
3124 static int si_write_smc_soft_register(struct radeon_device *rdev,
3125                                       u16 reg_offset, u32 value)
3126 {
3127         struct si_power_info *si_pi = si_get_pi(rdev);
3128
3129         return si_write_smc_sram_dword(rdev,
3130                                        si_pi->soft_regs_start + reg_offset,
3131                                        value, si_pi->sram_end);
3132 }
3133
3134 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3135 {
3136         bool ret = false;
3137         u32 tmp, width, row, column, bank, density;
3138         bool is_memory_gddr5, is_special;
3139
3140         tmp = RREG32(MC_SEQ_MISC0);
3141         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3142         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3143                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3144
3145         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3146         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3147
3148         tmp = RREG32(MC_ARB_RAMCFG);
3149         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3150         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3151         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3152
3153         density = (1 << (row + column - 20 + bank)) * width;
3154
3155         if ((rdev->pdev->device == 0x6819) &&
3156             is_memory_gddr5 && is_special && (density == 0x400))
3157                 ret = true;
3158
3159         return ret;
3160 }
3161
3162 static void si_get_leakage_vddc(struct radeon_device *rdev)
3163 {
3164         struct si_power_info *si_pi = si_get_pi(rdev);
3165         u16 vddc, count = 0;
3166         int i, ret;
3167
3168         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3169                 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3170
3171                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3172                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3173                         si_pi->leakage_voltage.entries[count].leakage_index =
3174                                 SISLANDS_LEAKAGE_INDEX0 + i;
3175                         count++;
3176                 }
3177         }
3178         si_pi->leakage_voltage.count = count;
3179 }
3180
3181 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3182                                                      u32 index, u16 *leakage_voltage)
3183 {
3184         struct si_power_info *si_pi = si_get_pi(rdev);
3185         int i;
3186
3187         if (leakage_voltage == NULL)
3188                 return -EINVAL;
3189
3190         if ((index & 0xff00) != 0xff00)
3191                 return -EINVAL;
3192
3193         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3194                 return -EINVAL;
3195
3196         if (index < SISLANDS_LEAKAGE_INDEX0)
3197                 return -EINVAL;
3198
3199         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3200                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3201                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3202                         return 0;
3203                 }
3204         }
3205         return -EAGAIN;
3206 }
3207
3208 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3209 {
3210         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3211         bool want_thermal_protection;
3212         enum radeon_dpm_event_src dpm_event_src;
3213
3214         switch (sources) {
3215         case 0:
3216         default:
3217                 want_thermal_protection = false;
3218                 break;
3219         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3220                 want_thermal_protection = true;
3221                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3222                 break;
3223         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3224                 want_thermal_protection = true;
3225                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3226                 break;
3227         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3228               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3229                 want_thermal_protection = true;
3230                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3231                 break;
3232         }
3233
3234         if (want_thermal_protection) {
3235                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3236                 if (pi->thermal_protection)
3237                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3238         } else {
3239                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3240         }
3241 }
3242
3243 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3244                                            enum radeon_dpm_auto_throttle_src source,
3245                                            bool enable)
3246 {
3247         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3248
3249         if (enable) {
3250                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3251                         pi->active_auto_throttle_sources |= 1 << source;
3252                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3253                 }
3254         } else {
3255                 if (pi->active_auto_throttle_sources & (1 << source)) {
3256                         pi->active_auto_throttle_sources &= ~(1 << source);
3257                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3258                 }
3259         }
3260 }
3261
3262 static void si_start_dpm(struct radeon_device *rdev)
3263 {
3264         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3265 }
3266
3267 static void si_stop_dpm(struct radeon_device *rdev)
3268 {
3269         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3270 }
3271
3272 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3273 {
3274         if (enable)
3275                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3276         else
3277                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3278
3279 }
3280
3281 #if 0
3282 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3283                                                u32 thermal_level)
3284 {
3285         PPSMC_Result ret;
3286
3287         if (thermal_level == 0) {
3288                 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3289                 if (ret == PPSMC_Result_OK)
3290                         return 0;
3291                 else
3292                         return -EINVAL;
3293         }
3294         return 0;
3295 }
3296
3297 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3298 {
3299         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3300 }
3301 #endif
3302
3303 #if 0
3304 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3305 {
3306         if (ac_power)
3307                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3308                         0 : -EINVAL;
3309
3310         return 0;
3311 }
3312 #endif
3313
3314 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3315                                                       PPSMC_Msg msg, u32 parameter)
3316 {
3317         WREG32(SMC_SCRATCH0, parameter);
3318         return si_send_msg_to_smc(rdev, msg);
3319 }
3320
3321 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3322 {
3323         if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3324                 return -EINVAL;
3325
3326         return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3327                 0 : -EINVAL;
3328 }
3329
3330 int si_dpm_force_performance_level(struct radeon_device *rdev,
3331                                    enum radeon_dpm_forced_level level)
3332 {
3333         struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3334         struct ni_ps *ps = ni_get_ps(rps);
3335         u32 levels = ps->performance_level_count;
3336
3337         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3338                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3339                         return -EINVAL;
3340
3341                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3342                         return -EINVAL;
3343         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3344                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3345                         return -EINVAL;
3346
3347                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3348                         return -EINVAL;
3349         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3350                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3351                         return -EINVAL;
3352
3353                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3354                         return -EINVAL;
3355         }
3356
3357         rdev->pm.dpm.forced_level = level;
3358
3359         return 0;
3360 }
3361
3362 static int si_set_boot_state(struct radeon_device *rdev)
3363 {
3364         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3365                 0 : -EINVAL;
3366 }
3367
3368 static int si_set_sw_state(struct radeon_device *rdev)
3369 {
3370         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3371                 0 : -EINVAL;
3372 }
3373
3374 static int si_halt_smc(struct radeon_device *rdev)
3375 {
3376         if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3377                 return -EINVAL;
3378
3379         return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3380                 0 : -EINVAL;
3381 }
3382
3383 static int si_resume_smc(struct radeon_device *rdev)
3384 {
3385         if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3386                 return -EINVAL;
3387
3388         return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3389                 0 : -EINVAL;
3390 }
3391
3392 static void si_dpm_start_smc(struct radeon_device *rdev)
3393 {
3394         si_program_jump_on_start(rdev);
3395         si_start_smc(rdev);
3396         si_start_smc_clock(rdev);
3397 }
3398
3399 static void si_dpm_stop_smc(struct radeon_device *rdev)
3400 {
3401         si_reset_smc(rdev);
3402         si_stop_smc_clock(rdev);
3403 }
3404
3405 static int si_process_firmware_header(struct radeon_device *rdev)
3406 {
3407         struct si_power_info *si_pi = si_get_pi(rdev);
3408         u32 tmp;
3409         int ret;
3410
3411         ret = si_read_smc_sram_dword(rdev,
3412                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3413                                      SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3414                                      &tmp, si_pi->sram_end);
3415         if (ret)
3416                 return ret;
3417
3418         si_pi->state_table_start = tmp;
3419
3420         ret = si_read_smc_sram_dword(rdev,
3421                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3422                                      SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3423                                      &tmp, si_pi->sram_end);
3424         if (ret)
3425                 return ret;
3426
3427         si_pi->soft_regs_start = tmp;
3428
3429         ret = si_read_smc_sram_dword(rdev,
3430                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3431                                      SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3432                                      &tmp, si_pi->sram_end);
3433         if (ret)
3434                 return ret;
3435
3436         si_pi->mc_reg_table_start = tmp;
3437
3438         ret = si_read_smc_sram_dword(rdev,
3439                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3440                                      SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3441                                      &tmp, si_pi->sram_end);
3442         if (ret)
3443                 return ret;
3444
3445         si_pi->fan_table_start = tmp;
3446
3447         ret = si_read_smc_sram_dword(rdev,
3448                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3449                                      SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3450                                      &tmp, si_pi->sram_end);
3451         if (ret)
3452                 return ret;
3453
3454         si_pi->arb_table_start = tmp;
3455
3456         ret = si_read_smc_sram_dword(rdev,
3457                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3458                                      SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3459                                      &tmp, si_pi->sram_end);
3460         if (ret)
3461                 return ret;
3462
3463         si_pi->cac_table_start = tmp;
3464
3465         ret = si_read_smc_sram_dword(rdev,
3466                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3467                                      SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3468                                      &tmp, si_pi->sram_end);
3469         if (ret)
3470                 return ret;
3471
3472         si_pi->dte_table_start = tmp;
3473
3474         ret = si_read_smc_sram_dword(rdev,
3475                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3476                                      SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3477                                      &tmp, si_pi->sram_end);
3478         if (ret)
3479                 return ret;
3480
3481         si_pi->spll_table_start = tmp;
3482
3483         ret = si_read_smc_sram_dword(rdev,
3484                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3485                                      SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3486                                      &tmp, si_pi->sram_end);
3487         if (ret)
3488                 return ret;
3489
3490         si_pi->papm_cfg_table_start = tmp;
3491
3492         return ret;
3493 }
3494
3495 static void si_read_clock_registers(struct radeon_device *rdev)
3496 {
3497         struct si_power_info *si_pi = si_get_pi(rdev);
3498
3499         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3500         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3501         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3502         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3503         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3504         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3505         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3506         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3507         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3508         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3509         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3510         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3511         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3512         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3513         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3514 }
3515
3516 static void si_enable_thermal_protection(struct radeon_device *rdev,
3517                                           bool enable)
3518 {
3519         if (enable)
3520                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3521         else
3522                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3523 }
3524
3525 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3526 {
3527         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3528 }
3529
3530 #if 0
3531 static int si_enter_ulp_state(struct radeon_device *rdev)
3532 {
3533         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3534
3535         udelay(25000);
3536
3537         return 0;
3538 }
3539
3540 static int si_exit_ulp_state(struct radeon_device *rdev)
3541 {
3542         int i;
3543
3544         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3545
3546         udelay(7000);
3547
3548         for (i = 0; i < rdev->usec_timeout; i++) {
3549                 if (RREG32(SMC_RESP_0) == 1)
3550                         break;
3551                 udelay(1000);
3552         }
3553
3554         return 0;
3555 }
3556 #endif
3557
3558 static int si_notify_smc_display_change(struct radeon_device *rdev,
3559                                      bool has_display)
3560 {
3561         PPSMC_Msg msg = has_display ?
3562                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3563
3564         return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3565                 0 : -EINVAL;
3566 }
3567
3568 static void si_program_response_times(struct radeon_device *rdev)
3569 {
3570         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3571         u32 vddc_dly, acpi_dly, vbi_dly;
3572         u32 reference_clock;
3573
3574         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3575
3576         voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3577         backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3578
3579         if (voltage_response_time == 0)
3580                 voltage_response_time = 1000;
3581
3582         acpi_delay_time = 15000;
3583         vbi_time_out = 100000;
3584
3585         reference_clock = radeon_get_xclk(rdev);
3586
3587         vddc_dly = (voltage_response_time  * reference_clock) / 100;
3588         acpi_dly = (acpi_delay_time * reference_clock) / 100;
3589         vbi_dly  = (vbi_time_out * reference_clock) / 100;
3590
3591         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
3592         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
3593         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3594         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3595 }
3596
3597 static void si_program_ds_registers(struct radeon_device *rdev)
3598 {
3599         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3600         u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3601
3602         if (eg_pi->sclk_deep_sleep) {
3603                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3604                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3605                          ~AUTOSCALE_ON_SS_CLEAR);
3606         }
3607 }
3608
3609 static void si_program_display_gap(struct radeon_device *rdev)
3610 {
3611         u32 tmp, pipe;
3612         int i;
3613
3614         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3615         if (rdev->pm.dpm.new_active_crtc_count > 0)
3616                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3617         else
3618                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3619
3620         if (rdev->pm.dpm.new_active_crtc_count > 1)
3621                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3622         else
3623                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3624
3625         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3626
3627         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3628         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3629
3630         if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3631             (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3632                 /* find the first active crtc */
3633                 for (i = 0; i < rdev->num_crtc; i++) {
3634                         if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3635                                 break;
3636                 }
3637                 if (i == rdev->num_crtc)
3638                         pipe = 0;
3639                 else
3640                         pipe = i;
3641
3642                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3643                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3644                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3645         }
3646
3647         /* Setting this to false forces the performance state to low if the crtcs are disabled.
3648          * This can be a problem on PowerXpress systems or if you want to use the card
3649          * for offscreen rendering or compute if there are no crtcs enabled.
3650          */
3651         si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3652 }
3653
3654 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3655 {
3656         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3657
3658         if (enable) {
3659                 if (pi->sclk_ss)
3660                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3661         } else {
3662                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3663                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3664         }
3665 }
3666
3667 static void si_setup_bsp(struct radeon_device *rdev)
3668 {
3669         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3670         u32 xclk = radeon_get_xclk(rdev);
3671
3672         r600_calculate_u_and_p(pi->asi,
3673                                xclk,
3674                                16,
3675                                &pi->bsp,
3676                                &pi->bsu);
3677
3678         r600_calculate_u_and_p(pi->pasi,
3679                                xclk,
3680                                16,
3681                                &pi->pbsp,
3682                                &pi->pbsu);
3683
3684
3685         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3686         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3687
3688         WREG32(CG_BSP, pi->dsp);
3689 }
3690
3691 static void si_program_git(struct radeon_device *rdev)
3692 {
3693         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3694 }
3695
3696 static void si_program_tp(struct radeon_device *rdev)
3697 {
3698         int i;
3699         enum r600_td td = R600_TD_DFLT;
3700
3701         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3702                 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3703
3704         if (td == R600_TD_AUTO)
3705                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3706         else
3707                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3708
3709         if (td == R600_TD_UP)
3710                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3711
3712         if (td == R600_TD_DOWN)
3713                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3714 }
3715
3716 static void si_program_tpp(struct radeon_device *rdev)
3717 {
3718         WREG32(CG_TPC, R600_TPC_DFLT);
3719 }
3720
3721 static void si_program_sstp(struct radeon_device *rdev)
3722 {
3723         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3724 }
3725
3726 static void si_enable_display_gap(struct radeon_device *rdev)
3727 {
3728         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3729
3730         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3731         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3732                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3733
3734         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3735         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3736                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3737         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3738 }
3739
3740 static void si_program_vc(struct radeon_device *rdev)
3741 {
3742         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3743
3744         WREG32(CG_FTV, pi->vrc);
3745 }
3746
3747 static void si_clear_vc(struct radeon_device *rdev)
3748 {
3749         WREG32(CG_FTV, 0);
3750 }
3751
3752 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3753 {
3754         u8 mc_para_index;
3755
3756         if (memory_clock < 10000)
3757                 mc_para_index = 0;
3758         else if (memory_clock >= 80000)
3759                 mc_para_index = 0x0f;
3760         else
3761                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3762         return mc_para_index;
3763 }
3764
3765 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3766 {
3767         u8 mc_para_index;
3768
3769         if (strobe_mode) {
3770                 if (memory_clock < 12500)
3771                         mc_para_index = 0x00;
3772                 else if (memory_clock > 47500)
3773                         mc_para_index = 0x0f;
3774                 else
3775                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
3776         } else {
3777                 if (memory_clock < 65000)
3778                         mc_para_index = 0x00;
3779                 else if (memory_clock > 135000)
3780                         mc_para_index = 0x0f;
3781                 else
3782                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
3783         }
3784         return mc_para_index;
3785 }
3786
3787 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3788 {
3789         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3790         bool strobe_mode = false;
3791         u8 result = 0;
3792
3793         if (mclk <= pi->mclk_strobe_mode_threshold)
3794                 strobe_mode = true;
3795
3796         if (pi->mem_gddr5)
3797                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3798         else
3799                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3800
3801         if (strobe_mode)
3802                 result |= SISLANDS_SMC_STROBE_ENABLE;
3803
3804         return result;
3805 }
3806
3807 static int si_upload_firmware(struct radeon_device *rdev)
3808 {
3809         struct si_power_info *si_pi = si_get_pi(rdev);
3810         int ret;
3811
3812         si_reset_smc(rdev);
3813         si_stop_smc_clock(rdev);
3814
3815         ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3816
3817         return ret;
3818 }
3819
3820 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3821                                               const struct atom_voltage_table *table,
3822                                               const struct radeon_phase_shedding_limits_table *limits)
3823 {
3824         u32 data, num_bits, num_levels;
3825
3826         if ((table == NULL) || (limits == NULL))
3827                 return false;
3828
3829         data = table->mask_low;
3830
3831         num_bits = hweight32(data);
3832
3833         if (num_bits == 0)
3834                 return false;
3835
3836         num_levels = (1 << num_bits);
3837
3838         if (table->count != num_levels)
3839                 return false;
3840
3841         if (limits->count != (num_levels - 1))
3842                 return false;
3843
3844         return true;
3845 }
3846
3847 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3848                                               u32 max_voltage_steps,
3849                                               struct atom_voltage_table *voltage_table)
3850 {
3851         unsigned int i, diff;
3852
3853         if (voltage_table->count <= max_voltage_steps)
3854                 return;
3855
3856         diff = voltage_table->count - max_voltage_steps;
3857
3858         for (i= 0; i < max_voltage_steps; i++)
3859                 voltage_table->entries[i] = voltage_table->entries[i + diff];
3860
3861         voltage_table->count = max_voltage_steps;
3862 }
3863
3864 static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3865                                      struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3866                                      struct atom_voltage_table *voltage_table)
3867 {
3868         u32 i;
3869
3870         if (voltage_dependency_table == NULL)
3871                 return -EINVAL;
3872
3873         voltage_table->mask_low = 0;
3874         voltage_table->phase_delay = 0;
3875
3876         voltage_table->count = voltage_dependency_table->count;
3877         for (i = 0; i < voltage_table->count; i++) {
3878                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
3879                 voltage_table->entries[i].smio_low = 0;
3880         }
3881
3882         return 0;
3883 }
3884
3885 static int si_construct_voltage_tables(struct radeon_device *rdev)
3886 {
3887         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3888         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3889         struct si_power_info *si_pi = si_get_pi(rdev);
3890         int ret;
3891
3892         if (pi->voltage_control) {
3893                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3894                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3895                 if (ret)
3896                         return ret;
3897
3898                 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3899                         si_trim_voltage_table_to_fit_state_table(rdev,
3900                                                                  SISLANDS_MAX_NO_VREG_STEPS,
3901                                                                  &eg_pi->vddc_voltage_table);
3902         } else if (si_pi->voltage_control_svi2) {
3903                 ret = si_get_svi2_voltage_table(rdev,
3904                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3905                                                 &eg_pi->vddc_voltage_table);
3906                 if (ret)
3907                         return ret;
3908         } else {
3909                 return -EINVAL;
3910         }
3911
3912         if (eg_pi->vddci_control) {
3913                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3914                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3915                 if (ret)
3916                         return ret;
3917
3918                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3919                         si_trim_voltage_table_to_fit_state_table(rdev,
3920                                                                  SISLANDS_MAX_NO_VREG_STEPS,
3921                                                                  &eg_pi->vddci_voltage_table);
3922         }
3923         if (si_pi->vddci_control_svi2) {
3924                 ret = si_get_svi2_voltage_table(rdev,
3925                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3926                                                 &eg_pi->vddci_voltage_table);
3927                 if (ret)
3928                         return ret;
3929         }
3930
3931         if (pi->mvdd_control) {
3932                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3933                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
3934
3935                 if (ret) {
3936                         pi->mvdd_control = false;
3937                         return ret;
3938                 }
3939
3940                 if (si_pi->mvdd_voltage_table.count == 0) {
3941                         pi->mvdd_control = false;
3942                         return -EINVAL;
3943                 }
3944
3945                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3946                         si_trim_voltage_table_to_fit_state_table(rdev,
3947                                                                  SISLANDS_MAX_NO_VREG_STEPS,
3948                                                                  &si_pi->mvdd_voltage_table);
3949         }
3950
3951         if (si_pi->vddc_phase_shed_control) {
3952                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3953                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
3954                 if (ret)
3955                         si_pi->vddc_phase_shed_control = false;
3956
3957                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
3958                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
3959                         si_pi->vddc_phase_shed_control = false;
3960         }
3961
3962         return 0;
3963 }
3964
3965 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
3966                                           const struct atom_voltage_table *voltage_table,
3967                                           SISLANDS_SMC_STATETABLE *table)
3968 {
3969         unsigned int i;
3970
3971         for (i = 0; i < voltage_table->count; i++)
3972                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
3973 }
3974
3975 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
3976                                           SISLANDS_SMC_STATETABLE *table)
3977 {
3978         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3979         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3980         struct si_power_info *si_pi = si_get_pi(rdev);
3981         u8 i;
3982
3983         if (si_pi->voltage_control_svi2) {
3984                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
3985                         si_pi->svc_gpio_id);
3986                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
3987                         si_pi->svd_gpio_id);
3988                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
3989                                            2);
3990         } else {
3991                 if (eg_pi->vddc_voltage_table.count) {
3992                         si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
3993                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3994                                 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
3995
3996                         for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
3997                                 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
3998                                         table->maxVDDCIndexInPPTable = i;
3999                                         break;
4000                                 }
4001                         }
4002                 }
4003
4004                 if (eg_pi->vddci_voltage_table.count) {
4005                         si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4006
4007                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4008                                 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4009                 }
4010
4011
4012                 if (si_pi->mvdd_voltage_table.count) {
4013                         si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4014
4015                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4016                                 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4017                 }
4018
4019                 if (si_pi->vddc_phase_shed_control) {
4020                         if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4021                                                               &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4022                                 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4023
4024                                 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4025                                         cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4026
4027                                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4028                                                            (u32)si_pi->vddc_phase_shed_table.phase_delay);
4029                         } else {
4030                                 si_pi->vddc_phase_shed_control = false;
4031                         }
4032                 }
4033         }
4034
4035         return 0;
4036 }
4037
4038 static int si_populate_voltage_value(struct radeon_device *rdev,
4039                                      const struct atom_voltage_table *table,
4040                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4041 {
4042         unsigned int i;
4043
4044         for (i = 0; i < table->count; i++) {
4045                 if (value <= table->entries[i].value) {
4046                         voltage->index = (u8)i;
4047                         voltage->value = cpu_to_be16(table->entries[i].value);
4048                         break;
4049                 }
4050         }
4051
4052         if (i >= table->count)
4053                 return -EINVAL;
4054
4055         return 0;
4056 }
4057
4058 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4059                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4060 {
4061         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4062         struct si_power_info *si_pi = si_get_pi(rdev);
4063
4064         if (pi->mvdd_control) {
4065                 if (mclk <= pi->mvdd_split_frequency)
4066                         voltage->index = 0;
4067                 else
4068                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4069
4070                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4071         }
4072         return 0;
4073 }
4074
4075 static int si_get_std_voltage_value(struct radeon_device *rdev,
4076                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4077                                     u16 *std_voltage)
4078 {
4079         u16 v_index;
4080         bool voltage_found = false;
4081         *std_voltage = be16_to_cpu(voltage->value);
4082
4083         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4084                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4085                         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4086                                 return -EINVAL;
4087
4088                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4089                                 if (be16_to_cpu(voltage->value) ==
4090                                     (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4091                                         voltage_found = true;
4092                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4093                                                 *std_voltage =
4094                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4095                                         else
4096                                                 *std_voltage =
4097                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4098                                         break;
4099                                 }
4100                         }
4101
4102                         if (!voltage_found) {
4103                                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4104                                         if (be16_to_cpu(voltage->value) <=
4105                                             (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4106                                                 voltage_found = true;
4107                                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4108                                                         *std_voltage =
4109                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4110                                                 else
4111                                                         *std_voltage =
4112                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4113                                                 break;
4114                                         }
4115                                 }
4116                         }
4117                 } else {
4118                         if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4119                                 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4120                 }
4121         }
4122
4123         return 0;
4124 }
4125
4126 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4127                                          u16 value, u8 index,
4128                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4129 {
4130         voltage->index = index;
4131         voltage->value = cpu_to_be16(value);
4132
4133         return 0;
4134 }
4135
4136 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4137                                             const struct radeon_phase_shedding_limits_table *limits,
4138                                             u16 voltage, u32 sclk, u32 mclk,
4139                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4140 {
4141         unsigned int i;
4142
4143         for (i = 0; i < limits->count; i++) {
4144                 if ((voltage <= limits->entries[i].voltage) &&
4145                     (sclk <= limits->entries[i].sclk) &&
4146                     (mclk <= limits->entries[i].mclk))
4147                         break;
4148         }
4149
4150         smc_voltage->phase_settings = (u8)i;
4151
4152         return 0;
4153 }
4154
4155 static int si_init_arb_table_index(struct radeon_device *rdev)
4156 {
4157         struct si_power_info *si_pi = si_get_pi(rdev);
4158         u32 tmp;
4159         int ret;
4160
4161         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4162         if (ret)
4163                 return ret;
4164
4165         tmp &= 0x00FFFFFF;
4166         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4167
4168         return si_write_smc_sram_dword(rdev, si_pi->arb_table_start,  tmp, si_pi->sram_end);
4169 }
4170
4171 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4172 {
4173         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4174 }
4175
4176 static int si_reset_to_default(struct radeon_device *rdev)
4177 {
4178         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4179                 0 : -EINVAL;
4180 }
4181
4182 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4183 {
4184         struct si_power_info *si_pi = si_get_pi(rdev);
4185         u32 tmp;
4186         int ret;
4187
4188         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4189                                      &tmp, si_pi->sram_end);
4190         if (ret)
4191                 return ret;
4192
4193         tmp = (tmp >> 24) & 0xff;
4194
4195         if (tmp == MC_CG_ARB_FREQ_F0)
4196                 return 0;
4197
4198         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4199 }
4200
4201 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4202                                             u32 engine_clock)
4203 {
4204         u32 dram_rows;
4205         u32 dram_refresh_rate;
4206         u32 mc_arb_rfsh_rate;
4207         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4208
4209         if (tmp >= 4)
4210                 dram_rows = 16384;
4211         else
4212                 dram_rows = 1 << (tmp + 10);
4213
4214         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4215         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4216
4217         return mc_arb_rfsh_rate;
4218 }
4219
4220 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4221                                                 struct rv7xx_pl *pl,
4222                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4223 {
4224         u32 dram_timing;
4225         u32 dram_timing2;
4226         u32 burst_time;
4227
4228         arb_regs->mc_arb_rfsh_rate =
4229                 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4230
4231         radeon_atom_set_engine_dram_timings(rdev,
4232                                             pl->sclk,
4233                                             pl->mclk);
4234
4235         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4236         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4237         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4238
4239         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4240         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4241         arb_regs->mc_arb_burst_time = (u8)burst_time;
4242
4243         return 0;
4244 }
4245
4246 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4247                                                   struct radeon_ps *radeon_state,
4248                                                   unsigned int first_arb_set)
4249 {
4250         struct si_power_info *si_pi = si_get_pi(rdev);
4251         struct ni_ps *state = ni_get_ps(radeon_state);
4252         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4253         int i, ret = 0;
4254
4255         for (i = 0; i < state->performance_level_count; i++) {
4256                 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4257                 if (ret)
4258                         break;
4259                 ret = si_copy_bytes_to_smc(rdev,
4260                                            si_pi->arb_table_start +
4261                                            offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4262                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4263                                            (u8 *)&arb_regs,
4264                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4265                                            si_pi->sram_end);
4266                 if (ret)
4267                         break;
4268         }
4269
4270         return ret;
4271 }
4272
4273 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4274                                                struct radeon_ps *radeon_new_state)
4275 {
4276         return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4277                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4278 }
4279
4280 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4281                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4282 {
4283         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4284         struct si_power_info *si_pi = si_get_pi(rdev);
4285
4286         if (pi->mvdd_control)
4287                 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4288                                                  si_pi->mvdd_bootup_value, voltage);
4289
4290         return 0;
4291 }
4292
4293 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4294                                          struct radeon_ps *radeon_initial_state,
4295                                          SISLANDS_SMC_STATETABLE *table)
4296 {
4297         struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4298         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4299         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4300         struct si_power_info *si_pi = si_get_pi(rdev);
4301         u32 reg;
4302         int ret;
4303
4304         table->initialState.levels[0].mclk.vDLL_CNTL =
4305                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4306         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4307                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4308         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4309                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4310         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4311                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4312         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4313                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4314         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4315                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4316         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4317                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4318         table->initialState.levels[0].mclk.vMPLL_SS =
4319                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4320         table->initialState.levels[0].mclk.vMPLL_SS2 =
4321                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4322
4323         table->initialState.levels[0].mclk.mclk_value =
4324                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4325
4326         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4327                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4328         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4329                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4330         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4331                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4332         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4333                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4334         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4335                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4336         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4337                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4338
4339         table->initialState.levels[0].sclk.sclk_value =
4340                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4341
4342         table->initialState.levels[0].arbRefreshState =
4343                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4344
4345         table->initialState.levels[0].ACIndex = 0;
4346
4347         ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4348                                         initial_state->performance_levels[0].vddc,
4349                                         &table->initialState.levels[0].vddc);
4350
4351         if (!ret) {
4352                 u16 std_vddc;
4353
4354                 ret = si_get_std_voltage_value(rdev,
4355                                                &table->initialState.levels[0].vddc,
4356                                                &std_vddc);
4357                 if (!ret)
4358                         si_populate_std_voltage_value(rdev, std_vddc,
4359                                                       table->initialState.levels[0].vddc.index,
4360                                                       &table->initialState.levels[0].std_vddc);
4361         }
4362
4363         if (eg_pi->vddci_control)
4364                 si_populate_voltage_value(rdev,
4365                                           &eg_pi->vddci_voltage_table,
4366                                           initial_state->performance_levels[0].vddci,
4367                                           &table->initialState.levels[0].vddci);
4368
4369         if (si_pi->vddc_phase_shed_control)
4370                 si_populate_phase_shedding_value(rdev,
4371                                                  &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4372                                                  initial_state->performance_levels[0].vddc,
4373                                                  initial_state->performance_levels[0].sclk,
4374                                                  initial_state->performance_levels[0].mclk,
4375                                                  &table->initialState.levels[0].vddc);
4376
4377         si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4378
4379         reg = CG_R(0xffff) | CG_L(0);
4380         table->initialState.levels[0].aT = cpu_to_be32(reg);
4381
4382         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4383
4384         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4385
4386         if (pi->mem_gddr5) {
4387                 table->initialState.levels[0].strobeMode =
4388                         si_get_strobe_mode_settings(rdev,
4389                                                     initial_state->performance_levels[0].mclk);
4390
4391                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4392                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4393                 else
4394                         table->initialState.levels[0].mcFlags =  0;
4395         }
4396
4397         table->initialState.levelCount = 1;
4398
4399         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4400
4401         table->initialState.levels[0].dpm2.MaxPS = 0;
4402         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4403         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4404         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4405         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4406
4407         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4408         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4409
4410         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4411         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4412
4413         return 0;
4414 }
4415
4416 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4417                                       SISLANDS_SMC_STATETABLE *table)
4418 {
4419         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4420         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4421         struct si_power_info *si_pi = si_get_pi(rdev);
4422         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4423         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4424         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4425         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4426         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4427         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4428         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4429         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4430         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4431         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4432         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4433         u32 reg;
4434         int ret;
4435
4436         table->ACPIState = table->initialState;
4437
4438         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4439
4440         if (pi->acpi_vddc) {
4441                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4442                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4443                 if (!ret) {
4444                         u16 std_vddc;
4445
4446                         ret = si_get_std_voltage_value(rdev,
4447                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4448                         if (!ret)
4449                                 si_populate_std_voltage_value(rdev, std_vddc,
4450                                                               table->ACPIState.levels[0].vddc.index,
4451                                                               &table->ACPIState.levels[0].std_vddc);
4452                 }
4453                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4454
4455                 if (si_pi->vddc_phase_shed_control) {
4456                         si_populate_phase_shedding_value(rdev,
4457                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4458                                                          pi->acpi_vddc,
4459                                                          0,
4460                                                          0,
4461                                                          &table->ACPIState.levels[0].vddc);
4462                 }
4463         } else {
4464                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4465                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4466                 if (!ret) {
4467                         u16 std_vddc;
4468
4469                         ret = si_get_std_voltage_value(rdev,
4470                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4471
4472                         if (!ret)
4473                                 si_populate_std_voltage_value(rdev, std_vddc,
4474                                                               table->ACPIState.levels[0].vddc.index,
4475                                                               &table->ACPIState.levels[0].std_vddc);
4476                 }
4477                 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4478                                                                                     si_pi->sys_pcie_mask,
4479                                                                                     si_pi->boot_pcie_gen,
4480                                                                                     RADEON_PCIE_GEN1);
4481
4482                 if (si_pi->vddc_phase_shed_control)
4483                         si_populate_phase_shedding_value(rdev,
4484                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4485                                                          pi->min_vddc_in_table,
4486                                                          0,
4487                                                          0,
4488                                                          &table->ACPIState.levels[0].vddc);
4489         }
4490
4491         if (pi->acpi_vddc) {
4492                 if (eg_pi->acpi_vddci)
4493                         si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4494                                                   eg_pi->acpi_vddci,
4495                                                   &table->ACPIState.levels[0].vddci);
4496         }
4497
4498         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4499         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4500
4501         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4502
4503         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4504         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4505
4506         table->ACPIState.levels[0].mclk.vDLL_CNTL =
4507                 cpu_to_be32(dll_cntl);
4508         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4509                 cpu_to_be32(mclk_pwrmgt_cntl);
4510         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4511                 cpu_to_be32(mpll_ad_func_cntl);
4512         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4513                 cpu_to_be32(mpll_dq_func_cntl);
4514         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4515                 cpu_to_be32(mpll_func_cntl);
4516         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4517                 cpu_to_be32(mpll_func_cntl_1);
4518         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4519                 cpu_to_be32(mpll_func_cntl_2);
4520         table->ACPIState.levels[0].mclk.vMPLL_SS =
4521                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4522         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4523                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4524
4525         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4526                 cpu_to_be32(spll_func_cntl);
4527         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4528                 cpu_to_be32(spll_func_cntl_2);
4529         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4530                 cpu_to_be32(spll_func_cntl_3);
4531         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4532                 cpu_to_be32(spll_func_cntl_4);
4533
4534         table->ACPIState.levels[0].mclk.mclk_value = 0;
4535         table->ACPIState.levels[0].sclk.sclk_value = 0;
4536
4537         si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4538
4539         if (eg_pi->dynamic_ac_timing)
4540                 table->ACPIState.levels[0].ACIndex = 0;
4541
4542         table->ACPIState.levels[0].dpm2.MaxPS = 0;
4543         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4544         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4545         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4546         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4547
4548         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4549         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4550
4551         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4552         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4553
4554         return 0;
4555 }
4556
4557 static int si_populate_ulv_state(struct radeon_device *rdev,
4558                                  SISLANDS_SMC_SWSTATE *state)
4559 {
4560         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4561         struct si_power_info *si_pi = si_get_pi(rdev);
4562         struct si_ulv_param *ulv = &si_pi->ulv;
4563         u32 sclk_in_sr = 1350; /* ??? */
4564         int ret;
4565
4566         ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4567                                             &state->levels[0]);
4568         if (!ret) {
4569                 if (eg_pi->sclk_deep_sleep) {
4570                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4571                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4572                         else
4573                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4574                 }
4575                 if (ulv->one_pcie_lane_in_ulv)
4576                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4577                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4578                 state->levels[0].ACIndex = 1;
4579                 state->levels[0].std_vddc = state->levels[0].vddc;
4580                 state->levelCount = 1;
4581
4582                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4583         }
4584
4585         return ret;
4586 }
4587
4588 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4589 {
4590         struct si_power_info *si_pi = si_get_pi(rdev);
4591         struct si_ulv_param *ulv = &si_pi->ulv;
4592         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4593         int ret;
4594
4595         ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4596                                                    &arb_regs);
4597         if (ret)
4598                 return ret;
4599
4600         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4601                                    ulv->volt_change_delay);
4602
4603         ret = si_copy_bytes_to_smc(rdev,
4604                                    si_pi->arb_table_start +
4605                                    offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4606                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4607                                    (u8 *)&arb_regs,
4608                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4609                                    si_pi->sram_end);
4610
4611         return ret;
4612 }
4613
4614 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4615 {
4616         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4617
4618         pi->mvdd_split_frequency = 30000;
4619 }
4620
4621 static int si_init_smc_table(struct radeon_device *rdev)
4622 {
4623         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4624         struct si_power_info *si_pi = si_get_pi(rdev);
4625         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4626         const struct si_ulv_param *ulv = &si_pi->ulv;
4627         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
4628         int ret;
4629         u32 lane_width;
4630         u32 vr_hot_gpio;
4631
4632         si_populate_smc_voltage_tables(rdev, table);
4633
4634         switch (rdev->pm.int_thermal_type) {
4635         case THERMAL_TYPE_SI:
4636         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4637                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4638                 break;
4639         case THERMAL_TYPE_NONE:
4640                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4641                 break;
4642         default:
4643                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4644                 break;
4645         }
4646
4647         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4648                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4649
4650         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4651                 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4652                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4653         }
4654
4655         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4656                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4657
4658         if (pi->mem_gddr5)
4659                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4660
4661         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4662                 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4663
4664         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4665                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4666                 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4667                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4668                                            vr_hot_gpio);
4669         }
4670
4671         ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4672         if (ret)
4673                 return ret;
4674
4675         ret = si_populate_smc_acpi_state(rdev, table);
4676         if (ret)
4677                 return ret;
4678
4679         table->driverState = table->initialState;
4680
4681         ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4682                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
4683         if (ret)
4684                 return ret;
4685
4686         if (ulv->supported && ulv->pl.vddc) {
4687                 ret = si_populate_ulv_state(rdev, &table->ULVState);
4688                 if (ret)
4689                         return ret;
4690
4691                 ret = si_program_ulv_memory_timing_parameters(rdev);
4692                 if (ret)
4693                         return ret;
4694
4695                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4696                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4697
4698                 lane_width = radeon_get_pcie_lanes(rdev);
4699                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4700         } else {
4701                 table->ULVState = table->initialState;
4702         }
4703
4704         return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4705                                     (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4706                                     si_pi->sram_end);
4707 }
4708
4709 static int si_calculate_sclk_params(struct radeon_device *rdev,
4710                                     u32 engine_clock,
4711                                     SISLANDS_SMC_SCLK_VALUE *sclk)
4712 {
4713         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4714         struct si_power_info *si_pi = si_get_pi(rdev);
4715         struct atom_clock_dividers dividers;
4716         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4717         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4718         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4719         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4720         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4721         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4722         u64 tmp;
4723         u32 reference_clock = rdev->clock.spll.reference_freq;
4724         u32 reference_divider;
4725         u32 fbdiv;
4726         int ret;
4727
4728         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4729                                              engine_clock, false, &dividers);
4730         if (ret)
4731                 return ret;
4732
4733         reference_divider = 1 + dividers.ref_div;
4734
4735         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4736         do_div(tmp, reference_clock);
4737         fbdiv = (u32) tmp;
4738
4739         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4740         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4741         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4742
4743         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4744         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4745
4746         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4747         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4748         spll_func_cntl_3 |= SPLL_DITHEN;
4749
4750         if (pi->sclk_ss) {
4751                 struct radeon_atom_ss ss;
4752                 u32 vco_freq = engine_clock * dividers.post_div;
4753
4754                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4755                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4756                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4757                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4758
4759                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
4760                         cg_spll_spread_spectrum |= CLK_S(clk_s);
4761                         cg_spll_spread_spectrum |= SSEN;
4762
4763                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4764                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4765                 }
4766         }
4767
4768         sclk->sclk_value = engine_clock;
4769         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4770         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4771         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4772         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4773         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4774         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4775
4776         return 0;
4777 }
4778
4779 static int si_populate_sclk_value(struct radeon_device *rdev,
4780                                   u32 engine_clock,
4781                                   SISLANDS_SMC_SCLK_VALUE *sclk)
4782 {
4783         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4784         int ret;
4785
4786         ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4787         if (!ret) {
4788                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4789                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4790                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4791                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4792                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4793                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4794                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4795         }
4796
4797         return ret;
4798 }
4799
4800 static int si_populate_mclk_value(struct radeon_device *rdev,
4801                                   u32 engine_clock,
4802                                   u32 memory_clock,
4803                                   SISLANDS_SMC_MCLK_VALUE *mclk,
4804                                   bool strobe_mode,
4805                                   bool dll_state_on)
4806 {
4807         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4808         struct si_power_info *si_pi = si_get_pi(rdev);
4809         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
4810         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4811         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4812         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4813         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4814         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4815         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4816         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4817         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4818         struct atom_mpll_param mpll_param;
4819         int ret;
4820
4821         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4822         if (ret)
4823                 return ret;
4824
4825         mpll_func_cntl &= ~BWCTRL_MASK;
4826         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4827
4828         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4829         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4830                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4831
4832         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4833         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4834
4835         if (pi->mem_gddr5) {
4836                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4837                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4838                         YCLK_POST_DIV(mpll_param.post_div);
4839         }
4840
4841         if (pi->mclk_ss) {
4842                 struct radeon_atom_ss ss;
4843                 u32 freq_nom;
4844                 u32 tmp;
4845                 u32 reference_clock = rdev->clock.mpll.reference_freq;
4846
4847                 if (pi->mem_gddr5)
4848                         freq_nom = memory_clock * 4;
4849                 else
4850                         freq_nom = memory_clock * 2;
4851
4852                 tmp = freq_nom / reference_clock;
4853                 tmp = tmp * tmp;
4854                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4855                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4856                         u32 clks = reference_clock * 5 / ss.rate;
4857                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4858
4859                         mpll_ss1 &= ~CLKV_MASK;
4860                         mpll_ss1 |= CLKV(clkv);
4861
4862                         mpll_ss2 &= ~CLKS_MASK;
4863                         mpll_ss2 |= CLKS(clks);
4864                 }
4865         }
4866
4867         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4868         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4869
4870         if (dll_state_on)
4871                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4872         else
4873                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4874
4875         mclk->mclk_value = cpu_to_be32(memory_clock);
4876         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4877         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4878         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4879         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4880         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4881         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4882         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4883         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4884         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4885
4886         return 0;
4887 }
4888
4889 static void si_populate_smc_sp(struct radeon_device *rdev,
4890                                struct radeon_ps *radeon_state,
4891                                SISLANDS_SMC_SWSTATE *smc_state)
4892 {
4893         struct ni_ps *ps = ni_get_ps(radeon_state);
4894         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4895         int i;
4896
4897         for (i = 0; i < ps->performance_level_count - 1; i++)
4898                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4899
4900         smc_state->levels[ps->performance_level_count - 1].bSP =
4901                 cpu_to_be32(pi->psp);
4902 }
4903
4904 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4905                                          struct rv7xx_pl *pl,
4906                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4907 {
4908         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4909         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4910         struct si_power_info *si_pi = si_get_pi(rdev);
4911         int ret;
4912         bool dll_state_on;
4913         u16 std_vddc;
4914         bool gmc_pg = false;
4915
4916         if (eg_pi->pcie_performance_request &&
4917             (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4918                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4919         else
4920                 level->gen2PCIE = (u8)pl->pcie_gen;
4921
4922         ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4923         if (ret)
4924                 return ret;
4925
4926         level->mcFlags =  0;
4927
4928         if (pi->mclk_stutter_mode_threshold &&
4929             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4930             !eg_pi->uvd_enabled &&
4931             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
4932             (rdev->pm.dpm.new_active_crtc_count <= 2)) {
4933                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
4934
4935                 if (gmc_pg)
4936                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
4937         }
4938
4939         if (pi->mem_gddr5) {
4940                 if (pl->mclk > pi->mclk_edc_enable_threshold)
4941                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
4942
4943                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
4944                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
4945
4946                 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
4947
4948                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
4949                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
4950                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
4951                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4952                         else
4953                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
4954                 } else {
4955                         dll_state_on = false;
4956                 }
4957         } else {
4958                 level->strobeMode = si_get_strobe_mode_settings(rdev,
4959                                                                 pl->mclk);
4960
4961                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4962         }
4963
4964         ret = si_populate_mclk_value(rdev,
4965                                      pl->sclk,
4966                                      pl->mclk,
4967                                      &level->mclk,
4968                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
4969         if (ret)
4970                 return ret;
4971
4972         ret = si_populate_voltage_value(rdev,
4973                                         &eg_pi->vddc_voltage_table,
4974                                         pl->vddc, &level->vddc);
4975         if (ret)
4976                 return ret;
4977
4978
4979         ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
4980         if (ret)
4981                 return ret;
4982
4983         ret = si_populate_std_voltage_value(rdev, std_vddc,
4984                                             level->vddc.index, &level->std_vddc);
4985         if (ret)
4986                 return ret;
4987
4988         if (eg_pi->vddci_control) {
4989                 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4990                                                 pl->vddci, &level->vddci);
4991                 if (ret)
4992                         return ret;
4993         }
4994
4995         if (si_pi->vddc_phase_shed_control) {
4996                 ret = si_populate_phase_shedding_value(rdev,
4997                                                        &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4998                                                        pl->vddc,
4999                                                        pl->sclk,
5000                                                        pl->mclk,
5001                                                        &level->vddc);
5002                 if (ret)
5003                         return ret;
5004         }
5005
5006         level->MaxPoweredUpCU = si_pi->max_cu;
5007
5008         ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5009
5010         return ret;
5011 }
5012
5013 static int si_populate_smc_t(struct radeon_device *rdev,
5014                              struct radeon_ps *radeon_state,
5015                              SISLANDS_SMC_SWSTATE *smc_state)
5016 {
5017         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5018         struct ni_ps *state = ni_get_ps(radeon_state);
5019         u32 a_t;
5020         u32 t_l, t_h;
5021         u32 high_bsp;
5022         int i, ret;
5023
5024         if (state->performance_level_count >= 9)
5025                 return -EINVAL;
5026
5027         if (state->performance_level_count < 2) {
5028                 a_t = CG_R(0xffff) | CG_L(0);
5029                 smc_state->levels[0].aT = cpu_to_be32(a_t);
5030                 return 0;
5031         }
5032
5033         smc_state->levels[0].aT = cpu_to_be32(0);
5034
5035         for (i = 0; i <= state->performance_level_count - 2; i++) {
5036                 ret = r600_calculate_at(
5037                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5038                         100 * R600_AH_DFLT,
5039                         state->performance_levels[i + 1].sclk,
5040                         state->performance_levels[i].sclk,
5041                         &t_l,
5042                         &t_h);
5043
5044                 if (ret) {
5045                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5046                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5047                 }
5048
5049                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5050                 a_t |= CG_R(t_l * pi->bsp / 20000);
5051                 smc_state->levels[i].aT = cpu_to_be32(a_t);
5052
5053                 high_bsp = (i == state->performance_level_count - 2) ?
5054                         pi->pbsp : pi->bsp;
5055                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5056                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5057         }
5058
5059         return 0;
5060 }
5061
5062 static int si_disable_ulv(struct radeon_device *rdev)
5063 {
5064         struct si_power_info *si_pi = si_get_pi(rdev);
5065         struct si_ulv_param *ulv = &si_pi->ulv;
5066
5067         if (ulv->supported)
5068                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5069                         0 : -EINVAL;
5070
5071         return 0;
5072 }
5073
5074 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5075                                        struct radeon_ps *radeon_state)
5076 {
5077         const struct si_power_info *si_pi = si_get_pi(rdev);
5078         const struct si_ulv_param *ulv = &si_pi->ulv;
5079         const struct ni_ps *state = ni_get_ps(radeon_state);
5080         int i;
5081
5082         if (state->performance_levels[0].mclk != ulv->pl.mclk)
5083                 return false;
5084
5085         /* XXX validate against display requirements! */
5086
5087         for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5088                 if (rdev->clock.current_dispclk <=
5089                     rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5090                         if (ulv->pl.vddc <
5091                             rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5092                                 return false;
5093                 }
5094         }
5095
5096         if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5097                 return false;
5098
5099         return true;
5100 }
5101
5102 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5103                                                        struct radeon_ps *radeon_new_state)
5104 {
5105         const struct si_power_info *si_pi = si_get_pi(rdev);
5106         const struct si_ulv_param *ulv = &si_pi->ulv;
5107
5108         if (ulv->supported) {
5109                 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5110                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5111                                 0 : -EINVAL;
5112         }
5113         return 0;
5114 }
5115
5116 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5117                                          struct radeon_ps *radeon_state,
5118                                          SISLANDS_SMC_SWSTATE *smc_state)
5119 {
5120         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5121         struct ni_power_info *ni_pi = ni_get_pi(rdev);
5122         struct si_power_info *si_pi = si_get_pi(rdev);
5123         struct ni_ps *state = ni_get_ps(radeon_state);
5124         int i, ret;
5125         u32 threshold;
5126         u32 sclk_in_sr = 1350; /* ??? */
5127
5128         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5129                 return -EINVAL;
5130
5131         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5132
5133         if (radeon_state->vclk && radeon_state->dclk) {
5134                 eg_pi->uvd_enabled = true;
5135                 if (eg_pi->smu_uvd_hs)
5136                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5137         } else {
5138                 eg_pi->uvd_enabled = false;
5139         }
5140
5141         if (state->dc_compatible)
5142                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5143
5144         smc_state->levelCount = 0;
5145         for (i = 0; i < state->performance_level_count; i++) {
5146                 if (eg_pi->sclk_deep_sleep) {
5147                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5148                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5149                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5150                                 else
5151                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5152                         }
5153                 }
5154
5155                 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5156                                                     &smc_state->levels[i]);
5157                 smc_state->levels[i].arbRefreshState =
5158                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5159
5160                 if (ret)
5161                         return ret;
5162
5163                 if (ni_pi->enable_power_containment)
5164                         smc_state->levels[i].displayWatermark =
5165                                 (state->performance_levels[i].sclk < threshold) ?
5166                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5167                 else
5168                         smc_state->levels[i].displayWatermark = (i < 2) ?
5169                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5170
5171                 if (eg_pi->dynamic_ac_timing)
5172                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5173                 else
5174                         smc_state->levels[i].ACIndex = 0;
5175
5176                 smc_state->levelCount++;
5177         }
5178
5179         si_write_smc_soft_register(rdev,
5180                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5181                                    threshold / 512);
5182
5183         si_populate_smc_sp(rdev, radeon_state, smc_state);
5184
5185         ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5186         if (ret)
5187                 ni_pi->enable_power_containment = false;
5188
5189         ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5190         if (ret)
5191                 ni_pi->enable_sq_ramping = false;
5192
5193         return si_populate_smc_t(rdev, radeon_state, smc_state);
5194 }
5195
5196 static int si_upload_sw_state(struct radeon_device *rdev,
5197                               struct radeon_ps *radeon_new_state)
5198 {
5199         struct si_power_info *si_pi = si_get_pi(rdev);
5200         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5201         int ret;
5202         u32 address = si_pi->state_table_start +
5203                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5204         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5205                 ((new_state->performance_level_count - 1) *
5206                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5207         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5208
5209         memset(smc_state, 0, state_size);
5210
5211         ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5212         if (ret)
5213                 return ret;
5214
5215         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5216                                    state_size, si_pi->sram_end);
5217
5218         return ret;
5219 }
5220
5221 static int si_upload_ulv_state(struct radeon_device *rdev)
5222 {
5223         struct si_power_info *si_pi = si_get_pi(rdev);
5224         struct si_ulv_param *ulv = &si_pi->ulv;
5225         int ret = 0;
5226
5227         if (ulv->supported && ulv->pl.vddc) {
5228                 u32 address = si_pi->state_table_start +
5229                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5230                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5231                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5232
5233                 memset(smc_state, 0, state_size);
5234
5235                 ret = si_populate_ulv_state(rdev, smc_state);
5236                 if (!ret)
5237                         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5238                                                    state_size, si_pi->sram_end);
5239         }
5240
5241         return ret;
5242 }
5243
5244 static int si_upload_smc_data(struct radeon_device *rdev)
5245 {
5246         struct radeon_crtc *radeon_crtc = NULL;
5247         int i;
5248
5249         if (rdev->pm.dpm.new_active_crtc_count == 0)
5250                 return 0;
5251
5252         for (i = 0; i < rdev->num_crtc; i++) {
5253                 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5254                         radeon_crtc = rdev->mode_info.crtcs[i];
5255                         break;
5256                 }
5257         }
5258
5259         if (radeon_crtc == NULL)
5260                 return 0;
5261
5262         if (radeon_crtc->line_time <= 0)
5263                 return 0;
5264
5265         if (si_write_smc_soft_register(rdev,
5266                                        SI_SMC_SOFT_REGISTER_crtc_index,
5267                                        radeon_crtc->crtc_id) != PPSMC_Result_OK)
5268                 return 0;
5269
5270         if (si_write_smc_soft_register(rdev,
5271                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5272                                        radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5273                 return 0;
5274
5275         if (si_write_smc_soft_register(rdev,
5276                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5277                                        radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5278                 return 0;
5279
5280         return 0;
5281 }
5282
5283 static int si_set_mc_special_registers(struct radeon_device *rdev,
5284                                        struct si_mc_reg_table *table)
5285 {
5286         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5287         u8 i, j, k;
5288         u32 temp_reg;
5289
5290         for (i = 0, j = table->last; i < table->last; i++) {
5291                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5292                         return -EINVAL;
5293                 switch (table->mc_reg_address[i].s1 << 2) {
5294                 case MC_SEQ_MISC1:
5295                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5296                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5297                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5298                         for (k = 0; k < table->num_entries; k++)
5299                                 table->mc_reg_table_entry[k].mc_data[j] =
5300                                         ((temp_reg & 0xffff0000)) |
5301                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5302                         j++;
5303                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5304                                 return -EINVAL;
5305
5306                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5307                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5308                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5309                         for (k = 0; k < table->num_entries; k++) {
5310                                 table->mc_reg_table_entry[k].mc_data[j] =
5311                                         (temp_reg & 0xffff0000) |
5312                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5313                                 if (!pi->mem_gddr5)
5314                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5315                         }
5316                         j++;
5317                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5318                                 return -EINVAL;
5319
5320                         if (!pi->mem_gddr5) {
5321                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5322                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5323                                 for (k = 0; k < table->num_entries; k++)
5324                                         table->mc_reg_table_entry[k].mc_data[j] =
5325                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5326                                 j++;
5327                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5328                                         return -EINVAL;
5329                         }
5330                         break;
5331                 case MC_SEQ_RESERVE_M:
5332                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5333                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5334                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5335                         for(k = 0; k < table->num_entries; k++)
5336                                 table->mc_reg_table_entry[k].mc_data[j] =
5337                                         (temp_reg & 0xffff0000) |
5338                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5339                         j++;
5340                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5341                                 return -EINVAL;
5342                         break;
5343                 default:
5344                         break;
5345                 }
5346         }
5347
5348         table->last = j;
5349
5350         return 0;
5351 }
5352
5353 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5354 {
5355         bool result = true;
5356
5357         switch (in_reg) {
5358         case  MC_SEQ_RAS_TIMING >> 2:
5359                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5360                 break;
5361         case MC_SEQ_CAS_TIMING >> 2:
5362                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5363                 break;
5364         case MC_SEQ_MISC_TIMING >> 2:
5365                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5366                 break;
5367         case MC_SEQ_MISC_TIMING2 >> 2:
5368                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5369                 break;
5370         case MC_SEQ_RD_CTL_D0 >> 2:
5371                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5372                 break;
5373         case MC_SEQ_RD_CTL_D1 >> 2:
5374                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5375                 break;
5376         case MC_SEQ_WR_CTL_D0 >> 2:
5377                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5378                 break;
5379         case MC_SEQ_WR_CTL_D1 >> 2:
5380                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5381                 break;
5382         case MC_PMG_CMD_EMRS >> 2:
5383                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5384                 break;
5385         case MC_PMG_CMD_MRS >> 2:
5386                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5387                 break;
5388         case MC_PMG_CMD_MRS1 >> 2:
5389                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5390                 break;
5391         case MC_SEQ_PMG_TIMING >> 2:
5392                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5393                 break;
5394         case MC_PMG_CMD_MRS2 >> 2:
5395                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5396                 break;
5397         case MC_SEQ_WR_CTL_2 >> 2:
5398                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5399                 break;
5400         default:
5401                 result = false;
5402                 break;
5403         }
5404
5405         return result;
5406 }
5407
5408 static void si_set_valid_flag(struct si_mc_reg_table *table)
5409 {
5410         u8 i, j;
5411
5412         for (i = 0; i < table->last; i++) {
5413                 for (j = 1; j < table->num_entries; j++) {
5414                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5415                                 table->valid_flag |= 1 << i;
5416                                 break;
5417                         }
5418                 }
5419         }
5420 }
5421
5422 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5423 {
5424         u32 i;
5425         u16 address;
5426
5427         for (i = 0; i < table->last; i++)
5428                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5429                         address : table->mc_reg_address[i].s1;
5430
5431 }
5432
5433 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5434                                       struct si_mc_reg_table *si_table)
5435 {
5436         u8 i, j;
5437
5438         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5439                 return -EINVAL;
5440         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5441                 return -EINVAL;
5442
5443         for (i = 0; i < table->last; i++)
5444                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5445         si_table->last = table->last;
5446
5447         for (i = 0; i < table->num_entries; i++) {
5448                 si_table->mc_reg_table_entry[i].mclk_max =
5449                         table->mc_reg_table_entry[i].mclk_max;
5450                 for (j = 0; j < table->last; j++) {
5451                         si_table->mc_reg_table_entry[i].mc_data[j] =
5452                                 table->mc_reg_table_entry[i].mc_data[j];
5453                 }
5454         }
5455         si_table->num_entries = table->num_entries;
5456
5457         return 0;
5458 }
5459
5460 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5461 {
5462         struct si_power_info *si_pi = si_get_pi(rdev);
5463         struct atom_mc_reg_table *table;
5464         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5465         u8 module_index = rv770_get_memory_module_index(rdev);
5466         int ret;
5467
5468         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5469         if (!table)
5470                 return -ENOMEM;
5471
5472         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5473         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5474         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5475         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5476         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5477         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5478         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5479         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5480         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5481         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5482         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5483         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5484         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5485         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5486
5487         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5488         if (ret)
5489                 goto init_mc_done;
5490
5491         ret = si_copy_vbios_mc_reg_table(table, si_table);
5492         if (ret)
5493                 goto init_mc_done;
5494
5495         si_set_s0_mc_reg_index(si_table);
5496
5497         ret = si_set_mc_special_registers(rdev, si_table);
5498         if (ret)
5499                 goto init_mc_done;
5500
5501         si_set_valid_flag(si_table);
5502
5503 init_mc_done:
5504         kfree(table);
5505
5506         return ret;
5507
5508 }
5509
5510 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5511                                          SMC_SIslands_MCRegisters *mc_reg_table)
5512 {
5513         struct si_power_info *si_pi = si_get_pi(rdev);
5514         u32 i, j;
5515
5516         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5517                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5518                         if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5519                                 break;
5520                         mc_reg_table->address[i].s0 =
5521                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5522                         mc_reg_table->address[i].s1 =
5523                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5524                         i++;
5525                 }
5526         }
5527         mc_reg_table->last = (u8)i;
5528 }
5529
5530 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5531                                     SMC_SIslands_MCRegisterSet *data,
5532                                     u32 num_entries, u32 valid_flag)
5533 {
5534         u32 i, j;
5535
5536         for(i = 0, j = 0; j < num_entries; j++) {
5537                 if (valid_flag & (1 << j)) {
5538                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
5539                         i++;
5540                 }
5541         }
5542 }
5543
5544 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5545                                                  struct rv7xx_pl *pl,
5546                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5547 {
5548         struct si_power_info *si_pi = si_get_pi(rdev);
5549         u32 i = 0;
5550
5551         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5552                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5553                         break;
5554         }
5555
5556         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5557                 --i;
5558
5559         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5560                                 mc_reg_table_data, si_pi->mc_reg_table.last,
5561                                 si_pi->mc_reg_table.valid_flag);
5562 }
5563
5564 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5565                                            struct radeon_ps *radeon_state,
5566                                            SMC_SIslands_MCRegisters *mc_reg_table)
5567 {
5568         struct ni_ps *state = ni_get_ps(radeon_state);
5569         int i;
5570
5571         for (i = 0; i < state->performance_level_count; i++) {
5572                 si_convert_mc_reg_table_entry_to_smc(rdev,
5573                                                      &state->performance_levels[i],
5574                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5575         }
5576 }
5577
5578 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5579                                     struct radeon_ps *radeon_boot_state)
5580 {
5581         struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5582         struct si_power_info *si_pi = si_get_pi(rdev);
5583         struct si_ulv_param *ulv = &si_pi->ulv;
5584         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5585
5586         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5587
5588         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5589
5590         si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5591
5592         si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5593                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5594
5595         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5596                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5597                                 si_pi->mc_reg_table.last,
5598                                 si_pi->mc_reg_table.valid_flag);
5599
5600         if (ulv->supported && ulv->pl.vddc != 0)
5601                 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5602                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5603         else
5604                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5605                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5606                                         si_pi->mc_reg_table.last,
5607                                         si_pi->mc_reg_table.valid_flag);
5608
5609         si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5610
5611         return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5612                                     (u8 *)smc_mc_reg_table,
5613                                     sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5614 }
5615
5616 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5617                                   struct radeon_ps *radeon_new_state)
5618 {
5619         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5620         struct si_power_info *si_pi = si_get_pi(rdev);
5621         u32 address = si_pi->mc_reg_table_start +
5622                 offsetof(SMC_SIslands_MCRegisters,
5623                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5624         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5625
5626         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5627
5628         si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5629
5630
5631         return si_copy_bytes_to_smc(rdev, address,
5632                                     (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5633                                     sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5634                                     si_pi->sram_end);
5635
5636 }
5637
5638 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5639 {
5640         if (enable)
5641                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5642         else
5643                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5644 }
5645
5646 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5647                                                       struct radeon_ps *radeon_state)
5648 {
5649         struct ni_ps *state = ni_get_ps(radeon_state);
5650         int i;
5651         u16 pcie_speed, max_speed = 0;
5652
5653         for (i = 0; i < state->performance_level_count; i++) {
5654                 pcie_speed = state->performance_levels[i].pcie_gen;
5655                 if (max_speed < pcie_speed)
5656                         max_speed = pcie_speed;
5657         }
5658         return max_speed;
5659 }
5660
5661 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5662 {
5663         u32 speed_cntl;
5664
5665         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5666         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5667
5668         return (u16)speed_cntl;
5669 }
5670
5671 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5672                                                              struct radeon_ps *radeon_new_state,
5673                                                              struct radeon_ps *radeon_current_state)
5674 {
5675         struct si_power_info *si_pi = si_get_pi(rdev);
5676         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5677         enum radeon_pcie_gen current_link_speed;
5678
5679         if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5680                 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5681         else
5682                 current_link_speed = si_pi->force_pcie_gen;
5683
5684         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5685         si_pi->pspp_notify_required = false;
5686         if (target_link_speed > current_link_speed) {
5687                 switch (target_link_speed) {
5688 #if defined(CONFIG_ACPI)
5689                 case RADEON_PCIE_GEN3:
5690                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5691                                 break;
5692                         si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5693                         if (current_link_speed == RADEON_PCIE_GEN2)
5694                                 break;
5695                 case RADEON_PCIE_GEN2:
5696                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5697                                 break;
5698 #endif
5699                 default:
5700                         si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5701                         break;
5702                 }
5703         } else {
5704                 if (target_link_speed < current_link_speed)
5705                         si_pi->pspp_notify_required = true;
5706         }
5707 }
5708
5709 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5710                                                            struct radeon_ps *radeon_new_state,
5711                                                            struct radeon_ps *radeon_current_state)
5712 {
5713         struct si_power_info *si_pi = si_get_pi(rdev);
5714         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5715         u8 request;
5716
5717         if (si_pi->pspp_notify_required) {
5718                 if (target_link_speed == RADEON_PCIE_GEN3)
5719                         request = PCIE_PERF_REQ_PECI_GEN3;
5720                 else if (target_link_speed == RADEON_PCIE_GEN2)
5721                         request = PCIE_PERF_REQ_PECI_GEN2;
5722                 else
5723                         request = PCIE_PERF_REQ_PECI_GEN1;
5724
5725                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5726                     (si_get_current_pcie_speed(rdev) > 0))
5727                         return;
5728
5729 #if defined(CONFIG_ACPI)
5730                 radeon_acpi_pcie_performance_request(rdev, request, false);
5731 #endif
5732         }
5733 }
5734
5735 #if 0
5736 static int si_ds_request(struct radeon_device *rdev,
5737                          bool ds_status_on, u32 count_write)
5738 {
5739         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5740
5741         if (eg_pi->sclk_deep_sleep) {
5742                 if (ds_status_on)
5743                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5744                                 PPSMC_Result_OK) ?
5745                                 0 : -EINVAL;
5746                 else
5747                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5748                                 PPSMC_Result_OK) ? 0 : -EINVAL;
5749         }
5750         return 0;
5751 }
5752 #endif
5753
5754 static void si_set_max_cu_value(struct radeon_device *rdev)
5755 {
5756         struct si_power_info *si_pi = si_get_pi(rdev);
5757
5758         if (rdev->family == CHIP_VERDE) {
5759                 switch (rdev->pdev->device) {
5760                 case 0x6820:
5761                 case 0x6825:
5762                 case 0x6821:
5763                 case 0x6823:
5764                 case 0x6827:
5765                         si_pi->max_cu = 10;
5766                         break;
5767                 case 0x682D:
5768                 case 0x6824:
5769                 case 0x682F:
5770                 case 0x6826:
5771                         si_pi->max_cu = 8;
5772                         break;
5773                 case 0x6828:
5774                 case 0x6830:
5775                 case 0x6831:
5776                 case 0x6838:
5777                 case 0x6839:
5778                 case 0x683D:
5779                         si_pi->max_cu = 10;
5780                         break;
5781                 case 0x683B:
5782                 case 0x683F:
5783                 case 0x6829:
5784                         si_pi->max_cu = 8;
5785                         break;
5786                 default:
5787                         si_pi->max_cu = 0;
5788                         break;
5789                 }
5790         } else {
5791                 si_pi->max_cu = 0;
5792         }
5793 }
5794
5795 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5796                                                              struct radeon_clock_voltage_dependency_table *table)
5797 {
5798         u32 i;
5799         int j;
5800         u16 leakage_voltage;
5801
5802         if (table) {
5803                 for (i = 0; i < table->count; i++) {
5804                         switch (si_get_leakage_voltage_from_leakage_index(rdev,
5805                                                                           table->entries[i].v,
5806                                                                           &leakage_voltage)) {
5807                         case 0:
5808                                 table->entries[i].v = leakage_voltage;
5809                                 break;
5810                         case -EAGAIN:
5811                                 return -EINVAL;
5812                         case -EINVAL:
5813                         default:
5814                                 break;
5815                         }
5816                 }
5817
5818                 for (j = (table->count - 2); j >= 0; j--) {
5819                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5820                                 table->entries[j].v : table->entries[j + 1].v;
5821                 }
5822         }
5823         return 0;
5824 }
5825
5826 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5827 {
5828         int ret = 0;
5829
5830         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5831                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5832         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5833                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5834         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5835                                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5836         return ret;
5837 }
5838
5839 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5840                                           struct radeon_ps *radeon_new_state,
5841                                           struct radeon_ps *radeon_current_state)
5842 {
5843         u32 lane_width;
5844         u32 new_lane_width =
5845                 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5846         u32 current_lane_width =
5847                 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5848
5849         if (new_lane_width != current_lane_width) {
5850                 radeon_set_pcie_lanes(rdev, new_lane_width);
5851                 lane_width = radeon_get_pcie_lanes(rdev);
5852                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5853         }
5854 }
5855
5856 void si_dpm_setup_asic(struct radeon_device *rdev)
5857 {
5858         int r;
5859
5860         r = si_mc_load_microcode(rdev);
5861         if (r)
5862                 DRM_ERROR("Failed to load MC firmware!\n");
5863         rv770_get_memory_type(rdev);
5864         si_read_clock_registers(rdev);
5865         si_enable_acpi_power_management(rdev);
5866 }
5867
5868 static int si_thermal_enable_alert(struct radeon_device *rdev,
5869                                    bool enable)
5870 {
5871         u32 thermal_int = RREG32(CG_THERMAL_INT);
5872
5873         if (enable) {
5874                 PPSMC_Result result;
5875
5876                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
5877                 WREG32(CG_THERMAL_INT, thermal_int);
5878                 rdev->irq.dpm_thermal = false;
5879                 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5880                 if (result != PPSMC_Result_OK) {
5881                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5882                         return -EINVAL;
5883                 }
5884         } else {
5885                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
5886                 WREG32(CG_THERMAL_INT, thermal_int);
5887                 rdev->irq.dpm_thermal = true;
5888         }
5889
5890         return 0;
5891 }
5892
5893 static int si_thermal_set_temperature_range(struct radeon_device *rdev,
5894                                             int min_temp, int max_temp)
5895 {
5896         int low_temp = 0 * 1000;
5897         int high_temp = 255 * 1000;
5898
5899         if (low_temp < min_temp)
5900                 low_temp = min_temp;
5901         if (high_temp > max_temp)
5902                 high_temp = max_temp;
5903         if (high_temp < low_temp) {
5904                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5905                 return -EINVAL;
5906         }
5907
5908         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5909         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5910         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5911
5912         rdev->pm.dpm.thermal.min_temp = low_temp;
5913         rdev->pm.dpm.thermal.max_temp = high_temp;
5914
5915         return 0;
5916 }
5917
5918 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
5919 {
5920         struct si_power_info *si_pi = si_get_pi(rdev);
5921         u32 tmp;
5922
5923         if (si_pi->fan_ctrl_is_in_default_mode) {
5924                 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
5925                 si_pi->fan_ctrl_default_mode = tmp;
5926                 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
5927                 si_pi->t_min = tmp;
5928                 si_pi->fan_ctrl_is_in_default_mode = false;
5929         }
5930
5931         tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
5932         tmp |= TMIN(0);
5933         WREG32(CG_FDO_CTRL2, tmp);
5934
5935         tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
5936         tmp |= FDO_PWM_MODE(mode);
5937         WREG32(CG_FDO_CTRL2, tmp);
5938 }
5939
5940 static int si_thermal_setup_fan_table(struct radeon_device *rdev)
5941 {
5942         struct si_power_info *si_pi = si_get_pi(rdev);
5943         PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
5944         u32 duty100;
5945         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
5946         u16 fdo_min, slope1, slope2;
5947         u32 reference_clock, tmp;
5948         int ret;
5949         u64 tmp64;
5950
5951         if (!si_pi->fan_table_start) {
5952                 rdev->pm.dpm.fan.ucode_fan_control = false;
5953                 return 0;
5954         }
5955
5956         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
5957
5958         if (duty100 == 0) {
5959                 rdev->pm.dpm.fan.ucode_fan_control = false;
5960                 return 0;
5961         }
5962
5963         tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
5964         do_div(tmp64, 10000);
5965         fdo_min = (u16)tmp64;
5966
5967         t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
5968         t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
5969
5970         pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
5971         pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
5972
5973         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
5974         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
5975
5976         fan_table.slope1 = cpu_to_be16(slope1);
5977         fan_table.slope2 = cpu_to_be16(slope2);
5978
5979         fan_table.fdo_min = cpu_to_be16(fdo_min);
5980
5981         fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
5982
5983         fan_table.hys_up = cpu_to_be16(1);
5984
5985         fan_table.hys_slope = cpu_to_be16(1);
5986
5987         fan_table.temp_resp_lim = cpu_to_be16(5);
5988
5989         reference_clock = radeon_get_xclk(rdev);
5990
5991         fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
5992                                                 reference_clock) / 1600);
5993
5994         fan_table.fdo_max = cpu_to_be16((u16)duty100);
5995
5996         tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
5997         fan_table.temp_src = (uint8_t)tmp;
5998
5999         ret = si_copy_bytes_to_smc(rdev,
6000                                    si_pi->fan_table_start,
6001                                    (u8 *)(&fan_table),
6002                                    sizeof(fan_table),
6003                                    si_pi->sram_end);
6004
6005         if (ret) {
6006                 DRM_ERROR("Failed to load fan table to the SMC.");
6007                 rdev->pm.dpm.fan.ucode_fan_control = false;
6008         }
6009
6010         return 0;
6011 }
6012
6013 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6014 {
6015         PPSMC_Result ret;
6016
6017         ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6018         if (ret == PPSMC_Result_OK)
6019                 return 0;
6020         else
6021                 return -EINVAL;
6022 }
6023
6024 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6025 {
6026         PPSMC_Result ret;
6027
6028         ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6029         if (ret == PPSMC_Result_OK)
6030                 return 0;
6031         else
6032                 return -EINVAL;
6033 }
6034
6035 #if 0
6036 static int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6037                                              u32 *speed)
6038 {
6039         u32 duty, duty100;
6040         u64 tmp64;
6041
6042         if (rdev->pm.no_fan)
6043                 return -ENOENT;
6044
6045         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6046         duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6047
6048         if (duty100 == 0)
6049                 return -EINVAL;
6050
6051         tmp64 = (u64)duty * 100;
6052         do_div(tmp64, duty100);
6053         *speed = (u32)tmp64;
6054
6055         if (*speed > 100)
6056                 *speed = 100;
6057
6058         return 0;
6059 }
6060
6061 static int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6062                                              u32 speed)
6063 {
6064         u32 tmp;
6065         u32 duty, duty100;
6066         u64 tmp64;
6067
6068         if (rdev->pm.no_fan)
6069                 return -ENOENT;
6070
6071         if (speed > 100)
6072                 return -EINVAL;
6073
6074         if (rdev->pm.dpm.fan.ucode_fan_control)
6075                 si_fan_ctrl_stop_smc_fan_control(rdev);
6076
6077         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6078
6079         if (duty100 == 0)
6080                 return -EINVAL;
6081
6082         tmp64 = (u64)speed * duty100;
6083         do_div(tmp64, 100);
6084         duty = (u32)tmp64;
6085
6086         tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6087         tmp |= FDO_STATIC_DUTY(duty);
6088         WREG32(CG_FDO_CTRL0, tmp);
6089
6090         si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6091
6092         return 0;
6093 }
6094
6095 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6096                                          u32 *speed)
6097 {
6098         u32 tach_period;
6099         u32 xclk = radeon_get_xclk(rdev);
6100
6101         if (rdev->pm.no_fan)
6102                 return -ENOENT;
6103
6104         if (rdev->pm.fan_pulses_per_revolution == 0)
6105                 return -ENOENT;
6106
6107         tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6108         if (tach_period == 0)
6109                 return -ENOENT;
6110
6111         *speed = 60 * xclk * 10000 / tach_period;
6112
6113         return 0;
6114 }
6115
6116 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6117                                          u32 speed)
6118 {
6119         u32 tach_period, tmp;
6120         u32 xclk = radeon_get_xclk(rdev);
6121
6122         if (rdev->pm.no_fan)
6123                 return -ENOENT;
6124
6125         if (rdev->pm.fan_pulses_per_revolution == 0)
6126                 return -ENOENT;
6127
6128         if ((speed < rdev->pm.fan_min_rpm) ||
6129             (speed > rdev->pm.fan_max_rpm))
6130                 return -EINVAL;
6131
6132         if (rdev->pm.dpm.fan.ucode_fan_control)
6133                 si_fan_ctrl_stop_smc_fan_control(rdev);
6134
6135         tach_period = 60 * xclk * 10000 / (8 * speed);
6136         tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6137         tmp |= TARGET_PERIOD(tach_period);
6138         WREG32(CG_TACH_CTRL, tmp);
6139
6140         si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6141
6142         return 0;
6143 }
6144 #endif
6145
6146 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6147 {
6148         struct si_power_info *si_pi = si_get_pi(rdev);
6149         u32 tmp;
6150
6151         if (!si_pi->fan_ctrl_is_in_default_mode) {
6152                 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6153                 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6154                 WREG32(CG_FDO_CTRL2, tmp);
6155
6156                 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6157                 tmp |= TMIN(si_pi->t_min);
6158                 WREG32(CG_FDO_CTRL2, tmp);
6159                 si_pi->fan_ctrl_is_in_default_mode = true;
6160         }
6161 }
6162
6163 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6164 {
6165         if (rdev->pm.dpm.fan.ucode_fan_control) {
6166                 si_fan_ctrl_start_smc_fan_control(rdev);
6167                 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6168         }
6169 }
6170
6171 static void si_thermal_initialize(struct radeon_device *rdev)
6172 {
6173         u32 tmp;
6174
6175         if (rdev->pm.fan_pulses_per_revolution) {
6176                 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6177                 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6178                 WREG32(CG_TACH_CTRL, tmp);
6179         }
6180
6181         tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6182         tmp |= TACH_PWM_RESP_RATE(0x28);
6183         WREG32(CG_FDO_CTRL2, tmp);
6184 }
6185
6186 static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6187 {
6188         int ret;
6189
6190         si_thermal_initialize(rdev);
6191         ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6192         if (ret)
6193                 return ret;
6194         ret = si_thermal_enable_alert(rdev, true);
6195         if (ret)
6196                 return ret;
6197         if (rdev->pm.dpm.fan.ucode_fan_control) {
6198                 ret = si_halt_smc(rdev);
6199                 if (ret)
6200                         return ret;
6201                 ret = si_thermal_setup_fan_table(rdev);
6202                 if (ret)
6203                         return ret;
6204                 ret = si_resume_smc(rdev);
6205                 if (ret)
6206                         return ret;
6207                 si_thermal_start_smc_fan_control(rdev);
6208         }
6209
6210         return 0;
6211 }
6212
6213 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6214 {
6215         if (!rdev->pm.no_fan) {
6216                 si_fan_ctrl_set_default_mode(rdev);
6217                 si_fan_ctrl_stop_smc_fan_control(rdev);
6218         }
6219 }
6220
6221 int si_dpm_enable(struct radeon_device *rdev)
6222 {
6223         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6224         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6225         struct si_power_info *si_pi = si_get_pi(rdev);
6226         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6227         int ret;
6228
6229         if (si_is_smc_running(rdev))
6230                 return -EINVAL;
6231         if (pi->voltage_control || si_pi->voltage_control_svi2)
6232                 si_enable_voltage_control(rdev, true);
6233         if (pi->mvdd_control)
6234                 si_get_mvdd_configuration(rdev);
6235         if (pi->voltage_control || si_pi->voltage_control_svi2) {
6236                 ret = si_construct_voltage_tables(rdev);
6237                 if (ret) {
6238                         DRM_ERROR("si_construct_voltage_tables failed\n");
6239                         return ret;
6240                 }
6241         }
6242         if (eg_pi->dynamic_ac_timing) {
6243                 ret = si_initialize_mc_reg_table(rdev);
6244                 if (ret)
6245                         eg_pi->dynamic_ac_timing = false;
6246         }
6247         if (pi->dynamic_ss)
6248                 si_enable_spread_spectrum(rdev, true);
6249         if (pi->thermal_protection)
6250                 si_enable_thermal_protection(rdev, true);
6251         si_setup_bsp(rdev);
6252         si_program_git(rdev);
6253         si_program_tp(rdev);
6254         si_program_tpp(rdev);
6255         si_program_sstp(rdev);
6256         si_enable_display_gap(rdev);
6257         si_program_vc(rdev);
6258         ret = si_upload_firmware(rdev);
6259         if (ret) {
6260                 DRM_ERROR("si_upload_firmware failed\n");
6261                 return ret;
6262         }
6263         ret = si_process_firmware_header(rdev);
6264         if (ret) {
6265                 DRM_ERROR("si_process_firmware_header failed\n");
6266                 return ret;
6267         }
6268         ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6269         if (ret) {
6270                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6271                 return ret;
6272         }
6273         ret = si_init_smc_table(rdev);
6274         if (ret) {
6275                 DRM_ERROR("si_init_smc_table failed\n");
6276                 return ret;
6277         }
6278         ret = si_init_smc_spll_table(rdev);
6279         if (ret) {
6280                 DRM_ERROR("si_init_smc_spll_table failed\n");
6281                 return ret;
6282         }
6283         ret = si_init_arb_table_index(rdev);
6284         if (ret) {
6285                 DRM_ERROR("si_init_arb_table_index failed\n");
6286                 return ret;
6287         }
6288         if (eg_pi->dynamic_ac_timing) {
6289                 ret = si_populate_mc_reg_table(rdev, boot_ps);
6290                 if (ret) {
6291                         DRM_ERROR("si_populate_mc_reg_table failed\n");
6292                         return ret;
6293                 }
6294         }
6295         ret = si_initialize_smc_cac_tables(rdev);
6296         if (ret) {
6297                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6298                 return ret;
6299         }
6300         ret = si_initialize_hardware_cac_manager(rdev);
6301         if (ret) {
6302                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6303                 return ret;
6304         }
6305         ret = si_initialize_smc_dte_tables(rdev);
6306         if (ret) {
6307                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6308                 return ret;
6309         }
6310         ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6311         if (ret) {
6312                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6313                 return ret;
6314         }
6315         ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6316         if (ret) {
6317                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6318                 return ret;
6319         }
6320         si_program_response_times(rdev);
6321         si_program_ds_registers(rdev);
6322         si_dpm_start_smc(rdev);
6323         ret = si_notify_smc_display_change(rdev, false);
6324         if (ret) {
6325                 DRM_ERROR("si_notify_smc_display_change failed\n");
6326                 return ret;
6327         }
6328         si_enable_sclk_control(rdev, true);
6329         si_start_dpm(rdev);
6330
6331         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6332
6333         si_thermal_start_thermal_controller(rdev);
6334
6335         ni_update_current_ps(rdev, boot_ps);
6336
6337         return 0;
6338 }
6339
6340 static int si_set_temperature_range(struct radeon_device *rdev)
6341 {
6342         int ret;
6343
6344         ret = si_thermal_enable_alert(rdev, false);
6345         if (ret)
6346                 return ret;
6347         ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6348         if (ret)
6349                 return ret;
6350         ret = si_thermal_enable_alert(rdev, true);
6351         if (ret)
6352                 return ret;
6353
6354         return ret;
6355 }
6356
6357 int si_dpm_late_enable(struct radeon_device *rdev)
6358 {
6359         int ret;
6360
6361         ret = si_set_temperature_range(rdev);
6362         if (ret)
6363                 return ret;
6364
6365         return ret;
6366 }
6367
6368 void si_dpm_disable(struct radeon_device *rdev)
6369 {
6370         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6371         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6372
6373         if (!si_is_smc_running(rdev))
6374                 return;
6375         si_thermal_stop_thermal_controller(rdev);
6376         si_disable_ulv(rdev);
6377         si_clear_vc(rdev);
6378         if (pi->thermal_protection)
6379                 si_enable_thermal_protection(rdev, false);
6380         si_enable_power_containment(rdev, boot_ps, false);
6381         si_enable_smc_cac(rdev, boot_ps, false);
6382         si_enable_spread_spectrum(rdev, false);
6383         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6384         si_stop_dpm(rdev);
6385         si_reset_to_default(rdev);
6386         si_dpm_stop_smc(rdev);
6387         si_force_switch_to_arb_f0(rdev);
6388
6389         ni_update_current_ps(rdev, boot_ps);
6390 }
6391
6392 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6393 {
6394         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6395         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6396         struct radeon_ps *new_ps = &requested_ps;
6397
6398         ni_update_requested_ps(rdev, new_ps);
6399
6400         si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6401
6402         return 0;
6403 }
6404
6405 static int si_power_control_set_level(struct radeon_device *rdev)
6406 {
6407         struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6408         int ret;
6409
6410         ret = si_restrict_performance_levels_before_switch(rdev);
6411         if (ret)
6412                 return ret;
6413         ret = si_halt_smc(rdev);
6414         if (ret)
6415                 return ret;
6416         ret = si_populate_smc_tdp_limits(rdev, new_ps);
6417         if (ret)
6418                 return ret;
6419         ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6420         if (ret)
6421                 return ret;
6422         ret = si_resume_smc(rdev);
6423         if (ret)
6424                 return ret;
6425         ret = si_set_sw_state(rdev);
6426         if (ret)
6427                 return ret;
6428         return 0;
6429 }
6430
6431 int si_dpm_set_power_state(struct radeon_device *rdev)
6432 {
6433         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6434         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6435         struct radeon_ps *old_ps = &eg_pi->current_rps;
6436         int ret;
6437
6438         ret = si_disable_ulv(rdev);
6439         if (ret) {
6440                 DRM_ERROR("si_disable_ulv failed\n");
6441                 return ret;
6442         }
6443         ret = si_restrict_performance_levels_before_switch(rdev);
6444         if (ret) {
6445                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6446                 return ret;
6447         }
6448         if (eg_pi->pcie_performance_request)
6449                 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6450         ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6451         ret = si_enable_power_containment(rdev, new_ps, false);
6452         if (ret) {
6453                 DRM_ERROR("si_enable_power_containment failed\n");
6454                 return ret;
6455         }
6456         ret = si_enable_smc_cac(rdev, new_ps, false);
6457         if (ret) {
6458                 DRM_ERROR("si_enable_smc_cac failed\n");
6459                 return ret;
6460         }
6461         ret = si_halt_smc(rdev);
6462         if (ret) {
6463                 DRM_ERROR("si_halt_smc failed\n");
6464                 return ret;
6465         }
6466         ret = si_upload_sw_state(rdev, new_ps);
6467         if (ret) {
6468                 DRM_ERROR("si_upload_sw_state failed\n");
6469                 return ret;
6470         }
6471         ret = si_upload_smc_data(rdev);
6472         if (ret) {
6473                 DRM_ERROR("si_upload_smc_data failed\n");
6474                 return ret;
6475         }
6476         ret = si_upload_ulv_state(rdev);
6477         if (ret) {
6478                 DRM_ERROR("si_upload_ulv_state failed\n");
6479                 return ret;
6480         }
6481         if (eg_pi->dynamic_ac_timing) {
6482                 ret = si_upload_mc_reg_table(rdev, new_ps);
6483                 if (ret) {
6484                         DRM_ERROR("si_upload_mc_reg_table failed\n");
6485                         return ret;
6486                 }
6487         }
6488         ret = si_program_memory_timing_parameters(rdev, new_ps);
6489         if (ret) {
6490                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6491                 return ret;
6492         }
6493         si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6494
6495         ret = si_resume_smc(rdev);
6496         if (ret) {
6497                 DRM_ERROR("si_resume_smc failed\n");
6498                 return ret;
6499         }
6500         ret = si_set_sw_state(rdev);
6501         if (ret) {
6502                 DRM_ERROR("si_set_sw_state failed\n");
6503                 return ret;
6504         }
6505         ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6506         if (eg_pi->pcie_performance_request)
6507                 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6508         ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6509         if (ret) {
6510                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6511                 return ret;
6512         }
6513         ret = si_enable_smc_cac(rdev, new_ps, true);
6514         if (ret) {
6515                 DRM_ERROR("si_enable_smc_cac failed\n");
6516                 return ret;
6517         }
6518         ret = si_enable_power_containment(rdev, new_ps, true);
6519         if (ret) {
6520                 DRM_ERROR("si_enable_power_containment failed\n");
6521                 return ret;
6522         }
6523
6524         ret = si_power_control_set_level(rdev);
6525         if (ret) {
6526                 DRM_ERROR("si_power_control_set_level failed\n");
6527                 return ret;
6528         }
6529
6530         return 0;
6531 }
6532
6533 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6534 {
6535         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6536         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6537
6538         ni_update_current_ps(rdev, new_ps);
6539 }
6540
6541
6542 void si_dpm_reset_asic(struct radeon_device *rdev)
6543 {
6544         si_restrict_performance_levels_before_switch(rdev);
6545         si_disable_ulv(rdev);
6546         si_set_boot_state(rdev);
6547 }
6548
6549 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6550 {
6551         si_program_display_gap(rdev);
6552 }
6553
6554 union power_info {
6555         struct _ATOM_POWERPLAY_INFO info;
6556         struct _ATOM_POWERPLAY_INFO_V2 info_2;
6557         struct _ATOM_POWERPLAY_INFO_V3 info_3;
6558         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6559         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6560         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6561 };
6562
6563 union pplib_clock_info {
6564         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6565         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6566         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6567         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6568         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6569 };
6570
6571 union pplib_power_state {
6572         struct _ATOM_PPLIB_STATE v1;
6573         struct _ATOM_PPLIB_STATE_V2 v2;
6574 };
6575
6576 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6577                                           struct radeon_ps *rps,
6578                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6579                                           u8 table_rev)
6580 {
6581         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6582         rps->class = le16_to_cpu(non_clock_info->usClassification);
6583         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6584
6585         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6586                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6587                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6588         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6589                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6590                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6591         } else {
6592                 rps->vclk = 0;
6593                 rps->dclk = 0;
6594         }
6595
6596         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6597                 rdev->pm.dpm.boot_ps = rps;
6598         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6599                 rdev->pm.dpm.uvd_ps = rps;
6600 }
6601
6602 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6603                                       struct radeon_ps *rps, int index,
6604                                       union pplib_clock_info *clock_info)
6605 {
6606         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6607         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6608         struct si_power_info *si_pi = si_get_pi(rdev);
6609         struct ni_ps *ps = ni_get_ps(rps);
6610         u16 leakage_voltage;
6611         struct rv7xx_pl *pl = &ps->performance_levels[index];
6612         int ret;
6613
6614         ps->performance_level_count = index + 1;
6615
6616         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6617         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6618         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6619         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6620
6621         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6622         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6623         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6624         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6625                                                  si_pi->sys_pcie_mask,
6626                                                  si_pi->boot_pcie_gen,
6627                                                  clock_info->si.ucPCIEGen);
6628
6629         /* patch up vddc if necessary */
6630         ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6631                                                         &leakage_voltage);
6632         if (ret == 0)
6633                 pl->vddc = leakage_voltage;
6634
6635         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6636                 pi->acpi_vddc = pl->vddc;
6637                 eg_pi->acpi_vddci = pl->vddci;
6638                 si_pi->acpi_pcie_gen = pl->pcie_gen;
6639         }
6640
6641         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6642             index == 0) {
6643                 /* XXX disable for A0 tahiti */
6644                 si_pi->ulv.supported = false;
6645                 si_pi->ulv.pl = *pl;
6646                 si_pi->ulv.one_pcie_lane_in_ulv = false;
6647                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6648                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6649                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6650         }
6651
6652         if (pi->min_vddc_in_table > pl->vddc)
6653                 pi->min_vddc_in_table = pl->vddc;
6654
6655         if (pi->max_vddc_in_table < pl->vddc)
6656                 pi->max_vddc_in_table = pl->vddc;
6657
6658         /* patch up boot state */
6659         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6660                 u16 vddc, vddci, mvdd;
6661                 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6662                 pl->mclk = rdev->clock.default_mclk;
6663                 pl->sclk = rdev->clock.default_sclk;
6664                 pl->vddc = vddc;
6665                 pl->vddci = vddci;
6666                 si_pi->mvdd_bootup_value = mvdd;
6667         }
6668
6669         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6670             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6671                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6672                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6673                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6674                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6675         }
6676 }
6677
6678 static int si_parse_power_table(struct radeon_device *rdev)
6679 {
6680         struct radeon_mode_info *mode_info = &rdev->mode_info;
6681         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6682         union pplib_power_state *power_state;
6683         int i, j, k, non_clock_array_index, clock_array_index;
6684         union pplib_clock_info *clock_info;
6685         struct _StateArray *state_array;
6686         struct _ClockInfoArray *clock_info_array;
6687         struct _NonClockInfoArray *non_clock_info_array;
6688         union power_info *power_info;
6689         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6690         u16 data_offset;
6691         u8 frev, crev;
6692         u8 *power_state_offset;
6693         struct ni_ps *ps;
6694
6695         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6696                                    &frev, &crev, &data_offset))
6697                 return -EINVAL;
6698         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6699
6700         state_array = (struct _StateArray *)
6701                 (mode_info->atom_context->bios + data_offset +
6702                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
6703         clock_info_array = (struct _ClockInfoArray *)
6704                 (mode_info->atom_context->bios + data_offset +
6705                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6706         non_clock_info_array = (struct _NonClockInfoArray *)
6707                 (mode_info->atom_context->bios + data_offset +
6708                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6709
6710         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6711                                   state_array->ucNumEntries, GFP_KERNEL);
6712         if (!rdev->pm.dpm.ps)
6713                 return -ENOMEM;
6714         power_state_offset = (u8 *)state_array->states;
6715         for (i = 0; i < state_array->ucNumEntries; i++) {
6716                 u8 *idx;
6717                 power_state = (union pplib_power_state *)power_state_offset;
6718                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6719                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6720                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
6721                 if (!rdev->pm.power_state[i].clock_info)
6722                         return -EINVAL;
6723                 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6724                 if (ps == NULL) {
6725                         kfree(rdev->pm.dpm.ps);
6726                         return -ENOMEM;
6727                 }
6728                 rdev->pm.dpm.ps[i].ps_priv = ps;
6729                 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6730                                               non_clock_info,
6731                                               non_clock_info_array->ucEntrySize);
6732                 k = 0;
6733                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6734                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6735                         clock_array_index = idx[j];
6736                         if (clock_array_index >= clock_info_array->ucNumEntries)
6737                                 continue;
6738                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6739                                 break;
6740                         clock_info = (union pplib_clock_info *)
6741                                 ((u8 *)&clock_info_array->clockInfo[0] +
6742                                  (clock_array_index * clock_info_array->ucEntrySize));
6743                         si_parse_pplib_clock_info(rdev,
6744                                                   &rdev->pm.dpm.ps[i], k,
6745                                                   clock_info);
6746                         k++;
6747                 }
6748                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6749         }
6750         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6751         return 0;
6752 }
6753
6754 int si_dpm_init(struct radeon_device *rdev)
6755 {
6756         struct rv7xx_power_info *pi;
6757         struct evergreen_power_info *eg_pi;
6758         struct ni_power_info *ni_pi;
6759         struct si_power_info *si_pi;
6760         struct atom_clock_dividers dividers;
6761         int ret;
6762         u32 mask;
6763
6764         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6765         if (si_pi == NULL)
6766                 return -ENOMEM;
6767         rdev->pm.dpm.priv = si_pi;
6768         ni_pi = &si_pi->ni;
6769         eg_pi = &ni_pi->eg;
6770         pi = &eg_pi->rv7xx;
6771
6772         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6773         if (ret)
6774                 si_pi->sys_pcie_mask = 0;
6775         else
6776                 si_pi->sys_pcie_mask = mask;
6777         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6778         si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6779
6780         si_set_max_cu_value(rdev);
6781
6782         rv770_get_max_vddc(rdev);
6783         si_get_leakage_vddc(rdev);
6784         si_patch_dependency_tables_based_on_leakage(rdev);
6785
6786         pi->acpi_vddc = 0;
6787         eg_pi->acpi_vddci = 0;
6788         pi->min_vddc_in_table = 0;
6789         pi->max_vddc_in_table = 0;
6790
6791         ret = r600_get_platform_caps(rdev);
6792         if (ret)
6793                 return ret;
6794
6795         ret = si_parse_power_table(rdev);
6796         if (ret)
6797                 return ret;
6798         ret = r600_parse_extended_power_table(rdev);
6799         if (ret)
6800                 return ret;
6801
6802         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6803                 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6804         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6805                 r600_free_extended_power_table(rdev);
6806                 return -ENOMEM;
6807         }
6808         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6809         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6810         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6811         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6812         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6813         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6814         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6815         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6816         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6817
6818         if (rdev->pm.dpm.voltage_response_time == 0)
6819                 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6820         if (rdev->pm.dpm.backbias_response_time == 0)
6821                 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6822
6823         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6824                                              0, false, &dividers);
6825         if (ret)
6826                 pi->ref_div = dividers.ref_div + 1;
6827         else
6828                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6829
6830         eg_pi->smu_uvd_hs = false;
6831
6832         pi->mclk_strobe_mode_threshold = 40000;
6833         if (si_is_special_1gb_platform(rdev))
6834                 pi->mclk_stutter_mode_threshold = 0;
6835         else
6836                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6837         pi->mclk_edc_enable_threshold = 40000;
6838         eg_pi->mclk_edc_wr_enable_threshold = 40000;
6839
6840         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6841
6842         pi->voltage_control =
6843                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6844                                             VOLTAGE_OBJ_GPIO_LUT);
6845         if (!pi->voltage_control) {
6846                 si_pi->voltage_control_svi2 =
6847                         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6848                                                     VOLTAGE_OBJ_SVID2);
6849                 if (si_pi->voltage_control_svi2)
6850                         radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6851                                                   &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
6852         }
6853
6854         pi->mvdd_control =
6855                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
6856                                             VOLTAGE_OBJ_GPIO_LUT);
6857
6858         eg_pi->vddci_control =
6859                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
6860                                             VOLTAGE_OBJ_GPIO_LUT);
6861         if (!eg_pi->vddci_control)
6862                 si_pi->vddci_control_svi2 =
6863                         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
6864                                                     VOLTAGE_OBJ_SVID2);
6865
6866         si_pi->vddc_phase_shed_control =
6867                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6868                                             VOLTAGE_OBJ_PHASE_LUT);
6869
6870         rv770_get_engine_memory_ss(rdev);
6871
6872         pi->asi = RV770_ASI_DFLT;
6873         pi->pasi = CYPRESS_HASI_DFLT;
6874         pi->vrc = SISLANDS_VRC_DFLT;
6875
6876         pi->gfx_clock_gating = true;
6877
6878         eg_pi->sclk_deep_sleep = true;
6879         si_pi->sclk_deep_sleep_above_low = false;
6880
6881         if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6882                 pi->thermal_protection = true;
6883         else
6884                 pi->thermal_protection = false;
6885
6886         eg_pi->dynamic_ac_timing = true;
6887
6888         eg_pi->light_sleep = true;
6889 #if defined(CONFIG_ACPI)
6890         eg_pi->pcie_performance_request =
6891                 radeon_acpi_is_pcie_performance_request_supported(rdev);
6892 #else
6893         eg_pi->pcie_performance_request = false;
6894 #endif
6895
6896         si_pi->sram_end = SMC_RAM_END;
6897
6898         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
6899         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
6900         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
6901         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
6902         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
6903         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
6904         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
6905
6906         si_initialize_powertune_defaults(rdev);
6907
6908         /* make sure dc limits are valid */
6909         if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6910             (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6911                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6912                         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6913
6914         si_pi->fan_ctrl_is_in_default_mode = true;
6915         rdev->pm.dpm.fan.ucode_fan_control = false;
6916
6917         return 0;
6918 }
6919
6920 void si_dpm_fini(struct radeon_device *rdev)
6921 {
6922         int i;
6923
6924         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
6925                 kfree(rdev->pm.dpm.ps[i].ps_priv);
6926         }
6927         kfree(rdev->pm.dpm.ps);
6928         kfree(rdev->pm.dpm.priv);
6929         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
6930         r600_free_extended_power_table(rdev);
6931 }
6932
6933 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
6934                                                     struct seq_file *m)
6935 {
6936         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6937         struct radeon_ps *rps = &eg_pi->current_rps;
6938         struct ni_ps *ps = ni_get_ps(rps);
6939         struct rv7xx_pl *pl;
6940         u32 current_index =
6941                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
6942                 CURRENT_STATE_INDEX_SHIFT;
6943
6944         if (current_index >= ps->performance_level_count) {
6945                 seq_printf(m, "invalid dpm profile %d\n", current_index);
6946         } else {
6947                 pl = &ps->performance_levels[current_index];
6948                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6949                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
6950                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
6951         }
6952 }