drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include <drm/drmP.h>
  24 #include "radeon.h"
  25 #include "avivod.h"
  26 #include "atom.h"
  27 #include <linux/power_supply.h>
  28 #include <linux/hwmon.h>
  29 #include <linux/hwmon-sysfs.h>
  30
  31 #define RADEON_IDLE_LOOP_MS 100
  32 #define RADEON_RECLOCK_DELAY_MS 200
  33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  34
  35 static const char *radeon_pm_state_type_name[5] = {
  36         "",
  37         "Powersave",
  38         "Battery",
  39         "Balanced",
  40         "Performance",
  41 };
  42
  43 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  44 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  45 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  47 static void radeon_pm_update_profile(struct radeon_device *rdev);
  48 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  49
  50 int radeon_pm_get_type_index(struct radeon_device *rdev,
  51                              enum radeon_pm_state_type ps_type,
  52                              int instance)
  53 {
  54         int i;
  55         int found_instance = -1;
  56
  57         for (i = 0; i < rdev->pm.num_power_states; i++) {
  58                 if (rdev->pm.power_state[i].type == ps_type) {
  59                         found_instance++;
  60                         if (found_instance == instance)
  61                                 return i;
  62                 }
  63         }
  64         /* return default if no match */
  65         return rdev->pm.default_power_state_index;
  66 }
  67
  68 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
  69 {
  70         if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
  71                 mutex_lock(&rdev->pm.mutex);
  72                 if (power_supply_is_system_supplied() > 0)
  73                         rdev->pm.dpm.ac_power = true;
  74                 else
  75                         rdev->pm.dpm.ac_power = false;
  76                 if (rdev->asic->dpm.enable_bapm)
  77                         radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
  78                 mutex_unlock(&rdev->pm.mutex);
  79         } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  80                 if (rdev->pm.profile == PM_PROFILE_AUTO) {
  81                         mutex_lock(&rdev->pm.mutex);
  82                         radeon_pm_update_profile(rdev);
  83                         radeon_pm_set_clocks(rdev);
  84                         mutex_unlock(&rdev->pm.mutex);
  85                 }
  86         }
  87 }
  88
  89 static void radeon_pm_update_profile(struct radeon_device *rdev)
  90 {
  91         switch (rdev->pm.profile) {
  92         case PM_PROFILE_DEFAULT:
  93                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
  94                 break;
  95         case PM_PROFILE_AUTO:
  96                 if (power_supply_is_system_supplied() > 0) {
  97                         if (rdev->pm.active_crtc_count > 1)
  98                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  99                         else
 100                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 101                 } else {
 102                         if (rdev->pm.active_crtc_count > 1)
 103                                 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 104                         else
 105                                 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 106                 }
 107                 break;
 108         case PM_PROFILE_LOW:
 109                 if (rdev->pm.active_crtc_count > 1)
 110                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
 111                 else
 112                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
 113                 break;
 114         case PM_PROFILE_MID:
 115                 if (rdev->pm.active_crtc_count > 1)
 116                         rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 117                 else
 118                         rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 119                 break;
 120         case PM_PROFILE_HIGH:
 121                 if (rdev->pm.active_crtc_count > 1)
 122                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 123                 else
 124                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 125                 break;
 126         }
 127
 128         if (rdev->pm.active_crtc_count == 0) {
 129                 rdev->pm.requested_power_state_index =
 130                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 131                 rdev->pm.requested_clock_mode_index =
 132                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 133         } else {
 134                 rdev->pm.requested_power_state_index =
 135                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 136                 rdev->pm.requested_clock_mode_index =
 137                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 138         }
 139 }
 140
 141 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 142 {
 143         struct radeon_bo *bo, *n;
 144
 145         if (list_empty(&rdev->gem.objects))
 146                 return;
 147
 148         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 149                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 150                         ttm_bo_unmap_virtual(&bo->tbo);
 151         }
 152 }
 153
 154 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 155 {
 156         if (rdev->pm.active_crtcs) {
 157                 rdev->pm.vblank_sync = false;
 158                 wait_event_timeout(
 159                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 160                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 161         }
 162 }
 163
 164 static void radeon_set_power_state(struct radeon_device *rdev)
 165 {
 166         u32 sclk, mclk;
 167         bool misc_after = false;
 168
 169         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 170             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 171                 return;
 172
 173         if (radeon_gui_idle(rdev)) {
 174                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 175                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 176                 if (sclk > rdev->pm.default_sclk)
 177                         sclk = rdev->pm.default_sclk;
 178
 179                 /* starting with BTC, there is one state that is used for both
 180                  * MH and SH.  Difference is that we always use the high clock index for
 181                  * mclk and vddci.
 182                  */
 183                 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
 184                     (rdev->family >= CHIP_BARTS) &&
 185                     rdev->pm.active_crtc_count &&
 186                     ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
 187                      (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
 188                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 189                                 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
 190                 else
 191                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 192                                 clock_info[rdev->pm.requested_clock_mode_index].mclk;
 193
 194                 if (mclk > rdev->pm.default_mclk)
 195                         mclk = rdev->pm.default_mclk;
 196
 197                 /* upvolt before raising clocks, downvolt after lowering clocks */
 198                 if (sclk < rdev->pm.current_sclk)
 199                         misc_after = true;
 200
 201                 radeon_sync_with_vblank(rdev);
 202
 203                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 204                         if (!radeon_pm_in_vbl(rdev))
 205                                 return;
 206                 }
 207
 208                 radeon_pm_prepare(rdev);
 209
 210                 if (!misc_after)
 211                         /* voltage, pcie lanes, etc.*/
 212                         radeon_pm_misc(rdev);
 213
 214                 /* set engine clock */
 215                 if (sclk != rdev->pm.current_sclk) {
 216                         radeon_pm_debug_check_in_vbl(rdev, false);
 217                         radeon_set_engine_clock(rdev, sclk);
 218                         radeon_pm_debug_check_in_vbl(rdev, true);
 219                         rdev->pm.current_sclk = sclk;
 220                         DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
 221                 }
 222
 223                 /* set memory clock */
 224                 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 225                         radeon_pm_debug_check_in_vbl(rdev, false);
 226                         radeon_set_memory_clock(rdev, mclk);
 227                         radeon_pm_debug_check_in_vbl(rdev, true);
 228                         rdev->pm.current_mclk = mclk;
 229                         DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
 230                 }
 231
 232                 if (misc_after)
 233                         /* voltage, pcie lanes, etc.*/
 234                         radeon_pm_misc(rdev);
 235
 236                 radeon_pm_finish(rdev);
 237
 238                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 239                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 240         } else
 241                 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
 242 }
 243
 244 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 245 {
 246         int i, r;
 247
 248         /* no need to take locks, etc. if nothing's going to change */
 249         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 250             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 251                 return;
 252
 253         mutex_lock(&rdev->ddev->struct_mutex);
 254         down_write(&rdev->pm.mclk_lock);
 255         mutex_lock(&rdev->ring_lock);
 256
 257         /* wait for the rings to drain */
 258         for (i = 0; i < RADEON_NUM_RINGS; i++) {
 259                 struct radeon_ring *ring = &rdev->ring[i];
 260                 if (!ring->ready) {
 261                         continue;
 262                 }
 263                 r = radeon_fence_wait_empty_locked(rdev, i);
 264                 if (r) {
 265                         /* needs a GPU reset dont reset here */
 266                         mutex_unlock(&rdev->ring_lock);
 267                         up_write(&rdev->pm.mclk_lock);
 268                         mutex_unlock(&rdev->ddev->struct_mutex);
 269                         return;
 270                 }
 271         }
 272
 273         radeon_unmap_vram_bos(rdev);
 274
 275         if (rdev->irq.installed) {
 276                 for (i = 0; i < rdev->num_crtc; i++) {
 277                         if (rdev->pm.active_crtcs & (1 << i)) {
 278                                 rdev->pm.req_vblank |= (1 << i);
 279                                 drm_vblank_get(rdev->ddev, i);
 280                         }
 281                 }
 282         }
 283
 284         radeon_set_power_state(rdev);
 285
 286         if (rdev->irq.installed) {
 287                 for (i = 0; i < rdev->num_crtc; i++) {
 288                         if (rdev->pm.req_vblank & (1 << i)) {
 289                                 rdev->pm.req_vblank &= ~(1 << i);
 290                                 drm_vblank_put(rdev->ddev, i);
 291                         }
 292                 }
 293         }
 294
 295         /* update display watermarks based on new power state */
 296         radeon_update_bandwidth_info(rdev);
 297         if (rdev->pm.active_crtc_count)
 298                 radeon_bandwidth_update(rdev);
 299
 300         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 301
 302         mutex_unlock(&rdev->ring_lock);
 303         up_write(&rdev->pm.mclk_lock);
 304         mutex_unlock(&rdev->ddev->struct_mutex);
 305 }
 306
 307 static void radeon_pm_print_states(struct radeon_device *rdev)
 308 {
 309         int i, j;
 310         struct radeon_power_state *power_state;
 311         struct radeon_pm_clock_info *clock_info;
 312
 313         DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
 314         for (i = 0; i < rdev->pm.num_power_states; i++) {
 315                 power_state = &rdev->pm.power_state[i];
 316                 DRM_DEBUG_DRIVER("State %d: %s\n", i,
 317                         radeon_pm_state_type_name[power_state->type]);
 318                 if (i == rdev->pm.default_power_state_index)
 319                         DRM_DEBUG_DRIVER("\tDefault");
 320                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 321                         DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
 322                 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 323                         DRM_DEBUG_DRIVER("\tSingle display only\n");
 324                 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
 325                 for (j = 0; j < power_state->num_clock_modes; j++) {
 326                         clock_info = &(power_state->clock_info[j]);
 327                         if (rdev->flags & RADEON_IS_IGP)
 328                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
 329                                                  j,
 330                                                  clock_info->sclk * 10);
 331                         else
 332                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
 333                                                  j,
 334                                                  clock_info->sclk * 10,
 335                                                  clock_info->mclk * 10,
 336                                                  clock_info->voltage.voltage);
 337                 }
 338         }
 339 }
 340
 341 static ssize_t radeon_get_pm_profile(struct device *dev,
 342                                      struct device_attribute *attr,
 343                                      char *buf)
 344 {
 345         struct drm_device *ddev = dev_get_drvdata(dev);
 346         struct radeon_device *rdev = ddev->dev_private;
 347         int cp = rdev->pm.profile;
 348
 349         return snprintf(buf, PAGE_SIZE, "%s\n",
 350                         (cp == PM_PROFILE_AUTO) ? "auto" :
 351                         (cp == PM_PROFILE_LOW) ? "low" :
 352                         (cp == PM_PROFILE_MID) ? "mid" :
 353                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 354 }
 355
 356 static ssize_t radeon_set_pm_profile(struct device *dev,
 357                                      struct device_attribute *attr,
 358                                      const char *buf,
 359                                      size_t count)
 360 {
 361         struct drm_device *ddev = dev_get_drvdata(dev);
 362         struct radeon_device *rdev = ddev->dev_private;
 363
 364         mutex_lock(&rdev->pm.mutex);
 365         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 366                 if (strncmp("default", buf, strlen("default")) == 0)
 367                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 368                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 369                         rdev->pm.profile = PM_PROFILE_AUTO;
 370                 else if (strncmp("low", buf, strlen("low")) == 0)
 371                         rdev->pm.profile = PM_PROFILE_LOW;
 372                 else if (strncmp("mid", buf, strlen("mid")) == 0)
 373                         rdev->pm.profile = PM_PROFILE_MID;
 374                 else if (strncmp("high", buf, strlen("high")) == 0)
 375                         rdev->pm.profile = PM_PROFILE_HIGH;
 376                 else {
 377                         count = -EINVAL;
 378                         goto fail;
 379                 }
 380                 radeon_pm_update_profile(rdev);
 381                 radeon_pm_set_clocks(rdev);
 382         } else
 383                 count = -EINVAL;
 384
 385 fail:
 386         mutex_unlock(&rdev->pm.mutex);
 387
 388         return count;
 389 }
 390
 391 static ssize_t radeon_get_pm_method(struct device *dev,
 392                                     struct device_attribute *attr,
 393                                     char *buf)
 394 {
 395         struct drm_device *ddev = dev_get_drvdata(dev);
 396         struct radeon_device *rdev = ddev->dev_private;
 397         int pm = rdev->pm.pm_method;
 398
 399         return snprintf(buf, PAGE_SIZE, "%s\n",
 400                         (pm == PM_METHOD_DYNPM) ? "dynpm" :
 401                         (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
 402 }
 403
 404 static ssize_t radeon_set_pm_method(struct device *dev,
 405                                     struct device_attribute *attr,
 406                                     const char *buf,
 407                                     size_t count)
 408 {
 409         struct drm_device *ddev = dev_get_drvdata(dev);
 410         struct radeon_device *rdev = ddev->dev_private;
 411
 412         /* we don't support the legacy modes with dpm */
 413         if (rdev->pm.pm_method == PM_METHOD_DPM) {
 414                 count = -EINVAL;
 415                 goto fail;
 416         }
 417
 418         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 419                 mutex_lock(&rdev->pm.mutex);
 420                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 421                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 422                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 423                 mutex_unlock(&rdev->pm.mutex);
 424         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 425                 mutex_lock(&rdev->pm.mutex);
 426                 /* disable dynpm */
 427                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 428                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 429                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 430                 mutex_unlock(&rdev->pm.mutex);
 431                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 432         } else {
 433                 count = -EINVAL;
 434                 goto fail;
 435         }
 436         radeon_pm_compute_clocks(rdev);
 437 fail:
 438         return count;
 439 }
 440
 441 static ssize_t radeon_get_dpm_state(struct device *dev,
 442                                     struct device_attribute *attr,
 443                                     char *buf)
 444 {
 445         struct drm_device *ddev = dev_get_drvdata(dev);
 446         struct radeon_device *rdev = ddev->dev_private;
 447         enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
 448
 449         return snprintf(buf, PAGE_SIZE, "%s\n",
 450                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 451                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 452 }
 453
 454 static ssize_t radeon_set_dpm_state(struct device *dev,
 455                                     struct device_attribute *attr,
 456                                     const char *buf,
 457                                     size_t count)
 458 {
 459         struct drm_device *ddev = dev_get_drvdata(dev);
 460         struct radeon_device *rdev = ddev->dev_private;
 461
 462         mutex_lock(&rdev->pm.mutex);
 463         if (strncmp("battery", buf, strlen("battery")) == 0)
 464                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
 465         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 466                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
 467         else if (strncmp("performance", buf, strlen("performance")) == 0)
 468                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
 469         else {
 470                 mutex_unlock(&rdev->pm.mutex);
 471                 count = -EINVAL;
 472                 goto fail;
 473         }
 474         mutex_unlock(&rdev->pm.mutex);
 475         radeon_pm_compute_clocks(rdev);
 476 fail:
 477         return count;
 478 }
 479
 480 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
 481                                                        struct device_attribute *attr,
 482                                                        char *buf)
 483 {
 484         struct drm_device *ddev = dev_get_drvdata(dev);
 485         struct radeon_device *rdev = ddev->dev_private;
 486         enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
 487
 488         return snprintf(buf, PAGE_SIZE, "%s\n",
 489                         (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 490                         (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
 491 }
 492
 493 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
 494                                                        struct device_attribute *attr,
 495                                                        const char *buf,
 496                                                        size_t count)
 497 {
 498         struct drm_device *ddev = dev_get_drvdata(dev);
 499         struct radeon_device *rdev = ddev->dev_private;
 500         enum radeon_dpm_forced_level level;
 501         int ret = 0;
 502
 503         mutex_lock(&rdev->pm.mutex);
 504         if (strncmp("low", buf, strlen("low")) == 0) {
 505                 level = RADEON_DPM_FORCED_LEVEL_LOW;
 506         } else if (strncmp("high", buf, strlen("high")) == 0) {
 507                 level = RADEON_DPM_FORCED_LEVEL_HIGH;
 508         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 509                 level = RADEON_DPM_FORCED_LEVEL_AUTO;
 510         } else {
 511                 count = -EINVAL;
 512                 goto fail;
 513         }
 514         if (rdev->asic->dpm.force_performance_level) {
 515                 if (rdev->pm.dpm.thermal_active) {
 516                         count = -EINVAL;
 517                         goto fail;
 518                 }
 519                 ret = radeon_dpm_force_performance_level(rdev, level);
 520                 if (ret)
 521                         count = -EINVAL;
 522         }
 523 fail:
 524         mutex_unlock(&rdev->pm.mutex);
 525
 526         return count;
 527 }
 528
 529 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 530 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 531 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
 532 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 533                    radeon_get_dpm_forced_performance_level,
 534                    radeon_set_dpm_forced_performance_level);
 535
 536 static ssize_t radeon_hwmon_show_temp(struct device *dev,
 537                                       struct device_attribute *attr,
 538                                       char *buf)
 539 {
 540         struct radeon_device *rdev = dev_get_drvdata(dev);
 541         int temp;
 542
 543         if (rdev->asic->pm.get_temperature)
 544                 temp = radeon_get_temperature(rdev);
 545         else
 546                 temp = 0;
 547
 548         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 549 }
 550
 551 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
 552                                              struct device_attribute *attr,
 553                                              char *buf)
 554 {
 555         struct radeon_device *rdev = dev_get_drvdata(dev);
 556         int hyst = to_sensor_dev_attr(attr)->index;
 557         int temp;
 558
 559         if (hyst)
 560                 temp = rdev->pm.dpm.thermal.min_temp;
 561         else
 562                 temp = rdev->pm.dpm.thermal.max_temp;
 563
 564         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 565 }
 566
 567 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
 568 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
 569 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
 570
 571 static struct attribute *hwmon_attributes[] = {
 572         &sensor_dev_attr_temp1_input.dev_attr.attr,
 573         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 574         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
 575         NULL
 576 };
 577
 578 static umode_t hwmon_attributes_visible(struct kobject *kobj,
 579                                         struct attribute *attr, int index)
 580 {
 581         struct device *dev = container_of(kobj, struct device, kobj);
 582         struct radeon_device *rdev = dev_get_drvdata(dev);
 583
 584         /* Skip limit attributes if DPM is not enabled */
 585         if (rdev->pm.pm_method != PM_METHOD_DPM &&
 586             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
 587              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
 588                 return 0;
 589
 590         return attr->mode;
 591 }
 592
 593 static const struct attribute_group hwmon_attrgroup = {
 594         .attrs = hwmon_attributes,
 595         .is_visible = hwmon_attributes_visible,
 596 };
 597
 598 static const struct attribute_group *hwmon_groups[] = {
 599         &hwmon_attrgroup,
 600         NULL
 601 };
 602
 603 static int radeon_hwmon_init(struct radeon_device *rdev)
 604 {
 605         int err = 0;
 606         struct device *hwmon_dev;
 607
 608         switch (rdev->pm.int_thermal_type) {
 609         case THERMAL_TYPE_RV6XX:
 610         case THERMAL_TYPE_RV770:
 611         case THERMAL_TYPE_EVERGREEN:
 612         case THERMAL_TYPE_NI:
 613         case THERMAL_TYPE_SUMO:
 614         case THERMAL_TYPE_SI:
 615         case THERMAL_TYPE_CI:
 616         case THERMAL_TYPE_KV:
 617                 if (rdev->asic->pm.get_temperature == NULL)
 618                         return err;
 619                 hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
 620                                                               "radeon", rdev,
 621                                                               hwmon_groups);
 622                 if (IS_ERR(hwmon_dev)) {
 623                         err = PTR_ERR(hwmon_dev);
 624                         dev_err(rdev->dev,
 625                                 "Unable to register hwmon device: %d\n", err);
 626                 }
 627                 break;
 628         default:
 629                 break;
 630         }
 631
 632         return err;
 633 }
 634
 635 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
 636 {
 637         struct radeon_device *rdev =
 638                 container_of(work, struct radeon_device,
 639                              pm.dpm.thermal.work);
 640         /* switch to the thermal state */
 641         enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
 642
 643         if (!rdev->pm.dpm_enabled)
 644                 return;
 645
 646         if (rdev->asic->pm.get_temperature) {
 647                 int temp = radeon_get_temperature(rdev);
 648
 649                 if (temp < rdev->pm.dpm.thermal.min_temp)
 650                         /* switch back the user state */
 651                         dpm_state = rdev->pm.dpm.user_state;
 652         } else {
 653                 if (rdev->pm.dpm.thermal.high_to_low)
 654                         /* switch back the user state */
 655                         dpm_state = rdev->pm.dpm.user_state;
 656         }
 657         mutex_lock(&rdev->pm.mutex);
 658         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
 659                 rdev->pm.dpm.thermal_active = true;
 660         else
 661                 rdev->pm.dpm.thermal_active = false;
 662         rdev->pm.dpm.state = dpm_state;
 663         mutex_unlock(&rdev->pm.mutex);
 664
 665         radeon_pm_compute_clocks(rdev);
 666 }
 667
 668 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
 669                                                      enum radeon_pm_state_type dpm_state)
 670 {
 671         int i;
 672         struct radeon_ps *ps;
 673         u32 ui_class;
 674         bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
 675                 true : false;
 676
 677         /* check if the vblank period is too short to adjust the mclk */
 678         if (single_display && rdev->asic->dpm.vblank_too_short) {
 679                 if (radeon_dpm_vblank_too_short(rdev))
 680                         single_display = false;
 681         }
 682
 683         /* certain older asics have a separare 3D performance state,
 684          * so try that first if the user selected performance
 685          */
 686         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
 687                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
 688         /* balanced states don't exist at the moment */
 689         if (dpm_state == POWER_STATE_TYPE_BALANCED)
 690                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 691
 692 restart_search:
 693         /* Pick the best power state based on current conditions */
 694         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
 695                 ps = &rdev->pm.dpm.ps[i];
 696                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
 697                 switch (dpm_state) {
 698                 /* user states */
 699                 case POWER_STATE_TYPE_BATTERY:
 700                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
 701                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 702                                         if (single_display)
 703                                                 return ps;
 704                                 } else
 705                                         return ps;
 706                         }
 707                         break;
 708                 case POWER_STATE_TYPE_BALANCED:
 709                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
 710                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 711                                         if (single_display)
 712                                                 return ps;
 713                                 } else
 714                                         return ps;
 715                         }
 716                         break;
 717                 case POWER_STATE_TYPE_PERFORMANCE:
 718                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
 719                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 720                                         if (single_display)
 721                                                 return ps;
 722                                 } else
 723                                         return ps;
 724                         }
 725                         break;
 726                 /* internal states */
 727                 case POWER_STATE_TYPE_INTERNAL_UVD:
 728                         if (rdev->pm.dpm.uvd_ps)
 729                                 return rdev->pm.dpm.uvd_ps;
 730                         else
 731                                 break;
 732                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 733                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
 734                                 return ps;
 735                         break;
 736                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 737                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
 738                                 return ps;
 739                         break;
 740                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 741                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
 742                                 return ps;
 743                         break;
 744                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 745                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
 746                                 return ps;
 747                         break;
 748                 case POWER_STATE_TYPE_INTERNAL_BOOT:
 749                         return rdev->pm.dpm.boot_ps;
 750                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
 751                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
 752                                 return ps;
 753                         break;
 754                 case POWER_STATE_TYPE_INTERNAL_ACPI:
 755                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
 756                                 return ps;
 757                         break;
 758                 case POWER_STATE_TYPE_INTERNAL_ULV:
 759                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
 760                                 return ps;
 761                         break;
 762                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
 763                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
 764                                 return ps;
 765                         break;
 766                 default:
 767                         break;
 768                 }
 769         }
 770         /* use a fallback state if we didn't match */
 771         switch (dpm_state) {
 772         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 773                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
 774                 goto restart_search;
 775         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 776         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 777         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 778                 if (rdev->pm.dpm.uvd_ps) {
 779                         return rdev->pm.dpm.uvd_ps;
 780                 } else {
 781                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 782                         goto restart_search;
 783                 }
 784         case POWER_STATE_TYPE_INTERNAL_THERMAL:
 785                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
 786                 goto restart_search;
 787         case POWER_STATE_TYPE_INTERNAL_ACPI:
 788                 dpm_state = POWER_STATE_TYPE_BATTERY;
 789                 goto restart_search;
 790         case POWER_STATE_TYPE_BATTERY:
 791         case POWER_STATE_TYPE_BALANCED:
 792         case POWER_STATE_TYPE_INTERNAL_3DPERF:
 793                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 794                 goto restart_search;
 795         default:
 796                 break;
 797         }
 798
 799         return NULL;
 800 }
 801
 802 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
 803 {
 804         int i;
 805         struct radeon_ps *ps;
 806         enum radeon_pm_state_type dpm_state;
 807         int ret;
 808
 809         /* if dpm init failed */
 810         if (!rdev->pm.dpm_enabled)
 811                 return;
 812
 813         if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
 814                 /* add other state override checks here */
 815                 if ((!rdev->pm.dpm.thermal_active) &&
 816                     (!rdev->pm.dpm.uvd_active))
 817                         rdev->pm.dpm.state = rdev->pm.dpm.user_state;
 818         }
 819         dpm_state = rdev->pm.dpm.state;
 820
 821         ps = radeon_dpm_pick_power_state(rdev, dpm_state);
 822         if (ps)
 823                 rdev->pm.dpm.requested_ps = ps;
 824         else
 825                 return;
 826
 827         /* no need to reprogram if nothing changed unless we are on BTC+ */
 828         if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
 829                 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
 830                         /* for pre-BTC and APUs if the num crtcs changed but state is the same,
 831                          * all we need to do is update the display configuration.
 832                          */
 833                         if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
 834                                 /* update display watermarks based on new power state */
 835                                 radeon_bandwidth_update(rdev);
 836                                 /* update displays */
 837                                 radeon_dpm_display_configuration_changed(rdev);
 838                                 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 839                                 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 840                         }
 841                         return;
 842                 } else {
 843                         /* for BTC+ if the num crtcs hasn't changed and state is the same,
 844                          * nothing to do, if the num crtcs is > 1 and state is the same,
 845                          * update display configuration.
 846                          */
 847                         if (rdev->pm.dpm.new_active_crtcs ==
 848                             rdev->pm.dpm.current_active_crtcs) {
 849                                 return;
 850                         } else {
 851                                 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
 852                                     (rdev->pm.dpm.new_active_crtc_count > 1)) {
 853                                         /* update display watermarks based on new power state */
 854                                         radeon_bandwidth_update(rdev);
 855                                         /* update displays */
 856                                         radeon_dpm_display_configuration_changed(rdev);
 857                                         rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 858                                         rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 859                                         return;
 860                                 }
 861                         }
 862                 }
 863         }
 864
 865         if (radeon_dpm == 1) {
 866                 printk("switching from power state:\n");
 867                 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
 868                 printk("switching to power state:\n");
 869                 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
 870         }
 871         mutex_lock(&rdev->ddev->struct_mutex);
 872         down_write(&rdev->pm.mclk_lock);
 873         mutex_lock(&rdev->ring_lock);
 874
 875         ret = radeon_dpm_pre_set_power_state(rdev);
 876         if (ret)
 877                 goto done;
 878
 879         /* update display watermarks based on new power state */
 880         radeon_bandwidth_update(rdev);
 881         /* update displays */
 882         radeon_dpm_display_configuration_changed(rdev);
 883
 884         rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 885         rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 886
 887         /* wait for the rings to drain */
 888         for (i = 0; i < RADEON_NUM_RINGS; i++) {
 889                 struct radeon_ring *ring = &rdev->ring[i];
 890                 if (ring->ready)
 891                         radeon_fence_wait_empty_locked(rdev, i);
 892         }
 893
 894         /* program the new power state */
 895         radeon_dpm_set_power_state(rdev);
 896
 897         /* update current power state */
 898         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
 899
 900         radeon_dpm_post_set_power_state(rdev);
 901
 902         if (rdev->asic->dpm.force_performance_level) {
 903                 if (rdev->pm.dpm.thermal_active) {
 904                         enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
 905                         /* force low perf level for thermal */
 906                         radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
 907                         /* save the user's level */
 908                         rdev->pm.dpm.forced_level = level;
 909                 } else {
 910                         /* otherwise, user selected level */
 911                         radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
 912                 }
 913         }
 914
 915 done:
 916         mutex_unlock(&rdev->ring_lock);
 917         up_write(&rdev->pm.mclk_lock);
 918         mutex_unlock(&rdev->ddev->struct_mutex);
 919 }
 920
 921 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
 922 {
 923         enum radeon_pm_state_type dpm_state;
 924
 925         if (rdev->asic->dpm.powergate_uvd) {
 926                 mutex_lock(&rdev->pm.mutex);
 927                 /* enable/disable UVD */
 928                 radeon_dpm_powergate_uvd(rdev, !enable);
 929                 mutex_unlock(&rdev->pm.mutex);
 930         } else {
 931                 if (enable) {
 932                         mutex_lock(&rdev->pm.mutex);
 933                         rdev->pm.dpm.uvd_active = true;
 934                         /* disable this for now */
 935 #if 0
 936                         if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
 937                                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
 938                         else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
 939                                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
 940                         else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
 941                                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
 942                         else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
 943                                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
 944                         else
 945 #endif
 946                                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
 947                         rdev->pm.dpm.state = dpm_state;
 948                         mutex_unlock(&rdev->pm.mutex);
 949                 } else {
 950                         mutex_lock(&rdev->pm.mutex);
 951                         rdev->pm.dpm.uvd_active = false;
 952                         mutex_unlock(&rdev->pm.mutex);
 953                 }
 954
 955                 radeon_pm_compute_clocks(rdev);
 956         }
 957 }
 958
 959 static void radeon_pm_suspend_old(struct radeon_device *rdev)
 960 {
 961         mutex_lock(&rdev->pm.mutex);
 962         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 963                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
 964                         rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
 965         }
 966         mutex_unlock(&rdev->pm.mutex);
 967
 968         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 969 }
 970
 971 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
 972 {
 973         mutex_lock(&rdev->pm.mutex);
 974         /* disable dpm */
 975         radeon_dpm_disable(rdev);
 976         /* reset the power state */
 977         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
 978         rdev->pm.dpm_enabled = false;
 979         mutex_unlock(&rdev->pm.mutex);
 980 }
 981
 982 void radeon_pm_suspend(struct radeon_device *rdev)
 983 {
 984         if (rdev->pm.pm_method == PM_METHOD_DPM)
 985                 radeon_pm_suspend_dpm(rdev);
 986         else
 987                 radeon_pm_suspend_old(rdev);
 988 }
 989
 990 static void radeon_pm_resume_old(struct radeon_device *rdev)
 991 {
 992         /* set up the default clocks if the MC ucode is loaded */
 993         if ((rdev->family >= CHIP_BARTS) &&
 994             (rdev->family <= CHIP_CAYMAN) &&
 995             rdev->mc_fw) {
 996                 if (rdev->pm.default_vddc)
 997                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 998                                                 SET_VOLTAGE_TYPE_ASIC_VDDC);
 999                 if (rdev->pm.default_vddci)
1000                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1001                                                 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1002                 if (rdev->pm.default_sclk)
1003                         radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1004                 if (rdev->pm.default_mclk)
1005                         radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1006         }
1007         /* asic init will reset the default power state */
1008         mutex_lock(&rdev->pm.mutex);
1009         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1010         rdev->pm.current_clock_mode_index = 0;
1011         rdev->pm.current_sclk = rdev->pm.default_sclk;
1012         rdev->pm.current_mclk = rdev->pm.default_mclk;
1013         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1014         rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1015         if (rdev->pm.pm_method == PM_METHOD_DYNPM
1016             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1017                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1018                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1019                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1020         }
1021         mutex_unlock(&rdev->pm.mutex);
1022         radeon_pm_compute_clocks(rdev);
1023 }
1024
1025 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1026 {
1027         int ret;
1028
1029         /* asic init will reset to the boot state */
1030         mutex_lock(&rdev->pm.mutex);
1031         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1032         radeon_dpm_setup_asic(rdev);
1033         ret = radeon_dpm_enable(rdev);
1034         mutex_unlock(&rdev->pm.mutex);
1035         if (ret) {
1036                 DRM_ERROR("radeon: dpm resume failed\n");
1037                 if ((rdev->family >= CHIP_BARTS) &&
1038                     (rdev->family <= CHIP_CAYMAN) &&
1039                     rdev->mc_fw) {
1040                         if (rdev->pm.default_vddc)
1041                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1042                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
1043                         if (rdev->pm.default_vddci)
1044                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1045                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1046                         if (rdev->pm.default_sclk)
1047                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1048                         if (rdev->pm.default_mclk)
1049                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1050                 }
1051         } else {
1052                 rdev->pm.dpm_enabled = true;
1053                 radeon_pm_compute_clocks(rdev);
1054         }
1055 }
1056
1057 void radeon_pm_resume(struct radeon_device *rdev)
1058 {
1059         if (rdev->pm.pm_method == PM_METHOD_DPM)
1060                 radeon_pm_resume_dpm(rdev);
1061         else
1062                 radeon_pm_resume_old(rdev);
1063 }
1064
1065 static int radeon_pm_init_old(struct radeon_device *rdev)
1066 {
1067         int ret;
1068
1069         rdev->pm.profile = PM_PROFILE_DEFAULT;
1070         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1071         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1072         rdev->pm.dynpm_can_upclock = true;
1073         rdev->pm.dynpm_can_downclock = true;
1074         rdev->pm.default_sclk = rdev->clock.default_sclk;
1075         rdev->pm.default_mclk = rdev->clock.default_mclk;
1076         rdev->pm.current_sclk = rdev->clock.default_sclk;
1077         rdev->pm.current_mclk = rdev->clock.default_mclk;
1078         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1079
1080         if (rdev->bios) {
1081                 if (rdev->is_atom_bios)
1082                         radeon_atombios_get_power_modes(rdev);
1083                 else
1084                         radeon_combios_get_power_modes(rdev);
1085                 radeon_pm_print_states(rdev);
1086                 radeon_pm_init_profile(rdev);
1087                 /* set up the default clocks if the MC ucode is loaded */
1088                 if ((rdev->family >= CHIP_BARTS) &&
1089                     (rdev->family <= CHIP_CAYMAN) &&
1090                     rdev->mc_fw) {
1091                         if (rdev->pm.default_vddc)
1092                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1093                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
1094                         if (rdev->pm.default_vddci)
1095                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1096                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1097                         if (rdev->pm.default_sclk)
1098                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1099                         if (rdev->pm.default_mclk)
1100                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1101                 }
1102         }
1103
1104         /* set up the internal thermal sensor if applicable */
1105         ret = radeon_hwmon_init(rdev);
1106         if (ret)
1107                 return ret;
1108
1109         INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1110
1111         if (rdev->pm.num_power_states > 1) {
1112                 /* where's the best place to put these? */
1113                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1114                 if (ret)
1115                         DRM_ERROR("failed to create device file for power profile\n");
1116                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1117                 if (ret)
1118                         DRM_ERROR("failed to create device file for power method\n");
1119
1120                 if (radeon_debugfs_pm_init(rdev)) {
1121                         DRM_ERROR("Failed to register debugfs file for PM!\n");
1122                 }
1123
1124                 DRM_INFO("radeon: power management initialized\n");
1125         }
1126
1127         return 0;
1128 }
1129
1130 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1131 {
1132         int i;
1133
1134         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1135                 printk("== power state %d ==\n", i);
1136                 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1137         }
1138 }
1139
1140 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1141 {
1142         int ret;
1143
1144         /* default to balanced state */
1145         rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1146         rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1147         rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1148         rdev->pm.default_sclk = rdev->clock.default_sclk;
1149         rdev->pm.default_mclk = rdev->clock.default_mclk;
1150         rdev->pm.current_sclk = rdev->clock.default_sclk;
1151         rdev->pm.current_mclk = rdev->clock.default_mclk;
1152         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1153
1154         if (rdev->bios && rdev->is_atom_bios)
1155                 radeon_atombios_get_power_modes(rdev);
1156         else
1157                 return -EINVAL;
1158
1159         /* set up the internal thermal sensor if applicable */
1160         ret = radeon_hwmon_init(rdev);
1161         if (ret)
1162                 return ret;
1163
1164         INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1165         mutex_lock(&rdev->pm.mutex);
1166         radeon_dpm_init(rdev);
1167         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1168         if (radeon_dpm == 1)
1169                 radeon_dpm_print_power_states(rdev);
1170         radeon_dpm_setup_asic(rdev);
1171         ret = radeon_dpm_enable(rdev);
1172         mutex_unlock(&rdev->pm.mutex);
1173         if (ret) {
1174                 rdev->pm.dpm_enabled = false;
1175                 if ((rdev->family >= CHIP_BARTS) &&
1176                     (rdev->family <= CHIP_CAYMAN) &&
1177                     rdev->mc_fw) {
1178                         if (rdev->pm.default_vddc)
1179                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1180                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
1181                         if (rdev->pm.default_vddci)
1182                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1183                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1184                         if (rdev->pm.default_sclk)
1185                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1186                         if (rdev->pm.default_mclk)
1187                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1188                 }
1189                 DRM_ERROR("radeon: dpm initialization failed\n");
1190                 return ret;
1191         }
1192         rdev->pm.dpm_enabled = true;
1193         radeon_pm_compute_clocks(rdev);
1194
1195         if (rdev->pm.num_power_states > 1) {
1196                 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1197                 if (ret)
1198                         DRM_ERROR("failed to create device file for dpm state\n");
1199                 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1200                 if (ret)
1201                         DRM_ERROR("failed to create device file for dpm state\n");
1202                 /* XXX: these are noops for dpm but are here for backwards compat */
1203                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1204                 if (ret)
1205                         DRM_ERROR("failed to create device file for power profile\n");
1206                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1207                 if (ret)
1208                         DRM_ERROR("failed to create device file for power method\n");
1209
1210                 if (radeon_debugfs_pm_init(rdev)) {
1211                         DRM_ERROR("Failed to register debugfs file for dpm!\n");
1212                 }
1213
1214                 DRM_INFO("radeon: dpm initialized\n");
1215         }
1216
1217         return 0;
1218 }
1219
1220 int radeon_pm_init(struct radeon_device *rdev)
1221 {
1222         /* enable dpm on rv6xx+ */
1223         switch (rdev->family) {
1224         case CHIP_RV610:
1225         case CHIP_RV630:
1226         case CHIP_RV620:
1227         case CHIP_RV635:
1228         case CHIP_RV670:
1229         case CHIP_RS780:
1230         case CHIP_RS880:
1231         case CHIP_CAYMAN:
1232         case CHIP_BONAIRE:
1233         case CHIP_KABINI:
1234         case CHIP_KAVERI:
1235         case CHIP_HAWAII:
1236                 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1237                 if (!rdev->rlc_fw)
1238                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1239                 else if ((rdev->family >= CHIP_RV770) &&
1240                          (!(rdev->flags & RADEON_IS_IGP)) &&
1241                          (!rdev->smc_fw))
1242                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1243                 else if (radeon_dpm == 1)
1244                         rdev->pm.pm_method = PM_METHOD_DPM;
1245                 else
1246                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1247                 break;
1248         case CHIP_RV770:
1249         case CHIP_RV730:
1250         case CHIP_RV710:
1251         case CHIP_RV740:
1252         case CHIP_CEDAR:
1253         case CHIP_REDWOOD:
1254         case CHIP_JUNIPER:
1255         case CHIP_CYPRESS:
1256         case CHIP_HEMLOCK:
1257         case CHIP_PALM:
1258         case CHIP_SUMO:
1259         case CHIP_SUMO2:
1260         case CHIP_BARTS:
1261         case CHIP_TURKS:
1262         case CHIP_CAICOS:
1263         case CHIP_ARUBA:
1264         case CHIP_TAHITI:
1265         case CHIP_PITCAIRN:
1266         case CHIP_VERDE:
1267         case CHIP_OLAND:
1268         case CHIP_HAINAN:
1269                 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1270                 if (!rdev->rlc_fw)
1271                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1272                 else if ((rdev->family >= CHIP_RV770) &&
1273                          (!(rdev->flags & RADEON_IS_IGP)) &&
1274                          (!rdev->smc_fw))
1275                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1276                 else if (radeon_dpm == 0)
1277                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1278                 else
1279                         rdev->pm.pm_method = PM_METHOD_DPM;
1280                 break;
1281         default:
1282                 /* default to profile method */
1283                 rdev->pm.pm_method = PM_METHOD_PROFILE;
1284                 break;
1285         }
1286
1287         if (rdev->pm.pm_method == PM_METHOD_DPM)
1288                 return radeon_pm_init_dpm(rdev);
1289         else
1290                 return radeon_pm_init_old(rdev);
1291 }
1292
1293 static void radeon_pm_fini_old(struct radeon_device *rdev)
1294 {
1295         if (rdev->pm.num_power_states > 1) {
1296                 mutex_lock(&rdev->pm.mutex);
1297                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1298                         rdev->pm.profile = PM_PROFILE_DEFAULT;
1299                         radeon_pm_update_profile(rdev);
1300                         radeon_pm_set_clocks(rdev);
1301                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1302                         /* reset default clocks */
1303                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1304                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1305                         radeon_pm_set_clocks(rdev);
1306                 }
1307                 mutex_unlock(&rdev->pm.mutex);
1308
1309                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1310
1311                 device_remove_file(rdev->dev, &dev_attr_power_profile);
1312                 device_remove_file(rdev->dev, &dev_attr_power_method);
1313         }
1314
1315         if (rdev->pm.power_state)
1316                 kfree(rdev->pm.power_state);
1317 }
1318
1319 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1320 {
1321         if (rdev->pm.num_power_states > 1) {
1322                 mutex_lock(&rdev->pm.mutex);
1323                 radeon_dpm_disable(rdev);
1324                 mutex_unlock(&rdev->pm.mutex);
1325
1326                 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1327                 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1328                 /* XXX backwards compat */
1329                 device_remove_file(rdev->dev, &dev_attr_power_profile);
1330                 device_remove_file(rdev->dev, &dev_attr_power_method);
1331         }
1332         radeon_dpm_fini(rdev);
1333
1334         if (rdev->pm.power_state)
1335                 kfree(rdev->pm.power_state);
1336 }
1337
1338 void radeon_pm_fini(struct radeon_device *rdev)
1339 {
1340         if (rdev->pm.pm_method == PM_METHOD_DPM)
1341                 radeon_pm_fini_dpm(rdev);
1342         else
1343                 radeon_pm_fini_old(rdev);
1344 }
1345
1346 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1347 {
1348         struct drm_device *ddev = rdev->ddev;
1349         struct drm_crtc *crtc;
1350         struct radeon_crtc *radeon_crtc;
1351
1352         if (rdev->pm.num_power_states < 2)
1353                 return;
1354
1355         mutex_lock(&rdev->pm.mutex);
1356
1357         rdev->pm.active_crtcs = 0;
1358         rdev->pm.active_crtc_count = 0;
1359         list_for_each_entry(crtc,
1360                 &ddev->mode_config.crtc_list, head) {
1361                 radeon_crtc = to_radeon_crtc(crtc);
1362                 if (radeon_crtc->enabled) {
1363                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1364                         rdev->pm.active_crtc_count++;
1365                 }
1366         }
1367
1368         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1369                 radeon_pm_update_profile(rdev);
1370                 radeon_pm_set_clocks(rdev);
1371         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1372                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1373                         if (rdev->pm.active_crtc_count > 1) {
1374                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1375                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1376
1377                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1378                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1379                                         radeon_pm_get_dynpm_state(rdev);
1380                                         radeon_pm_set_clocks(rdev);
1381
1382                                         DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1383                                 }
1384                         } else if (rdev->pm.active_crtc_count == 1) {
1385                                 /* TODO: Increase clocks if needed for current mode */
1386
1387                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1388                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1389                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1390                                         radeon_pm_get_dynpm_state(rdev);
1391                                         radeon_pm_set_clocks(rdev);
1392
1393                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1394                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1395                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1396                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1397                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1398                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1399                                         DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1400                                 }
1401                         } else { /* count == 0 */
1402                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1403                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1404
1405                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1406                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1407                                         radeon_pm_get_dynpm_state(rdev);
1408                                         radeon_pm_set_clocks(rdev);
1409                                 }
1410                         }
1411                 }
1412         }
1413
1414         mutex_unlock(&rdev->pm.mutex);
1415 }
1416
1417 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1418 {
1419         struct drm_device *ddev = rdev->ddev;
1420         struct drm_crtc *crtc;
1421         struct radeon_crtc *radeon_crtc;
1422
1423         mutex_lock(&rdev->pm.mutex);
1424
1425         /* update active crtc counts */
1426         rdev->pm.dpm.new_active_crtcs = 0;
1427         rdev->pm.dpm.new_active_crtc_count = 0;
1428         list_for_each_entry(crtc,
1429                 &ddev->mode_config.crtc_list, head) {
1430                 radeon_crtc = to_radeon_crtc(crtc);
1431                 if (crtc->enabled) {
1432                         rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1433                         rdev->pm.dpm.new_active_crtc_count++;
1434                 }
1435         }
1436
1437         /* update battery/ac status */
1438         if (power_supply_is_system_supplied() > 0)
1439                 rdev->pm.dpm.ac_power = true;
1440         else
1441                 rdev->pm.dpm.ac_power = false;
1442
1443         radeon_dpm_change_power_state_locked(rdev);
1444
1445         mutex_unlock(&rdev->pm.mutex);
1446
1447 }
1448
1449 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1450 {
1451         if (rdev->pm.pm_method == PM_METHOD_DPM)
1452                 radeon_pm_compute_clocks_dpm(rdev);
1453         else
1454                 radeon_pm_compute_clocks_old(rdev);
1455 }
1456
1457 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1458 {
1459         int  crtc, vpos, hpos, vbl_status;
1460         bool in_vbl = true;
1461
1462         /* Iterate over all active crtc's. All crtc's must be in vblank,
1463          * otherwise return in_vbl == false.
1464          */
1465         for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1466                 if (rdev->pm.active_crtcs & (1 << crtc)) {
1467                         vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos, NULL, NULL);
1468                         if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1469                             !(vbl_status & DRM_SCANOUTPOS_INVBL))
1470                                 in_vbl = false;
1471                 }
1472         }
1473
1474         return in_vbl;
1475 }
1476
1477 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1478 {
1479         u32 stat_crtc = 0;
1480         bool in_vbl = radeon_pm_in_vbl(rdev);
1481
1482         if (in_vbl == false)
1483                 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1484                          finish ? "exit" : "entry");
1485         return in_vbl;
1486 }
1487
1488 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1489 {
1490         struct radeon_device *rdev;
1491         int resched;
1492         rdev = container_of(work, struct radeon_device,
1493                                 pm.dynpm_idle_work.work);
1494
1495         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1496         mutex_lock(&rdev->pm.mutex);
1497         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1498                 int not_processed = 0;
1499                 int i;
1500
1501                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1502                         struct radeon_ring *ring = &rdev->ring[i];
1503
1504                         if (ring->ready) {
1505                                 not_processed += radeon_fence_count_emitted(rdev, i);
1506                                 if (not_processed >= 3)
1507                                         break;
1508                         }
1509                 }
1510
1511                 if (not_processed >= 3) { /* should upclock */
1512                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1513                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1514                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1515                                    rdev->pm.dynpm_can_upclock) {
1516                                 rdev->pm.dynpm_planned_action =
1517                                         DYNPM_ACTION_UPCLOCK;
1518                                 rdev->pm.dynpm_action_timeout = jiffies +
1519                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1520                         }
1521                 } else if (not_processed == 0) { /* should downclock */
1522                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1523                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1524                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1525                                    rdev->pm.dynpm_can_downclock) {
1526                                 rdev->pm.dynpm_planned_action =
1527                                         DYNPM_ACTION_DOWNCLOCK;
1528                                 rdev->pm.dynpm_action_timeout = jiffies +
1529                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1530                         }
1531                 }
1532
1533                 /* Note, radeon_pm_set_clocks is called with static_switch set
1534                  * to false since we want to wait for vbl to avoid flicker.
1535                  */
1536                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1537                     jiffies > rdev->pm.dynpm_action_timeout) {
1538                         radeon_pm_get_dynpm_state(rdev);
1539                         radeon_pm_set_clocks(rdev);
1540                 }
1541
1542                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1543                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1544         }
1545         mutex_unlock(&rdev->pm.mutex);
1546         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1547 }
1548
1549 /*
1550  * Debugfs info
1551  */
1552 #if defined(CONFIG_DEBUG_FS)
1553
1554 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1555 {
1556         struct drm_info_node *node = (struct drm_info_node *) m->private;
1557         struct drm_device *dev = node->minor->dev;
1558         struct radeon_device *rdev = dev->dev_private;
1559
1560         if (rdev->pm.dpm_enabled) {
1561                 mutex_lock(&rdev->pm.mutex);
1562                 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1563                         radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1564                 else
1565                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1566                 mutex_unlock(&rdev->pm.mutex);
1567         } else {
1568                 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1569                 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1570                 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1571                         seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1572                 else
1573                         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1574                 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1575                 if (rdev->asic->pm.get_memory_clock)
1576                         seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1577                 if (rdev->pm.current_vddc)
1578                         seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1579                 if (rdev->asic->pm.get_pcie_lanes)
1580                         seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1581         }
1582
1583         return 0;
1584 }
1585
1586 static struct drm_info_list radeon_pm_info_list[] = {
1587         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1588 };
1589 #endif
1590
1591 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1592 {
1593 #if defined(CONFIG_DEBUG_FS)
1594         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1595 #else
1596         return 0;
1597 #endif
1598 }