drivers/gpu/drm/radeon/radeon_fence.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Dave Airlie
  30  */
  31 #include <linux/seq_file.h>
  32 #include <linux/atomic.h>
  33 #include <linux/wait.h>
  34 #include <linux/kref.h>
  35 #include <linux/slab.h>
  36 #include <linux/firmware.h>
  37 #include <drm/drmP.h>
  38 #include "radeon_reg.h"
  39 #include "radeon.h"
  40 #include "radeon_trace.h"
  41
  42 /*
  43  * Fences
  44  * Fences mark an event in the GPUs pipeline and are used
  45  * for GPU/CPU synchronization.  When the fence is written,
  46  * it is expected that all buffers associated with that fence
  47  * are no longer in use by the associated ring on the GPU and
  48  * that the the relevant GPU caches have been flushed.  Whether
  49  * we use a scratch register or memory location depends on the asic
  50  * and whether writeback is enabled.
  51  */
  52
  53 /**
  54  * radeon_fence_write - write a fence value
  55  *
  56  * @rdev: radeon_device pointer
  57  * @seq: sequence number to write
  58  * @ring: ring index the fence is associated with
  59  *
  60  * Writes a fence value to memory or a scratch register (all asics).
  61  */
  62 static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
  63 {
  64         struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
  65         if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
  66                 if (drv->cpu_addr) {
  67                         *drv->cpu_addr = cpu_to_le32(seq);
  68                 }
  69         } else {
  70                 WREG32(drv->scratch_reg, seq);
  71         }
  72 }
  73
  74 /**
  75  * radeon_fence_read - read a fence value
  76  *
  77  * @rdev: radeon_device pointer
  78  * @ring: ring index the fence is associated with
  79  *
  80  * Reads a fence value from memory or a scratch register (all asics).
  81  * Returns the value of the fence read from memory or register.
  82  */
  83 static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
  84 {
  85         struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
  86         u32 seq = 0;
  87
  88         if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
  89                 if (drv->cpu_addr) {
  90                         seq = le32_to_cpu(*drv->cpu_addr);
  91                 } else {
  92                         seq = lower_32_bits(atomic64_read(&drv->last_seq));
  93                 }
  94         } else {
  95                 seq = RREG32(drv->scratch_reg);
  96         }
  97         return seq;
  98 }
  99
 100 /**
 101  * radeon_fence_emit - emit a fence on the requested ring
 102  *
 103  * @rdev: radeon_device pointer
 104  * @fence: radeon fence object
 105  * @ring: ring index the fence is associated with
 106  *
 107  * Emits a fence command on the requested ring (all asics).
 108  * Returns 0 on success, -ENOMEM on failure.
 109  */
 110 int radeon_fence_emit(struct radeon_device *rdev,
 111                       struct radeon_fence **fence,
 112                       int ring)
 113 {
 114         /* we are protected by the ring emission mutex */
 115         *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
 116         if ((*fence) == NULL) {
 117                 return -ENOMEM;
 118         }
 119         kref_init(&((*fence)->kref));
 120         (*fence)->rdev = rdev;
 121         (*fence)->seq = ++rdev->fence_drv[ring].sync_seq[ring];
 122         (*fence)->ring = ring;
 123         radeon_fence_ring_emit(rdev, ring, *fence);
 124         trace_radeon_fence_emit(rdev->ddev, (*fence)->seq);
 125         return 0;
 126 }
 127
 128 /**
 129  * radeon_fence_process - process a fence
 130  *
 131  * @rdev: radeon_device pointer
 132  * @ring: ring index the fence is associated with
 133  *
 134  * Checks the current fence value and wakes the fence queue
 135  * if the sequence number has increased (all asics).
 136  */
 137 void radeon_fence_process(struct radeon_device *rdev, int ring)
 138 {
 139         uint64_t seq, last_seq, last_emitted;
 140         unsigned count_loop = 0;
 141         bool wake = false;
 142
 143         /* Note there is a scenario here for an infinite loop but it's
 144          * very unlikely to happen. For it to happen, the current polling
 145          * process need to be interrupted by another process and another
 146          * process needs to update the last_seq btw the atomic read and
 147          * xchg of the current process.
 148          *
 149          * More over for this to go in infinite loop there need to be
 150          * continuously new fence signaled ie radeon_fence_read needs
 151          * to return a different value each time for both the currently
 152          * polling process and the other process that xchg the last_seq
 153          * btw atomic read and xchg of the current process. And the
 154          * value the other process set as last seq must be higher than
 155          * the seq value we just read. Which means that current process
 156          * need to be interrupted after radeon_fence_read and before
 157          * atomic xchg.
 158          *
 159          * To be even more safe we count the number of time we loop and
 160          * we bail after 10 loop just accepting the fact that we might
 161          * have temporarly set the last_seq not to the true real last
 162          * seq but to an older one.
 163          */
 164         last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
 165         do {
 166                 last_emitted = rdev->fence_drv[ring].sync_seq[ring];
 167                 seq = radeon_fence_read(rdev, ring);
 168                 seq |= last_seq & 0xffffffff00000000LL;
 169                 if (seq < last_seq) {
 170                         seq &= 0xffffffff;
 171                         seq |= last_emitted & 0xffffffff00000000LL;
 172                 }
 173
 174                 if (seq <= last_seq || seq > last_emitted) {
 175                         break;
 176                 }
 177                 /* If we loop over we don't want to return without
 178                  * checking if a fence is signaled as it means that the
 179                  * seq we just read is different from the previous on.
 180                  */
 181                 wake = true;
 182                 last_seq = seq;
 183                 if ((count_loop++) > 10) {
 184                         /* We looped over too many time leave with the
 185                          * fact that we might have set an older fence
 186                          * seq then the current real last seq as signaled
 187                          * by the hw.
 188                          */
 189                         break;
 190                 }
 191         } while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);
 192
 193         if (wake)
 194                 wake_up_all(&rdev->fence_queue);
 195 }
 196
 197 /**
 198  * radeon_fence_destroy - destroy a fence
 199  *
 200  * @kref: fence kref
 201  *
 202  * Frees the fence object (all asics).
 203  */
 204 static void radeon_fence_destroy(struct kref *kref)
 205 {
 206         struct radeon_fence *fence;
 207
 208         fence = container_of(kref, struct radeon_fence, kref);
 209         kfree(fence);
 210 }
 211
 212 /**
 213  * radeon_fence_seq_signaled - check if a fence sequence number has signaled
 214  *
 215  * @rdev: radeon device pointer
 216  * @seq: sequence number
 217  * @ring: ring index the fence is associated with
 218  *
 219  * Check if the last signaled fence sequnce number is >= the requested
 220  * sequence number (all asics).
 221  * Returns true if the fence has signaled (current fence value
 222  * is >= requested value) or false if it has not (current fence
 223  * value is < the requested value.  Helper function for
 224  * radeon_fence_signaled().
 225  */
 226 static bool radeon_fence_seq_signaled(struct radeon_device *rdev,
 227                                       u64 seq, unsigned ring)
 228 {
 229         if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
 230                 return true;
 231         }
 232         /* poll new last sequence at least once */
 233         radeon_fence_process(rdev, ring);
 234         if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
 235                 return true;
 236         }
 237         return false;
 238 }
 239
 240 /**
 241  * radeon_fence_signaled - check if a fence has signaled
 242  *
 243  * @fence: radeon fence object
 244  *
 245  * Check if the requested fence has signaled (all asics).
 246  * Returns true if the fence has signaled or false if it has not.
 247  */
 248 bool radeon_fence_signaled(struct radeon_fence *fence)
 249 {
 250         if (!fence) {
 251                 return true;
 252         }
 253         if (fence->seq == RADEON_FENCE_SIGNALED_SEQ) {
 254                 return true;
 255         }
 256         if (radeon_fence_seq_signaled(fence->rdev, fence->seq, fence->ring)) {
 257                 fence->seq = RADEON_FENCE_SIGNALED_SEQ;
 258                 return true;
 259         }
 260         return false;
 261 }
 262
 263 /**
 264  * radeon_fence_any_seq_signaled - check if any sequence number is signaled
 265  *
 266  * @rdev: radeon device pointer
 267  * @seq: sequence numbers
 268  *
 269  * Check if the last signaled fence sequnce number is >= the requested
 270  * sequence number (all asics).
 271  * Returns true if any has signaled (current value is >= requested value)
 272  * or false if it has not. Helper function for radeon_fence_wait_seq.
 273  */
 274 static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)
 275 {
 276         unsigned i;
 277
 278         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 279                 if (seq[i] && radeon_fence_seq_signaled(rdev, seq[i], i))
 280                         return true;
 281         }
 282         return false;
 283 }
 284
 285 /**
 286  * radeon_fence_wait_seq - wait for a specific sequence numbers
 287  *
 288  * @rdev: radeon device pointer
 289  * @target_seq: sequence number(s) we want to wait for
 290  * @intr: use interruptable sleep
 291  * @lock_ring: whether the ring should be locked or not
 292  *
 293  * Wait for the requested sequence number(s) to be written by any ring
 294  * (all asics).  Sequnce number array is indexed by ring id.
 295  * @intr selects whether to use interruptable (true) or non-interruptable
 296  * (false) sleep when waiting for the sequence number.  Helper function
 297  * for radeon_fence_wait_*().
 298  * Returns 0 if the sequence number has passed, error for all other cases.
 299  * -EDEADLK is returned when a GPU lockup has been detected.
 300  */
 301 static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 *target_seq,
 302                                  bool intr, bool lock_ring)
 303 {
 304         uint64_t last_seq[RADEON_NUM_RINGS];
 305         bool signaled;
 306         int i, r;
 307
 308         while (!radeon_fence_any_seq_signaled(rdev, target_seq)) {
 309
 310                 /* Save current sequence values, used to check for GPU lockups */
 311                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 312                         if (!target_seq[i])
 313                                 continue;
 314
 315                         last_seq[i] = atomic64_read(&rdev->fence_drv[i].last_seq);
 316                         trace_radeon_fence_wait_begin(rdev->ddev, target_seq[i]);
 317                         radeon_irq_kms_sw_irq_get(rdev, i);
 318                 }
 319
 320                 if (intr) {
 321                         r = wait_event_interruptible_timeout(rdev->fence_queue, (
 322                                 (signaled = radeon_fence_any_seq_signaled(rdev, target_seq))
 323                                  || rdev->needs_reset), RADEON_FENCE_JIFFIES_TIMEOUT);
 324                 } else {
 325                         r = wait_event_timeout(rdev->fence_queue, (
 326                                 (signaled = radeon_fence_any_seq_signaled(rdev, target_seq))
 327                                  || rdev->needs_reset), RADEON_FENCE_JIFFIES_TIMEOUT);
 328                 }
 329
 330                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 331                         if (!target_seq[i])
 332                                 continue;
 333
 334                         radeon_irq_kms_sw_irq_put(rdev, i);
 335                         trace_radeon_fence_wait_end(rdev->ddev, target_seq[i]);
 336                 }
 337
 338                 if (unlikely(r < 0))
 339                         return r;
 340
 341                 if (unlikely(!signaled)) {
 342                         if (rdev->needs_reset)
 343                                 return -EDEADLK;
 344
 345                         /* we were interrupted for some reason and fence
 346                          * isn't signaled yet, resume waiting */
 347                         if (r)
 348                                 continue;
 349
 350                         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 351                                 if (!target_seq[i])
 352                                         continue;
 353
 354                                 if (last_seq[i] != atomic64_read(&rdev->fence_drv[i].last_seq))
 355                                         break;
 356                         }
 357
 358                         if (i != RADEON_NUM_RINGS)
 359                                 continue;
 360
 361                         if (lock_ring)
 362                                 mutex_lock(&rdev->ring_lock);
 363
 364                         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 365                                 if (!target_seq[i])
 366                                         continue;
 367
 368                                 if (radeon_ring_is_lockup(rdev, i, &rdev->ring[i]))
 369                                         break;
 370                         }
 371
 372                         if (i < RADEON_NUM_RINGS) {
 373                                 /* good news we believe it's a lockup */
 374                                 dev_warn(rdev->dev, "GPU lockup (waiting for "
 375                                          "0x%016llx last fence id 0x%016llx on"
 376                                          " ring %d)\n",
 377                                          target_seq[i], last_seq[i], i);
 378
 379                                 /* remember that we need an reset */
 380                                 rdev->needs_reset = true;
 381                                 if (lock_ring)
 382                                         mutex_unlock(&rdev->ring_lock);
 383                                 wake_up_all(&rdev->fence_queue);
 384                                 return -EDEADLK;
 385                         }
 386
 387                         if (lock_ring)
 388                                 mutex_unlock(&rdev->ring_lock);
 389                 }
 390         }
 391         return 0;
 392 }
 393
 394 /**
 395  * radeon_fence_wait - wait for a fence to signal
 396  *
 397  * @fence: radeon fence object
 398  * @intr: use interruptable sleep
 399  *
 400  * Wait for the requested fence to signal (all asics).
 401  * @intr selects whether to use interruptable (true) or non-interruptable
 402  * (false) sleep when waiting for the fence.
 403  * Returns 0 if the fence has passed, error for all other cases.
 404  */
 405 int radeon_fence_wait(struct radeon_fence *fence, bool intr)
 406 {
 407         uint64_t seq[RADEON_NUM_RINGS] = {};
 408         int r;
 409
 410         if (fence == NULL) {
 411                 WARN(1, "Querying an invalid fence : %p !\n", fence);
 412                 return -EINVAL;
 413         }
 414
 415         seq[fence->ring] = fence->seq;
 416         if (seq[fence->ring] == RADEON_FENCE_SIGNALED_SEQ)
 417                 return 0;
 418
 419         r = radeon_fence_wait_seq(fence->rdev, seq, intr, true);
 420         if (r)
 421                 return r;
 422
 423         fence->seq = RADEON_FENCE_SIGNALED_SEQ;
 424         return 0;
 425 }
 426
 427 /**
 428  * radeon_fence_wait_any - wait for a fence to signal on any ring
 429  *
 430  * @rdev: radeon device pointer
 431  * @fences: radeon fence object(s)
 432  * @intr: use interruptable sleep
 433  *
 434  * Wait for any requested fence to signal (all asics).  Fence
 435  * array is indexed by ring id.  @intr selects whether to use
 436  * interruptable (true) or non-interruptable (false) sleep when
 437  * waiting for the fences. Used by the suballocator.
 438  * Returns 0 if any fence has passed, error for all other cases.
 439  */
 440 int radeon_fence_wait_any(struct radeon_device *rdev,
 441                           struct radeon_fence **fences,
 442                           bool intr)
 443 {
 444         uint64_t seq[RADEON_NUM_RINGS];
 445         unsigned i, num_rings = 0;
 446         int r;
 447
 448         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 449                 seq[i] = 0;
 450
 451                 if (!fences[i]) {
 452                         continue;
 453                 }
 454
 455                 seq[i] = fences[i]->seq;
 456                 ++num_rings;
 457
 458                 /* test if something was allready signaled */
 459                 if (seq[i] == RADEON_FENCE_SIGNALED_SEQ)
 460                         return 0;
 461         }
 462
 463         /* nothing to wait for ? */
 464         if (num_rings == 0)
 465                 return -ENOENT;
 466
 467         r = radeon_fence_wait_seq(rdev, seq, intr, true);
 468         if (r) {
 469                 return r;
 470         }
 471         return 0;
 472 }
 473
 474 /**
 475  * radeon_fence_wait_locked - wait for a fence to signal
 476  *
 477  * @fence: radeon fence object
 478  *
 479  * Wait for the requested fence to signal (all asics).
 480  * Returns 0 if the fence has passed, error for all other cases.
 481  */
 482 int radeon_fence_wait_locked(struct radeon_fence *fence)
 483 {
 484         uint64_t seq[RADEON_NUM_RINGS] = {};
 485         int r;
 486
 487         if (fence == NULL) {
 488                 WARN(1, "Querying an invalid fence : %p !\n", fence);
 489                 return -EINVAL;
 490         }
 491
 492         seq[fence->ring] = fence->seq;
 493         if (seq[fence->ring] == RADEON_FENCE_SIGNALED_SEQ)
 494                 return 0;
 495
 496         r = radeon_fence_wait_seq(fence->rdev, seq, false, false);
 497         if (r)
 498                 return r;
 499
 500         fence->seq = RADEON_FENCE_SIGNALED_SEQ;
 501         return 0;
 502 }
 503
 504 /**
 505  * radeon_fence_wait_next_locked - wait for the next fence to signal
 506  *
 507  * @rdev: radeon device pointer
 508  * @ring: ring index the fence is associated with
 509  *
 510  * Wait for the next fence on the requested ring to signal (all asics).
 511  * Returns 0 if the next fence has passed, error for all other cases.
 512  * Caller must hold ring lock.
 513  */
 514 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring)
 515 {
 516         uint64_t seq[RADEON_NUM_RINGS] = {};
 517
 518         seq[ring] = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL;
 519         if (seq[ring] >= rdev->fence_drv[ring].sync_seq[ring]) {
 520                 /* nothing to wait for, last_seq is
 521                    already the last emited fence */
 522                 return -ENOENT;
 523         }
 524         return radeon_fence_wait_seq(rdev, seq, false, false);
 525 }
 526
 527 /**
 528  * radeon_fence_wait_empty_locked - wait for all fences to signal
 529  *
 530  * @rdev: radeon device pointer
 531  * @ring: ring index the fence is associated with
 532  *
 533  * Wait for all fences on the requested ring to signal (all asics).
 534  * Returns 0 if the fences have passed, error for all other cases.
 535  * Caller must hold ring lock.
 536  */
 537 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring)
 538 {
 539         uint64_t seq[RADEON_NUM_RINGS] = {};
 540         int r;
 541
 542         seq[ring] = rdev->fence_drv[ring].sync_seq[ring];
 543         if (!seq[ring])
 544                 return 0;
 545
 546         r = radeon_fence_wait_seq(rdev, seq, false, false);
 547         if (r) {
 548                 if (r == -EDEADLK)
 549                         return -EDEADLK;
 550
 551                 dev_err(rdev->dev, "error waiting for ring[%d] to become idle (%d)\n",
 552                         ring, r);
 553         }
 554         return 0;
 555 }
 556
 557 /**
 558  * radeon_fence_ref - take a ref on a fence
 559  *
 560  * @fence: radeon fence object
 561  *
 562  * Take a reference on a fence (all asics).
 563  * Returns the fence.
 564  */
 565 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
 566 {
 567         kref_get(&fence->kref);
 568         return fence;
 569 }
 570
 571 /**
 572  * radeon_fence_unref - remove a ref on a fence
 573  *
 574  * @fence: radeon fence object
 575  *
 576  * Remove a reference on a fence (all asics).
 577  */
 578 void radeon_fence_unref(struct radeon_fence **fence)
 579 {
 580         struct radeon_fence *tmp = *fence;
 581
 582         *fence = NULL;
 583         if (tmp) {
 584                 kref_put(&tmp->kref, radeon_fence_destroy);
 585         }
 586 }
 587
 588 /**
 589  * radeon_fence_count_emitted - get the count of emitted fences
 590  *
 591  * @rdev: radeon device pointer
 592  * @ring: ring index the fence is associated with
 593  *
 594  * Get the number of fences emitted on the requested ring (all asics).
 595  * Returns the number of emitted fences on the ring.  Used by the
 596  * dynpm code to ring track activity.
 597  */
 598 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring)
 599 {
 600         uint64_t emitted;
 601
 602         /* We are not protected by ring lock when reading the last sequence
 603          * but it's ok to report slightly wrong fence count here.
 604          */
 605         radeon_fence_process(rdev, ring);
 606         emitted = rdev->fence_drv[ring].sync_seq[ring]
 607                 - atomic64_read(&rdev->fence_drv[ring].last_seq);
 608         /* to avoid 32bits warp around */
 609         if (emitted > 0x10000000) {
 610                 emitted = 0x10000000;
 611         }
 612         return (unsigned)emitted;
 613 }
 614
 615 /**
 616  * radeon_fence_need_sync - do we need a semaphore
 617  *
 618  * @fence: radeon fence object
 619  * @dst_ring: which ring to check against
 620  *
 621  * Check if the fence needs to be synced against another ring
 622  * (all asics).  If so, we need to emit a semaphore.
 623  * Returns true if we need to sync with another ring, false if
 624  * not.
 625  */
 626 bool radeon_fence_need_sync(struct radeon_fence *fence, int dst_ring)
 627 {
 628         struct radeon_fence_driver *fdrv;
 629
 630         if (!fence) {
 631                 return false;
 632         }
 633
 634         if (fence->ring == dst_ring) {
 635                 return false;
 636         }
 637
 638         /* we are protected by the ring mutex */
 639         fdrv = &fence->rdev->fence_drv[dst_ring];
 640         if (fence->seq <= fdrv->sync_seq[fence->ring]) {
 641                 return false;
 642         }
 643
 644         return true;
 645 }
 646
 647 /**
 648  * radeon_fence_note_sync - record the sync point
 649  *
 650  * @fence: radeon fence object
 651  * @dst_ring: which ring to check against
 652  *
 653  * Note the sequence number at which point the fence will
 654  * be synced with the requested ring (all asics).
 655  */
 656 void radeon_fence_note_sync(struct radeon_fence *fence, int dst_ring)
 657 {
 658         struct radeon_fence_driver *dst, *src;
 659         unsigned i;
 660
 661         if (!fence) {
 662                 return;
 663         }
 664
 665         if (fence->ring == dst_ring) {
 666                 return;
 667         }
 668
 669         /* we are protected by the ring mutex */
 670         src = &fence->rdev->fence_drv[fence->ring];
 671         dst = &fence->rdev->fence_drv[dst_ring];
 672         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 673                 if (i == dst_ring) {
 674                         continue;
 675                 }
 676                 dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
 677         }
 678 }
 679
 680 /**
 681  * radeon_fence_driver_start_ring - make the fence driver
 682  * ready for use on the requested ring.
 683  *
 684  * @rdev: radeon device pointer
 685  * @ring: ring index to start the fence driver on
 686  *
 687  * Make the fence driver ready for processing (all asics).
 688  * Not all asics have all rings, so each asic will only
 689  * start the fence driver on the rings it has.
 690  * Returns 0 for success, errors for failure.
 691  */
 692 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
 693 {
 694         uint64_t index;
 695         int r;
 696
 697         radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
 698         if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) {
 699                 rdev->fence_drv[ring].scratch_reg = 0;
 700                 if (ring != R600_RING_TYPE_UVD_INDEX) {
 701                         index = R600_WB_EVENT_OFFSET + ring * 4;
 702                         rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
 703                         rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr +
 704                                                          index;
 705
 706                 } else {
 707                         /* put fence directly behind firmware */
 708                         index = ALIGN(rdev->uvd_fw->size, 8);
 709                         rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index;
 710                         rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index;
 711                 }
 712
 713         } else {
 714                 r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
 715                 if (r) {
 716                         dev_err(rdev->dev, "fence failed to get scratch register\n");
 717                         return r;
 718                 }
 719                 index = RADEON_WB_SCRATCH_OFFSET +
 720                         rdev->fence_drv[ring].scratch_reg -
 721                         rdev->scratch.reg_base;
 722                 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
 723                 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
 724         }
 725         radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring);
 726         rdev->fence_drv[ring].initialized = true;
 727         dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx and cpu addr 0x%p\n",
 728                  ring, rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr);
 729         return 0;
 730 }
 731
 732 /**
 733  * radeon_fence_driver_init_ring - init the fence driver
 734  * for the requested ring.
 735  *
 736  * @rdev: radeon device pointer
 737  * @ring: ring index to start the fence driver on
 738  *
 739  * Init the fence driver for the requested ring (all asics).
 740  * Helper function for radeon_fence_driver_init().
 741  */
 742 static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
 743 {
 744         int i;
 745
 746         rdev->fence_drv[ring].scratch_reg = -1;
 747         rdev->fence_drv[ring].cpu_addr = NULL;
 748         rdev->fence_drv[ring].gpu_addr = 0;
 749         for (i = 0; i < RADEON_NUM_RINGS; ++i)
 750                 rdev->fence_drv[ring].sync_seq[i] = 0;
 751         atomic64_set(&rdev->fence_drv[ring].last_seq, 0);
 752         rdev->fence_drv[ring].initialized = false;
 753 }
 754
 755 /**
 756  * radeon_fence_driver_init - init the fence driver
 757  * for all possible rings.
 758  *
 759  * @rdev: radeon device pointer
 760  *
 761  * Init the fence driver for all possible rings (all asics).
 762  * Not all asics have all rings, so each asic will only
 763  * start the fence driver on the rings it has using
 764  * radeon_fence_driver_start_ring().
 765  * Returns 0 for success.
 766  */
 767 int radeon_fence_driver_init(struct radeon_device *rdev)
 768 {
 769         int ring;
 770
 771         init_waitqueue_head(&rdev->fence_queue);
 772         for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
 773                 radeon_fence_driver_init_ring(rdev, ring);
 774         }
 775         if (radeon_debugfs_fence_init(rdev)) {
 776                 dev_err(rdev->dev, "fence debugfs file creation failed\n");
 777         }
 778         return 0;
 779 }
 780
 781 /**
 782  * radeon_fence_driver_fini - tear down the fence driver
 783  * for all possible rings.
 784  *
 785  * @rdev: radeon device pointer
 786  *
 787  * Tear down the fence driver for all possible rings (all asics).
 788  */
 789 void radeon_fence_driver_fini(struct radeon_device *rdev)
 790 {
 791         int ring, r;
 792
 793         mutex_lock(&rdev->ring_lock);
 794         for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
 795                 if (!rdev->fence_drv[ring].initialized)
 796                         continue;
 797                 r = radeon_fence_wait_empty_locked(rdev, ring);
 798                 if (r) {
 799                         /* no need to trigger GPU reset as we are unloading */
 800                         radeon_fence_driver_force_completion(rdev);
 801                 }
 802                 wake_up_all(&rdev->fence_queue);
 803                 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
 804                 rdev->fence_drv[ring].initialized = false;
 805         }
 806         mutex_unlock(&rdev->ring_lock);
 807 }
 808
 809 /**
 810  * radeon_fence_driver_force_completion - force all fence waiter to complete
 811  *
 812  * @rdev: radeon device pointer
 813  *
 814  * In case of GPU reset failure make sure no process keep waiting on fence
 815  * that will never complete.
 816  */
 817 void radeon_fence_driver_force_completion(struct radeon_device *rdev)
 818 {
 819         int ring;
 820
 821         for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
 822                 if (!rdev->fence_drv[ring].initialized)
 823                         continue;
 824                 radeon_fence_write(rdev, rdev->fence_drv[ring].sync_seq[ring], ring);
 825         }
 826 }
 827
 828
 829 /*
 830  * Fence debugfs
 831  */
 832 #if defined(CONFIG_DEBUG_FS)
 833 static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
 834 {
 835         struct drm_info_node *node = (struct drm_info_node *)m->private;
 836         struct drm_device *dev = node->minor->dev;
 837         struct radeon_device *rdev = dev->dev_private;
 838         int i, j;
 839
 840         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 841                 if (!rdev->fence_drv[i].initialized)
 842                         continue;
 843
 844                 seq_printf(m, "--- ring %d ---\n", i);
 845                 seq_printf(m, "Last signaled fence 0x%016llx\n",
 846                            (unsigned long long)atomic64_read(&rdev->fence_drv[i].last_seq));
 847                 seq_printf(m, "Last emitted        0x%016llx\n",
 848                            rdev->fence_drv[i].sync_seq[i]);
 849
 850                 for (j = 0; j < RADEON_NUM_RINGS; ++j) {
 851                         if (i != j && rdev->fence_drv[j].initialized)
 852                                 seq_printf(m, "Last sync to ring %d 0x%016llx\n",
 853                                            j, rdev->fence_drv[i].sync_seq[j]);
 854                 }
 855         }
 856         return 0;
 857 }
 858
 859 static struct drm_info_list radeon_debugfs_fence_list[] = {
 860         {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
 861 };
 862 #endif
 863
 864 int radeon_debugfs_fence_init(struct radeon_device *rdev)
 865 {
 866 #if defined(CONFIG_DEBUG_FS)
 867         return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
 868 #else
 869         return 0;
 870 #endif
 871 }