drivers/gpu/drm/radeon/r300.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include <drm/radeon_drm.h>
  37 #include "r100_track.h"
  38 #include "r300d.h"
  39 #include "rv350d.h"
  40 #include "r300_reg_safe.h"
  41
  42 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
  43  *
  44  * GPU Errata:
  45  * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
  46  *   using MMIO to flush host path read cache, this lead to HARDLOCKUP.
  47  *   However, scheduling such write to the ring seems harmless, i suspect
  48  *   the CP read collide with the flush somehow, or maybe the MC, hard to
  49  *   tell. (Jerome Glisse)
  50  */
  51
  52 /*
  53  * rv370,rv380 PCIE GART
  54  */
  55 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
  56
  57 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
  58 {
  59         uint32_t tmp;
  60         int i;
  61
  62         /* Workaround HW bug do flush 2 times */
  63         for (i = 0; i < 2; i++) {
  64                 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  65                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
  66                 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  67                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
  68         }
  69         mb();
  70 }
  71
  72 #define R300_PTE_UNSNOOPED (1 << 0)
  73 #define R300_PTE_WRITEABLE (1 << 2)
  74 #define R300_PTE_READABLE  (1 << 3)
  75
  76 uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags)
  77 {
  78         addr = (lower_32_bits(addr) >> 8) |
  79                 ((upper_32_bits(addr) & 0xff) << 24);
  80         if (flags & RADEON_GART_PAGE_READ)
  81                 addr |= R300_PTE_READABLE;
  82         if (flags & RADEON_GART_PAGE_WRITE)
  83                 addr |= R300_PTE_WRITEABLE;
  84         if (!(flags & RADEON_GART_PAGE_SNOOP))
  85                 addr |= R300_PTE_UNSNOOPED;
  86         return addr;
  87 }
  88
  89 void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
  90                               uint64_t entry)
  91 {
  92         void __iomem *ptr = rdev->gart.ptr;
  93
  94         /* on x86 we want this to be CPU endian, on powerpc
  95          * on powerpc without HW swappers, it'll get swapped on way
  96          * into VRAM - so no need for cpu_to_le32 on VRAM tables */
  97         writel(entry, ((void __iomem *)ptr) + (i * 4));
  98 }
  99
 100 int rv370_pcie_gart_init(struct radeon_device *rdev)
 101 {
 102         int r;
 103
 104         if (rdev->gart.robj) {
 105                 WARN(1, "RV370 PCIE GART already initialized\n");
 106                 return 0;
 107         }
 108         /* Initialize common gart structure */
 109         r = radeon_gart_init(rdev);
 110         if (r)
 111                 return r;
 112         r = rv370_debugfs_pcie_gart_info_init(rdev);
 113         if (r)
 114                 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
 115         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 116         rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 117         rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
 118         rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 119         return radeon_gart_table_vram_alloc(rdev);
 120 }
 121
 122 int rv370_pcie_gart_enable(struct radeon_device *rdev)
 123 {
 124         uint32_t table_addr;
 125         uint32_t tmp;
 126         int r;
 127
 128         if (rdev->gart.robj == NULL) {
 129                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 130                 return -EINVAL;
 131         }
 132         r = radeon_gart_table_vram_pin(rdev);
 133         if (r)
 134                 return r;
 135         /* discard memory request outside of configured range */
 136         tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 137         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 138         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
 139         tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
 140         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
 141         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
 142         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
 143         table_addr = rdev->gart.table_addr;
 144         WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
 145         /* FIXME: setup default page */
 146         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
 147         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
 148         /* Clear error */
 149         WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
 150         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 151         tmp |= RADEON_PCIE_TX_GART_EN;
 152         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 153         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 154         rv370_pcie_gart_tlb_flush(rdev);
 155         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 156                  (unsigned)(rdev->mc.gtt_size >> 20),
 157                  (unsigned long long)table_addr);
 158         rdev->gart.ready = true;
 159         return 0;
 160 }
 161
 162 void rv370_pcie_gart_disable(struct radeon_device *rdev)
 163 {
 164         u32 tmp;
 165
 166         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
 167         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
 168         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
 169         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
 170         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 171         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 172         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
 173         radeon_gart_table_vram_unpin(rdev);
 174 }
 175
 176 void rv370_pcie_gart_fini(struct radeon_device *rdev)
 177 {
 178         radeon_gart_fini(rdev);
 179         rv370_pcie_gart_disable(rdev);
 180         radeon_gart_table_vram_free(rdev);
 181 }
 182
 183 void r300_fence_ring_emit(struct radeon_device *rdev,
 184                           struct radeon_fence *fence)
 185 {
 186         struct radeon_ring *ring = &rdev->ring[fence->ring];
 187
 188         /* Who ever call radeon_fence_emit should call ring_lock and ask
 189          * for enough space (today caller are ib schedule and buffer move) */
 190         /* Write SC register so SC & US assert idle */
 191         radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));
 192         radeon_ring_write(ring, 0);
 193         radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));
 194         radeon_ring_write(ring, 0);
 195         /* Flush 3D cache */
 196         radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 197         radeon_ring_write(ring, R300_RB3D_DC_FLUSH);
 198         radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 199         radeon_ring_write(ring, R300_ZC_FLUSH);
 200         /* Wait until IDLE & CLEAN */
 201         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 202         radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN |
 203                                  RADEON_WAIT_2D_IDLECLEAN |
 204                                  RADEON_WAIT_DMA_GUI_IDLE));
 205         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 206         radeon_ring_write(ring, rdev->config.r300.hdp_cntl |
 207                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 208         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 209         radeon_ring_write(ring, rdev->config.r300.hdp_cntl);
 210         /* Emit fence sequence & fire IRQ */
 211         radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
 212         radeon_ring_write(ring, fence->seq);
 213         radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
 214         radeon_ring_write(ring, RADEON_SW_INT_FIRE);
 215 }
 216
 217 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
 218 {
 219         unsigned gb_tile_config;
 220         int r;
 221
 222         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
 223         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 224         switch(rdev->num_gb_pipes) {
 225         case 2:
 226                 gb_tile_config |= R300_PIPE_COUNT_R300;
 227                 break;
 228         case 3:
 229                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 230                 break;
 231         case 4:
 232                 gb_tile_config |= R300_PIPE_COUNT_R420;
 233                 break;
 234         case 1:
 235         default:
 236                 gb_tile_config |= R300_PIPE_COUNT_RV350;
 237                 break;
 238         }
 239
 240         r = radeon_ring_lock(rdev, ring, 64);
 241         if (r) {
 242                 return;
 243         }
 244         radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
 245         radeon_ring_write(ring,
 246                           RADEON_ISYNC_ANY2D_IDLE3D |
 247                           RADEON_ISYNC_ANY3D_IDLE2D |
 248                           RADEON_ISYNC_WAIT_IDLEGUI |
 249                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 250         radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0));
 251         radeon_ring_write(ring, gb_tile_config);
 252         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 253         radeon_ring_write(ring,
 254                           RADEON_WAIT_2D_IDLECLEAN |
 255                           RADEON_WAIT_3D_IDLECLEAN);
 256         radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
 257         radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
 258         radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0));
 259         radeon_ring_write(ring, 0);
 260         radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0));
 261         radeon_ring_write(ring, 0);
 262         radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 263         radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 264         radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 265         radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
 266         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 267         radeon_ring_write(ring,
 268                           RADEON_WAIT_2D_IDLECLEAN |
 269                           RADEON_WAIT_3D_IDLECLEAN);
 270         radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0));
 271         radeon_ring_write(ring, 0);
 272         radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 273         radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 274         radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 275         radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
 276         radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0));
 277         radeon_ring_write(ring,
 278                           ((6 << R300_MS_X0_SHIFT) |
 279                            (6 << R300_MS_Y0_SHIFT) |
 280                            (6 << R300_MS_X1_SHIFT) |
 281                            (6 << R300_MS_Y1_SHIFT) |
 282                            (6 << R300_MS_X2_SHIFT) |
 283                            (6 << R300_MS_Y2_SHIFT) |
 284                            (6 << R300_MSBD0_Y_SHIFT) |
 285                            (6 << R300_MSBD0_X_SHIFT)));
 286         radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0));
 287         radeon_ring_write(ring,
 288                           ((6 << R300_MS_X3_SHIFT) |
 289                            (6 << R300_MS_Y3_SHIFT) |
 290                            (6 << R300_MS_X4_SHIFT) |
 291                            (6 << R300_MS_Y4_SHIFT) |
 292                            (6 << R300_MS_X5_SHIFT) |
 293                            (6 << R300_MS_Y5_SHIFT) |
 294                            (6 << R300_MSBD1_SHIFT)));
 295         radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0));
 296         radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
 297         radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0));
 298         radeon_ring_write(ring,
 299                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
 300         radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));
 301         radeon_ring_write(ring,
 302                           R300_GEOMETRY_ROUND_NEAREST |
 303                           R300_COLOR_ROUND_NEAREST);
 304         radeon_ring_unlock_commit(rdev, ring, false);
 305 }
 306
 307 static void r300_errata(struct radeon_device *rdev)
 308 {
 309         rdev->pll_errata = 0;
 310
 311         if (rdev->family == CHIP_R300 &&
 312             (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
 313                 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
 314         }
 315 }
 316
 317 int r300_mc_wait_for_idle(struct radeon_device *rdev)
 318 {
 319         unsigned i;
 320         uint32_t tmp;
 321
 322         for (i = 0; i < rdev->usec_timeout; i++) {
 323                 /* read MC_STATUS */
 324                 tmp = RREG32(RADEON_MC_STATUS);
 325                 if (tmp & R300_MC_IDLE) {
 326                         return 0;
 327                 }
 328                 DRM_UDELAY(1);
 329         }
 330         return -1;
 331 }
 332
 333 static void r300_gpu_init(struct radeon_device *rdev)
 334 {
 335         uint32_t gb_tile_config, tmp;
 336
 337         if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
 338             (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
 339                 /* r300,r350 */
 340                 rdev->num_gb_pipes = 2;
 341         } else {
 342                 /* rv350,rv370,rv380,r300 AD, r350 AH */
 343                 rdev->num_gb_pipes = 1;
 344         }
 345         rdev->num_z_pipes = 1;
 346         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 347         switch (rdev->num_gb_pipes) {
 348         case 2:
 349                 gb_tile_config |= R300_PIPE_COUNT_R300;
 350                 break;
 351         case 3:
 352                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 353                 break;
 354         case 4:
 355                 gb_tile_config |= R300_PIPE_COUNT_R420;
 356                 break;
 357         default:
 358         case 1:
 359                 gb_tile_config |= R300_PIPE_COUNT_RV350;
 360                 break;
 361         }
 362         WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
 363
 364         if (r100_gui_wait_for_idle(rdev)) {
 365                 printk(KERN_WARNING "Failed to wait GUI idle while "
 366                        "programming pipes. Bad things might happen.\n");
 367         }
 368
 369         tmp = RREG32(R300_DST_PIPE_CONFIG);
 370         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
 371
 372         WREG32(R300_RB2D_DSTCACHE_MODE,
 373                R300_DC_AUTOFLUSH_ENABLE |
 374                R300_DC_DC_DISABLE_IGNORE_PE);
 375
 376         if (r100_gui_wait_for_idle(rdev)) {
 377                 printk(KERN_WARNING "Failed to wait GUI idle while "
 378                        "programming pipes. Bad things might happen.\n");
 379         }
 380         if (r300_mc_wait_for_idle(rdev)) {
 381                 printk(KERN_WARNING "Failed to wait MC idle while "
 382                        "programming pipes. Bad things might happen.\n");
 383         }
 384         DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
 385                  rdev->num_gb_pipes, rdev->num_z_pipes);
 386 }
 387
 388 int r300_asic_reset(struct radeon_device *rdev)
 389 {
 390         struct r100_mc_save save;
 391         u32 status, tmp;
 392         int ret = 0;
 393
 394         status = RREG32(R_000E40_RBBM_STATUS);
 395         if (!G_000E40_GUI_ACTIVE(status)) {
 396                 return 0;
 397         }
 398         r100_mc_stop(rdev, &save);
 399         status = RREG32(R_000E40_RBBM_STATUS);
 400         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 401         /* stop CP */
 402         WREG32(RADEON_CP_CSQ_CNTL, 0);
 403         tmp = RREG32(RADEON_CP_RB_CNTL);
 404         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 405         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 406         WREG32(RADEON_CP_RB_WPTR, 0);
 407         WREG32(RADEON_CP_RB_CNTL, tmp);
 408         /* save PCI state */
 409         pci_save_state(rdev->pdev);
 410         /* disable bus mastering */
 411         r100_bm_disable(rdev);
 412         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
 413                                         S_0000F0_SOFT_RESET_GA(1));
 414         RREG32(R_0000F0_RBBM_SOFT_RESET);
 415         mdelay(500);
 416         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 417         mdelay(1);
 418         status = RREG32(R_000E40_RBBM_STATUS);
 419         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 420         /* resetting the CP seems to be problematic sometimes it end up
 421          * hard locking the computer, but it's necessary for successful
 422          * reset more test & playing is needed on R3XX/R4XX to find a
 423          * reliable (if any solution)
 424          */
 425         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
 426         RREG32(R_0000F0_RBBM_SOFT_RESET);
 427         mdelay(500);
 428         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 429         mdelay(1);
 430         status = RREG32(R_000E40_RBBM_STATUS);
 431         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 432         /* restore PCI & busmastering */
 433         pci_restore_state(rdev->pdev);
 434         r100_enable_bm(rdev);
 435         /* Check if GPU is idle */
 436         if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
 437                 dev_err(rdev->dev, "failed to reset GPU\n");
 438                 ret = -1;
 439         } else
 440                 dev_info(rdev->dev, "GPU reset succeed\n");
 441         r100_mc_resume(rdev, &save);
 442         return ret;
 443 }
 444
 445 /*
 446  * r300,r350,rv350,rv380 VRAM info
 447  */
 448 void r300_mc_init(struct radeon_device *rdev)
 449 {
 450         u64 base;
 451         u32 tmp;
 452
 453         /* DDR for all card after R300 & IGP */
 454         rdev->mc.vram_is_ddr = true;
 455         tmp = RREG32(RADEON_MEM_CNTL);
 456         tmp &= R300_MEM_NUM_CHANNELS_MASK;
 457         switch (tmp) {
 458         case 0: rdev->mc.vram_width = 64; break;
 459         case 1: rdev->mc.vram_width = 128; break;
 460         case 2: rdev->mc.vram_width = 256; break;
 461         default:  rdev->mc.vram_width = 128; break;
 462         }
 463         r100_vram_init_sizes(rdev);
 464         base = rdev->mc.aper_base;
 465         if (rdev->flags & RADEON_IS_IGP)
 466                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
 467         radeon_vram_location(rdev, &rdev->mc, base);
 468         rdev->mc.gtt_base_align = 0;
 469         if (!(rdev->flags & RADEON_IS_AGP))
 470                 radeon_gtt_location(rdev, &rdev->mc);
 471         radeon_update_bandwidth_info(rdev);
 472 }
 473
 474 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
 475 {
 476         uint32_t link_width_cntl, mask;
 477
 478         if (rdev->flags & RADEON_IS_IGP)
 479                 return;
 480
 481         if (!(rdev->flags & RADEON_IS_PCIE))
 482                 return;
 483
 484         /* FIXME wait for idle */
 485
 486         switch (lanes) {
 487         case 0:
 488                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
 489                 break;
 490         case 1:
 491                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
 492                 break;
 493         case 2:
 494                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
 495                 break;
 496         case 4:
 497                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
 498                 break;
 499         case 8:
 500                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
 501                 break;
 502         case 12:
 503                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
 504                 break;
 505         case 16:
 506         default:
 507                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
 508                 break;
 509         }
 510
 511         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 512
 513         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
 514             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
 515                 return;
 516
 517         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
 518                              RADEON_PCIE_LC_RECONFIG_NOW |
 519                              RADEON_PCIE_LC_RECONFIG_LATER |
 520                              RADEON_PCIE_LC_SHORT_RECONFIG_EN);
 521         link_width_cntl |= mask;
 522         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
 523         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
 524                                                      RADEON_PCIE_LC_RECONFIG_NOW));
 525
 526         /* wait for lane set to complete */
 527         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 528         while (link_width_cntl == 0xffffffff)
 529                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 530
 531 }
 532
 533 int rv370_get_pcie_lanes(struct radeon_device *rdev)
 534 {
 535         u32 link_width_cntl;
 536
 537         if (rdev->flags & RADEON_IS_IGP)
 538                 return 0;
 539
 540         if (!(rdev->flags & RADEON_IS_PCIE))
 541                 return 0;
 542
 543         /* FIXME wait for idle */
 544
 545         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 546
 547         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
 548         case RADEON_PCIE_LC_LINK_WIDTH_X0:
 549                 return 0;
 550         case RADEON_PCIE_LC_LINK_WIDTH_X1:
 551                 return 1;
 552         case RADEON_PCIE_LC_LINK_WIDTH_X2:
 553                 return 2;
 554         case RADEON_PCIE_LC_LINK_WIDTH_X4:
 555                 return 4;
 556         case RADEON_PCIE_LC_LINK_WIDTH_X8:
 557                 return 8;
 558         case RADEON_PCIE_LC_LINK_WIDTH_X16:
 559         default:
 560                 return 16;
 561         }
 562 }
 563
 564 #if defined(CONFIG_DEBUG_FS)
 565 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
 566 {
 567         struct drm_info_node *node = (struct drm_info_node *) m->private;
 568         struct drm_device *dev = node->minor->dev;
 569         struct radeon_device *rdev = dev->dev_private;
 570         uint32_t tmp;
 571
 572         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 573         seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
 574         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
 575         seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
 576         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
 577         seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
 578         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
 579         seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
 580         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
 581         seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
 582         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
 583         seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
 584         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
 585         seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
 586         return 0;
 587 }
 588
 589 static struct drm_info_list rv370_pcie_gart_info_list[] = {
 590         {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
 591 };
 592 #endif
 593
 594 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
 595 {
 596 #if defined(CONFIG_DEBUG_FS)
 597         return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
 598 #else
 599         return 0;
 600 #endif
 601 }
 602
 603 static int r300_packet0_check(struct radeon_cs_parser *p,
 604                 struct radeon_cs_packet *pkt,
 605                 unsigned idx, unsigned reg)
 606 {
 607         struct radeon_bo_list *reloc;
 608         struct r100_cs_track *track;
 609         volatile uint32_t *ib;
 610         uint32_t tmp, tile_flags = 0;
 611         unsigned i;
 612         int r;
 613         u32 idx_value;
 614
 615         ib = p->ib.ptr;
 616         track = (struct r100_cs_track *)p->track;
 617         idx_value = radeon_get_ib_value(p, idx);
 618
 619         switch(reg) {
 620         case AVIVO_D1MODE_VLINE_START_END:
 621         case RADEON_CRTC_GUI_TRIG_VLINE:
 622                 r = r100_cs_packet_parse_vline(p);
 623                 if (r) {
 624                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 625                                         idx, reg);
 626                         radeon_cs_dump_packet(p, pkt);
 627                         return r;
 628                 }
 629                 break;
 630         case RADEON_DST_PITCH_OFFSET:
 631         case RADEON_SRC_PITCH_OFFSET:
 632                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
 633                 if (r)
 634                         return r;
 635                 break;
 636         case R300_RB3D_COLOROFFSET0:
 637         case R300_RB3D_COLOROFFSET1:
 638         case R300_RB3D_COLOROFFSET2:
 639         case R300_RB3D_COLOROFFSET3:
 640                 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
 641                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 642                 if (r) {
 643                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 644                                         idx, reg);
 645                         radeon_cs_dump_packet(p, pkt);
 646                         return r;
 647                 }
 648                 track->cb[i].robj = reloc->robj;
 649                 track->cb[i].offset = idx_value;
 650                 track->cb_dirty = true;
 651                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
 652                 break;
 653         case R300_ZB_DEPTHOFFSET:
 654                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 655                 if (r) {
 656                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 657                                         idx, reg);
 658                         radeon_cs_dump_packet(p, pkt);
 659                         return r;
 660                 }
 661                 track->zb.robj = reloc->robj;
 662                 track->zb.offset = idx_value;
 663                 track->zb_dirty = true;
 664                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
 665                 break;
 666         case R300_TX_OFFSET_0:
 667         case R300_TX_OFFSET_0+4:
 668         case R300_TX_OFFSET_0+8:
 669         case R300_TX_OFFSET_0+12:
 670         case R300_TX_OFFSET_0+16:
 671         case R300_TX_OFFSET_0+20:
 672         case R300_TX_OFFSET_0+24:
 673         case R300_TX_OFFSET_0+28:
 674         case R300_TX_OFFSET_0+32:
 675         case R300_TX_OFFSET_0+36:
 676         case R300_TX_OFFSET_0+40:
 677         case R300_TX_OFFSET_0+44:
 678         case R300_TX_OFFSET_0+48:
 679         case R300_TX_OFFSET_0+52:
 680         case R300_TX_OFFSET_0+56:
 681         case R300_TX_OFFSET_0+60:
 682                 i = (reg - R300_TX_OFFSET_0) >> 2;
 683                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 684                 if (r) {
 685                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 686                                         idx, reg);
 687                         radeon_cs_dump_packet(p, pkt);
 688                         return r;
 689                 }
 690
 691                 if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) {
 692                         ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
 693                                   ((idx_value & ~31) + (u32)reloc->gpu_offset);
 694                 } else {
 695                         if (reloc->tiling_flags & RADEON_TILING_MACRO)
 696                                 tile_flags |= R300_TXO_MACRO_TILE;
 697                         if (reloc->tiling_flags & RADEON_TILING_MICRO)
 698                                 tile_flags |= R300_TXO_MICRO_TILE;
 699                         else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
 700                                 tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
 701
 702                         tmp = idx_value + ((u32)reloc->gpu_offset);
 703                         tmp |= tile_flags;
 704                         ib[idx] = tmp;
 705                 }
 706                 track->textures[i].robj = reloc->robj;
 707                 track->tex_dirty = true;
 708                 break;
 709         /* Tracked registers */
 710         case 0x2084:
 711                 /* VAP_VF_CNTL */
 712                 track->vap_vf_cntl = idx_value;
 713                 break;
 714         case 0x20B4:
 715                 /* VAP_VTX_SIZE */
 716                 track->vtx_size = idx_value & 0x7F;
 717                 break;
 718         case 0x2134:
 719                 /* VAP_VF_MAX_VTX_INDX */
 720                 track->max_indx = idx_value & 0x00FFFFFFUL;
 721                 break;
 722         case 0x2088:
 723                 /* VAP_ALT_NUM_VERTICES - only valid on r500 */
 724                 if (p->rdev->family < CHIP_RV515)
 725                         goto fail;
 726                 track->vap_alt_nverts = idx_value & 0xFFFFFF;
 727                 break;
 728         case 0x43E4:
 729                 /* SC_SCISSOR1 */
 730                 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
 731                 if (p->rdev->family < CHIP_RV515) {
 732                         track->maxy -= 1440;
 733                 }
 734                 track->cb_dirty = true;
 735                 track->zb_dirty = true;
 736                 break;
 737         case 0x4E00:
 738                 /* RB3D_CCTL */
 739                 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */
 740                     p->rdev->cmask_filp != p->filp) {
 741                         DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n");
 742                         return -EINVAL;
 743                 }
 744                 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
 745                 track->cb_dirty = true;
 746                 break;
 747         case 0x4E38:
 748         case 0x4E3C:
 749         case 0x4E40:
 750         case 0x4E44:
 751                 /* RB3D_COLORPITCH0 */
 752                 /* RB3D_COLORPITCH1 */
 753                 /* RB3D_COLORPITCH2 */
 754                 /* RB3D_COLORPITCH3 */
 755                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
 756                         r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 757                         if (r) {
 758                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 759                                           idx, reg);
 760                                 radeon_cs_dump_packet(p, pkt);
 761                                 return r;
 762                         }
 763
 764                         if (reloc->tiling_flags & RADEON_TILING_MACRO)
 765                                 tile_flags |= R300_COLOR_TILE_ENABLE;
 766                         if (reloc->tiling_flags & RADEON_TILING_MICRO)
 767                                 tile_flags |= R300_COLOR_MICROTILE_ENABLE;
 768                         else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
 769                                 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
 770
 771                         tmp = idx_value & ~(0x7 << 16);
 772                         tmp |= tile_flags;
 773                         ib[idx] = tmp;
 774                 }
 775                 i = (reg - 0x4E38) >> 2;
 776                 track->cb[i].pitch = idx_value & 0x3FFE;
 777                 switch (((idx_value >> 21) & 0xF)) {
 778                 case 9:
 779                 case 11:
 780                 case 12:
 781                         track->cb[i].cpp = 1;
 782                         break;
 783                 case 3:
 784                 case 4:
 785                 case 13:
 786                 case 15:
 787                         track->cb[i].cpp = 2;
 788                         break;
 789                 case 5:
 790                         if (p->rdev->family < CHIP_RV515) {
 791                                 DRM_ERROR("Invalid color buffer format (%d)!\n",
 792                                           ((idx_value >> 21) & 0xF));
 793                                 return -EINVAL;
 794                         }
 795                         /* Pass through. */
 796                 case 6:
 797                         track->cb[i].cpp = 4;
 798                         break;
 799                 case 10:
 800                         track->cb[i].cpp = 8;
 801                         break;
 802                 case 7:
 803                         track->cb[i].cpp = 16;
 804                         break;
 805                 default:
 806                         DRM_ERROR("Invalid color buffer format (%d) !\n",
 807                                   ((idx_value >> 21) & 0xF));
 808                         return -EINVAL;
 809                 }
 810                 track->cb_dirty = true;
 811                 break;
 812         case 0x4F00:
 813                 /* ZB_CNTL */
 814                 if (idx_value & 2) {
 815                         track->z_enabled = true;
 816                 } else {
 817                         track->z_enabled = false;
 818                 }
 819                 track->zb_dirty = true;
 820                 break;
 821         case 0x4F10:
 822                 /* ZB_FORMAT */
 823                 switch ((idx_value & 0xF)) {
 824                 case 0:
 825                 case 1:
 826                         track->zb.cpp = 2;
 827                         break;
 828                 case 2:
 829                         track->zb.cpp = 4;
 830                         break;
 831                 default:
 832                         DRM_ERROR("Invalid z buffer format (%d) !\n",
 833                                   (idx_value & 0xF));
 834                         return -EINVAL;
 835                 }
 836                 track->zb_dirty = true;
 837                 break;
 838         case 0x4F24:
 839                 /* ZB_DEPTHPITCH */
 840                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
 841                         r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 842                         if (r) {
 843                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 844                                           idx, reg);
 845                                 radeon_cs_dump_packet(p, pkt);
 846                                 return r;
 847                         }
 848
 849                         if (reloc->tiling_flags & RADEON_TILING_MACRO)
 850                                 tile_flags |= R300_DEPTHMACROTILE_ENABLE;
 851                         if (reloc->tiling_flags & RADEON_TILING_MICRO)
 852                                 tile_flags |= R300_DEPTHMICROTILE_TILED;
 853                         else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
 854                                 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
 855
 856                         tmp = idx_value & ~(0x7 << 16);
 857                         tmp |= tile_flags;
 858                         ib[idx] = tmp;
 859                 }
 860                 track->zb.pitch = idx_value & 0x3FFC;
 861                 track->zb_dirty = true;
 862                 break;
 863         case 0x4104:
 864                 /* TX_ENABLE */
 865                 for (i = 0; i < 16; i++) {
 866                         bool enabled;
 867
 868                         enabled = !!(idx_value & (1 << i));
 869                         track->textures[i].enabled = enabled;
 870                 }
 871                 track->tex_dirty = true;
 872                 break;
 873         case 0x44C0:
 874         case 0x44C4:
 875         case 0x44C8:
 876         case 0x44CC:
 877         case 0x44D0:
 878         case 0x44D4:
 879         case 0x44D8:
 880         case 0x44DC:
 881         case 0x44E0:
 882         case 0x44E4:
 883         case 0x44E8:
 884         case 0x44EC:
 885         case 0x44F0:
 886         case 0x44F4:
 887         case 0x44F8:
 888         case 0x44FC:
 889                 /* TX_FORMAT1_[0-15] */
 890                 i = (reg - 0x44C0) >> 2;
 891                 tmp = (idx_value >> 25) & 0x3;
 892                 track->textures[i].tex_coord_type = tmp;
 893                 switch ((idx_value & 0x1F)) {
 894                 case R300_TX_FORMAT_X8:
 895                 case R300_TX_FORMAT_Y4X4:
 896                 case R300_TX_FORMAT_Z3Y3X2:
 897                         track->textures[i].cpp = 1;
 898                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 899                         break;
 900                 case R300_TX_FORMAT_X16:
 901                 case R300_TX_FORMAT_FL_I16:
 902                 case R300_TX_FORMAT_Y8X8:
 903                 case R300_TX_FORMAT_Z5Y6X5:
 904                 case R300_TX_FORMAT_Z6Y5X5:
 905                 case R300_TX_FORMAT_W4Z4Y4X4:
 906                 case R300_TX_FORMAT_W1Z5Y5X5:
 907                 case R300_TX_FORMAT_D3DMFT_CxV8U8:
 908                 case R300_TX_FORMAT_B8G8_B8G8:
 909                 case R300_TX_FORMAT_G8R8_G8B8:
 910                         track->textures[i].cpp = 2;
 911                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 912                         break;
 913                 case R300_TX_FORMAT_Y16X16:
 914                 case R300_TX_FORMAT_FL_I16A16:
 915                 case R300_TX_FORMAT_Z11Y11X10:
 916                 case R300_TX_FORMAT_Z10Y11X11:
 917                 case R300_TX_FORMAT_W8Z8Y8X8:
 918                 case R300_TX_FORMAT_W2Z10Y10X10:
 919                 case 0x17:
 920                 case R300_TX_FORMAT_FL_I32:
 921                 case 0x1e:
 922                         track->textures[i].cpp = 4;
 923                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 924                         break;
 925                 case R300_TX_FORMAT_W16Z16Y16X16:
 926                 case R300_TX_FORMAT_FL_R16G16B16A16:
 927                 case R300_TX_FORMAT_FL_I32A32:
 928                         track->textures[i].cpp = 8;
 929                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 930                         break;
 931                 case R300_TX_FORMAT_FL_R32G32B32A32:
 932                         track->textures[i].cpp = 16;
 933                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 934                         break;
 935                 case R300_TX_FORMAT_DXT1:
 936                         track->textures[i].cpp = 1;
 937                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
 938                         break;
 939                 case R300_TX_FORMAT_ATI2N:
 940                         if (p->rdev->family < CHIP_R420) {
 941                                 DRM_ERROR("Invalid texture format %u\n",
 942                                           (idx_value & 0x1F));
 943                                 return -EINVAL;
 944                         }
 945                         /* The same rules apply as for DXT3/5. */
 946                         /* Pass through. */
 947                 case R300_TX_FORMAT_DXT3:
 948                 case R300_TX_FORMAT_DXT5:
 949                         track->textures[i].cpp = 1;
 950                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
 951                         break;
 952                 default:
 953                         DRM_ERROR("Invalid texture format %u\n",
 954                                   (idx_value & 0x1F));
 955                         return -EINVAL;
 956                 }
 957                 track->tex_dirty = true;
 958                 break;
 959         case 0x4400:
 960         case 0x4404:
 961         case 0x4408:
 962         case 0x440C:
 963         case 0x4410:
 964         case 0x4414:
 965         case 0x4418:
 966         case 0x441C:
 967         case 0x4420:
 968         case 0x4424:
 969         case 0x4428:
 970         case 0x442C:
 971         case 0x4430:
 972         case 0x4434:
 973         case 0x4438:
 974         case 0x443C:
 975                 /* TX_FILTER0_[0-15] */
 976                 i = (reg - 0x4400) >> 2;
 977                 tmp = idx_value & 0x7;
 978                 if (tmp == 2 || tmp == 4 || tmp == 6) {
 979                         track->textures[i].roundup_w = false;
 980                 }
 981                 tmp = (idx_value >> 3) & 0x7;
 982                 if (tmp == 2 || tmp == 4 || tmp == 6) {
 983                         track->textures[i].roundup_h = false;
 984                 }
 985                 track->tex_dirty = true;
 986                 break;
 987         case 0x4500:
 988         case 0x4504:
 989         case 0x4508:
 990         case 0x450C:
 991         case 0x4510:
 992         case 0x4514:
 993         case 0x4518:
 994         case 0x451C:
 995         case 0x4520:
 996         case 0x4524:
 997         case 0x4528:
 998         case 0x452C:
 999         case 0x4530:
1000         case 0x4534:
1001         case 0x4538:
1002         case 0x453C:
1003                 /* TX_FORMAT2_[0-15] */
1004                 i = (reg - 0x4500) >> 2;
1005                 tmp = idx_value & 0x3FFF;
1006                 track->textures[i].pitch = tmp + 1;
1007                 if (p->rdev->family >= CHIP_RV515) {
1008                         tmp = ((idx_value >> 15) & 1) << 11;
1009                         track->textures[i].width_11 = tmp;
1010                         tmp = ((idx_value >> 16) & 1) << 11;
1011                         track->textures[i].height_11 = tmp;
1012
1013                         /* ATI1N */
1014                         if (idx_value & (1 << 14)) {
1015                                 /* The same rules apply as for DXT1. */
1016                                 track->textures[i].compress_format =
1017                                         R100_TRACK_COMP_DXT1;
1018                         }
1019                 } else if (idx_value & (1 << 14)) {
1020                         DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1021                         return -EINVAL;
1022                 }
1023                 track->tex_dirty = true;
1024                 break;
1025         case 0x4480:
1026         case 0x4484:
1027         case 0x4488:
1028         case 0x448C:
1029         case 0x4490:
1030         case 0x4494:
1031         case 0x4498:
1032         case 0x449C:
1033         case 0x44A0:
1034         case 0x44A4:
1035         case 0x44A8:
1036         case 0x44AC:
1037         case 0x44B0:
1038         case 0x44B4:
1039         case 0x44B8:
1040         case 0x44BC:
1041                 /* TX_FORMAT0_[0-15] */
1042                 i = (reg - 0x4480) >> 2;
1043                 tmp = idx_value & 0x7FF;
1044                 track->textures[i].width = tmp + 1;
1045                 tmp = (idx_value >> 11) & 0x7FF;
1046                 track->textures[i].height = tmp + 1;
1047                 tmp = (idx_value >> 26) & 0xF;
1048                 track->textures[i].num_levels = tmp;
1049                 tmp = idx_value & (1 << 31);
1050                 track->textures[i].use_pitch = !!tmp;
1051                 tmp = (idx_value >> 22) & 0xF;
1052                 track->textures[i].txdepth = tmp;
1053                 track->tex_dirty = true;
1054                 break;
1055         case R300_ZB_ZPASS_ADDR:
1056                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1057                 if (r) {
1058                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1059                                         idx, reg);
1060                         radeon_cs_dump_packet(p, pkt);
1061                         return r;
1062                 }
1063                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1064                 break;
1065         case 0x4e0c:
1066                 /* RB3D_COLOR_CHANNEL_MASK */
1067                 track->color_channel_mask = idx_value;
1068                 track->cb_dirty = true;
1069                 break;
1070         case 0x43a4:
1071                 /* SC_HYPERZ_EN */
1072                 /* r300c emits this register - we need to disable hyperz for it
1073                  * without complaining */
1074                 if (p->rdev->hyperz_filp != p->filp) {
1075                         if (idx_value & 0x1)
1076                                 ib[idx] = idx_value & ~1;
1077                 }
1078                 break;
1079         case 0x4f1c:
1080                 /* ZB_BW_CNTL */
1081                 track->zb_cb_clear = !!(idx_value & (1 << 5));
1082                 track->cb_dirty = true;
1083                 track->zb_dirty = true;
1084                 if (p->rdev->hyperz_filp != p->filp) {
1085                         if (idx_value & (R300_HIZ_ENABLE |
1086                                          R300_RD_COMP_ENABLE |
1087                                          R300_WR_COMP_ENABLE |
1088                                          R300_FAST_FILL_ENABLE))
1089                                 goto fail;
1090                 }
1091                 break;
1092         case 0x4e04:
1093                 /* RB3D_BLENDCNTL */
1094                 track->blend_read_enable = !!(idx_value & (1 << 2));
1095                 track->cb_dirty = true;
1096                 break;
1097         case R300_RB3D_AARESOLVE_OFFSET:
1098                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1099                 if (r) {
1100                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1101                                   idx, reg);
1102                         radeon_cs_dump_packet(p, pkt);
1103                         return r;
1104                 }
1105                 track->aa.robj = reloc->robj;
1106                 track->aa.offset = idx_value;
1107                 track->aa_dirty = true;
1108                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1109                 break;
1110         case R300_RB3D_AARESOLVE_PITCH:
1111                 track->aa.pitch = idx_value & 0x3FFE;
1112                 track->aa_dirty = true;
1113                 break;
1114         case R300_RB3D_AARESOLVE_CTL:
1115                 track->aaresolve = idx_value & 0x1;
1116                 track->aa_dirty = true;
1117                 break;
1118         case 0x4f30: /* ZB_MASK_OFFSET */
1119         case 0x4f34: /* ZB_ZMASK_PITCH */
1120         case 0x4f44: /* ZB_HIZ_OFFSET */
1121         case 0x4f54: /* ZB_HIZ_PITCH */
1122                 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1123                         goto fail;
1124                 break;
1125         case 0x4028:
1126                 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1127                         goto fail;
1128                 /* GB_Z_PEQ_CONFIG */
1129                 if (p->rdev->family >= CHIP_RV350)
1130                         break;
1131                 goto fail;
1132                 break;
1133         case 0x4be8:
1134                 /* valid register only on RV530 */
1135                 if (p->rdev->family == CHIP_RV530)
1136                         break;
1137                 /* fallthrough do not move */
1138         default:
1139                 goto fail;
1140         }
1141         return 0;
1142 fail:
1143         printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n",
1144                reg, idx, idx_value);
1145         return -EINVAL;
1146 }
1147
1148 static int r300_packet3_check(struct radeon_cs_parser *p,
1149                               struct radeon_cs_packet *pkt)
1150 {
1151         struct radeon_bo_list *reloc;
1152         struct r100_cs_track *track;
1153         volatile uint32_t *ib;
1154         unsigned idx;
1155         int r;
1156
1157         ib = p->ib.ptr;
1158         idx = pkt->idx + 1;
1159         track = (struct r100_cs_track *)p->track;
1160         switch(pkt->opcode) {
1161         case PACKET3_3D_LOAD_VBPNTR:
1162                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1163                 if (r)
1164                         return r;
1165                 break;
1166         case PACKET3_INDX_BUFFER:
1167                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1168                 if (r) {
1169                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1170                         radeon_cs_dump_packet(p, pkt);
1171                         return r;
1172                 }
1173                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1174                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1175                 if (r) {
1176                         return r;
1177                 }
1178                 break;
1179         /* Draw packet */
1180         case PACKET3_3D_DRAW_IMMD:
1181                 /* Number of dwords is vtx_size * (num_vertices - 1)
1182                  * PRIM_WALK must be equal to 3 vertex data in embedded
1183                  * in cmd stream */
1184                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1185                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1186                         return -EINVAL;
1187                 }
1188                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1189                 track->immd_dwords = pkt->count - 1;
1190                 r = r100_cs_track_check(p->rdev, track);
1191                 if (r) {
1192                         return r;
1193                 }
1194                 break;
1195         case PACKET3_3D_DRAW_IMMD_2:
1196                 /* Number of dwords is vtx_size * (num_vertices - 1)
1197                  * PRIM_WALK must be equal to 3 vertex data in embedded
1198                  * in cmd stream */
1199                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1200                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1201                         return -EINVAL;
1202                 }
1203                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1204                 track->immd_dwords = pkt->count;
1205                 r = r100_cs_track_check(p->rdev, track);
1206                 if (r) {
1207                         return r;
1208                 }
1209                 break;
1210         case PACKET3_3D_DRAW_VBUF:
1211                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1212                 r = r100_cs_track_check(p->rdev, track);
1213                 if (r) {
1214                         return r;
1215                 }
1216                 break;
1217         case PACKET3_3D_DRAW_VBUF_2:
1218                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1219                 r = r100_cs_track_check(p->rdev, track);
1220                 if (r) {
1221                         return r;
1222                 }
1223                 break;
1224         case PACKET3_3D_DRAW_INDX:
1225                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1226                 r = r100_cs_track_check(p->rdev, track);
1227                 if (r) {
1228                         return r;
1229                 }
1230                 break;
1231         case PACKET3_3D_DRAW_INDX_2:
1232                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1233                 r = r100_cs_track_check(p->rdev, track);
1234                 if (r) {
1235                         return r;
1236                 }
1237                 break;
1238         case PACKET3_3D_CLEAR_HIZ:
1239         case PACKET3_3D_CLEAR_ZMASK:
1240                 if (p->rdev->hyperz_filp != p->filp)
1241                         return -EINVAL;
1242                 break;
1243         case PACKET3_3D_CLEAR_CMASK:
1244                 if (p->rdev->cmask_filp != p->filp)
1245                         return -EINVAL;
1246                 break;
1247         case PACKET3_NOP:
1248                 break;
1249         default:
1250                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1251                 return -EINVAL;
1252         }
1253         return 0;
1254 }
1255
1256 int r300_cs_parse(struct radeon_cs_parser *p)
1257 {
1258         struct radeon_cs_packet pkt;
1259         struct r100_cs_track *track;
1260         int r;
1261
1262         track = kzalloc(sizeof(*track), GFP_KERNEL);
1263         if (track == NULL)
1264                 return -ENOMEM;
1265         r100_cs_track_clear(p->rdev, track);
1266         p->track = track;
1267         do {
1268                 r = radeon_cs_packet_parse(p, &pkt, p->idx);
1269                 if (r) {
1270                         return r;
1271                 }
1272                 p->idx += pkt.count + 2;
1273                 switch (pkt.type) {
1274                 case RADEON_PACKET_TYPE0:
1275                         r = r100_cs_parse_packet0(p, &pkt,
1276                                                   p->rdev->config.r300.reg_safe_bm,
1277                                                   p->rdev->config.r300.reg_safe_bm_size,
1278                                                   &r300_packet0_check);
1279                         break;
1280                 case RADEON_PACKET_TYPE2:
1281                         break;
1282                 case RADEON_PACKET_TYPE3:
1283                         r = r300_packet3_check(p, &pkt);
1284                         break;
1285                 default:
1286                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1287                         return -EINVAL;
1288                 }
1289                 if (r) {
1290                         return r;
1291                 }
1292         } while (p->idx < p->chunk_ib->length_dw);
1293         return 0;
1294 }
1295
1296 void r300_set_reg_safe(struct radeon_device *rdev)
1297 {
1298         rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1299         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1300 }
1301
1302 void r300_mc_program(struct radeon_device *rdev)
1303 {
1304         struct r100_mc_save save;
1305         int r;
1306
1307         r = r100_debugfs_mc_info_init(rdev);
1308         if (r) {
1309                 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1310         }
1311
1312         /* Stops all mc clients */
1313         r100_mc_stop(rdev, &save);
1314         if (rdev->flags & RADEON_IS_AGP) {
1315                 WREG32(R_00014C_MC_AGP_LOCATION,
1316                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1317                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1318                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1319                 WREG32(R_00015C_AGP_BASE_2,
1320                         upper_32_bits(rdev->mc.agp_base) & 0xff);
1321         } else {
1322                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1323                 WREG32(R_000170_AGP_BASE, 0);
1324                 WREG32(R_00015C_AGP_BASE_2, 0);
1325         }
1326         /* Wait for mc idle */
1327         if (r300_mc_wait_for_idle(rdev))
1328                 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1329         /* Program MC, should be a 32bits limited address space */
1330         WREG32(R_000148_MC_FB_LOCATION,
1331                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1332                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1333         r100_mc_resume(rdev, &save);
1334 }
1335
1336 void r300_clock_startup(struct radeon_device *rdev)
1337 {
1338         u32 tmp;
1339
1340         if (radeon_dynclks != -1 && radeon_dynclks)
1341                 radeon_legacy_set_clock_gating(rdev, 1);
1342         /* We need to force on some of the block */
1343         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1344         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1345         if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1346                 tmp |= S_00000D_FORCE_VAP(1);
1347         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1348 }
1349
1350 static int r300_startup(struct radeon_device *rdev)
1351 {
1352         int r;
1353
1354         /* set common regs */
1355         r100_set_common_regs(rdev);
1356         /* program mc */
1357         r300_mc_program(rdev);
1358         /* Resume clock */
1359         r300_clock_startup(rdev);
1360         /* Initialize GPU configuration (# pipes, ...) */
1361         r300_gpu_init(rdev);
1362         /* Initialize GART (initialize after TTM so we can allocate
1363          * memory through TTM but finalize after TTM) */
1364         if (rdev->flags & RADEON_IS_PCIE) {
1365                 r = rv370_pcie_gart_enable(rdev);
1366                 if (r)
1367                         return r;
1368         }
1369
1370         if (rdev->family == CHIP_R300 ||
1371             rdev->family == CHIP_R350 ||
1372             rdev->family == CHIP_RV350)
1373                 r100_enable_bm(rdev);
1374
1375         if (rdev->flags & RADEON_IS_PCI) {
1376                 r = r100_pci_gart_enable(rdev);
1377                 if (r)
1378                         return r;
1379         }
1380
1381         /* allocate wb buffer */
1382         r = radeon_wb_init(rdev);
1383         if (r)
1384                 return r;
1385
1386         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1387         if (r) {
1388                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1389                 return r;
1390         }
1391
1392         /* Enable IRQ */
1393         if (!rdev->irq.installed) {
1394                 r = radeon_irq_kms_init(rdev);
1395                 if (r)
1396                         return r;
1397         }
1398
1399         r100_irq_set(rdev);
1400         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1401         /* 1M ring buffer */
1402         r = r100_cp_init(rdev, 1024 * 1024);
1403         if (r) {
1404                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1405                 return r;
1406         }
1407
1408         r = radeon_ib_pool_init(rdev);
1409         if (r) {
1410                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1411                 return r;
1412         }
1413
1414         return 0;
1415 }
1416
1417 int r300_resume(struct radeon_device *rdev)
1418 {
1419         int r;
1420
1421         /* Make sur GART are not working */
1422         if (rdev->flags & RADEON_IS_PCIE)
1423                 rv370_pcie_gart_disable(rdev);
1424         if (rdev->flags & RADEON_IS_PCI)
1425                 r100_pci_gart_disable(rdev);
1426         /* Resume clock before doing reset */
1427         r300_clock_startup(rdev);
1428         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1429         if (radeon_asic_reset(rdev)) {
1430                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1431                         RREG32(R_000E40_RBBM_STATUS),
1432                         RREG32(R_0007C0_CP_STAT));
1433         }
1434         /* post */
1435         radeon_combios_asic_init(rdev->ddev);
1436         /* Resume clock after posting */
1437         r300_clock_startup(rdev);
1438         /* Initialize surface registers */
1439         radeon_surface_init(rdev);
1440
1441         rdev->accel_working = true;
1442         r = r300_startup(rdev);
1443         if (r) {
1444                 rdev->accel_working = false;
1445         }
1446         return r;
1447 }
1448
1449 int r300_suspend(struct radeon_device *rdev)
1450 {
1451         radeon_pm_suspend(rdev);
1452         r100_cp_disable(rdev);
1453         radeon_wb_disable(rdev);
1454         r100_irq_disable(rdev);
1455         if (rdev->flags & RADEON_IS_PCIE)
1456                 rv370_pcie_gart_disable(rdev);
1457         if (rdev->flags & RADEON_IS_PCI)
1458                 r100_pci_gart_disable(rdev);
1459         return 0;
1460 }
1461
1462 void r300_fini(struct radeon_device *rdev)
1463 {
1464         radeon_pm_fini(rdev);
1465         r100_cp_fini(rdev);
1466         radeon_wb_fini(rdev);
1467         radeon_ib_pool_fini(rdev);
1468         radeon_gem_fini(rdev);
1469         if (rdev->flags & RADEON_IS_PCIE)
1470                 rv370_pcie_gart_fini(rdev);
1471         if (rdev->flags & RADEON_IS_PCI)
1472                 r100_pci_gart_fini(rdev);
1473         radeon_agp_fini(rdev);
1474         radeon_irq_kms_fini(rdev);
1475         radeon_fence_driver_fini(rdev);
1476         radeon_bo_fini(rdev);
1477         radeon_atombios_fini(rdev);
1478         kfree(rdev->bios);
1479         rdev->bios = NULL;
1480 }
1481
1482 int r300_init(struct radeon_device *rdev)
1483 {
1484         int r;
1485
1486         /* Disable VGA */
1487         r100_vga_render_disable(rdev);
1488         /* Initialize scratch registers */
1489         radeon_scratch_init(rdev);
1490         /* Initialize surface registers */
1491         radeon_surface_init(rdev);
1492         /* TODO: disable VGA need to use VGA request */
1493         /* restore some register to sane defaults */
1494         r100_restore_sanity(rdev);
1495         /* BIOS*/
1496         if (!radeon_get_bios(rdev)) {
1497                 if (ASIC_IS_AVIVO(rdev))
1498                         return -EINVAL;
1499         }
1500         if (rdev->is_atom_bios) {
1501                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1502                 return -EINVAL;
1503         } else {
1504                 r = radeon_combios_init(rdev);
1505                 if (r)
1506                         return r;
1507         }
1508         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1509         if (radeon_asic_reset(rdev)) {
1510                 dev_warn(rdev->dev,
1511                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1512                         RREG32(R_000E40_RBBM_STATUS),
1513                         RREG32(R_0007C0_CP_STAT));
1514         }
1515         /* check if cards are posted or not */
1516         if (radeon_boot_test_post_card(rdev) == false)
1517                 return -EINVAL;
1518         /* Set asic errata */
1519         r300_errata(rdev);
1520         /* Initialize clocks */
1521         radeon_get_clock_info(rdev->ddev);
1522         /* initialize AGP */
1523         if (rdev->flags & RADEON_IS_AGP) {
1524                 r = radeon_agp_init(rdev);
1525                 if (r) {
1526                         radeon_agp_disable(rdev);
1527                 }
1528         }
1529         /* initialize memory controller */
1530         r300_mc_init(rdev);
1531         /* Fence driver */
1532         r = radeon_fence_driver_init(rdev);
1533         if (r)
1534                 return r;
1535         /* Memory manager */
1536         r = radeon_bo_init(rdev);
1537         if (r)
1538                 return r;
1539         if (rdev->flags & RADEON_IS_PCIE) {
1540                 r = rv370_pcie_gart_init(rdev);
1541                 if (r)
1542                         return r;
1543         }
1544         if (rdev->flags & RADEON_IS_PCI) {
1545                 r = r100_pci_gart_init(rdev);
1546                 if (r)
1547                         return r;
1548         }
1549         r300_set_reg_safe(rdev);
1550
1551         /* Initialize power management */
1552         radeon_pm_init(rdev);
1553
1554         rdev->accel_working = true;
1555         r = r300_startup(rdev);
1556         if (r) {
1557                 /* Something went wrong with the accel init, so stop accel */
1558                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1559                 r100_cp_fini(rdev);
1560                 radeon_wb_fini(rdev);
1561                 radeon_ib_pool_fini(rdev);
1562                 radeon_irq_kms_fini(rdev);
1563                 if (rdev->flags & RADEON_IS_PCIE)
1564                         rv370_pcie_gart_fini(rdev);
1565                 if (rdev->flags & RADEON_IS_PCI)
1566                         r100_pci_gart_fini(rdev);
1567                 radeon_agp_fini(rdev);
1568                 rdev->accel_working = false;
1569         }
1570         return 0;
1571 }