drivers/gpu/drm/nouveau/core/engine/software/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/os.h>
  26 #include <core/class.h>
  27 #include <core/engctx.h>
  28 #include <core/namedb.h>
  29 #include <core/handle.h>
  30 #include <core/gpuobj.h>
  31 #include <core/event.h>
  32
  33 #include <subdev/bar.h>
  34
  35 #include <engine/disp.h>
  36
  37 #include "nv50.h"
  38
  39 /*******************************************************************************
  40  * software object classes
  41  ******************************************************************************/
  42
  43 static int
  44 nv50_software_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd,
  45                               void *args, u32 size)
  46 {
  47         struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
  48         struct nouveau_fifo_chan *fifo = (void *)nv_object(chan)->parent;
  49         struct nouveau_handle *handle;
  50         int ret = -EINVAL;
  51
  52         handle = nouveau_namedb_get(nv_namedb(fifo), *(u32 *)args);
  53         if (!handle)
  54                 return -ENOENT;
  55
  56         if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) {
  57                 struct nouveau_gpuobj *gpuobj = nv_gpuobj(handle->object);
  58                 chan->vblank.ctxdma = gpuobj->node->offset >> 4;
  59                 ret = 0;
  60         }
  61         nouveau_namedb_put(handle);
  62         return ret;
  63 }
  64
  65 static int
  66 nv50_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
  67                                  void *args, u32 size)
  68 {
  69         struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
  70         chan->vblank.offset = *(u32 *)args;
  71         return 0;
  72 }
  73
  74 int
  75 nv50_software_mthd_vblsem_value(struct nouveau_object *object, u32 mthd,
  76                                 void *args, u32 size)
  77 {
  78         struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
  79         chan->vblank.value = *(u32 *)args;
  80         return 0;
  81 }
  82
  83 int
  84 nv50_software_mthd_vblsem_release(struct nouveau_object *object, u32 mthd,
  85                                   void *args, u32 size)
  86 {
  87         struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
  88         u32 head = *(u32 *)args;
  89         if (head >= chan->vblank.nr_event)
  90                 return -EINVAL;
  91
  92         nouveau_event_get(chan->vblank.event[head]);
  93         return 0;
  94 }
  95
  96 int
  97 nv50_software_mthd_flip(struct nouveau_object *object, u32 mthd,
  98                         void *args, u32 size)
  99 {
 100         struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
 101         if (chan->base.flip)
 102                 return chan->base.flip(chan->base.flip_data);
 103         return -EINVAL;
 104 }
 105
 106 static struct nouveau_omthds
 107 nv50_software_omthds[] = {
 108         { 0x018c, 0x018c, nv50_software_mthd_dma_vblsem },
 109         { 0x0400, 0x0400, nv50_software_mthd_vblsem_offset },
 110         { 0x0404, 0x0404, nv50_software_mthd_vblsem_value },
 111         { 0x0408, 0x0408, nv50_software_mthd_vblsem_release },
 112         { 0x0500, 0x0500, nv50_software_mthd_flip },
 113         {}
 114 };
 115
 116 static struct nouveau_oclass
 117 nv50_software_sclass[] = {
 118         { 0x506e, &nouveau_object_ofuncs, nv50_software_omthds },
 119         {}
 120 };
 121
 122 /*******************************************************************************
 123  * software context
 124  ******************************************************************************/
 125
 126 static int
 127 nv50_software_vblsem_release(void *data, int head)
 128 {
 129         struct nv50_software_chan *chan = data;
 130         struct nv50_software_priv *priv = (void *)nv_object(chan)->engine;
 131         struct nouveau_bar *bar = nouveau_bar(priv);
 132
 133         nv_wr32(priv, 0x001704, chan->vblank.channel);
 134         nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
 135         bar->flush(bar);
 136
 137         if (nv_device(priv)->chipset == 0x50) {
 138                 nv_wr32(priv, 0x001570, chan->vblank.offset);
 139                 nv_wr32(priv, 0x001574, chan->vblank.value);
 140         } else {
 141                 nv_wr32(priv, 0x060010, chan->vblank.offset);
 142                 nv_wr32(priv, 0x060014, chan->vblank.value);
 143         }
 144
 145         return NVKM_EVENT_DROP;
 146 }
 147
 148 void
 149 nv50_software_context_dtor(struct nouveau_object *object)
 150 {
 151         struct nv50_software_chan *chan = (void *)object;
 152         int i;
 153
 154         if (chan->vblank.event) {
 155                 for (i = 0; i < chan->vblank.nr_event; i++)
 156                         nouveau_event_ref(NULL, &chan->vblank.event[i]);
 157                 kfree(chan->vblank.event);
 158         }
 159
 160         nouveau_software_context_destroy(&chan->base);
 161 }
 162
 163 int
 164 nv50_software_context_ctor(struct nouveau_object *parent,
 165                            struct nouveau_object *engine,
 166                            struct nouveau_oclass *oclass, void *data, u32 size,
 167                            struct nouveau_object **pobject)
 168 {
 169         struct nouveau_disp *pdisp = nouveau_disp(parent);
 170         struct nv50_software_cclass *pclass = (void *)oclass;
 171         struct nv50_software_chan *chan;
 172         int ret, i;
 173
 174         ret = nouveau_software_context_create(parent, engine, oclass, &chan);
 175         *pobject = nv_object(chan);
 176         if (ret)
 177                 return ret;
 178
 179         chan->vblank.nr_event = pdisp ? pdisp->vblank->index_nr : 0;
 180         chan->vblank.event = kzalloc(chan->vblank.nr_event *
 181                                      sizeof(*chan->vblank.event), GFP_KERNEL);
 182         if (!chan->vblank.event)
 183                 return -ENOMEM;
 184
 185         for (i = 0; i < chan->vblank.nr_event; i++) {
 186                 ret = nouveau_event_new(pdisp->vblank, i, pclass->vblank,
 187                                         chan, &chan->vblank.event[i]);
 188                 if (ret)
 189                         return ret;
 190         }
 191
 192         chan->vblank.channel = nv_gpuobj(parent->parent)->addr >> 12;
 193         return 0;
 194 }
 195
 196 static struct nv50_software_cclass
 197 nv50_software_cclass = {
 198         .base.handle = NV_ENGCTX(SW, 0x50),
 199         .base.ofuncs = &(struct nouveau_ofuncs) {
 200                 .ctor = nv50_software_context_ctor,
 201                 .dtor = _nouveau_software_context_dtor,
 202                 .init = _nouveau_software_context_init,
 203                 .fini = _nouveau_software_context_fini,
 204         },
 205         .vblank = nv50_software_vblsem_release,
 206 };
 207
 208 /*******************************************************************************
 209  * software engine/subdev functions
 210  ******************************************************************************/
 211
 212 int
 213 nv50_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 214                    struct nouveau_oclass *oclass, void *data, u32 size,
 215                    struct nouveau_object **pobject)
 216 {
 217         struct nv50_software_oclass *pclass = (void *)oclass;
 218         struct nv50_software_priv *priv;
 219         int ret;
 220
 221         ret = nouveau_software_create(parent, engine, oclass, &priv);
 222         *pobject = nv_object(priv);
 223         if (ret)
 224                 return ret;
 225
 226         nv_engine(priv)->cclass = pclass->cclass;
 227         nv_engine(priv)->sclass = pclass->sclass;
 228         nv_subdev(priv)->intr = nv04_software_intr;
 229         return 0;
 230 }
 231
 232 struct nouveau_oclass *
 233 nv50_software_oclass = &(struct nv50_software_oclass) {
 234         .base.handle = NV_ENGINE(SW, 0x50),
 235         .base.ofuncs = &(struct nouveau_ofuncs) {
 236                 .ctor = nv50_software_ctor,
 237                 .dtor = _nouveau_software_dtor,
 238                 .init = _nouveau_software_init,
 239                 .fini = _nouveau_software_fini,
 240         },
 241         .cclass = &nv50_software_cclass.base,
 242         .sclass =  nv50_software_sclass,
 243 }.base;