2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138 #include "intel_mocs.h"
140 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
144 #define RING_EXECLIST_QFULL (1 << 0x2)
145 #define RING_EXECLIST1_VALID (1 << 0x3)
146 #define RING_EXECLIST0_VALID (1 << 0x4)
147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
148 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
149 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
158 #define CTX_LRI_HEADER_0 0x01
159 #define CTX_CONTEXT_CONTROL 0x02
160 #define CTX_RING_HEAD 0x04
161 #define CTX_RING_TAIL 0x06
162 #define CTX_RING_BUFFER_START 0x08
163 #define CTX_RING_BUFFER_CONTROL 0x0a
164 #define CTX_BB_HEAD_U 0x0c
165 #define CTX_BB_HEAD_L 0x0e
166 #define CTX_BB_STATE 0x10
167 #define CTX_SECOND_BB_HEAD_U 0x12
168 #define CTX_SECOND_BB_HEAD_L 0x14
169 #define CTX_SECOND_BB_STATE 0x16
170 #define CTX_BB_PER_CTX_PTR 0x18
171 #define CTX_RCS_INDIRECT_CTX 0x1a
172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
173 #define CTX_LRI_HEADER_1 0x21
174 #define CTX_CTX_TIMESTAMP 0x22
175 #define CTX_PDP3_UDW 0x24
176 #define CTX_PDP3_LDW 0x26
177 #define CTX_PDP2_UDW 0x28
178 #define CTX_PDP2_LDW 0x2a
179 #define CTX_PDP1_UDW 0x2c
180 #define CTX_PDP1_LDW 0x2e
181 #define CTX_PDP0_UDW 0x30
182 #define CTX_PDP0_LDW 0x32
183 #define CTX_LRI_HEADER_2 0x41
184 #define CTX_R_PWR_CLK_STATE 0x42
185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
187 #define GEN8_CTX_VALID (1<<0)
188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
189 #define GEN8_CTX_FORCE_RESTORE (1<<2)
190 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
191 #define GEN8_CTX_PRIVILEGE (1<<8)
193 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
194 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
195 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
196 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
200 ADVANCED_CONTEXT = 0,
205 #define GEN8_CTX_MODE_SHIFT 3
208 FAULT_AND_HALT, /* Debug only */
210 FAULT_AND_CONTINUE /* Unsupported */
212 #define GEN8_CTX_ID_SHIFT 32
213 #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
215 static int intel_lr_context_pin(struct drm_i915_gem_request *rq);
218 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
220 * @enable_execlists: value of i915.enable_execlists module parameter.
222 * Only certain platforms support Execlists (the prerequisites being
223 * support for Logical Ring Contexts and Aliasing PPGTT or better).
225 * Return: 1 if Execlists is supported and has to be enabled.
227 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
229 WARN_ON(i915.enable_ppgtt == -1);
231 if (INTEL_INFO(dev)->gen >= 9)
234 if (enable_execlists == 0)
237 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
238 i915.use_mmio_flip >= 0)
245 * intel_execlists_ctx_id() - get the Execlists Context ID
246 * @ctx_obj: Logical Ring Context backing object.
248 * Do not confuse with ctx->id! Unfortunately we have a name overload
249 * here: the old context ID we pass to userspace as a handler so that
250 * they can refer to a context, and the new context ID we pass to the
251 * ELSP so that the GPU can inform us of the context status via
254 * Return: 20-bits globally unique context ID.
256 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
258 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
260 /* LRCA is required to be 4K aligned so the more significant 20 bits
261 * are globally unique */
265 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_request *rq)
267 struct intel_engine_cs *ring = rq->ring;
268 struct drm_device *dev = ring->dev;
269 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
271 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
273 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
275 desc = GEN8_CTX_VALID;
276 desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
277 if (IS_GEN8(ctx_obj->base.dev))
278 desc |= GEN8_CTX_L3LLC_COHERENT;
279 desc |= GEN8_CTX_PRIVILEGE;
281 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
283 /* TODO: WaDisableLiteRestore when we start using semaphore
284 * signalling between Command Streamers */
285 /* desc |= GEN8_CTX_FORCE_RESTORE; */
287 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
289 INTEL_REVID(dev) <= SKL_REVID_B0 &&
290 (ring->id == BCS || ring->id == VCS ||
291 ring->id == VECS || ring->id == VCS2))
292 desc |= GEN8_CTX_FORCE_RESTORE;
297 static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
298 struct drm_i915_gem_request *rq1)
301 struct intel_engine_cs *ring = rq0->ring;
302 struct drm_device *dev = ring->dev;
303 struct drm_i915_private *dev_priv = dev->dev_private;
307 desc[1] = execlists_ctx_descriptor(rq1);
308 rq1->elsp_submitted++;
313 desc[0] = execlists_ctx_descriptor(rq0);
314 rq0->elsp_submitted++;
316 /* You must always write both descriptors in the order below. */
317 spin_lock(&dev_priv->uncore.lock);
318 intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
319 I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1]));
320 I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1]));
322 I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[0]));
323 /* The context is automatically loaded after the following */
324 I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0]));
326 /* ELSP is a wo register, use another nearby reg for posting */
327 POSTING_READ_FW(RING_EXECLIST_STATUS(ring));
328 intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
329 spin_unlock(&dev_priv->uncore.lock);
332 static int execlists_update_context(struct drm_i915_gem_request *rq)
334 struct intel_engine_cs *ring = rq->ring;
335 struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
336 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
337 struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
342 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj));
343 WARN_ON(!i915_gem_obj_is_pinned(rb_obj));
345 page = i915_gem_object_get_page(ctx_obj, 1);
346 reg_state = kmap_atomic(page);
348 reg_state[CTX_RING_TAIL+1] = rq->tail;
349 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
351 /* True PPGTT with dynamic page allocation: update PDP registers and
352 * point the unallocated PDPs to the scratch page
355 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
356 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
357 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
358 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
361 kunmap_atomic(reg_state);
366 static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
367 struct drm_i915_gem_request *rq1)
369 execlists_update_context(rq0);
372 execlists_update_context(rq1);
374 execlists_elsp_write(rq0, rq1);
377 static void execlists_context_unqueue(struct intel_engine_cs *ring)
379 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
380 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
382 assert_spin_locked(&ring->execlist_lock);
385 * If irqs are not active generate a warning as batches that finish
386 * without the irqs may get lost and a GPU Hang may occur.
388 WARN_ON(!intel_irqs_enabled(ring->dev->dev_private));
390 if (list_empty(&ring->execlist_queue))
393 /* Try to read in pairs */
394 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
398 } else if (req0->ctx == cursor->ctx) {
399 /* Same ctx: ignore first request, as second request
400 * will update tail past first request's workload */
401 cursor->elsp_submitted = req0->elsp_submitted;
402 list_del(&req0->execlist_link);
403 list_add_tail(&req0->execlist_link,
404 &ring->execlist_retired_req_list);
412 if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
414 * WaIdleLiteRestore: make sure we never cause a lite
415 * restore with HEAD==TAIL
417 if (req0->elsp_submitted) {
419 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
420 * as we resubmit the request. See gen8_emit_request()
421 * for where we prepare the padding after the end of the
424 struct intel_ringbuffer *ringbuf;
426 ringbuf = req0->ctx->engine[ring->id].ringbuf;
428 req0->tail &= ringbuf->size - 1;
432 WARN_ON(req1 && req1->elsp_submitted);
434 execlists_submit_requests(req0, req1);
437 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
440 struct drm_i915_gem_request *head_req;
442 assert_spin_locked(&ring->execlist_lock);
444 head_req = list_first_entry_or_null(&ring->execlist_queue,
445 struct drm_i915_gem_request,
448 if (head_req != NULL) {
449 struct drm_i915_gem_object *ctx_obj =
450 head_req->ctx->engine[ring->id].state;
451 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
452 WARN(head_req->elsp_submitted == 0,
453 "Never submitted head request\n");
455 if (--head_req->elsp_submitted <= 0) {
456 list_del(&head_req->execlist_link);
457 list_add_tail(&head_req->execlist_link,
458 &ring->execlist_retired_req_list);
468 * intel_lrc_irq_handler() - handle Context Switch interrupts
469 * @ring: Engine Command Streamer to handle.
471 * Check the unread Context Status Buffers and manage the submission of new
472 * contexts to the ELSP accordingly.
474 void intel_lrc_irq_handler(struct intel_engine_cs *ring)
476 struct drm_i915_private *dev_priv = ring->dev->dev_private;
482 u32 submit_contexts = 0;
484 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
486 read_pointer = ring->next_context_status_buffer;
487 write_pointer = status_pointer & 0x07;
488 if (read_pointer > write_pointer)
491 spin_lock(&ring->execlist_lock);
493 while (read_pointer < write_pointer) {
495 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
496 (read_pointer % 6) * 8);
497 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
498 (read_pointer % 6) * 8 + 4);
500 if (status & GEN8_CTX_STATUS_PREEMPTED) {
501 if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
502 if (execlists_check_remove_request(ring, status_id))
503 WARN(1, "Lite Restored request removed from queue\n");
505 WARN(1, "Preemption without Lite Restore\n");
508 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
509 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
510 if (execlists_check_remove_request(ring, status_id))
515 if (submit_contexts != 0)
516 execlists_context_unqueue(ring);
518 spin_unlock(&ring->execlist_lock);
520 WARN(submit_contexts > 2, "More than two context complete events?\n");
521 ring->next_context_status_buffer = write_pointer % 6;
523 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
524 ((u32)ring->next_context_status_buffer & 0x07) << 8);
527 static int execlists_context_queue(struct drm_i915_gem_request *request)
529 struct intel_engine_cs *ring = request->ring;
530 struct drm_i915_gem_request *cursor;
531 int num_elements = 0;
533 if (request->ctx != ring->default_context)
534 intel_lr_context_pin(request);
536 i915_gem_request_reference(request);
538 request->tail = request->ringbuf->tail;
540 spin_lock_irq(&ring->execlist_lock);
542 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
543 if (++num_elements > 2)
546 if (num_elements > 2) {
547 struct drm_i915_gem_request *tail_req;
549 tail_req = list_last_entry(&ring->execlist_queue,
550 struct drm_i915_gem_request,
553 if (request->ctx == tail_req->ctx) {
554 WARN(tail_req->elsp_submitted != 0,
555 "More than 2 already-submitted reqs queued\n");
556 list_del(&tail_req->execlist_link);
557 list_add_tail(&tail_req->execlist_link,
558 &ring->execlist_retired_req_list);
562 list_add_tail(&request->execlist_link, &ring->execlist_queue);
563 if (num_elements == 0)
564 execlists_context_unqueue(ring);
566 spin_unlock_irq(&ring->execlist_lock);
571 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
573 struct intel_engine_cs *ring = req->ring;
574 uint32_t flush_domains;
578 if (ring->gpu_caches_dirty)
579 flush_domains = I915_GEM_GPU_DOMAINS;
581 ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
585 ring->gpu_caches_dirty = false;
589 static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
590 struct list_head *vmas)
592 const unsigned other_rings = ~intel_ring_flag(req->ring);
593 struct i915_vma *vma;
594 uint32_t flush_domains = 0;
595 bool flush_chipset = false;
598 list_for_each_entry(vma, vmas, exec_list) {
599 struct drm_i915_gem_object *obj = vma->obj;
601 if (obj->active & other_rings) {
602 ret = i915_gem_object_sync(obj, req->ring, &req);
607 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
608 flush_chipset |= i915_gem_clflush_object(obj, false);
610 flush_domains |= obj->base.write_domain;
613 if (flush_domains & I915_GEM_DOMAIN_GTT)
616 /* Unconditionally invalidate gpu caches and ensure that we do flush
617 * any residual writes from the previous batch.
619 return logical_ring_invalidate_all_caches(req);
622 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
626 request->ringbuf = request->ctx->engine[request->ring->id].ringbuf;
628 if (request->ctx != request->ring->default_context) {
629 ret = intel_lr_context_pin(request);
637 static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,
640 struct intel_ringbuffer *ringbuf = req->ringbuf;
641 struct intel_engine_cs *ring = req->ring;
642 struct drm_i915_gem_request *target;
646 if (intel_ring_space(ringbuf) >= bytes)
649 /* The whole point of reserving space is to not wait! */
650 WARN_ON(ringbuf->reserved_in_use);
652 list_for_each_entry(target, &ring->request_list, list) {
654 * The request queue is per-engine, so can contain requests
655 * from multiple ringbuffers. Here, we must ignore any that
656 * aren't from the ringbuffer we're considering.
658 if (target->ringbuf != ringbuf)
661 /* Would completion of this request free enough space? */
662 space = __intel_ring_space(target->postfix, ringbuf->tail,
668 if (WARN_ON(&target->list == &ring->request_list))
671 ret = i915_wait_request(target);
675 ringbuf->space = space;
680 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
681 * @request: Request to advance the logical ringbuffer of.
683 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
684 * really happens during submission is that the context and current tail will be placed
685 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
686 * point, the tail *inside* the context is updated and the ELSP written to.
689 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
691 struct intel_engine_cs *ring = request->ring;
693 intel_logical_ring_advance(request->ringbuf);
695 if (intel_ring_stopped(ring))
698 execlists_context_queue(request);
701 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
703 uint32_t __iomem *virt;
704 int rem = ringbuf->size - ringbuf->tail;
706 virt = ringbuf->virtual_start + ringbuf->tail;
709 iowrite32(MI_NOOP, virt++);
712 intel_ring_update_space(ringbuf);
715 static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
717 struct intel_ringbuffer *ringbuf = req->ringbuf;
718 int remain_usable = ringbuf->effective_size - ringbuf->tail;
719 int remain_actual = ringbuf->size - ringbuf->tail;
720 int ret, total_bytes, wait_bytes = 0;
721 bool need_wrap = false;
723 if (ringbuf->reserved_in_use)
726 total_bytes = bytes + ringbuf->reserved_size;
728 if (unlikely(bytes > remain_usable)) {
730 * Not enough space for the basic request. So need to flush
731 * out the remainder and then wait for base + reserved.
733 wait_bytes = remain_actual + total_bytes;
736 if (unlikely(total_bytes > remain_usable)) {
738 * The base request will fit but the reserved space
739 * falls off the end. So only need to to wait for the
740 * reserved size after flushing out the remainder.
742 wait_bytes = remain_actual + ringbuf->reserved_size;
744 } else if (total_bytes > ringbuf->space) {
745 /* No wrapping required, just waiting. */
746 wait_bytes = total_bytes;
751 ret = logical_ring_wait_for_space(req, wait_bytes);
756 __wrap_ring_buffer(ringbuf);
763 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
765 * @request: The request to start some new work for
766 * @ctx: Logical ring context whose ringbuffer is being prepared.
767 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
769 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
770 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
771 * and also preallocates a request (every workload submission is still mediated through
772 * requests, same as it did with legacy ringbuffer submission).
774 * Return: non-zero if the ringbuffer is not ready to be written to.
776 int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
778 struct drm_i915_private *dev_priv;
781 WARN_ON(req == NULL);
782 dev_priv = req->ring->dev->dev_private;
784 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
785 dev_priv->mm.interruptible);
789 ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t));
793 req->ringbuf->space -= num_dwords * sizeof(uint32_t);
797 int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
800 * The first call merely notes the reserve request and is common for
801 * all back ends. The subsequent localised _begin() call actually
802 * ensures that the reservation is available. Without the begin, if
803 * the request creator immediately submitted the request without
804 * adding any commands to it then there might not actually be
805 * sufficient room for the submission commands.
807 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
809 return intel_logical_ring_begin(request, 0);
813 * execlists_submission() - submit a batchbuffer for execution, Execlists style
816 * @ring: Engine Command Streamer to submit to.
817 * @ctx: Context to employ for this submission.
818 * @args: execbuffer call arguments.
819 * @vmas: list of vmas.
820 * @batch_obj: the batchbuffer to submit.
821 * @exec_start: batchbuffer start virtual address pointer.
822 * @dispatch_flags: translated execbuffer call flags.
824 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
825 * away the submission details of the execbuffer ioctl call.
827 * Return: non-zero if the submission fails.
829 int intel_execlists_submission(struct i915_execbuffer_params *params,
830 struct drm_i915_gem_execbuffer2 *args,
831 struct list_head *vmas)
833 struct drm_device *dev = params->dev;
834 struct intel_engine_cs *ring = params->ring;
835 struct drm_i915_private *dev_priv = dev->dev_private;
836 struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf;
842 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
843 instp_mask = I915_EXEC_CONSTANTS_MASK;
844 switch (instp_mode) {
845 case I915_EXEC_CONSTANTS_REL_GENERAL:
846 case I915_EXEC_CONSTANTS_ABSOLUTE:
847 case I915_EXEC_CONSTANTS_REL_SURFACE:
848 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
849 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
853 if (instp_mode != dev_priv->relative_constants_mode) {
854 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
855 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
859 /* The HW changed the meaning on this bit on gen6 */
860 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
864 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
868 if (args->num_cliprects != 0) {
869 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
872 if (args->DR4 == 0xffffffff) {
873 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
877 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
878 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
883 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
884 DRM_DEBUG("sol reset is gen7 only\n");
888 ret = execlists_move_to_gpu(params->request, vmas);
892 if (ring == &dev_priv->ring[RCS] &&
893 instp_mode != dev_priv->relative_constants_mode) {
894 ret = intel_logical_ring_begin(params->request, 4);
898 intel_logical_ring_emit(ringbuf, MI_NOOP);
899 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
900 intel_logical_ring_emit(ringbuf, INSTPM);
901 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
902 intel_logical_ring_advance(ringbuf);
904 dev_priv->relative_constants_mode = instp_mode;
907 exec_start = params->batch_obj_vm_offset +
908 args->batch_start_offset;
910 ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags);
914 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
916 i915_gem_execbuffer_move_to_active(vmas, params->request);
917 i915_gem_execbuffer_retire_commands(params);
922 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
924 struct drm_i915_gem_request *req, *tmp;
925 struct list_head retired_list;
927 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
928 if (list_empty(&ring->execlist_retired_req_list))
931 INIT_LIST_HEAD(&retired_list);
932 spin_lock_irq(&ring->execlist_lock);
933 list_replace_init(&ring->execlist_retired_req_list, &retired_list);
934 spin_unlock_irq(&ring->execlist_lock);
936 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
937 struct intel_context *ctx = req->ctx;
938 struct drm_i915_gem_object *ctx_obj =
939 ctx->engine[ring->id].state;
941 if (ctx_obj && (ctx != ring->default_context))
942 intel_lr_context_unpin(req);
943 list_del(&req->execlist_link);
944 i915_gem_request_unreference(req);
948 void intel_logical_ring_stop(struct intel_engine_cs *ring)
950 struct drm_i915_private *dev_priv = ring->dev->dev_private;
953 if (!intel_ring_initialized(ring))
956 ret = intel_ring_idle(ring);
957 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
958 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
961 /* TODO: Is this correct with Execlists enabled? */
962 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
963 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
964 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
967 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
970 int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
972 struct intel_engine_cs *ring = req->ring;
975 if (!ring->gpu_caches_dirty)
978 ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
982 ring->gpu_caches_dirty = false;
986 static int intel_lr_context_pin(struct drm_i915_gem_request *rq)
988 struct intel_engine_cs *ring = rq->ring;
989 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
990 struct intel_ringbuffer *ringbuf = rq->ringbuf;
993 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
994 if (rq->ctx->engine[ring->id].pin_count++ == 0) {
995 ret = i915_gem_obj_ggtt_pin(ctx_obj,
996 GEN8_LR_CONTEXT_ALIGN, 0);
998 goto reset_pin_count;
1000 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
1008 i915_gem_object_ggtt_unpin(ctx_obj);
1010 rq->ctx->engine[ring->id].pin_count = 0;
1015 void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
1017 struct intel_engine_cs *ring = rq->ring;
1018 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
1019 struct intel_ringbuffer *ringbuf = rq->ringbuf;
1022 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1023 if (--rq->ctx->engine[ring->id].pin_count == 0) {
1024 intel_unpin_ringbuffer_obj(ringbuf);
1025 i915_gem_object_ggtt_unpin(ctx_obj);
1030 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
1033 struct intel_engine_cs *ring = req->ring;
1034 struct intel_ringbuffer *ringbuf = req->ringbuf;
1035 struct drm_device *dev = ring->dev;
1036 struct drm_i915_private *dev_priv = dev->dev_private;
1037 struct i915_workarounds *w = &dev_priv->workarounds;
1039 if (WARN_ON_ONCE(w->count == 0))
1042 ring->gpu_caches_dirty = true;
1043 ret = logical_ring_flush_all_caches(req);
1047 ret = intel_logical_ring_begin(req, w->count * 2 + 2);
1051 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1052 for (i = 0; i < w->count; i++) {
1053 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1054 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1056 intel_logical_ring_emit(ringbuf, MI_NOOP);
1058 intel_logical_ring_advance(ringbuf);
1060 ring->gpu_caches_dirty = true;
1061 ret = logical_ring_flush_all_caches(req);
1068 #define wa_ctx_emit(batch, index, cmd) \
1070 int __index = (index)++; \
1071 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1074 batch[__index] = (cmd); \
1079 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1080 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1081 * but there is a slight complication as this is applied in WA batch where the
1082 * values are only initialized once so we cannot take register value at the
1083 * beginning and reuse it further; hence we save its value to memory, upload a
1084 * constant value with bit21 set and then we restore it back with the saved value.
1085 * To simplify the WA, a constant value is formed by using the default value
1086 * of this register. This shouldn't be a problem because we are only modifying
1087 * it for a short period and this batch in non-premptible. We can ofcourse
1088 * use additional instructions that read the actual value of the register
1089 * at that time and set our bit of interest but it makes the WA complicated.
1091 * This WA is also required for Gen9 so extracting as a function avoids
1094 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
1095 uint32_t *const batch,
1098 uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
1101 * WaDisableLSQCROPERFforOCL:skl
1102 * This WA is implemented in skl_init_clock_gating() but since
1103 * this batch updates GEN8_L3SQCREG4 with default value we need to
1104 * set this bit here to retain the WA during flush.
1106 if (IS_SKYLAKE(ring->dev) && INTEL_REVID(ring->dev) <= SKL_REVID_E0)
1107 l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
1109 wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8(1) |
1110 MI_SRM_LRM_GLOBAL_GTT));
1111 wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
1112 wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
1113 wa_ctx_emit(batch, index, 0);
1115 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1116 wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
1117 wa_ctx_emit(batch, index, l3sqc4_flush);
1119 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1120 wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
1121 PIPE_CONTROL_DC_FLUSH_ENABLE));
1122 wa_ctx_emit(batch, index, 0);
1123 wa_ctx_emit(batch, index, 0);
1124 wa_ctx_emit(batch, index, 0);
1125 wa_ctx_emit(batch, index, 0);
1127 wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8(1) |
1128 MI_SRM_LRM_GLOBAL_GTT));
1129 wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
1130 wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
1131 wa_ctx_emit(batch, index, 0);
1136 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
1138 uint32_t start_alignment)
1140 return wa_ctx->offset = ALIGN(offset, start_alignment);
1143 static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
1145 uint32_t size_alignment)
1147 wa_ctx->size = offset - wa_ctx->offset;
1149 WARN(wa_ctx->size % size_alignment,
1150 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1151 wa_ctx->size, size_alignment);
1156 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1158 * @ring: only applicable for RCS
1159 * @wa_ctx: structure representing wa_ctx
1160 * offset: specifies start of the batch, should be cache-aligned. This is updated
1161 * with the offset value received as input.
1162 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1163 * @batch: page in which WA are loaded
1164 * @offset: This field specifies the start of the batch, it should be
1165 * cache-aligned otherwise it is adjusted accordingly.
1166 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1167 * initialized at the beginning and shared across all contexts but this field
1168 * helps us to have multiple batches at different offsets and select them based
1169 * on a criteria. At the moment this batch always start at the beginning of the page
1170 * and at this point we don't have multiple wa_ctx batch buffers.
1172 * The number of WA applied are not known at the beginning; we use this field
1173 * to return the no of DWORDS written.
1175 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1176 * so it adds NOOPs as padding to make it cacheline aligned.
1177 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1178 * makes a complete batch buffer.
1180 * Return: non-zero if we exceed the PAGE_SIZE limit.
1183 static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
1184 struct i915_wa_ctx_bb *wa_ctx,
1185 uint32_t *const batch,
1188 uint32_t scratch_addr;
1189 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1191 /* WaDisableCtxRestoreArbitration:bdw,chv */
1192 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1194 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1195 if (IS_BROADWELL(ring->dev)) {
1196 index = gen8_emit_flush_coherentl3_wa(ring, batch, index);
1201 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1202 /* Actual scratch location is at 128 bytes offset */
1203 scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES;
1205 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1206 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1207 PIPE_CONTROL_GLOBAL_GTT_IVB |
1208 PIPE_CONTROL_CS_STALL |
1209 PIPE_CONTROL_QW_WRITE));
1210 wa_ctx_emit(batch, index, scratch_addr);
1211 wa_ctx_emit(batch, index, 0);
1212 wa_ctx_emit(batch, index, 0);
1213 wa_ctx_emit(batch, index, 0);
1215 /* Pad to end of cacheline */
1216 while (index % CACHELINE_DWORDS)
1217 wa_ctx_emit(batch, index, MI_NOOP);
1220 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1221 * execution depends on the length specified in terms of cache lines
1222 * in the register CTX_RCS_INDIRECT_CTX
1225 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1229 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1231 * @ring: only applicable for RCS
1232 * @wa_ctx: structure representing wa_ctx
1233 * offset: specifies start of the batch, should be cache-aligned.
1234 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1235 * @batch: page in which WA are loaded
1236 * @offset: This field specifies the start of this batch.
1237 * This batch is started immediately after indirect_ctx batch. Since we ensure
1238 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1240 * The number of DWORDS written are returned using this field.
1242 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1243 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1245 static int gen8_init_perctx_bb(struct intel_engine_cs *ring,
1246 struct i915_wa_ctx_bb *wa_ctx,
1247 uint32_t *const batch,
1250 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1252 /* WaDisableCtxRestoreArbitration:bdw,chv */
1253 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1255 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1257 return wa_ctx_end(wa_ctx, *offset = index, 1);
1260 static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
1261 struct i915_wa_ctx_bb *wa_ctx,
1262 uint32_t *const batch,
1266 struct drm_device *dev = ring->dev;
1267 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1269 /* WaDisableCtxRestoreArbitration:skl,bxt */
1270 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) ||
1271 (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))
1272 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1274 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1275 ret = gen8_emit_flush_coherentl3_wa(ring, batch, index);
1280 /* Pad to end of cacheline */
1281 while (index % CACHELINE_DWORDS)
1282 wa_ctx_emit(batch, index, MI_NOOP);
1284 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1287 static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
1288 struct i915_wa_ctx_bb *wa_ctx,
1289 uint32_t *const batch,
1292 struct drm_device *dev = ring->dev;
1293 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1295 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1296 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
1297 (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
1298 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1299 wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1300 wa_ctx_emit(batch, index,
1301 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
1302 wa_ctx_emit(batch, index, MI_NOOP);
1305 /* WaDisableCtxRestoreArbitration:skl,bxt */
1306 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) ||
1307 (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))
1308 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1310 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1312 return wa_ctx_end(wa_ctx, *offset = index, 1);
1315 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
1319 ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size));
1320 if (!ring->wa_ctx.obj) {
1321 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1325 ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0);
1327 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1329 drm_gem_object_unreference(&ring->wa_ctx.obj->base);
1336 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring)
1338 if (ring->wa_ctx.obj) {
1339 i915_gem_object_ggtt_unpin(ring->wa_ctx.obj);
1340 drm_gem_object_unreference(&ring->wa_ctx.obj->base);
1341 ring->wa_ctx.obj = NULL;
1345 static int intel_init_workaround_bb(struct intel_engine_cs *ring)
1351 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
1353 WARN_ON(ring->id != RCS);
1355 /* update this when WA for higher Gen are added */
1356 if (INTEL_INFO(ring->dev)->gen > 9) {
1357 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1358 INTEL_INFO(ring->dev)->gen);
1362 /* some WA perform writes to scratch page, ensure it is valid */
1363 if (ring->scratch.obj == NULL) {
1364 DRM_ERROR("scratch page not allocated for %s\n", ring->name);
1368 ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE);
1370 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1374 page = i915_gem_object_get_page(wa_ctx->obj, 0);
1375 batch = kmap_atomic(page);
1378 if (INTEL_INFO(ring->dev)->gen == 8) {
1379 ret = gen8_init_indirectctx_bb(ring,
1380 &wa_ctx->indirect_ctx,
1386 ret = gen8_init_perctx_bb(ring,
1392 } else if (INTEL_INFO(ring->dev)->gen == 9) {
1393 ret = gen9_init_indirectctx_bb(ring,
1394 &wa_ctx->indirect_ctx,
1400 ret = gen9_init_perctx_bb(ring,
1409 kunmap_atomic(batch);
1411 lrc_destroy_wa_ctx_obj(ring);
1416 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1418 struct drm_device *dev = ring->dev;
1419 struct drm_i915_private *dev_priv = dev->dev_private;
1421 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1422 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1424 if (ring->status_page.obj) {
1425 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1426 (u32)ring->status_page.gfx_addr);
1427 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1430 I915_WRITE(RING_MODE_GEN7(ring),
1431 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1432 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1433 POSTING_READ(RING_MODE_GEN7(ring));
1434 ring->next_context_status_buffer = 0;
1435 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1437 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1442 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1444 struct drm_device *dev = ring->dev;
1445 struct drm_i915_private *dev_priv = dev->dev_private;
1448 ret = gen8_init_common_ring(ring);
1452 /* We need to disable the AsyncFlip performance optimisations in order
1453 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1454 * programmed to '1' on all products.
1456 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1458 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1460 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1462 return init_workarounds_ring(ring);
1465 static int gen9_init_render_ring(struct intel_engine_cs *ring)
1469 ret = gen8_init_common_ring(ring);
1473 return init_workarounds_ring(ring);
1476 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1478 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1479 struct intel_engine_cs *ring = req->ring;
1480 struct intel_ringbuffer *ringbuf = req->ringbuf;
1481 const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
1484 ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2);
1488 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
1489 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
1490 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1492 intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i));
1493 intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
1494 intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i));
1495 intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
1498 intel_logical_ring_emit(ringbuf, MI_NOOP);
1499 intel_logical_ring_advance(ringbuf);
1504 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1505 u64 offset, unsigned dispatch_flags)
1507 struct intel_ringbuffer *ringbuf = req->ringbuf;
1508 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1511 /* Don't rely in hw updating PDPs, specially in lite-restore.
1512 * Ideally, we should set Force PD Restore in ctx descriptor,
1513 * but we can't. Force Restore would be a second option, but
1514 * it is unsafe in case of lite-restore (because the ctx is
1516 if (req->ctx->ppgtt &&
1517 (intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) {
1518 ret = intel_logical_ring_emit_pdps(req);
1522 req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring);
1525 ret = intel_logical_ring_begin(req, 4);
1529 /* FIXME(BDW): Address space and security selectors. */
1530 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
1532 (dispatch_flags & I915_DISPATCH_RS ?
1533 MI_BATCH_RESOURCE_STREAMER : 0));
1534 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1535 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1536 intel_logical_ring_emit(ringbuf, MI_NOOP);
1537 intel_logical_ring_advance(ringbuf);
1542 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1544 struct drm_device *dev = ring->dev;
1545 struct drm_i915_private *dev_priv = dev->dev_private;
1546 unsigned long flags;
1548 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1551 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1552 if (ring->irq_refcount++ == 0) {
1553 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1554 POSTING_READ(RING_IMR(ring->mmio_base));
1556 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1561 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1563 struct drm_device *dev = ring->dev;
1564 struct drm_i915_private *dev_priv = dev->dev_private;
1565 unsigned long flags;
1567 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1568 if (--ring->irq_refcount == 0) {
1569 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1570 POSTING_READ(RING_IMR(ring->mmio_base));
1572 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1575 static int gen8_emit_flush(struct drm_i915_gem_request *request,
1576 u32 invalidate_domains,
1579 struct intel_ringbuffer *ringbuf = request->ringbuf;
1580 struct intel_engine_cs *ring = ringbuf->ring;
1581 struct drm_device *dev = ring->dev;
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1586 ret = intel_logical_ring_begin(request, 4);
1590 cmd = MI_FLUSH_DW + 1;
1592 /* We always require a command barrier so that subsequent
1593 * commands, such as breadcrumb interrupts, are strictly ordered
1594 * wrt the contents of the write cache being flushed to memory
1595 * (and thus being coherent from the CPU).
1597 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1599 if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1600 cmd |= MI_INVALIDATE_TLB;
1601 if (ring == &dev_priv->ring[VCS])
1602 cmd |= MI_INVALIDATE_BSD;
1605 intel_logical_ring_emit(ringbuf, cmd);
1606 intel_logical_ring_emit(ringbuf,
1607 I915_GEM_HWS_SCRATCH_ADDR |
1608 MI_FLUSH_DW_USE_GTT);
1609 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1610 intel_logical_ring_emit(ringbuf, 0); /* value */
1611 intel_logical_ring_advance(ringbuf);
1616 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1617 u32 invalidate_domains,
1620 struct intel_ringbuffer *ringbuf = request->ringbuf;
1621 struct intel_engine_cs *ring = ringbuf->ring;
1622 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1627 flags |= PIPE_CONTROL_CS_STALL;
1629 if (flush_domains) {
1630 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1631 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1634 if (invalidate_domains) {
1635 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1636 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1637 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1638 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1639 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1640 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1641 flags |= PIPE_CONTROL_QW_WRITE;
1642 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1646 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
1649 vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
1650 flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
1652 ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6);
1657 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1658 intel_logical_ring_emit(ringbuf, 0);
1659 intel_logical_ring_emit(ringbuf, 0);
1660 intel_logical_ring_emit(ringbuf, 0);
1661 intel_logical_ring_emit(ringbuf, 0);
1662 intel_logical_ring_emit(ringbuf, 0);
1665 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1666 intel_logical_ring_emit(ringbuf, flags);
1667 intel_logical_ring_emit(ringbuf, scratch_addr);
1668 intel_logical_ring_emit(ringbuf, 0);
1669 intel_logical_ring_emit(ringbuf, 0);
1670 intel_logical_ring_emit(ringbuf, 0);
1671 intel_logical_ring_advance(ringbuf);
1676 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1678 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1681 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1683 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1686 static int gen8_emit_request(struct drm_i915_gem_request *request)
1688 struct intel_ringbuffer *ringbuf = request->ringbuf;
1689 struct intel_engine_cs *ring = ringbuf->ring;
1694 * Reserve space for 2 NOOPs at the end of each request to be
1695 * used as a workaround for not being allowed to do lite
1696 * restore with HEAD==TAIL (WaIdleLiteRestore).
1698 ret = intel_logical_ring_begin(request, 8);
1702 cmd = MI_STORE_DWORD_IMM_GEN4;
1703 cmd |= MI_GLOBAL_GTT;
1705 intel_logical_ring_emit(ringbuf, cmd);
1706 intel_logical_ring_emit(ringbuf,
1707 (ring->status_page.gfx_addr +
1708 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1709 intel_logical_ring_emit(ringbuf, 0);
1710 intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1711 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1712 intel_logical_ring_emit(ringbuf, MI_NOOP);
1713 intel_logical_ring_advance_and_submit(request);
1716 * Here we add two extra NOOPs as padding to avoid
1717 * lite restore of a context with HEAD==TAIL.
1719 intel_logical_ring_emit(ringbuf, MI_NOOP);
1720 intel_logical_ring_emit(ringbuf, MI_NOOP);
1721 intel_logical_ring_advance(ringbuf);
1726 static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
1728 struct render_state so;
1731 ret = i915_gem_render_state_prepare(req->ring, &so);
1735 if (so.rodata == NULL)
1738 ret = req->ring->emit_bb_start(req, so.ggtt_offset,
1739 I915_DISPATCH_SECURE);
1743 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
1746 i915_gem_render_state_fini(&so);
1750 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1754 ret = intel_logical_ring_workarounds_emit(req);
1758 ret = intel_rcs_context_init_mocs(req);
1760 * Failing to program the MOCS is non-fatal.The system will not
1761 * run at peak performance. So generate an error and carry on.
1764 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1766 return intel_lr_context_render_state_init(req);
1770 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1772 * @ring: Engine Command Streamer.
1775 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1777 struct drm_i915_private *dev_priv;
1779 if (!intel_ring_initialized(ring))
1782 dev_priv = ring->dev->dev_private;
1784 intel_logical_ring_stop(ring);
1785 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1788 ring->cleanup(ring);
1790 i915_cmd_parser_fini_ring(ring);
1791 i915_gem_batch_pool_fini(&ring->batch_pool);
1793 if (ring->status_page.obj) {
1794 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1795 ring->status_page.obj = NULL;
1798 lrc_destroy_wa_ctx_obj(ring);
1801 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1805 /* Intentionally left blank. */
1806 ring->buffer = NULL;
1809 INIT_LIST_HEAD(&ring->active_list);
1810 INIT_LIST_HEAD(&ring->request_list);
1811 i915_gem_batch_pool_init(dev, &ring->batch_pool);
1812 init_waitqueue_head(&ring->irq_queue);
1814 INIT_LIST_HEAD(&ring->execlist_queue);
1815 INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1816 spin_lock_init(&ring->execlist_lock);
1818 ret = i915_cmd_parser_init_ring(ring);
1822 ret = intel_lr_context_deferred_create(ring->default_context, ring);
1827 static int logical_render_ring_init(struct drm_device *dev)
1829 struct drm_i915_private *dev_priv = dev->dev_private;
1830 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1833 ring->name = "render ring";
1835 ring->mmio_base = RENDER_RING_BASE;
1836 ring->irq_enable_mask =
1837 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1838 ring->irq_keep_mask =
1839 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1840 if (HAS_L3_DPF(dev))
1841 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1843 if (INTEL_INFO(dev)->gen >= 9)
1844 ring->init_hw = gen9_init_render_ring;
1846 ring->init_hw = gen8_init_render_ring;
1847 ring->init_context = gen8_init_rcs_context;
1848 ring->cleanup = intel_fini_pipe_control;
1849 ring->get_seqno = gen8_get_seqno;
1850 ring->set_seqno = gen8_set_seqno;
1851 ring->emit_request = gen8_emit_request;
1852 ring->emit_flush = gen8_emit_flush_render;
1853 ring->irq_get = gen8_logical_ring_get_irq;
1854 ring->irq_put = gen8_logical_ring_put_irq;
1855 ring->emit_bb_start = gen8_emit_bb_start;
1859 ret = intel_init_pipe_control(ring);
1863 ret = intel_init_workaround_bb(ring);
1866 * We continue even if we fail to initialize WA batch
1867 * because we only expect rare glitches but nothing
1868 * critical to prevent us from using GPU
1870 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1874 ret = logical_ring_init(dev, ring);
1876 lrc_destroy_wa_ctx_obj(ring);
1882 static int logical_bsd_ring_init(struct drm_device *dev)
1884 struct drm_i915_private *dev_priv = dev->dev_private;
1885 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1887 ring->name = "bsd ring";
1889 ring->mmio_base = GEN6_BSD_RING_BASE;
1890 ring->irq_enable_mask =
1891 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1892 ring->irq_keep_mask =
1893 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1895 ring->init_hw = gen8_init_common_ring;
1896 ring->get_seqno = gen8_get_seqno;
1897 ring->set_seqno = gen8_set_seqno;
1898 ring->emit_request = gen8_emit_request;
1899 ring->emit_flush = gen8_emit_flush;
1900 ring->irq_get = gen8_logical_ring_get_irq;
1901 ring->irq_put = gen8_logical_ring_put_irq;
1902 ring->emit_bb_start = gen8_emit_bb_start;
1904 return logical_ring_init(dev, ring);
1907 static int logical_bsd2_ring_init(struct drm_device *dev)
1909 struct drm_i915_private *dev_priv = dev->dev_private;
1910 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1912 ring->name = "bds2 ring";
1914 ring->mmio_base = GEN8_BSD2_RING_BASE;
1915 ring->irq_enable_mask =
1916 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1917 ring->irq_keep_mask =
1918 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1920 ring->init_hw = gen8_init_common_ring;
1921 ring->get_seqno = gen8_get_seqno;
1922 ring->set_seqno = gen8_set_seqno;
1923 ring->emit_request = gen8_emit_request;
1924 ring->emit_flush = gen8_emit_flush;
1925 ring->irq_get = gen8_logical_ring_get_irq;
1926 ring->irq_put = gen8_logical_ring_put_irq;
1927 ring->emit_bb_start = gen8_emit_bb_start;
1929 return logical_ring_init(dev, ring);
1932 static int logical_blt_ring_init(struct drm_device *dev)
1934 struct drm_i915_private *dev_priv = dev->dev_private;
1935 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1937 ring->name = "blitter ring";
1939 ring->mmio_base = BLT_RING_BASE;
1940 ring->irq_enable_mask =
1941 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1942 ring->irq_keep_mask =
1943 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1945 ring->init_hw = gen8_init_common_ring;
1946 ring->get_seqno = gen8_get_seqno;
1947 ring->set_seqno = gen8_set_seqno;
1948 ring->emit_request = gen8_emit_request;
1949 ring->emit_flush = gen8_emit_flush;
1950 ring->irq_get = gen8_logical_ring_get_irq;
1951 ring->irq_put = gen8_logical_ring_put_irq;
1952 ring->emit_bb_start = gen8_emit_bb_start;
1954 return logical_ring_init(dev, ring);
1957 static int logical_vebox_ring_init(struct drm_device *dev)
1959 struct drm_i915_private *dev_priv = dev->dev_private;
1960 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1962 ring->name = "video enhancement ring";
1964 ring->mmio_base = VEBOX_RING_BASE;
1965 ring->irq_enable_mask =
1966 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1967 ring->irq_keep_mask =
1968 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1970 ring->init_hw = gen8_init_common_ring;
1971 ring->get_seqno = gen8_get_seqno;
1972 ring->set_seqno = gen8_set_seqno;
1973 ring->emit_request = gen8_emit_request;
1974 ring->emit_flush = gen8_emit_flush;
1975 ring->irq_get = gen8_logical_ring_get_irq;
1976 ring->irq_put = gen8_logical_ring_put_irq;
1977 ring->emit_bb_start = gen8_emit_bb_start;
1979 return logical_ring_init(dev, ring);
1983 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1986 * This function inits the engines for an Execlists submission style (the equivalent in the
1987 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1988 * those engines that are present in the hardware.
1990 * Return: non-zero if the initialization failed.
1992 int intel_logical_rings_init(struct drm_device *dev)
1994 struct drm_i915_private *dev_priv = dev->dev_private;
1997 ret = logical_render_ring_init(dev);
2002 ret = logical_bsd_ring_init(dev);
2004 goto cleanup_render_ring;
2008 ret = logical_blt_ring_init(dev);
2010 goto cleanup_bsd_ring;
2013 if (HAS_VEBOX(dev)) {
2014 ret = logical_vebox_ring_init(dev);
2016 goto cleanup_blt_ring;
2019 if (HAS_BSD2(dev)) {
2020 ret = logical_bsd2_ring_init(dev);
2022 goto cleanup_vebox_ring;
2025 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
2027 goto cleanup_bsd2_ring;
2032 intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
2034 intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
2036 intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
2038 intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
2039 cleanup_render_ring:
2040 intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
2046 make_rpcs(struct drm_device *dev)
2051 * No explicit RPCS request is needed to ensure full
2052 * slice/subslice/EU enablement prior to Gen9.
2054 if (INTEL_INFO(dev)->gen < 9)
2058 * Starting in Gen9, render power gating can leave
2059 * slice/subslice/EU in a partially enabled state. We
2060 * must make an explicit request through RPCS for full
2063 if (INTEL_INFO(dev)->has_slice_pg) {
2064 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
2065 rpcs |= INTEL_INFO(dev)->slice_total <<
2066 GEN8_RPCS_S_CNT_SHIFT;
2067 rpcs |= GEN8_RPCS_ENABLE;
2070 if (INTEL_INFO(dev)->has_subslice_pg) {
2071 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
2072 rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
2073 GEN8_RPCS_SS_CNT_SHIFT;
2074 rpcs |= GEN8_RPCS_ENABLE;
2077 if (INTEL_INFO(dev)->has_eu_pg) {
2078 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2079 GEN8_RPCS_EU_MIN_SHIFT;
2080 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2081 GEN8_RPCS_EU_MAX_SHIFT;
2082 rpcs |= GEN8_RPCS_ENABLE;
2089 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
2090 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
2092 struct drm_device *dev = ring->dev;
2093 struct drm_i915_private *dev_priv = dev->dev_private;
2094 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2096 uint32_t *reg_state;
2100 ppgtt = dev_priv->mm.aliasing_ppgtt;
2102 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2104 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2108 ret = i915_gem_object_get_pages(ctx_obj);
2110 DRM_DEBUG_DRIVER("Could not get object pages\n");
2114 i915_gem_object_pin_pages(ctx_obj);
2116 /* The second page of the context object contains some fields which must
2117 * be set up prior to the first execution. */
2118 page = i915_gem_object_get_page(ctx_obj, 1);
2119 reg_state = kmap_atomic(page);
2121 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2122 * commands followed by (reg, value) pairs. The values we are setting here are
2123 * only for the first context restore: on a subsequent save, the GPU will
2124 * recreate this batchbuffer with new values (including all the missing
2125 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2126 if (ring->id == RCS)
2127 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
2129 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
2130 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
2131 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
2132 reg_state[CTX_CONTEXT_CONTROL+1] =
2133 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2134 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2135 CTX_CTRL_RS_CTX_ENABLE);
2136 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
2137 reg_state[CTX_RING_HEAD+1] = 0;
2138 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
2139 reg_state[CTX_RING_TAIL+1] = 0;
2140 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
2141 /* Ring buffer start address is not known until the buffer is pinned.
2142 * It is written to the context image in execlists_update_context()
2144 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
2145 reg_state[CTX_RING_BUFFER_CONTROL+1] =
2146 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
2147 reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
2148 reg_state[CTX_BB_HEAD_U+1] = 0;
2149 reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
2150 reg_state[CTX_BB_HEAD_L+1] = 0;
2151 reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
2152 reg_state[CTX_BB_STATE+1] = (1<<5);
2153 reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
2154 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
2155 reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
2156 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
2157 reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
2158 reg_state[CTX_SECOND_BB_STATE+1] = 0;
2159 if (ring->id == RCS) {
2160 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
2161 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
2162 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
2163 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
2164 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
2165 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
2166 if (ring->wa_ctx.obj) {
2167 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
2168 uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);
2170 reg_state[CTX_RCS_INDIRECT_CTX+1] =
2171 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
2172 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
2174 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2175 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6;
2177 reg_state[CTX_BB_PER_CTX_PTR+1] =
2178 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
2182 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
2183 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
2184 reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
2185 reg_state[CTX_CTX_TIMESTAMP+1] = 0;
2186 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
2187 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
2188 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
2189 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
2190 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
2191 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
2192 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
2193 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
2195 /* With dynamic page allocation, PDPs may not be allocated at this point,
2196 * Point the unallocated PDPs to the scratch page
2198 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
2199 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
2200 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
2201 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
2202 if (ring->id == RCS) {
2203 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2204 reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;
2205 reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);
2208 kunmap_atomic(reg_state);
2211 set_page_dirty(page);
2212 i915_gem_object_unpin_pages(ctx_obj);
2218 * intel_lr_context_free() - free the LRC specific bits of a context
2219 * @ctx: the LR context to free.
2221 * The real context freeing is done in i915_gem_context_free: this only
2222 * takes care of the bits that are LRC related: the per-engine backing
2223 * objects and the logical ringbuffer.
2225 void intel_lr_context_free(struct intel_context *ctx)
2229 for (i = 0; i < I915_NUM_RINGS; i++) {
2230 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
2233 struct intel_ringbuffer *ringbuf =
2234 ctx->engine[i].ringbuf;
2235 struct intel_engine_cs *ring = ringbuf->ring;
2237 if (ctx == ring->default_context) {
2238 intel_unpin_ringbuffer_obj(ringbuf);
2239 i915_gem_object_ggtt_unpin(ctx_obj);
2241 WARN_ON(ctx->engine[ring->id].pin_count);
2242 intel_destroy_ringbuffer_obj(ringbuf);
2244 drm_gem_object_unreference(&ctx_obj->base);
2249 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
2253 WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
2257 if (INTEL_INFO(ring->dev)->gen >= 9)
2258 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
2260 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2266 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
2273 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
2274 struct drm_i915_gem_object *default_ctx_obj)
2276 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2278 /* The status page is offset 0 from the default context object
2280 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj);
2281 ring->status_page.page_addr =
2282 kmap(sg_page(default_ctx_obj->pages->sgl));
2283 ring->status_page.obj = default_ctx_obj;
2285 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
2286 (u32)ring->status_page.gfx_addr);
2287 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
2291 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
2292 * @ctx: LR context to create.
2293 * @ring: engine to be used with the context.
2295 * This function can be called more than once, with different engines, if we plan
2296 * to use the context with them. The context backing objects and the ringbuffers
2297 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2298 * the creation is a deferred call: it's better to make sure first that we need to use
2299 * a given ring with the context.
2301 * Return: non-zero on error.
2303 int intel_lr_context_deferred_create(struct intel_context *ctx,
2304 struct intel_engine_cs *ring)
2306 const bool is_global_default_ctx = (ctx == ring->default_context);
2307 struct drm_device *dev = ring->dev;
2308 struct drm_i915_gem_object *ctx_obj;
2309 uint32_t context_size;
2310 struct intel_ringbuffer *ringbuf;
2313 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
2314 WARN_ON(ctx->engine[ring->id].state);
2316 context_size = round_up(get_lr_context_size(ring), 4096);
2318 ctx_obj = i915_gem_alloc_object(dev, context_size);
2320 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2324 if (is_global_default_ctx) {
2325 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
2327 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
2329 drm_gem_object_unreference(&ctx_obj->base);
2334 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2336 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2339 goto error_unpin_ctx;
2342 ringbuf->ring = ring;
2344 ringbuf->size = 32 * PAGE_SIZE;
2345 ringbuf->effective_size = ringbuf->size;
2348 ringbuf->last_retired_head = -1;
2349 intel_ring_update_space(ringbuf);
2351 if (ringbuf->obj == NULL) {
2352 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2355 "Failed to allocate ringbuffer obj %s: %d\n",
2357 goto error_free_rbuf;
2360 if (is_global_default_ctx) {
2361 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2364 "Failed to pin and map ringbuffer %s: %d\n",
2366 goto error_destroy_rbuf;
2372 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
2374 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2378 ctx->engine[ring->id].ringbuf = ringbuf;
2379 ctx->engine[ring->id].state = ctx_obj;
2381 if (ctx == ring->default_context)
2382 lrc_setup_hardware_status_page(ring, ctx_obj);
2383 else if (ring->id == RCS && !ctx->rcs_initialized) {
2384 if (ring->init_context) {
2385 struct drm_i915_gem_request *req;
2387 ret = i915_gem_request_alloc(ring, ctx, &req);
2391 ret = ring->init_context(req);
2393 DRM_ERROR("ring init context: %d\n", ret);
2394 i915_gem_request_cancel(req);
2395 ctx->engine[ring->id].ringbuf = NULL;
2396 ctx->engine[ring->id].state = NULL;
2400 i915_add_request_no_flush(req);
2403 ctx->rcs_initialized = true;
2409 if (is_global_default_ctx)
2410 intel_unpin_ringbuffer_obj(ringbuf);
2412 intel_destroy_ringbuffer_obj(ringbuf);
2416 if (is_global_default_ctx)
2417 i915_gem_object_ggtt_unpin(ctx_obj);
2418 drm_gem_object_unreference(&ctx_obj->base);
2422 void intel_lr_context_reset(struct drm_device *dev,
2423 struct intel_context *ctx)
2425 struct drm_i915_private *dev_priv = dev->dev_private;
2426 struct intel_engine_cs *ring;
2429 for_each_ring(ring, dev_priv, i) {
2430 struct drm_i915_gem_object *ctx_obj =
2431 ctx->engine[ring->id].state;
2432 struct intel_ringbuffer *ringbuf =
2433 ctx->engine[ring->id].ringbuf;
2434 uint32_t *reg_state;
2440 if (i915_gem_object_get_pages(ctx_obj)) {
2441 WARN(1, "Failed get_pages for context obj\n");
2444 page = i915_gem_object_get_page(ctx_obj, 1);
2445 reg_state = kmap_atomic(page);
2447 reg_state[CTX_RING_HEAD+1] = 0;
2448 reg_state[CTX_RING_TAIL+1] = 0;
2450 kunmap_atomic(reg_state);