drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75 };
  76
  77 /* Cursor formats */
  78 static const uint32_t intel_cursor_formats[] = {
  79         DRM_FORMAT_ARGB8888,
  80 };
  81
  82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  83
  84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  85                                 struct intel_crtc_state *pipe_config);
  86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  87                                    struct intel_crtc_state *pipe_config);
  88
  89 static int intel_framebuffer_init(struct drm_device *dev,
  90                                   struct intel_framebuffer *ifb,
  91                                   struct drm_mode_fb_cmd2 *mode_cmd,
  92                                   struct drm_i915_gem_object *obj);
  93 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  94 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  95 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  96                                          struct intel_link_m_n *m_n,
  97                                          struct intel_link_m_n *m2_n2);
  98 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  99 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 100 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 101 static void vlv_prepare_pll(struct intel_crtc *crtc,
 102                             const struct intel_crtc_state *pipe_config);
 103 static void chv_prepare_pll(struct intel_crtc *crtc,
 104                             const struct intel_crtc_state *pipe_config);
 105 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 106 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 107 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 108         struct intel_crtc_state *crtc_state);
 109 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 110                            int num_connectors);
 111 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 112
 113 typedef struct {
 114         int     min, max;
 115 } intel_range_t;
 116
 117 typedef struct {
 118         int     dot_limit;
 119         int     p2_slow, p2_fast;
 120 } intel_p2_t;
 121
 122 typedef struct intel_limit intel_limit_t;
 123 struct intel_limit {
 124         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 125         intel_p2_t          p2;
 126 };
 127
 128 int
 129 intel_pch_rawclk(struct drm_device *dev)
 130 {
 131         struct drm_i915_private *dev_priv = dev->dev_private;
 132
 133         WARN_ON(!HAS_PCH_SPLIT(dev));
 134
 135         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 136 }
 137
 138 static inline u32 /* units of 100MHz */
 139 intel_fdi_link_freq(struct drm_device *dev)
 140 {
 141         if (IS_GEN5(dev)) {
 142                 struct drm_i915_private *dev_priv = dev->dev_private;
 143                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 144         } else
 145                 return 27;
 146 }
 147
 148 static const intel_limit_t intel_limits_i8xx_dac = {
 149         .dot = { .min = 25000, .max = 350000 },
 150         .vco = { .min = 908000, .max = 1512000 },
 151         .n = { .min = 2, .max = 16 },
 152         .m = { .min = 96, .max = 140 },
 153         .m1 = { .min = 18, .max = 26 },
 154         .m2 = { .min = 6, .max = 16 },
 155         .p = { .min = 4, .max = 128 },
 156         .p1 = { .min = 2, .max = 33 },
 157         .p2 = { .dot_limit = 165000,
 158                 .p2_slow = 4, .p2_fast = 2 },
 159 };
 160
 161 static const intel_limit_t intel_limits_i8xx_dvo = {
 162         .dot = { .min = 25000, .max = 350000 },
 163         .vco = { .min = 908000, .max = 1512000 },
 164         .n = { .min = 2, .max = 16 },
 165         .m = { .min = 96, .max = 140 },
 166         .m1 = { .min = 18, .max = 26 },
 167         .m2 = { .min = 6, .max = 16 },
 168         .p = { .min = 4, .max = 128 },
 169         .p1 = { .min = 2, .max = 33 },
 170         .p2 = { .dot_limit = 165000,
 171                 .p2_slow = 4, .p2_fast = 4 },
 172 };
 173
 174 static const intel_limit_t intel_limits_i8xx_lvds = {
 175         .dot = { .min = 25000, .max = 350000 },
 176         .vco = { .min = 908000, .max = 1512000 },
 177         .n = { .min = 2, .max = 16 },
 178         .m = { .min = 96, .max = 140 },
 179         .m1 = { .min = 18, .max = 26 },
 180         .m2 = { .min = 6, .max = 16 },
 181         .p = { .min = 4, .max = 128 },
 182         .p1 = { .min = 1, .max = 6 },
 183         .p2 = { .dot_limit = 165000,
 184                 .p2_slow = 14, .p2_fast = 7 },
 185 };
 186
 187 static const intel_limit_t intel_limits_i9xx_sdvo = {
 188         .dot = { .min = 20000, .max = 400000 },
 189         .vco = { .min = 1400000, .max = 2800000 },
 190         .n = { .min = 1, .max = 6 },
 191         .m = { .min = 70, .max = 120 },
 192         .m1 = { .min = 8, .max = 18 },
 193         .m2 = { .min = 3, .max = 7 },
 194         .p = { .min = 5, .max = 80 },
 195         .p1 = { .min = 1, .max = 8 },
 196         .p2 = { .dot_limit = 200000,
 197                 .p2_slow = 10, .p2_fast = 5 },
 198 };
 199
 200 static const intel_limit_t intel_limits_i9xx_lvds = {
 201         .dot = { .min = 20000, .max = 400000 },
 202         .vco = { .min = 1400000, .max = 2800000 },
 203         .n = { .min = 1, .max = 6 },
 204         .m = { .min = 70, .max = 120 },
 205         .m1 = { .min = 8, .max = 18 },
 206         .m2 = { .min = 3, .max = 7 },
 207         .p = { .min = 7, .max = 98 },
 208         .p1 = { .min = 1, .max = 8 },
 209         .p2 = { .dot_limit = 112000,
 210                 .p2_slow = 14, .p2_fast = 7 },
 211 };
 212
 213
 214 static const intel_limit_t intel_limits_g4x_sdvo = {
 215         .dot = { .min = 25000, .max = 270000 },
 216         .vco = { .min = 1750000, .max = 3500000},
 217         .n = { .min = 1, .max = 4 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 10, .max = 30 },
 222         .p1 = { .min = 1, .max = 3},
 223         .p2 = { .dot_limit = 270000,
 224                 .p2_slow = 10,
 225                 .p2_fast = 10
 226         },
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_hdmi = {
 230         .dot = { .min = 22000, .max = 400000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 4 },
 233         .m = { .min = 104, .max = 138 },
 234         .m1 = { .min = 16, .max = 23 },
 235         .m2 = { .min = 5, .max = 11 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8},
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 243         .dot = { .min = 20000, .max = 115000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 14, .p2_fast = 14
 253         },
 254 };
 255
 256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 257         .dot = { .min = 80000, .max = 224000 },
 258         .vco = { .min = 1750000, .max = 3500000 },
 259         .n = { .min = 1, .max = 3 },
 260         .m = { .min = 104, .max = 138 },
 261         .m1 = { .min = 17, .max = 23 },
 262         .m2 = { .min = 5, .max = 11 },
 263         .p = { .min = 14, .max = 42 },
 264         .p1 = { .min = 2, .max = 6 },
 265         .p2 = { .dot_limit = 0,
 266                 .p2_slow = 7, .p2_fast = 7
 267         },
 268 };
 269
 270 static const intel_limit_t intel_limits_pineview_sdvo = {
 271         .dot = { .min = 20000, .max = 400000},
 272         .vco = { .min = 1700000, .max = 3500000 },
 273         /* Pineview's Ncounter is a ring counter */
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         /* Pineview only has one combined m divider, which we treat as m2. */
 277         .m1 = { .min = 0, .max = 0 },
 278         .m2 = { .min = 0, .max = 254 },
 279         .p = { .min = 5, .max = 80 },
 280         .p1 = { .min = 1, .max = 8 },
 281         .p2 = { .dot_limit = 200000,
 282                 .p2_slow = 10, .p2_fast = 5 },
 283 };
 284
 285 static const intel_limit_t intel_limits_pineview_lvds = {
 286         .dot = { .min = 20000, .max = 400000 },
 287         .vco = { .min = 1700000, .max = 3500000 },
 288         .n = { .min = 3, .max = 6 },
 289         .m = { .min = 2, .max = 256 },
 290         .m1 = { .min = 0, .max = 0 },
 291         .m2 = { .min = 0, .max = 254 },
 292         .p = { .min = 7, .max = 112 },
 293         .p1 = { .min = 1, .max = 8 },
 294         .p2 = { .dot_limit = 112000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296 };
 297
 298 /* Ironlake / Sandybridge
 299  *
 300  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 301  * the range value for them is (actual_value - 2).
 302  */
 303 static const intel_limit_t intel_limits_ironlake_dac = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 5 },
 307         .m = { .min = 79, .max = 127 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 5, .max = 80 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 10, .p2_fast = 5 },
 314 };
 315
 316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 3 },
 320         .m = { .min = 79, .max = 118 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2, .max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327 };
 328
 329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 79, .max = 127 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 14, .max = 56 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 7, .p2_fast = 7 },
 340 };
 341
 342 /* LVDS 100mhz refclk limits. */
 343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000 },
 346         .n = { .min = 1, .max = 2 },
 347         .m = { .min = 79, .max = 126 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 28, .max = 112 },
 351         .p1 = { .min = 2, .max = 8 },
 352         .p2 = { .dot_limit = 225000,
 353                 .p2_slow = 14, .p2_fast = 14 },
 354 };
 355
 356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 357         .dot = { .min = 25000, .max = 350000 },
 358         .vco = { .min = 1760000, .max = 3510000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 79, .max = 126 },
 361         .m1 = { .min = 12, .max = 22 },
 362         .m2 = { .min = 5, .max = 9 },
 363         .p = { .min = 14, .max = 42 },
 364         .p1 = { .min = 2, .max = 6 },
 365         .p2 = { .dot_limit = 225000,
 366                 .p2_slow = 7, .p2_fast = 7 },
 367 };
 368
 369 static const intel_limit_t intel_limits_vlv = {
 370          /*
 371           * These are the data rate limits (measured in fast clocks)
 372           * since those are the strictest limits we have. The fast
 373           * clock and actual rate limits are more relaxed, so checking
 374           * them would make no difference.
 375           */
 376         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m1 = { .min = 2, .max = 3 },
 380         .m2 = { .min = 11, .max = 156 },
 381         .p1 = { .min = 2, .max = 3 },
 382         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 383 };
 384
 385 static const intel_limit_t intel_limits_chv = {
 386         /*
 387          * These are the data rate limits (measured in fast clocks)
 388          * since those are the strictest limits we have.  The fast
 389          * clock and actual rate limits are more relaxed, so checking
 390          * them would make no difference.
 391          */
 392         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 393         .vco = { .min = 4800000, .max = 6480000 },
 394         .n = { .min = 1, .max = 1 },
 395         .m1 = { .min = 2, .max = 2 },
 396         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 397         .p1 = { .min = 2, .max = 4 },
 398         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 399 };
 400
 401 static const intel_limit_t intel_limits_bxt = {
 402         /* FIXME: find real dot limits */
 403         .dot = { .min = 0, .max = INT_MAX },
 404         .vco = { .min = 4800000, .max = 6700000 },
 405         .n = { .min = 1, .max = 1 },
 406         .m1 = { .min = 2, .max = 2 },
 407         /* FIXME: find real m2 limits */
 408         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 409         .p1 = { .min = 2, .max = 4 },
 410         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 411 };
 412
 413 static bool
 414 needs_modeset(struct drm_crtc_state *state)
 415 {
 416         return drm_atomic_crtc_needs_modeset(state);
 417 }
 418
 419 /**
 420  * Returns whether any output on the specified pipe is of the specified type
 421  */
 422 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 423 {
 424         struct drm_device *dev = crtc->base.dev;
 425         struct intel_encoder *encoder;
 426
 427         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 428                 if (encoder->type == type)
 429                         return true;
 430
 431         return false;
 432 }
 433
 434 /**
 435  * Returns whether any output on the specified pipe will have the specified
 436  * type after a staged modeset is complete, i.e., the same as
 437  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 438  * encoder->crtc.
 439  */
 440 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 441                                       int type)
 442 {
 443         struct drm_atomic_state *state = crtc_state->base.state;
 444         struct drm_connector *connector;
 445         struct drm_connector_state *connector_state;
 446         struct intel_encoder *encoder;
 447         int i, num_connectors = 0;
 448
 449         for_each_connector_in_state(state, connector, connector_state, i) {
 450                 if (connector_state->crtc != crtc_state->base.crtc)
 451                         continue;
 452
 453                 num_connectors++;
 454
 455                 encoder = to_intel_encoder(connector_state->best_encoder);
 456                 if (encoder->type == type)
 457                         return true;
 458         }
 459
 460         WARN_ON(num_connectors == 0);
 461
 462         return false;
 463 }
 464
 465 static const intel_limit_t *
 466 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 467 {
 468         struct drm_device *dev = crtc_state->base.crtc->dev;
 469         const intel_limit_t *limit;
 470
 471         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 472                 if (intel_is_dual_link_lvds(dev)) {
 473                         if (refclk == 100000)
 474                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 475                         else
 476                                 limit = &intel_limits_ironlake_dual_lvds;
 477                 } else {
 478                         if (refclk == 100000)
 479                                 limit = &intel_limits_ironlake_single_lvds_100m;
 480                         else
 481                                 limit = &intel_limits_ironlake_single_lvds;
 482                 }
 483         } else
 484                 limit = &intel_limits_ironlake_dac;
 485
 486         return limit;
 487 }
 488
 489 static const intel_limit_t *
 490 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 491 {
 492         struct drm_device *dev = crtc_state->base.crtc->dev;
 493         const intel_limit_t *limit;
 494
 495         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 496                 if (intel_is_dual_link_lvds(dev))
 497                         limit = &intel_limits_g4x_dual_channel_lvds;
 498                 else
 499                         limit = &intel_limits_g4x_single_channel_lvds;
 500         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 501                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 502                 limit = &intel_limits_g4x_hdmi;
 503         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 504                 limit = &intel_limits_g4x_sdvo;
 505         } else /* The option is for other outputs */
 506                 limit = &intel_limits_i9xx_sdvo;
 507
 508         return limit;
 509 }
 510
 511 static const intel_limit_t *
 512 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 513 {
 514         struct drm_device *dev = crtc_state->base.crtc->dev;
 515         const intel_limit_t *limit;
 516
 517         if (IS_BROXTON(dev))
 518                 limit = &intel_limits_bxt;
 519         else if (HAS_PCH_SPLIT(dev))
 520                 limit = intel_ironlake_limit(crtc_state, refclk);
 521         else if (IS_G4X(dev)) {
 522                 limit = intel_g4x_limit(crtc_state);
 523         } else if (IS_PINEVIEW(dev)) {
 524                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 525                         limit = &intel_limits_pineview_lvds;
 526                 else
 527                         limit = &intel_limits_pineview_sdvo;
 528         } else if (IS_CHERRYVIEW(dev)) {
 529                 limit = &intel_limits_chv;
 530         } else if (IS_VALLEYVIEW(dev)) {
 531                 limit = &intel_limits_vlv;
 532         } else if (!IS_GEN2(dev)) {
 533                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 534                         limit = &intel_limits_i9xx_lvds;
 535                 else
 536                         limit = &intel_limits_i9xx_sdvo;
 537         } else {
 538                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 539                         limit = &intel_limits_i8xx_lvds;
 540                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 541                         limit = &intel_limits_i8xx_dvo;
 542                 else
 543                         limit = &intel_limits_i8xx_dac;
 544         }
 545         return limit;
 546 }
 547
 548 /*
 549  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 550  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 551  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 552  * The helpers' return value is the rate of the clock that is fed to the
 553  * display engine's pipe which can be the above fast dot clock rate or a
 554  * divided-down version of it.
 555  */
 556 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 557 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 558 {
 559         clock->m = clock->m2 + 2;
 560         clock->p = clock->p1 * clock->p2;
 561         if (WARN_ON(clock->n == 0 || clock->p == 0))
 562                 return 0;
 563         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 564         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 565
 566         return clock->dot;
 567 }
 568
 569 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 570 {
 571         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 572 }
 573
 574 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 575 {
 576         clock->m = i9xx_dpll_compute_m(clock);
 577         clock->p = clock->p1 * clock->p2;
 578         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 579                 return 0;
 580         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 581         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 582
 583         return clock->dot;
 584 }
 585
 586 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 587 {
 588         clock->m = clock->m1 * clock->m2;
 589         clock->p = clock->p1 * clock->p2;
 590         if (WARN_ON(clock->n == 0 || clock->p == 0))
 591                 return 0;
 592         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 593         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 594
 595         return clock->dot / 5;
 596 }
 597
 598 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 599 {
 600         clock->m = clock->m1 * clock->m2;
 601         clock->p = clock->p1 * clock->p2;
 602         if (WARN_ON(clock->n == 0 || clock->p == 0))
 603                 return 0;
 604         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 605                         clock->n << 22);
 606         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 607
 608         return clock->dot / 5;
 609 }
 610
 611 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 612 /**
 613  * Returns whether the given set of divisors are valid for a given refclk with
 614  * the given connectors.
 615  */
 616
 617 static bool intel_PLL_is_valid(struct drm_device *dev,
 618                                const intel_limit_t *limit,
 619                                const intel_clock_t *clock)
 620 {
 621         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 622                 INTELPllInvalid("n out of range\n");
 623         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 624                 INTELPllInvalid("p1 out of range\n");
 625         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 626                 INTELPllInvalid("m2 out of range\n");
 627         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 628                 INTELPllInvalid("m1 out of range\n");
 629
 630         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 631                 if (clock->m1 <= clock->m2)
 632                         INTELPllInvalid("m1 <= m2\n");
 633
 634         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 635                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 636                         INTELPllInvalid("p out of range\n");
 637                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 638                         INTELPllInvalid("m out of range\n");
 639         }
 640
 641         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 642                 INTELPllInvalid("vco out of range\n");
 643         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 644          * connector, etc., rather than just a single range.
 645          */
 646         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 647                 INTELPllInvalid("dot out of range\n");
 648
 649         return true;
 650 }
 651
 652 static int
 653 i9xx_select_p2_div(const intel_limit_t *limit,
 654                    const struct intel_crtc_state *crtc_state,
 655                    int target)
 656 {
 657         struct drm_device *dev = crtc_state->base.crtc->dev;
 658
 659         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 660                 /*
 661                  * For LVDS just rely on its current settings for dual-channel.
 662                  * We haven't figured out how to reliably set up different
 663                  * single/dual channel state, if we even can.
 664                  */
 665                 if (intel_is_dual_link_lvds(dev))
 666                         return limit->p2.p2_fast;
 667                 else
 668                         return limit->p2.p2_slow;
 669         } else {
 670                 if (target < limit->p2.dot_limit)
 671                         return limit->p2.p2_slow;
 672                 else
 673                         return limit->p2.p2_fast;
 674         }
 675 }
 676
 677 static bool
 678 i9xx_find_best_dpll(const intel_limit_t *limit,
 679                     struct intel_crtc_state *crtc_state,
 680                     int target, int refclk, intel_clock_t *match_clock,
 681                     intel_clock_t *best_clock)
 682 {
 683         struct drm_device *dev = crtc_state->base.crtc->dev;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         memset(best_clock, 0, sizeof(*best_clock));
 688
 689         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 690
 691         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 692              clock.m1++) {
 693                 for (clock.m2 = limit->m2.min;
 694                      clock.m2 <= limit->m2.max; clock.m2++) {
 695                         if (clock.m2 >= clock.m1)
 696                                 break;
 697                         for (clock.n = limit->n.min;
 698                              clock.n <= limit->n.max; clock.n++) {
 699                                 for (clock.p1 = limit->p1.min;
 700                                         clock.p1 <= limit->p1.max; clock.p1++) {
 701                                         int this_err;
 702
 703                                         i9xx_calc_dpll_params(refclk, &clock);
 704                                         if (!intel_PLL_is_valid(dev, limit,
 705                                                                 &clock))
 706                                                 continue;
 707                                         if (match_clock &&
 708                                             clock.p != match_clock->p)
 709                                                 continue;
 710
 711                                         this_err = abs(clock.dot - target);
 712                                         if (this_err < err) {
 713                                                 *best_clock = clock;
 714                                                 err = this_err;
 715                                         }
 716                                 }
 717                         }
 718                 }
 719         }
 720
 721         return (err != target);
 722 }
 723
 724 static bool
 725 pnv_find_best_dpll(const intel_limit_t *limit,
 726                    struct intel_crtc_state *crtc_state,
 727                    int target, int refclk, intel_clock_t *match_clock,
 728                    intel_clock_t *best_clock)
 729 {
 730         struct drm_device *dev = crtc_state->base.crtc->dev;
 731         intel_clock_t clock;
 732         int err = target;
 733
 734         memset(best_clock, 0, sizeof(*best_clock));
 735
 736         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 737
 738         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 739              clock.m1++) {
 740                 for (clock.m2 = limit->m2.min;
 741                      clock.m2 <= limit->m2.max; clock.m2++) {
 742                         for (clock.n = limit->n.min;
 743                              clock.n <= limit->n.max; clock.n++) {
 744                                 for (clock.p1 = limit->p1.min;
 745                                         clock.p1 <= limit->p1.max; clock.p1++) {
 746                                         int this_err;
 747
 748                                         pnv_calc_dpll_params(refclk, &clock);
 749                                         if (!intel_PLL_is_valid(dev, limit,
 750                                                                 &clock))
 751                                                 continue;
 752                                         if (match_clock &&
 753                                             clock.p != match_clock->p)
 754                                                 continue;
 755
 756                                         this_err = abs(clock.dot - target);
 757                                         if (this_err < err) {
 758                                                 *best_clock = clock;
 759                                                 err = this_err;
 760                                         }
 761                                 }
 762                         }
 763                 }
 764         }
 765
 766         return (err != target);
 767 }
 768
 769 static bool
 770 g4x_find_best_dpll(const intel_limit_t *limit,
 771                    struct intel_crtc_state *crtc_state,
 772                    int target, int refclk, intel_clock_t *match_clock,
 773                    intel_clock_t *best_clock)
 774 {
 775         struct drm_device *dev = crtc_state->base.crtc->dev;
 776         intel_clock_t clock;
 777         int max_n;
 778         bool found = false;
 779         /* approximately equals target * 0.00585 */
 780         int err_most = (target >> 8) + (target >> 9);
 781
 782         memset(best_clock, 0, sizeof(*best_clock));
 783
 784         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 785
 786         max_n = limit->n.max;
 787         /* based on hardware requirement, prefer smaller n to precision */
 788         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 789                 /* based on hardware requirement, prefere larger m1,m2 */
 790                 for (clock.m1 = limit->m1.max;
 791                      clock.m1 >= limit->m1.min; clock.m1--) {
 792                         for (clock.m2 = limit->m2.max;
 793                              clock.m2 >= limit->m2.min; clock.m2--) {
 794                                 for (clock.p1 = limit->p1.max;
 795                                      clock.p1 >= limit->p1.min; clock.p1--) {
 796                                         int this_err;
 797
 798                                         i9xx_calc_dpll_params(refclk, &clock);
 799                                         if (!intel_PLL_is_valid(dev, limit,
 800                                                                 &clock))
 801                                                 continue;
 802
 803                                         this_err = abs(clock.dot - target);
 804                                         if (this_err < err_most) {
 805                                                 *best_clock = clock;
 806                                                 err_most = this_err;
 807                                                 max_n = clock.n;
 808                                                 found = true;
 809                                         }
 810                                 }
 811                         }
 812                 }
 813         }
 814         return found;
 815 }
 816
 817 /*
 818  * Check if the calculated PLL configuration is more optimal compared to the
 819  * best configuration and error found so far. Return the calculated error.
 820  */
 821 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 822                                const intel_clock_t *calculated_clock,
 823                                const intel_clock_t *best_clock,
 824                                unsigned int best_error_ppm,
 825                                unsigned int *error_ppm)
 826 {
 827         /*
 828          * For CHV ignore the error and consider only the P value.
 829          * Prefer a bigger P value based on HW requirements.
 830          */
 831         if (IS_CHERRYVIEW(dev)) {
 832                 *error_ppm = 0;
 833
 834                 return calculated_clock->p > best_clock->p;
 835         }
 836
 837         if (WARN_ON_ONCE(!target_freq))
 838                 return false;
 839
 840         *error_ppm = div_u64(1000000ULL *
 841                                 abs(target_freq - calculated_clock->dot),
 842                              target_freq);
 843         /*
 844          * Prefer a better P value over a better (smaller) error if the error
 845          * is small. Ensure this preference for future configurations too by
 846          * setting the error to 0.
 847          */
 848         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 849                 *error_ppm = 0;
 850
 851                 return true;
 852         }
 853
 854         return *error_ppm + 10 < best_error_ppm;
 855 }
 856
 857 static bool
 858 vlv_find_best_dpll(const intel_limit_t *limit,
 859                    struct intel_crtc_state *crtc_state,
 860                    int target, int refclk, intel_clock_t *match_clock,
 861                    intel_clock_t *best_clock)
 862 {
 863         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 864         struct drm_device *dev = crtc->base.dev;
 865         intel_clock_t clock;
 866         unsigned int bestppm = 1000000;
 867         /* min update 19.2 MHz */
 868         int max_n = min(limit->n.max, refclk / 19200);
 869         bool found = false;
 870
 871         target *= 5; /* fast clock */
 872
 873         memset(best_clock, 0, sizeof(*best_clock));
 874
 875         /* based on hardware requirement, prefer smaller n to precision */
 876         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 877                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 878                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 879                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 880                                 clock.p = clock.p1 * clock.p2;
 881                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 882                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 883                                         unsigned int ppm;
 884
 885                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 886                                                                      refclk * clock.m1);
 887
 888                                         vlv_calc_dpll_params(refclk, &clock);
 889
 890                                         if (!intel_PLL_is_valid(dev, limit,
 891                                                                 &clock))
 892                                                 continue;
 893
 894                                         if (!vlv_PLL_is_optimal(dev, target,
 895                                                                 &clock,
 896                                                                 best_clock,
 897                                                                 bestppm, &ppm))
 898                                                 continue;
 899
 900                                         *best_clock = clock;
 901                                         bestppm = ppm;
 902                                         found = true;
 903                                 }
 904                         }
 905                 }
 906         }
 907
 908         return found;
 909 }
 910
 911 static bool
 912 chv_find_best_dpll(const intel_limit_t *limit,
 913                    struct intel_crtc_state *crtc_state,
 914                    int target, int refclk, intel_clock_t *match_clock,
 915                    intel_clock_t *best_clock)
 916 {
 917         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 918         struct drm_device *dev = crtc->base.dev;
 919         unsigned int best_error_ppm;
 920         intel_clock_t clock;
 921         uint64_t m2;
 922         int found = false;
 923
 924         memset(best_clock, 0, sizeof(*best_clock));
 925         best_error_ppm = 1000000;
 926
 927         /*
 928          * Based on hardware doc, the n always set to 1, and m1 always
 929          * set to 2.  If requires to support 200Mhz refclk, we need to
 930          * revisit this because n may not 1 anymore.
 931          */
 932         clock.n = 1, clock.m1 = 2;
 933         target *= 5;    /* fast clock */
 934
 935         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 936                 for (clock.p2 = limit->p2.p2_fast;
 937                                 clock.p2 >= limit->p2.p2_slow;
 938                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 939                         unsigned int error_ppm;
 940
 941                         clock.p = clock.p1 * clock.p2;
 942
 943                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 944                                         clock.n) << 22, refclk * clock.m1);
 945
 946                         if (m2 > INT_MAX/clock.m1)
 947                                 continue;
 948
 949                         clock.m2 = m2;
 950
 951                         chv_calc_dpll_params(refclk, &clock);
 952
 953                         if (!intel_PLL_is_valid(dev, limit, &clock))
 954                                 continue;
 955
 956                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 957                                                 best_error_ppm, &error_ppm))
 958                                 continue;
 959
 960                         *best_clock = clock;
 961                         best_error_ppm = error_ppm;
 962                         found = true;
 963                 }
 964         }
 965
 966         return found;
 967 }
 968
 969 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 970                         intel_clock_t *best_clock)
 971 {
 972         int refclk = i9xx_get_refclk(crtc_state, 0);
 973
 974         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
 975                                   target_clock, refclk, NULL, best_clock);
 976 }
 977
 978 bool intel_crtc_active(struct drm_crtc *crtc)
 979 {
 980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 981
 982         /* Be paranoid as we can arrive here with only partial
 983          * state retrieved from the hardware during setup.
 984          *
 985          * We can ditch the adjusted_mode.crtc_clock check as soon
 986          * as Haswell has gained clock readout/fastboot support.
 987          *
 988          * We can ditch the crtc->primary->fb check as soon as we can
 989          * properly reconstruct framebuffers.
 990          *
 991          * FIXME: The intel_crtc->active here should be switched to
 992          * crtc->state->active once we have proper CRTC states wired up
 993          * for atomic.
 994          */
 995         return intel_crtc->active && crtc->primary->state->fb &&
 996                 intel_crtc->config->base.adjusted_mode.crtc_clock;
 997 }
 998
 999 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1000                                              enum pipe pipe)
1001 {
1002         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1004
1005         return intel_crtc->config->cpu_transcoder;
1006 }
1007
1008 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1009 {
1010         struct drm_i915_private *dev_priv = dev->dev_private;
1011         u32 reg = PIPEDSL(pipe);
1012         u32 line1, line2;
1013         u32 line_mask;
1014
1015         if (IS_GEN2(dev))
1016                 line_mask = DSL_LINEMASK_GEN2;
1017         else
1018                 line_mask = DSL_LINEMASK_GEN3;
1019
1020         line1 = I915_READ(reg) & line_mask;
1021         msleep(5);
1022         line2 = I915_READ(reg) & line_mask;
1023
1024         return line1 == line2;
1025 }
1026
1027 /*
1028  * intel_wait_for_pipe_off - wait for pipe to turn off
1029  * @crtc: crtc whose pipe to wait for
1030  *
1031  * After disabling a pipe, we can't wait for vblank in the usual way,
1032  * spinning on the vblank interrupt status bit, since we won't actually
1033  * see an interrupt when the pipe is disabled.
1034  *
1035  * On Gen4 and above:
1036  *   wait for the pipe register state bit to turn off
1037  *
1038  * Otherwise:
1039  *   wait for the display line value to settle (it usually
1040  *   ends up stopping at the start of the next frame).
1041  *
1042  */
1043 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1044 {
1045         struct drm_device *dev = crtc->base.dev;
1046         struct drm_i915_private *dev_priv = dev->dev_private;
1047         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1048         enum pipe pipe = crtc->pipe;
1049
1050         if (INTEL_INFO(dev)->gen >= 4) {
1051                 int reg = PIPECONF(cpu_transcoder);
1052
1053                 /* Wait for the Pipe State to go off */
1054                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1055                              100))
1056                         WARN(1, "pipe_off wait timed out\n");
1057         } else {
1058                 /* Wait for the display line to settle */
1059                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1060                         WARN(1, "pipe_off wait timed out\n");
1061         }
1062 }
1063
1064 /*
1065  * ibx_digital_port_connected - is the specified port connected?
1066  * @dev_priv: i915 private structure
1067  * @port: the port to test
1068  *
1069  * Returns true if @port is connected, false otherwise.
1070  */
1071 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1072                                 struct intel_digital_port *port)
1073 {
1074         u32 bit;
1075
1076         if (HAS_PCH_IBX(dev_priv->dev)) {
1077                 switch (port->port) {
1078                 case PORT_B:
1079                         bit = SDE_PORTB_HOTPLUG;
1080                         break;
1081                 case PORT_C:
1082                         bit = SDE_PORTC_HOTPLUG;
1083                         break;
1084                 case PORT_D:
1085                         bit = SDE_PORTD_HOTPLUG;
1086                         break;
1087                 default:
1088                         return true;
1089                 }
1090         } else {
1091                 switch (port->port) {
1092                 case PORT_B:
1093                         bit = SDE_PORTB_HOTPLUG_CPT;
1094                         break;
1095                 case PORT_C:
1096                         bit = SDE_PORTC_HOTPLUG_CPT;
1097                         break;
1098                 case PORT_D:
1099                         bit = SDE_PORTD_HOTPLUG_CPT;
1100                         break;
1101                 case PORT_E:
1102                         bit = SDE_PORTE_HOTPLUG_SPT;
1103                         break;
1104                 default:
1105                         return true;
1106                 }
1107         }
1108
1109         return I915_READ(SDEISR) & bit;
1110 }
1111
1112 static const char *state_string(bool enabled)
1113 {
1114         return enabled ? "on" : "off";
1115 }
1116
1117 /* Only for pre-ILK configs */
1118 void assert_pll(struct drm_i915_private *dev_priv,
1119                 enum pipe pipe, bool state)
1120 {
1121         int reg;
1122         u32 val;
1123         bool cur_state;
1124
1125         reg = DPLL(pipe);
1126         val = I915_READ(reg);
1127         cur_state = !!(val & DPLL_VCO_ENABLE);
1128         I915_STATE_WARN(cur_state != state,
1129              "PLL state assertion failure (expected %s, current %s)\n",
1130              state_string(state), state_string(cur_state));
1131 }
1132
1133 /* XXX: the dsi pll is shared between MIPI DSI ports */
1134 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1135 {
1136         u32 val;
1137         bool cur_state;
1138
1139         mutex_lock(&dev_priv->sb_lock);
1140         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1141         mutex_unlock(&dev_priv->sb_lock);
1142
1143         cur_state = val & DSI_PLL_VCO_EN;
1144         I915_STATE_WARN(cur_state != state,
1145              "DSI PLL state assertion failure (expected %s, current %s)\n",
1146              state_string(state), state_string(cur_state));
1147 }
1148 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1149 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1150
1151 struct intel_shared_dpll *
1152 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1153 {
1154         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1155
1156         if (crtc->config->shared_dpll < 0)
1157                 return NULL;
1158
1159         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1160 }
1161
1162 /* For ILK+ */
1163 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1164                         struct intel_shared_dpll *pll,
1165                         bool state)
1166 {
1167         bool cur_state;
1168         struct intel_dpll_hw_state hw_state;
1169
1170         if (WARN (!pll,
1171                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1172                 return;
1173
1174         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1175         I915_STATE_WARN(cur_state != state,
1176              "%s assertion failure (expected %s, current %s)\n",
1177              pll->name, state_string(state), state_string(cur_state));
1178 }
1179
1180 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1181                           enum pipe pipe, bool state)
1182 {
1183         int reg;
1184         u32 val;
1185         bool cur_state;
1186         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1187                                                                       pipe);
1188
1189         if (HAS_DDI(dev_priv->dev)) {
1190                 /* DDI does not have a specific FDI_TX register */
1191                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1192                 val = I915_READ(reg);
1193                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1194         } else {
1195                 reg = FDI_TX_CTL(pipe);
1196                 val = I915_READ(reg);
1197                 cur_state = !!(val & FDI_TX_ENABLE);
1198         }
1199         I915_STATE_WARN(cur_state != state,
1200              "FDI TX state assertion failure (expected %s, current %s)\n",
1201              state_string(state), state_string(cur_state));
1202 }
1203 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1204 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1205
1206 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1207                           enum pipe pipe, bool state)
1208 {
1209         int reg;
1210         u32 val;
1211         bool cur_state;
1212
1213         reg = FDI_RX_CTL(pipe);
1214         val = I915_READ(reg);
1215         cur_state = !!(val & FDI_RX_ENABLE);
1216         I915_STATE_WARN(cur_state != state,
1217              "FDI RX state assertion failure (expected %s, current %s)\n",
1218              state_string(state), state_string(cur_state));
1219 }
1220 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1221 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1222
1223 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1224                                       enum pipe pipe)
1225 {
1226         int reg;
1227         u32 val;
1228
1229         /* ILK FDI PLL is always enabled */
1230         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1231                 return;
1232
1233         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1234         if (HAS_DDI(dev_priv->dev))
1235                 return;
1236
1237         reg = FDI_TX_CTL(pipe);
1238         val = I915_READ(reg);
1239         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1240 }
1241
1242 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1243                        enum pipe pipe, bool state)
1244 {
1245         int reg;
1246         u32 val;
1247         bool cur_state;
1248
1249         reg = FDI_RX_CTL(pipe);
1250         val = I915_READ(reg);
1251         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1252         I915_STATE_WARN(cur_state != state,
1253              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1254              state_string(state), state_string(cur_state));
1255 }
1256
1257 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1258                            enum pipe pipe)
1259 {
1260         struct drm_device *dev = dev_priv->dev;
1261         int pp_reg;
1262         u32 val;
1263         enum pipe panel_pipe = PIPE_A;
1264         bool locked = true;
1265
1266         if (WARN_ON(HAS_DDI(dev)))
1267                 return;
1268
1269         if (HAS_PCH_SPLIT(dev)) {
1270                 u32 port_sel;
1271
1272                 pp_reg = PCH_PP_CONTROL;
1273                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1274
1275                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1276                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1277                         panel_pipe = PIPE_B;
1278                 /* XXX: else fix for eDP */
1279         } else if (IS_VALLEYVIEW(dev)) {
1280                 /* presumably write lock depends on pipe, not port select */
1281                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1282                 panel_pipe = pipe;
1283         } else {
1284                 pp_reg = PP_CONTROL;
1285                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1286                         panel_pipe = PIPE_B;
1287         }
1288
1289         val = I915_READ(pp_reg);
1290         if (!(val & PANEL_POWER_ON) ||
1291             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1292                 locked = false;
1293
1294         I915_STATE_WARN(panel_pipe == pipe && locked,
1295              "panel assertion failure, pipe %c regs locked\n",
1296              pipe_name(pipe));
1297 }
1298
1299 static void assert_cursor(struct drm_i915_private *dev_priv,
1300                           enum pipe pipe, bool state)
1301 {
1302         struct drm_device *dev = dev_priv->dev;
1303         bool cur_state;
1304
1305         if (IS_845G(dev) || IS_I865G(dev))
1306                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1307         else
1308                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1309
1310         I915_STATE_WARN(cur_state != state,
1311              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1312              pipe_name(pipe), state_string(state), state_string(cur_state));
1313 }
1314 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1315 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1316
1317 void assert_pipe(struct drm_i915_private *dev_priv,
1318                  enum pipe pipe, bool state)
1319 {
1320         int reg;
1321         u32 val;
1322         bool cur_state;
1323         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1324                                                                       pipe);
1325
1326         /* if we need the pipe quirk it must be always on */
1327         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1328             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1329                 state = true;
1330
1331         if (!intel_display_power_is_enabled(dev_priv,
1332                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1333                 cur_state = false;
1334         } else {
1335                 reg = PIPECONF(cpu_transcoder);
1336                 val = I915_READ(reg);
1337                 cur_state = !!(val & PIPECONF_ENABLE);
1338         }
1339
1340         I915_STATE_WARN(cur_state != state,
1341              "pipe %c assertion failure (expected %s, current %s)\n",
1342              pipe_name(pipe), state_string(state), state_string(cur_state));
1343 }
1344
1345 static void assert_plane(struct drm_i915_private *dev_priv,
1346                          enum plane plane, bool state)
1347 {
1348         int reg;
1349         u32 val;
1350         bool cur_state;
1351
1352         reg = DSPCNTR(plane);
1353         val = I915_READ(reg);
1354         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1355         I915_STATE_WARN(cur_state != state,
1356              "plane %c assertion failure (expected %s, current %s)\n",
1357              plane_name(plane), state_string(state), state_string(cur_state));
1358 }
1359
1360 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1361 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1362
1363 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1364                                    enum pipe pipe)
1365 {
1366         struct drm_device *dev = dev_priv->dev;
1367         int reg, i;
1368         u32 val;
1369         int cur_pipe;
1370
1371         /* Primary planes are fixed to pipes on gen4+ */
1372         if (INTEL_INFO(dev)->gen >= 4) {
1373                 reg = DSPCNTR(pipe);
1374                 val = I915_READ(reg);
1375                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1376                      "plane %c assertion failure, should be disabled but not\n",
1377                      plane_name(pipe));
1378                 return;
1379         }
1380
1381         /* Need to check both planes against the pipe */
1382         for_each_pipe(dev_priv, i) {
1383                 reg = DSPCNTR(i);
1384                 val = I915_READ(reg);
1385                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1386                         DISPPLANE_SEL_PIPE_SHIFT;
1387                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1388                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1389                      plane_name(i), pipe_name(pipe));
1390         }
1391 }
1392
1393 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1394                                     enum pipe pipe)
1395 {
1396         struct drm_device *dev = dev_priv->dev;
1397         int reg, sprite;
1398         u32 val;
1399
1400         if (INTEL_INFO(dev)->gen >= 9) {
1401                 for_each_sprite(dev_priv, pipe, sprite) {
1402                         val = I915_READ(PLANE_CTL(pipe, sprite));
1403                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1404                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1405                              sprite, pipe_name(pipe));
1406                 }
1407         } else if (IS_VALLEYVIEW(dev)) {
1408                 for_each_sprite(dev_priv, pipe, sprite) {
1409                         reg = SPCNTR(pipe, sprite);
1410                         val = I915_READ(reg);
1411                         I915_STATE_WARN(val & SP_ENABLE,
1412                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1413                              sprite_name(pipe, sprite), pipe_name(pipe));
1414                 }
1415         } else if (INTEL_INFO(dev)->gen >= 7) {
1416                 reg = SPRCTL(pipe);
1417                 val = I915_READ(reg);
1418                 I915_STATE_WARN(val & SPRITE_ENABLE,
1419                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1420                      plane_name(pipe), pipe_name(pipe));
1421         } else if (INTEL_INFO(dev)->gen >= 5) {
1422                 reg = DVSCNTR(pipe);
1423                 val = I915_READ(reg);
1424                 I915_STATE_WARN(val & DVS_ENABLE,
1425                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1426                      plane_name(pipe), pipe_name(pipe));
1427         }
1428 }
1429
1430 static void assert_vblank_disabled(struct drm_crtc *crtc)
1431 {
1432         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1433                 drm_crtc_vblank_put(crtc);
1434 }
1435
1436 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1437 {
1438         u32 val;
1439         bool enabled;
1440
1441         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1442
1443         val = I915_READ(PCH_DREF_CONTROL);
1444         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1445                             DREF_SUPERSPREAD_SOURCE_MASK));
1446         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1447 }
1448
1449 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1450                                            enum pipe pipe)
1451 {
1452         int reg;
1453         u32 val;
1454         bool enabled;
1455
1456         reg = PCH_TRANSCONF(pipe);
1457         val = I915_READ(reg);
1458         enabled = !!(val & TRANS_ENABLE);
1459         I915_STATE_WARN(enabled,
1460              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1461              pipe_name(pipe));
1462 }
1463
1464 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1465                             enum pipe pipe, u32 port_sel, u32 val)
1466 {
1467         if ((val & DP_PORT_EN) == 0)
1468                 return false;
1469
1470         if (HAS_PCH_CPT(dev_priv->dev)) {
1471                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1472                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1473                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1474                         return false;
1475         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1476                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1477                         return false;
1478         } else {
1479                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1480                         return false;
1481         }
1482         return true;
1483 }
1484
1485 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1486                               enum pipe pipe, u32 val)
1487 {
1488         if ((val & SDVO_ENABLE) == 0)
1489                 return false;
1490
1491         if (HAS_PCH_CPT(dev_priv->dev)) {
1492                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1493                         return false;
1494         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1495                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1496                         return false;
1497         } else {
1498                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1499                         return false;
1500         }
1501         return true;
1502 }
1503
1504 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1505                               enum pipe pipe, u32 val)
1506 {
1507         if ((val & LVDS_PORT_EN) == 0)
1508                 return false;
1509
1510         if (HAS_PCH_CPT(dev_priv->dev)) {
1511                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1512                         return false;
1513         } else {
1514                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1515                         return false;
1516         }
1517         return true;
1518 }
1519
1520 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1521                               enum pipe pipe, u32 val)
1522 {
1523         if ((val & ADPA_DAC_ENABLE) == 0)
1524                 return false;
1525         if (HAS_PCH_CPT(dev_priv->dev)) {
1526                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1527                         return false;
1528         } else {
1529                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1530                         return false;
1531         }
1532         return true;
1533 }
1534
1535 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1536                                    enum pipe pipe, int reg, u32 port_sel)
1537 {
1538         u32 val = I915_READ(reg);
1539         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1540              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1541              reg, pipe_name(pipe));
1542
1543         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1544              && (val & DP_PIPEB_SELECT),
1545              "IBX PCH dp port still using transcoder B\n");
1546 }
1547
1548 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1549                                      enum pipe pipe, int reg)
1550 {
1551         u32 val = I915_READ(reg);
1552         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1553              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1554              reg, pipe_name(pipe));
1555
1556         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1557              && (val & SDVO_PIPE_B_SELECT),
1558              "IBX PCH hdmi port still using transcoder B\n");
1559 }
1560
1561 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1562                                       enum pipe pipe)
1563 {
1564         int reg;
1565         u32 val;
1566
1567         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1568         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1569         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1570
1571         reg = PCH_ADPA;
1572         val = I915_READ(reg);
1573         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1574              "PCH VGA enabled on transcoder %c, should be disabled\n",
1575              pipe_name(pipe));
1576
1577         reg = PCH_LVDS;
1578         val = I915_READ(reg);
1579         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1580              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1581              pipe_name(pipe));
1582
1583         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1584         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1585         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1586 }
1587
1588 static void intel_init_dpio(struct drm_device *dev)
1589 {
1590         struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592         if (!IS_VALLEYVIEW(dev))
1593                 return;
1594
1595         /*
1596          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1597          * CHV x1 PHY (DP/HDMI D)
1598          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1599          */
1600         if (IS_CHERRYVIEW(dev)) {
1601                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1602                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1603         } else {
1604                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1605         }
1606 }
1607
1608 static void vlv_enable_pll(struct intel_crtc *crtc,
1609                            const struct intel_crtc_state *pipe_config)
1610 {
1611         struct drm_device *dev = crtc->base.dev;
1612         struct drm_i915_private *dev_priv = dev->dev_private;
1613         int reg = DPLL(crtc->pipe);
1614         u32 dpll = pipe_config->dpll_hw_state.dpll;
1615
1616         assert_pipe_disabled(dev_priv, crtc->pipe);
1617
1618         /* No really, not for ILK+ */
1619         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1620
1621         /* PLL is protected by panel, make sure we can write it */
1622         if (IS_MOBILE(dev_priv->dev))
1623                 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625         I915_WRITE(reg, dpll);
1626         POSTING_READ(reg);
1627         udelay(150);
1628
1629         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1630                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1631
1632         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1633         POSTING_READ(DPLL_MD(crtc->pipe));
1634
1635         /* We do this three times for luck */
1636         I915_WRITE(reg, dpll);
1637         POSTING_READ(reg);
1638         udelay(150); /* wait for warmup */
1639         I915_WRITE(reg, dpll);
1640         POSTING_READ(reg);
1641         udelay(150); /* wait for warmup */
1642         I915_WRITE(reg, dpll);
1643         POSTING_READ(reg);
1644         udelay(150); /* wait for warmup */
1645 }
1646
1647 static void chv_enable_pll(struct intel_crtc *crtc,
1648                            const struct intel_crtc_state *pipe_config)
1649 {
1650         struct drm_device *dev = crtc->base.dev;
1651         struct drm_i915_private *dev_priv = dev->dev_private;
1652         int pipe = crtc->pipe;
1653         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1654         u32 tmp;
1655
1656         assert_pipe_disabled(dev_priv, crtc->pipe);
1657
1658         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1659
1660         mutex_lock(&dev_priv->sb_lock);
1661
1662         /* Enable back the 10bit clock to display controller */
1663         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1664         tmp |= DPIO_DCLKP_EN;
1665         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1666
1667         mutex_unlock(&dev_priv->sb_lock);
1668
1669         /*
1670          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1671          */
1672         udelay(1);
1673
1674         /* Enable PLL */
1675         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1676
1677         /* Check PLL is locked */
1678         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1679                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1680
1681         /* not sure when this should be written */
1682         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1683         POSTING_READ(DPLL_MD(pipe));
1684 }
1685
1686 static int intel_num_dvo_pipes(struct drm_device *dev)
1687 {
1688         struct intel_crtc *crtc;
1689         int count = 0;
1690
1691         for_each_intel_crtc(dev, crtc)
1692                 count += crtc->base.state->active &&
1693                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1694
1695         return count;
1696 }
1697
1698 static void i9xx_enable_pll(struct intel_crtc *crtc)
1699 {
1700         struct drm_device *dev = crtc->base.dev;
1701         struct drm_i915_private *dev_priv = dev->dev_private;
1702         int reg = DPLL(crtc->pipe);
1703         u32 dpll = crtc->config->dpll_hw_state.dpll;
1704
1705         assert_pipe_disabled(dev_priv, crtc->pipe);
1706
1707         /* No really, not for ILK+ */
1708         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1709
1710         /* PLL is protected by panel, make sure we can write it */
1711         if (IS_MOBILE(dev) && !IS_I830(dev))
1712                 assert_panel_unlocked(dev_priv, crtc->pipe);
1713
1714         /* Enable DVO 2x clock on both PLLs if necessary */
1715         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1716                 /*
1717                  * It appears to be important that we don't enable this
1718                  * for the current pipe before otherwise configuring the
1719                  * PLL. No idea how this should be handled if multiple
1720                  * DVO outputs are enabled simultaneosly.
1721                  */
1722                 dpll |= DPLL_DVO_2X_MODE;
1723                 I915_WRITE(DPLL(!crtc->pipe),
1724                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1725         }
1726
1727         /* Wait for the clocks to stabilize. */
1728         POSTING_READ(reg);
1729         udelay(150);
1730
1731         if (INTEL_INFO(dev)->gen >= 4) {
1732                 I915_WRITE(DPLL_MD(crtc->pipe),
1733                            crtc->config->dpll_hw_state.dpll_md);
1734         } else {
1735                 /* The pixel multiplier can only be updated once the
1736                  * DPLL is enabled and the clocks are stable.
1737                  *
1738                  * So write it again.
1739                  */
1740                 I915_WRITE(reg, dpll);
1741         }
1742
1743         /* We do this three times for luck */
1744         I915_WRITE(reg, dpll);
1745         POSTING_READ(reg);
1746         udelay(150); /* wait for warmup */
1747         I915_WRITE(reg, dpll);
1748         POSTING_READ(reg);
1749         udelay(150); /* wait for warmup */
1750         I915_WRITE(reg, dpll);
1751         POSTING_READ(reg);
1752         udelay(150); /* wait for warmup */
1753 }
1754
1755 /**
1756  * i9xx_disable_pll - disable a PLL
1757  * @dev_priv: i915 private structure
1758  * @pipe: pipe PLL to disable
1759  *
1760  * Disable the PLL for @pipe, making sure the pipe is off first.
1761  *
1762  * Note!  This is for pre-ILK only.
1763  */
1764 static void i9xx_disable_pll(struct intel_crtc *crtc)
1765 {
1766         struct drm_device *dev = crtc->base.dev;
1767         struct drm_i915_private *dev_priv = dev->dev_private;
1768         enum pipe pipe = crtc->pipe;
1769
1770         /* Disable DVO 2x clock on both PLLs if necessary */
1771         if (IS_I830(dev) &&
1772             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1773             !intel_num_dvo_pipes(dev)) {
1774                 I915_WRITE(DPLL(PIPE_B),
1775                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1776                 I915_WRITE(DPLL(PIPE_A),
1777                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1778         }
1779
1780         /* Don't disable pipe or pipe PLLs if needed */
1781         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1782             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1783                 return;
1784
1785         /* Make sure the pipe isn't still relying on us */
1786         assert_pipe_disabled(dev_priv, pipe);
1787
1788         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1789         POSTING_READ(DPLL(pipe));
1790 }
1791
1792 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793 {
1794         u32 val;
1795
1796         /* Make sure the pipe isn't still relying on us */
1797         assert_pipe_disabled(dev_priv, pipe);
1798
1799         /*
1800          * Leave integrated clock source and reference clock enabled for pipe B.
1801          * The latter is needed for VGA hotplug / manual detection.
1802          */
1803         val = DPLL_VGA_MODE_DIS;
1804         if (pipe == PIPE_B)
1805                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1806         I915_WRITE(DPLL(pipe), val);
1807         POSTING_READ(DPLL(pipe));
1808
1809 }
1810
1811 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1812 {
1813         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1814         u32 val;
1815
1816         /* Make sure the pipe isn't still relying on us */
1817         assert_pipe_disabled(dev_priv, pipe);
1818
1819         /* Set PLL en = 0 */
1820         val = DPLL_SSC_REF_CLK_CHV |
1821                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1822         if (pipe != PIPE_A)
1823                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1824         I915_WRITE(DPLL(pipe), val);
1825         POSTING_READ(DPLL(pipe));
1826
1827         mutex_lock(&dev_priv->sb_lock);
1828
1829         /* Disable 10bit clock to display controller */
1830         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1831         val &= ~DPIO_DCLKP_EN;
1832         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1833
1834         /* disable left/right clock distribution */
1835         if (pipe != PIPE_B) {
1836                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1837                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1838                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1839         } else {
1840                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1841                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1842                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1843         }
1844
1845         mutex_unlock(&dev_priv->sb_lock);
1846 }
1847
1848 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1849                          struct intel_digital_port *dport,
1850                          unsigned int expected_mask)
1851 {
1852         u32 port_mask;
1853         int dpll_reg;
1854
1855         switch (dport->port) {
1856         case PORT_B:
1857                 port_mask = DPLL_PORTB_READY_MASK;
1858                 dpll_reg = DPLL(0);
1859                 break;
1860         case PORT_C:
1861                 port_mask = DPLL_PORTC_READY_MASK;
1862                 dpll_reg = DPLL(0);
1863                 expected_mask <<= 4;
1864                 break;
1865         case PORT_D:
1866                 port_mask = DPLL_PORTD_READY_MASK;
1867                 dpll_reg = DPIO_PHY_STATUS;
1868                 break;
1869         default:
1870                 BUG();
1871         }
1872
1873         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1874                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1875                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1876 }
1877
1878 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1879 {
1880         struct drm_device *dev = crtc->base.dev;
1881         struct drm_i915_private *dev_priv = dev->dev_private;
1882         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1883
1884         if (WARN_ON(pll == NULL))
1885                 return;
1886
1887         WARN_ON(!pll->config.crtc_mask);
1888         if (pll->active == 0) {
1889                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1890                 WARN_ON(pll->on);
1891                 assert_shared_dpll_disabled(dev_priv, pll);
1892
1893                 pll->mode_set(dev_priv, pll);
1894         }
1895 }
1896
1897 /**
1898  * intel_enable_shared_dpll - enable PCH PLL
1899  * @dev_priv: i915 private structure
1900  * @pipe: pipe PLL to enable
1901  *
1902  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1903  * drives the transcoder clock.
1904  */
1905 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1906 {
1907         struct drm_device *dev = crtc->base.dev;
1908         struct drm_i915_private *dev_priv = dev->dev_private;
1909         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1910
1911         if (WARN_ON(pll == NULL))
1912                 return;
1913
1914         if (WARN_ON(pll->config.crtc_mask == 0))
1915                 return;
1916
1917         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1918                       pll->name, pll->active, pll->on,
1919                       crtc->base.base.id);
1920
1921         if (pll->active++) {
1922                 WARN_ON(!pll->on);
1923                 assert_shared_dpll_enabled(dev_priv, pll);
1924                 return;
1925         }
1926         WARN_ON(pll->on);
1927
1928         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1929
1930         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1931         pll->enable(dev_priv, pll);
1932         pll->on = true;
1933 }
1934
1935 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1936 {
1937         struct drm_device *dev = crtc->base.dev;
1938         struct drm_i915_private *dev_priv = dev->dev_private;
1939         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1940
1941         /* PCH only available on ILK+ */
1942         if (INTEL_INFO(dev)->gen < 5)
1943                 return;
1944
1945         if (pll == NULL)
1946                 return;
1947
1948         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1949                 return;
1950
1951         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952                       pll->name, pll->active, pll->on,
1953                       crtc->base.base.id);
1954
1955         if (WARN_ON(pll->active == 0)) {
1956                 assert_shared_dpll_disabled(dev_priv, pll);
1957                 return;
1958         }
1959
1960         assert_shared_dpll_enabled(dev_priv, pll);
1961         WARN_ON(!pll->on);
1962         if (--pll->active)
1963                 return;
1964
1965         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1966         pll->disable(dev_priv, pll);
1967         pll->on = false;
1968
1969         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1970 }
1971
1972 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1973                                            enum pipe pipe)
1974 {
1975         struct drm_device *dev = dev_priv->dev;
1976         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1977         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1978         uint32_t reg, val, pipeconf_val;
1979
1980         /* PCH only available on ILK+ */
1981         BUG_ON(!HAS_PCH_SPLIT(dev));
1982
1983         /* Make sure PCH DPLL is enabled */
1984         assert_shared_dpll_enabled(dev_priv,
1985                                    intel_crtc_to_shared_dpll(intel_crtc));
1986
1987         /* FDI must be feeding us bits for PCH ports */
1988         assert_fdi_tx_enabled(dev_priv, pipe);
1989         assert_fdi_rx_enabled(dev_priv, pipe);
1990
1991         if (HAS_PCH_CPT(dev)) {
1992                 /* Workaround: Set the timing override bit before enabling the
1993                  * pch transcoder. */
1994                 reg = TRANS_CHICKEN2(pipe);
1995                 val = I915_READ(reg);
1996                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997                 I915_WRITE(reg, val);
1998         }
1999
2000         reg = PCH_TRANSCONF(pipe);
2001         val = I915_READ(reg);
2002         pipeconf_val = I915_READ(PIPECONF(pipe));
2003
2004         if (HAS_PCH_IBX(dev_priv->dev)) {
2005                 /*
2006                  * Make the BPC in transcoder be consistent with
2007                  * that in pipeconf reg. For HDMI we must use 8bpc
2008                  * here for both 8bpc and 12bpc.
2009                  */
2010                 val &= ~PIPECONF_BPC_MASK;
2011                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2012                         val |= PIPECONF_8BPC;
2013                 else
2014                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2015         }
2016
2017         val &= ~TRANS_INTERLACE_MASK;
2018         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2019                 if (HAS_PCH_IBX(dev_priv->dev) &&
2020                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2021                         val |= TRANS_LEGACY_INTERLACED_ILK;
2022                 else
2023                         val |= TRANS_INTERLACED;
2024         else
2025                 val |= TRANS_PROGRESSIVE;
2026
2027         I915_WRITE(reg, val | TRANS_ENABLE);
2028         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2029                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2030 }
2031
2032 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2033                                       enum transcoder cpu_transcoder)
2034 {
2035         u32 val, pipeconf_val;
2036
2037         /* PCH only available on ILK+ */
2038         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2039
2040         /* FDI must be feeding us bits for PCH ports */
2041         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2042         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2043
2044         /* Workaround: set timing override bit. */
2045         val = I915_READ(_TRANSA_CHICKEN2);
2046         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2047         I915_WRITE(_TRANSA_CHICKEN2, val);
2048
2049         val = TRANS_ENABLE;
2050         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2051
2052         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2053             PIPECONF_INTERLACED_ILK)
2054                 val |= TRANS_INTERLACED;
2055         else
2056                 val |= TRANS_PROGRESSIVE;
2057
2058         I915_WRITE(LPT_TRANSCONF, val);
2059         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2060                 DRM_ERROR("Failed to enable PCH transcoder\n");
2061 }
2062
2063 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2064                                             enum pipe pipe)
2065 {
2066         struct drm_device *dev = dev_priv->dev;
2067         uint32_t reg, val;
2068
2069         /* FDI relies on the transcoder */
2070         assert_fdi_tx_disabled(dev_priv, pipe);
2071         assert_fdi_rx_disabled(dev_priv, pipe);
2072
2073         /* Ports must be off as well */
2074         assert_pch_ports_disabled(dev_priv, pipe);
2075
2076         reg = PCH_TRANSCONF(pipe);
2077         val = I915_READ(reg);
2078         val &= ~TRANS_ENABLE;
2079         I915_WRITE(reg, val);
2080         /* wait for PCH transcoder off, transcoder state */
2081         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2082                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2083
2084         if (!HAS_PCH_IBX(dev)) {
2085                 /* Workaround: Clear the timing override chicken bit again. */
2086                 reg = TRANS_CHICKEN2(pipe);
2087                 val = I915_READ(reg);
2088                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2089                 I915_WRITE(reg, val);
2090         }
2091 }
2092
2093 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2094 {
2095         u32 val;
2096
2097         val = I915_READ(LPT_TRANSCONF);
2098         val &= ~TRANS_ENABLE;
2099         I915_WRITE(LPT_TRANSCONF, val);
2100         /* wait for PCH transcoder off, transcoder state */
2101         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2102                 DRM_ERROR("Failed to disable PCH transcoder\n");
2103
2104         /* Workaround: clear timing override bit. */
2105         val = I915_READ(_TRANSA_CHICKEN2);
2106         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2107         I915_WRITE(_TRANSA_CHICKEN2, val);
2108 }
2109
2110 /**
2111  * intel_enable_pipe - enable a pipe, asserting requirements
2112  * @crtc: crtc responsible for the pipe
2113  *
2114  * Enable @crtc's pipe, making sure that various hardware specific requirements
2115  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2116  */
2117 static void intel_enable_pipe(struct intel_crtc *crtc)
2118 {
2119         struct drm_device *dev = crtc->base.dev;
2120         struct drm_i915_private *dev_priv = dev->dev_private;
2121         enum pipe pipe = crtc->pipe;
2122         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2123                                                                       pipe);
2124         enum pipe pch_transcoder;
2125         int reg;
2126         u32 val;
2127
2128         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2129
2130         assert_planes_disabled(dev_priv, pipe);
2131         assert_cursor_disabled(dev_priv, pipe);
2132         assert_sprites_disabled(dev_priv, pipe);
2133
2134         if (HAS_PCH_LPT(dev_priv->dev))
2135                 pch_transcoder = TRANSCODER_A;
2136         else
2137                 pch_transcoder = pipe;
2138
2139         /*
2140          * A pipe without a PLL won't actually be able to drive bits from
2141          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2142          * need the check.
2143          */
2144         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2145                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2146                         assert_dsi_pll_enabled(dev_priv);
2147                 else
2148                         assert_pll_enabled(dev_priv, pipe);
2149         else {
2150                 if (crtc->config->has_pch_encoder) {
2151                         /* if driving the PCH, we need FDI enabled */
2152                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2153                         assert_fdi_tx_pll_enabled(dev_priv,
2154                                                   (enum pipe) cpu_transcoder);
2155                 }
2156                 /* FIXME: assert CPU port conditions for SNB+ */
2157         }
2158
2159         reg = PIPECONF(cpu_transcoder);
2160         val = I915_READ(reg);
2161         if (val & PIPECONF_ENABLE) {
2162                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2163                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2164                 return;
2165         }
2166
2167         I915_WRITE(reg, val | PIPECONF_ENABLE);
2168         POSTING_READ(reg);
2169 }
2170
2171 /**
2172  * intel_disable_pipe - disable a pipe, asserting requirements
2173  * @crtc: crtc whose pipes is to be disabled
2174  *
2175  * Disable the pipe of @crtc, making sure that various hardware
2176  * specific requirements are met, if applicable, e.g. plane
2177  * disabled, panel fitter off, etc.
2178  *
2179  * Will wait until the pipe has shut down before returning.
2180  */
2181 static void intel_disable_pipe(struct intel_crtc *crtc)
2182 {
2183         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2184         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2185         enum pipe pipe = crtc->pipe;
2186         int reg;
2187         u32 val;
2188
2189         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2190
2191         /*
2192          * Make sure planes won't keep trying to pump pixels to us,
2193          * or we might hang the display.
2194          */
2195         assert_planes_disabled(dev_priv, pipe);
2196         assert_cursor_disabled(dev_priv, pipe);
2197         assert_sprites_disabled(dev_priv, pipe);
2198
2199         reg = PIPECONF(cpu_transcoder);
2200         val = I915_READ(reg);
2201         if ((val & PIPECONF_ENABLE) == 0)
2202                 return;
2203
2204         /*
2205          * Double wide has implications for planes
2206          * so best keep it disabled when not needed.
2207          */
2208         if (crtc->config->double_wide)
2209                 val &= ~PIPECONF_DOUBLE_WIDE;
2210
2211         /* Don't disable pipe or pipe PLLs if needed */
2212         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2213             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2214                 val &= ~PIPECONF_ENABLE;
2215
2216         I915_WRITE(reg, val);
2217         if ((val & PIPECONF_ENABLE) == 0)
2218                 intel_wait_for_pipe_off(crtc);
2219 }
2220
2221 static bool need_vtd_wa(struct drm_device *dev)
2222 {
2223 #ifdef CONFIG_INTEL_IOMMU
2224         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2225                 return true;
2226 #endif
2227         return false;
2228 }
2229
2230 unsigned int
2231 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2232                   uint64_t fb_format_modifier)
2233 {
2234         unsigned int tile_height;
2235         uint32_t pixel_bytes;
2236
2237         switch (fb_format_modifier) {
2238         case DRM_FORMAT_MOD_NONE:
2239                 tile_height = 1;
2240                 break;
2241         case I915_FORMAT_MOD_X_TILED:
2242                 tile_height = IS_GEN2(dev) ? 16 : 8;
2243                 break;
2244         case I915_FORMAT_MOD_Y_TILED:
2245                 tile_height = 32;
2246                 break;
2247         case I915_FORMAT_MOD_Yf_TILED:
2248                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2249                 switch (pixel_bytes) {
2250                 default:
2251                 case 1:
2252                         tile_height = 64;
2253                         break;
2254                 case 2:
2255                 case 4:
2256                         tile_height = 32;
2257                         break;
2258                 case 8:
2259                         tile_height = 16;
2260                         break;
2261                 case 16:
2262                         WARN_ONCE(1,
2263                                   "128-bit pixels are not supported for display!");
2264                         tile_height = 16;
2265                         break;
2266                 }
2267                 break;
2268         default:
2269                 MISSING_CASE(fb_format_modifier);
2270                 tile_height = 1;
2271                 break;
2272         }
2273
2274         return tile_height;
2275 }
2276
2277 unsigned int
2278 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2279                       uint32_t pixel_format, uint64_t fb_format_modifier)
2280 {
2281         return ALIGN(height, intel_tile_height(dev, pixel_format,
2282                                                fb_format_modifier));
2283 }
2284
2285 static int
2286 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2287                         const struct drm_plane_state *plane_state)
2288 {
2289         struct intel_rotation_info *info = &view->rotation_info;
2290         unsigned int tile_height, tile_pitch;
2291
2292         *view = i915_ggtt_view_normal;
2293
2294         if (!plane_state)
2295                 return 0;
2296
2297         if (!intel_rotation_90_or_270(plane_state->rotation))
2298                 return 0;
2299
2300         *view = i915_ggtt_view_rotated;
2301
2302         info->height = fb->height;
2303         info->pixel_format = fb->pixel_format;
2304         info->pitch = fb->pitches[0];
2305         info->fb_modifier = fb->modifier[0];
2306
2307         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2308                                         fb->modifier[0]);
2309         tile_pitch = PAGE_SIZE / tile_height;
2310         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2311         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2312         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2313
2314         return 0;
2315 }
2316
2317 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2318 {
2319         if (INTEL_INFO(dev_priv)->gen >= 9)
2320                 return 256 * 1024;
2321         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2322                  IS_VALLEYVIEW(dev_priv))
2323                 return 128 * 1024;
2324         else if (INTEL_INFO(dev_priv)->gen >= 4)
2325                 return 4 * 1024;
2326         else
2327                 return 0;
2328 }
2329
2330 int
2331 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2332                            struct drm_framebuffer *fb,
2333                            const struct drm_plane_state *plane_state,
2334                            struct intel_engine_cs *pipelined,
2335                            struct drm_i915_gem_request **pipelined_request)
2336 {
2337         struct drm_device *dev = fb->dev;
2338         struct drm_i915_private *dev_priv = dev->dev_private;
2339         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2340         struct i915_ggtt_view view;
2341         u32 alignment;
2342         int ret;
2343
2344         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2345
2346         switch (fb->modifier[0]) {
2347         case DRM_FORMAT_MOD_NONE:
2348                 alignment = intel_linear_alignment(dev_priv);
2349                 break;
2350         case I915_FORMAT_MOD_X_TILED:
2351                 if (INTEL_INFO(dev)->gen >= 9)
2352                         alignment = 256 * 1024;
2353                 else {
2354                         /* pin() will align the object as required by fence */
2355                         alignment = 0;
2356                 }
2357                 break;
2358         case I915_FORMAT_MOD_Y_TILED:
2359         case I915_FORMAT_MOD_Yf_TILED:
2360                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2361                           "Y tiling bo slipped through, driver bug!\n"))
2362                         return -EINVAL;
2363                 alignment = 1 * 1024 * 1024;
2364                 break;
2365         default:
2366                 MISSING_CASE(fb->modifier[0]);
2367                 return -EINVAL;
2368         }
2369
2370         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2371         if (ret)
2372                 return ret;
2373
2374         /* Note that the w/a also requires 64 PTE of padding following the
2375          * bo. We currently fill all unused PTE with the shadow page and so
2376          * we should always have valid PTE following the scanout preventing
2377          * the VT-d warning.
2378          */
2379         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2380                 alignment = 256 * 1024;
2381
2382         /*
2383          * Global gtt pte registers are special registers which actually forward
2384          * writes to a chunk of system memory. Which means that there is no risk
2385          * that the register values disappear as soon as we call
2386          * intel_runtime_pm_put(), so it is correct to wrap only the
2387          * pin/unpin/fence and not more.
2388          */
2389         intel_runtime_pm_get(dev_priv);
2390
2391         dev_priv->mm.interruptible = false;
2392         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2393                                                    pipelined_request, &view);
2394         if (ret)
2395                 goto err_interruptible;
2396
2397         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2398          * fence, whereas 965+ only requires a fence if using
2399          * framebuffer compression.  For simplicity, we always install
2400          * a fence as the cost is not that onerous.
2401          */
2402         ret = i915_gem_object_get_fence(obj);
2403         if (ret == -EDEADLK) {
2404                 /*
2405                  * -EDEADLK means there are no free fences
2406                  * no pending flips.
2407                  *
2408                  * This is propagated to atomic, but it uses
2409                  * -EDEADLK to force a locking recovery, so
2410                  * change the returned error to -EBUSY.
2411                  */
2412                 ret = -EBUSY;
2413                 goto err_unpin;
2414         } else if (ret)
2415                 goto err_unpin;
2416
2417         i915_gem_object_pin_fence(obj);
2418
2419         dev_priv->mm.interruptible = true;
2420         intel_runtime_pm_put(dev_priv);
2421         return 0;
2422
2423 err_unpin:
2424         i915_gem_object_unpin_from_display_plane(obj, &view);
2425 err_interruptible:
2426         dev_priv->mm.interruptible = true;
2427         intel_runtime_pm_put(dev_priv);
2428         return ret;
2429 }
2430
2431 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2432                                const struct drm_plane_state *plane_state)
2433 {
2434         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2435         struct i915_ggtt_view view;
2436         int ret;
2437
2438         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2439
2440         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2441         WARN_ONCE(ret, "Couldn't get view from plane state!");
2442
2443         i915_gem_object_unpin_fence(obj);
2444         i915_gem_object_unpin_from_display_plane(obj, &view);
2445 }
2446
2447 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2448  * is assumed to be a power-of-two. */
2449 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2450                                              int *x, int *y,
2451                                              unsigned int tiling_mode,
2452                                              unsigned int cpp,
2453                                              unsigned int pitch)
2454 {
2455         if (tiling_mode != I915_TILING_NONE) {
2456                 unsigned int tile_rows, tiles;
2457
2458                 tile_rows = *y / 8;
2459                 *y %= 8;
2460
2461                 tiles = *x / (512/cpp);
2462                 *x %= 512/cpp;
2463
2464                 return tile_rows * pitch * 8 + tiles * 4096;
2465         } else {
2466                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2467                 unsigned int offset;
2468
2469                 offset = *y * pitch + *x * cpp;
2470                 *y = (offset & alignment) / pitch;
2471                 *x = ((offset & alignment) - *y * pitch) / cpp;
2472                 return offset & ~alignment;
2473         }
2474 }
2475
2476 static int i9xx_format_to_fourcc(int format)
2477 {
2478         switch (format) {
2479         case DISPPLANE_8BPP:
2480                 return DRM_FORMAT_C8;
2481         case DISPPLANE_BGRX555:
2482                 return DRM_FORMAT_XRGB1555;
2483         case DISPPLANE_BGRX565:
2484                 return DRM_FORMAT_RGB565;
2485         default:
2486         case DISPPLANE_BGRX888:
2487                 return DRM_FORMAT_XRGB8888;
2488         case DISPPLANE_RGBX888:
2489                 return DRM_FORMAT_XBGR8888;
2490         case DISPPLANE_BGRX101010:
2491                 return DRM_FORMAT_XRGB2101010;
2492         case DISPPLANE_RGBX101010:
2493                 return DRM_FORMAT_XBGR2101010;
2494         }
2495 }
2496
2497 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2498 {
2499         switch (format) {
2500         case PLANE_CTL_FORMAT_RGB_565:
2501                 return DRM_FORMAT_RGB565;
2502         default:
2503         case PLANE_CTL_FORMAT_XRGB_8888:
2504                 if (rgb_order) {
2505                         if (alpha)
2506                                 return DRM_FORMAT_ABGR8888;
2507                         else
2508                                 return DRM_FORMAT_XBGR8888;
2509                 } else {
2510                         if (alpha)
2511                                 return DRM_FORMAT_ARGB8888;
2512                         else
2513                                 return DRM_FORMAT_XRGB8888;
2514                 }
2515         case PLANE_CTL_FORMAT_XRGB_2101010:
2516                 if (rgb_order)
2517                         return DRM_FORMAT_XBGR2101010;
2518                 else
2519                         return DRM_FORMAT_XRGB2101010;
2520         }
2521 }
2522
2523 static bool
2524 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2525                               struct intel_initial_plane_config *plane_config)
2526 {
2527         struct drm_device *dev = crtc->base.dev;
2528         struct drm_i915_gem_object *obj = NULL;
2529         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2530         struct drm_framebuffer *fb = &plane_config->fb->base;
2531         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2532         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2533                                     PAGE_SIZE);
2534
2535         size_aligned -= base_aligned;
2536
2537         if (plane_config->size == 0)
2538                 return false;
2539
2540         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2541                                                              base_aligned,
2542                                                              base_aligned,
2543                                                              size_aligned);
2544         if (!obj)
2545                 return false;
2546
2547         obj->tiling_mode = plane_config->tiling;
2548         if (obj->tiling_mode == I915_TILING_X)
2549                 obj->stride = fb->pitches[0];
2550
2551         mode_cmd.pixel_format = fb->pixel_format;
2552         mode_cmd.width = fb->width;
2553         mode_cmd.height = fb->height;
2554         mode_cmd.pitches[0] = fb->pitches[0];
2555         mode_cmd.modifier[0] = fb->modifier[0];
2556         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2557
2558         mutex_lock(&dev->struct_mutex);
2559         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2560                                    &mode_cmd, obj)) {
2561                 DRM_DEBUG_KMS("intel fb init failed\n");
2562                 goto out_unref_obj;
2563         }
2564         mutex_unlock(&dev->struct_mutex);
2565
2566         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2567         return true;
2568
2569 out_unref_obj:
2570         drm_gem_object_unreference(&obj->base);
2571         mutex_unlock(&dev->struct_mutex);
2572         return false;
2573 }
2574
2575 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2576 static void
2577 update_state_fb(struct drm_plane *plane)
2578 {
2579         if (plane->fb == plane->state->fb)
2580                 return;
2581
2582         if (plane->state->fb)
2583                 drm_framebuffer_unreference(plane->state->fb);
2584         plane->state->fb = plane->fb;
2585         if (plane->state->fb)
2586                 drm_framebuffer_reference(plane->state->fb);
2587 }
2588
2589 static void
2590 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2591                              struct intel_initial_plane_config *plane_config)
2592 {
2593         struct drm_device *dev = intel_crtc->base.dev;
2594         struct drm_i915_private *dev_priv = dev->dev_private;
2595         struct drm_crtc *c;
2596         struct intel_crtc *i;
2597         struct drm_i915_gem_object *obj;
2598         struct drm_plane *primary = intel_crtc->base.primary;
2599         struct drm_plane_state *plane_state = primary->state;
2600         struct drm_framebuffer *fb;
2601
2602         if (!plane_config->fb)
2603                 return;
2604
2605         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2606                 fb = &plane_config->fb->base;
2607                 goto valid_fb;
2608         }
2609
2610         kfree(plane_config->fb);
2611
2612         /*
2613          * Failed to alloc the obj, check to see if we should share
2614          * an fb with another CRTC instead
2615          */
2616         for_each_crtc(dev, c) {
2617                 i = to_intel_crtc(c);
2618
2619                 if (c == &intel_crtc->base)
2620                         continue;
2621
2622                 if (!i->active)
2623                         continue;
2624
2625                 fb = c->primary->fb;
2626                 if (!fb)
2627                         continue;
2628
2629                 obj = intel_fb_obj(fb);
2630                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2631                         drm_framebuffer_reference(fb);
2632                         goto valid_fb;
2633                 }
2634         }
2635
2636         return;
2637
2638 valid_fb:
2639         plane_state->src_x = plane_state->src_y = 0;
2640         plane_state->src_w = fb->width << 16;
2641         plane_state->src_h = fb->height << 16;
2642
2643         plane_state->crtc_x = plane_state->src_y = 0;
2644         plane_state->crtc_w = fb->width;
2645         plane_state->crtc_h = fb->height;
2646
2647         obj = intel_fb_obj(fb);
2648         if (obj->tiling_mode != I915_TILING_NONE)
2649                 dev_priv->preserve_bios_swizzle = true;
2650
2651         drm_framebuffer_reference(fb);
2652         primary->fb = primary->state->fb = fb;
2653         primary->crtc = primary->state->crtc = &intel_crtc->base;
2654         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2655         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2656 }
2657
2658 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2659                                       struct drm_framebuffer *fb,
2660                                       int x, int y)
2661 {
2662         struct drm_device *dev = crtc->dev;
2663         struct drm_i915_private *dev_priv = dev->dev_private;
2664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2665         struct drm_plane *primary = crtc->primary;
2666         bool visible = to_intel_plane_state(primary->state)->visible;
2667         struct drm_i915_gem_object *obj;
2668         int plane = intel_crtc->plane;
2669         unsigned long linear_offset;
2670         u32 dspcntr;
2671         u32 reg = DSPCNTR(plane);
2672         int pixel_size;
2673
2674         if (!visible || !fb) {
2675                 I915_WRITE(reg, 0);
2676                 if (INTEL_INFO(dev)->gen >= 4)
2677                         I915_WRITE(DSPSURF(plane), 0);
2678                 else
2679                         I915_WRITE(DSPADDR(plane), 0);
2680                 POSTING_READ(reg);
2681                 return;
2682         }
2683
2684         obj = intel_fb_obj(fb);
2685         if (WARN_ON(obj == NULL))
2686                 return;
2687
2688         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2689
2690         dspcntr = DISPPLANE_GAMMA_ENABLE;
2691
2692         dspcntr |= DISPLAY_PLANE_ENABLE;
2693
2694         if (INTEL_INFO(dev)->gen < 4) {
2695                 if (intel_crtc->pipe == PIPE_B)
2696                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2697
2698                 /* pipesrc and dspsize control the size that is scaled from,
2699                  * which should always be the user's requested size.
2700                  */
2701                 I915_WRITE(DSPSIZE(plane),
2702                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2703                            (intel_crtc->config->pipe_src_w - 1));
2704                 I915_WRITE(DSPPOS(plane), 0);
2705         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2706                 I915_WRITE(PRIMSIZE(plane),
2707                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2708                            (intel_crtc->config->pipe_src_w - 1));
2709                 I915_WRITE(PRIMPOS(plane), 0);
2710                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2711         }
2712
2713         switch (fb->pixel_format) {
2714         case DRM_FORMAT_C8:
2715                 dspcntr |= DISPPLANE_8BPP;
2716                 break;
2717         case DRM_FORMAT_XRGB1555:
2718                 dspcntr |= DISPPLANE_BGRX555;
2719                 break;
2720         case DRM_FORMAT_RGB565:
2721                 dspcntr |= DISPPLANE_BGRX565;
2722                 break;
2723         case DRM_FORMAT_XRGB8888:
2724                 dspcntr |= DISPPLANE_BGRX888;
2725                 break;
2726         case DRM_FORMAT_XBGR8888:
2727                 dspcntr |= DISPPLANE_RGBX888;
2728                 break;
2729         case DRM_FORMAT_XRGB2101010:
2730                 dspcntr |= DISPPLANE_BGRX101010;
2731                 break;
2732         case DRM_FORMAT_XBGR2101010:
2733                 dspcntr |= DISPPLANE_RGBX101010;
2734                 break;
2735         default:
2736                 BUG();
2737         }
2738
2739         if (INTEL_INFO(dev)->gen >= 4 &&
2740             obj->tiling_mode != I915_TILING_NONE)
2741                 dspcntr |= DISPPLANE_TILED;
2742
2743         if (IS_G4X(dev))
2744                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2745
2746         linear_offset = y * fb->pitches[0] + x * pixel_size;
2747
2748         if (INTEL_INFO(dev)->gen >= 4) {
2749                 intel_crtc->dspaddr_offset =
2750                         intel_gen4_compute_page_offset(dev_priv,
2751                                                        &x, &y, obj->tiling_mode,
2752                                                        pixel_size,
2753                                                        fb->pitches[0]);
2754                 linear_offset -= intel_crtc->dspaddr_offset;
2755         } else {
2756                 intel_crtc->dspaddr_offset = linear_offset;
2757         }
2758
2759         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2760                 dspcntr |= DISPPLANE_ROTATE_180;
2761
2762                 x += (intel_crtc->config->pipe_src_w - 1);
2763                 y += (intel_crtc->config->pipe_src_h - 1);
2764
2765                 /* Finding the last pixel of the last line of the display
2766                 data and adding to linear_offset*/
2767                 linear_offset +=
2768                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2769                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2770         }
2771
2772         I915_WRITE(reg, dspcntr);
2773
2774         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2775         if (INTEL_INFO(dev)->gen >= 4) {
2776                 I915_WRITE(DSPSURF(plane),
2777                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2778                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2779                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2780         } else
2781                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2782         POSTING_READ(reg);
2783 }
2784
2785 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2786                                           struct drm_framebuffer *fb,
2787                                           int x, int y)
2788 {
2789         struct drm_device *dev = crtc->dev;
2790         struct drm_i915_private *dev_priv = dev->dev_private;
2791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2792         struct drm_plane *primary = crtc->primary;
2793         bool visible = to_intel_plane_state(primary->state)->visible;
2794         struct drm_i915_gem_object *obj;
2795         int plane = intel_crtc->plane;
2796         unsigned long linear_offset;
2797         u32 dspcntr;
2798         u32 reg = DSPCNTR(plane);
2799         int pixel_size;
2800
2801         if (!visible || !fb) {
2802                 I915_WRITE(reg, 0);
2803                 I915_WRITE(DSPSURF(plane), 0);
2804                 POSTING_READ(reg);
2805                 return;
2806         }
2807
2808         obj = intel_fb_obj(fb);
2809         if (WARN_ON(obj == NULL))
2810                 return;
2811
2812         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2813
2814         dspcntr = DISPPLANE_GAMMA_ENABLE;
2815
2816         dspcntr |= DISPLAY_PLANE_ENABLE;
2817
2818         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2819                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2820
2821         switch (fb->pixel_format) {
2822         case DRM_FORMAT_C8:
2823                 dspcntr |= DISPPLANE_8BPP;
2824                 break;
2825         case DRM_FORMAT_RGB565:
2826                 dspcntr |= DISPPLANE_BGRX565;
2827                 break;
2828         case DRM_FORMAT_XRGB8888:
2829                 dspcntr |= DISPPLANE_BGRX888;
2830                 break;
2831         case DRM_FORMAT_XBGR8888:
2832                 dspcntr |= DISPPLANE_RGBX888;
2833                 break;
2834         case DRM_FORMAT_XRGB2101010:
2835                 dspcntr |= DISPPLANE_BGRX101010;
2836                 break;
2837         case DRM_FORMAT_XBGR2101010:
2838                 dspcntr |= DISPPLANE_RGBX101010;
2839                 break;
2840         default:
2841                 BUG();
2842         }
2843
2844         if (obj->tiling_mode != I915_TILING_NONE)
2845                 dspcntr |= DISPPLANE_TILED;
2846
2847         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2848                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2849
2850         linear_offset = y * fb->pitches[0] + x * pixel_size;
2851         intel_crtc->dspaddr_offset =
2852                 intel_gen4_compute_page_offset(dev_priv,
2853                                                &x, &y, obj->tiling_mode,
2854                                                pixel_size,
2855                                                fb->pitches[0]);
2856         linear_offset -= intel_crtc->dspaddr_offset;
2857         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2858                 dspcntr |= DISPPLANE_ROTATE_180;
2859
2860                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2861                         x += (intel_crtc->config->pipe_src_w - 1);
2862                         y += (intel_crtc->config->pipe_src_h - 1);
2863
2864                         /* Finding the last pixel of the last line of the display
2865                         data and adding to linear_offset*/
2866                         linear_offset +=
2867                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2868                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2869                 }
2870         }
2871
2872         I915_WRITE(reg, dspcntr);
2873
2874         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2875         I915_WRITE(DSPSURF(plane),
2876                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2877         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2878                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2879         } else {
2880                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2881                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2882         }
2883         POSTING_READ(reg);
2884 }
2885
2886 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2887                               uint32_t pixel_format)
2888 {
2889         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2890
2891         /*
2892          * The stride is either expressed as a multiple of 64 bytes
2893          * chunks for linear buffers or in number of tiles for tiled
2894          * buffers.
2895          */
2896         switch (fb_modifier) {
2897         case DRM_FORMAT_MOD_NONE:
2898                 return 64;
2899         case I915_FORMAT_MOD_X_TILED:
2900                 if (INTEL_INFO(dev)->gen == 2)
2901                         return 128;
2902                 return 512;
2903         case I915_FORMAT_MOD_Y_TILED:
2904                 /* No need to check for old gens and Y tiling since this is
2905                  * about the display engine and those will be blocked before
2906                  * we get here.
2907                  */
2908                 return 128;
2909         case I915_FORMAT_MOD_Yf_TILED:
2910                 if (bits_per_pixel == 8)
2911                         return 64;
2912                 else
2913                         return 128;
2914         default:
2915                 MISSING_CASE(fb_modifier);
2916                 return 64;
2917         }
2918 }
2919
2920 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2921                                      struct drm_i915_gem_object *obj)
2922 {
2923         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2924
2925         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2926                 view = &i915_ggtt_view_rotated;
2927
2928         return i915_gem_obj_ggtt_offset_view(obj, view);
2929 }
2930
2931 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2932 {
2933         struct drm_device *dev = intel_crtc->base.dev;
2934         struct drm_i915_private *dev_priv = dev->dev_private;
2935
2936         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2937         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2938         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2939         DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2940                 intel_crtc->base.base.id, intel_crtc->pipe, id);
2941 }
2942
2943 /*
2944  * This function detaches (aka. unbinds) unused scalers in hardware
2945  */
2946 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2947 {
2948         struct intel_crtc_scaler_state *scaler_state;
2949         int i;
2950
2951         scaler_state = &intel_crtc->config->scaler_state;
2952
2953         /* loop through and disable scalers that aren't in use */
2954         for (i = 0; i < intel_crtc->num_scalers; i++) {
2955                 if (!scaler_state->scalers[i].in_use)
2956                         skl_detach_scaler(intel_crtc, i);
2957         }
2958 }
2959
2960 u32 skl_plane_ctl_format(uint32_t pixel_format)
2961 {
2962         switch (pixel_format) {
2963         case DRM_FORMAT_C8:
2964                 return PLANE_CTL_FORMAT_INDEXED;
2965         case DRM_FORMAT_RGB565:
2966                 return PLANE_CTL_FORMAT_RGB_565;
2967         case DRM_FORMAT_XBGR8888:
2968                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2969         case DRM_FORMAT_XRGB8888:
2970                 return PLANE_CTL_FORMAT_XRGB_8888;
2971         /*
2972          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2973          * to be already pre-multiplied. We need to add a knob (or a different
2974          * DRM_FORMAT) for user-space to configure that.
2975          */
2976         case DRM_FORMAT_ABGR8888:
2977                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2978                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2979         case DRM_FORMAT_ARGB8888:
2980                 return PLANE_CTL_FORMAT_XRGB_8888 |
2981                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2982         case DRM_FORMAT_XRGB2101010:
2983                 return PLANE_CTL_FORMAT_XRGB_2101010;
2984         case DRM_FORMAT_XBGR2101010:
2985                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2986         case DRM_FORMAT_YUYV:
2987                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2988         case DRM_FORMAT_YVYU:
2989                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2990         case DRM_FORMAT_UYVY:
2991                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2992         case DRM_FORMAT_VYUY:
2993                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2994         default:
2995                 MISSING_CASE(pixel_format);
2996         }
2997
2998         return 0;
2999 }
3000
3001 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3002 {
3003         switch (fb_modifier) {
3004         case DRM_FORMAT_MOD_NONE:
3005                 break;
3006         case I915_FORMAT_MOD_X_TILED:
3007                 return PLANE_CTL_TILED_X;
3008         case I915_FORMAT_MOD_Y_TILED:
3009                 return PLANE_CTL_TILED_Y;
3010         case I915_FORMAT_MOD_Yf_TILED:
3011                 return PLANE_CTL_TILED_YF;
3012         default:
3013                 MISSING_CASE(fb_modifier);
3014         }
3015
3016         return 0;
3017 }
3018
3019 u32 skl_plane_ctl_rotation(unsigned int rotation)
3020 {
3021         switch (rotation) {
3022         case BIT(DRM_ROTATE_0):
3023                 break;
3024         /*
3025          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3026          * while i915 HW rotation is clockwise, thats why this swapping.
3027          */
3028         case BIT(DRM_ROTATE_90):
3029                 return PLANE_CTL_ROTATE_270;
3030         case BIT(DRM_ROTATE_180):
3031                 return PLANE_CTL_ROTATE_180;
3032         case BIT(DRM_ROTATE_270):
3033                 return PLANE_CTL_ROTATE_90;
3034         default:
3035                 MISSING_CASE(rotation);
3036         }
3037
3038         return 0;
3039 }
3040
3041 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3042                                          struct drm_framebuffer *fb,
3043                                          int x, int y)
3044 {
3045         struct drm_device *dev = crtc->dev;
3046         struct drm_i915_private *dev_priv = dev->dev_private;
3047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3048         struct drm_plane *plane = crtc->primary;
3049         bool visible = to_intel_plane_state(plane->state)->visible;
3050         struct drm_i915_gem_object *obj;
3051         int pipe = intel_crtc->pipe;
3052         u32 plane_ctl, stride_div, stride;
3053         u32 tile_height, plane_offset, plane_size;
3054         unsigned int rotation;
3055         int x_offset, y_offset;
3056         unsigned long surf_addr;
3057         struct intel_crtc_state *crtc_state = intel_crtc->config;
3058         struct intel_plane_state *plane_state;
3059         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3060         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3061         int scaler_id = -1;
3062
3063         plane_state = to_intel_plane_state(plane->state);
3064
3065         if (!visible || !fb) {
3066                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3067                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3068                 POSTING_READ(PLANE_CTL(pipe, 0));
3069                 return;
3070         }
3071
3072         plane_ctl = PLANE_CTL_ENABLE |
3073                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3074                     PLANE_CTL_PIPE_CSC_ENABLE;
3075
3076         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3077         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3078         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3079
3080         rotation = plane->state->rotation;
3081         plane_ctl |= skl_plane_ctl_rotation(rotation);
3082
3083         obj = intel_fb_obj(fb);
3084         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3085                                                fb->pixel_format);
3086         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3087
3088         /*
3089          * FIXME: intel_plane_state->src, dst aren't set when transitional
3090          * update_plane helpers are called from legacy paths.
3091          * Once full atomic crtc is available, below check can be avoided.
3092          */
3093         if (drm_rect_width(&plane_state->src)) {
3094                 scaler_id = plane_state->scaler_id;
3095                 src_x = plane_state->src.x1 >> 16;
3096                 src_y = plane_state->src.y1 >> 16;
3097                 src_w = drm_rect_width(&plane_state->src) >> 16;
3098                 src_h = drm_rect_height(&plane_state->src) >> 16;
3099                 dst_x = plane_state->dst.x1;
3100                 dst_y = plane_state->dst.y1;
3101                 dst_w = drm_rect_width(&plane_state->dst);
3102                 dst_h = drm_rect_height(&plane_state->dst);
3103
3104                 WARN_ON(x != src_x || y != src_y);
3105         } else {
3106                 src_w = intel_crtc->config->pipe_src_w;
3107                 src_h = intel_crtc->config->pipe_src_h;
3108         }
3109
3110         if (intel_rotation_90_or_270(rotation)) {
3111                 /* stride = Surface height in tiles */
3112                 tile_height = intel_tile_height(dev, fb->pixel_format,
3113                                                 fb->modifier[0]);
3114                 stride = DIV_ROUND_UP(fb->height, tile_height);
3115                 x_offset = stride * tile_height - y - src_h;
3116                 y_offset = x;
3117                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3118         } else {
3119                 stride = fb->pitches[0] / stride_div;
3120                 x_offset = x;
3121                 y_offset = y;
3122                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3123         }
3124         plane_offset = y_offset << 16 | x_offset;
3125
3126         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3127         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3128         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3129         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3130
3131         if (scaler_id >= 0) {
3132                 uint32_t ps_ctrl = 0;
3133
3134                 WARN_ON(!dst_w || !dst_h);
3135                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3136                         crtc_state->scaler_state.scalers[scaler_id].mode;
3137                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3138                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3139                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3140                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3141                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3142         } else {
3143                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3144         }
3145
3146         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3147
3148         POSTING_READ(PLANE_SURF(pipe, 0));
3149 }
3150
3151 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3152 static int
3153 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3154                            int x, int y, enum mode_set_atomic state)
3155 {
3156         struct drm_device *dev = crtc->dev;
3157         struct drm_i915_private *dev_priv = dev->dev_private;
3158
3159         if (dev_priv->fbc.disable_fbc)
3160                 dev_priv->fbc.disable_fbc(dev_priv);
3161
3162         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3163
3164         return 0;
3165 }
3166
3167 static void intel_complete_page_flips(struct drm_device *dev)
3168 {
3169         struct drm_crtc *crtc;
3170
3171         for_each_crtc(dev, crtc) {
3172                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3173                 enum plane plane = intel_crtc->plane;
3174
3175                 intel_prepare_page_flip(dev, plane);
3176                 intel_finish_page_flip_plane(dev, plane);
3177         }
3178 }
3179
3180 static void intel_update_primary_planes(struct drm_device *dev)
3181 {
3182         struct drm_i915_private *dev_priv = dev->dev_private;
3183         struct drm_crtc *crtc;
3184
3185         for_each_crtc(dev, crtc) {
3186                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3187
3188                 drm_modeset_lock(&crtc->mutex, NULL);
3189                 /*
3190                  * FIXME: Once we have proper support for primary planes (and
3191                  * disabling them without disabling the entire crtc) allow again
3192                  * a NULL crtc->primary->fb.
3193                  */
3194                 if (intel_crtc->active && crtc->primary->fb)
3195                         dev_priv->display.update_primary_plane(crtc,
3196                                                                crtc->primary->fb,
3197                                                                crtc->x,
3198                                                                crtc->y);
3199                 drm_modeset_unlock(&crtc->mutex);
3200         }
3201 }
3202
3203 void intel_prepare_reset(struct drm_device *dev)
3204 {
3205         /* no reset support for gen2 */
3206         if (IS_GEN2(dev))
3207                 return;
3208
3209         /* reset doesn't touch the display */
3210         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3211                 return;
3212
3213         drm_modeset_lock_all(dev);
3214         /*
3215          * Disabling the crtcs gracefully seems nicer. Also the
3216          * g33 docs say we should at least disable all the planes.
3217          */
3218         intel_display_suspend(dev);
3219 }
3220
3221 void intel_finish_reset(struct drm_device *dev)
3222 {
3223         struct drm_i915_private *dev_priv = to_i915(dev);
3224
3225         /*
3226          * Flips in the rings will be nuked by the reset,
3227          * so complete all pending flips so that user space
3228          * will get its events and not get stuck.
3229          */
3230         intel_complete_page_flips(dev);
3231
3232         /* no reset support for gen2 */
3233         if (IS_GEN2(dev))
3234                 return;
3235
3236         /* reset doesn't touch the display */
3237         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3238                 /*
3239                  * Flips in the rings have been nuked by the reset,
3240                  * so update the base address of all primary
3241                  * planes to the the last fb to make sure we're
3242                  * showing the correct fb after a reset.
3243                  */
3244                 intel_update_primary_planes(dev);
3245                 return;
3246         }
3247
3248         /*
3249          * The display has been reset as well,
3250          * so need a full re-initialization.
3251          */
3252         intel_runtime_pm_disable_interrupts(dev_priv);
3253         intel_runtime_pm_enable_interrupts(dev_priv);
3254
3255         intel_modeset_init_hw(dev);
3256
3257         spin_lock_irq(&dev_priv->irq_lock);
3258         if (dev_priv->display.hpd_irq_setup)
3259                 dev_priv->display.hpd_irq_setup(dev);
3260         spin_unlock_irq(&dev_priv->irq_lock);
3261
3262         intel_display_resume(dev);
3263
3264         intel_hpd_init(dev_priv);
3265
3266         drm_modeset_unlock_all(dev);
3267 }
3268
3269 static void
3270 intel_finish_fb(struct drm_framebuffer *old_fb)
3271 {
3272         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3273         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3274         bool was_interruptible = dev_priv->mm.interruptible;
3275         int ret;
3276
3277         /* Big Hammer, we also need to ensure that any pending
3278          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3279          * current scanout is retired before unpinning the old
3280          * framebuffer. Note that we rely on userspace rendering
3281          * into the buffer attached to the pipe they are waiting
3282          * on. If not, userspace generates a GPU hang with IPEHR
3283          * point to the MI_WAIT_FOR_EVENT.
3284          *
3285          * This should only fail upon a hung GPU, in which case we
3286          * can safely continue.
3287          */
3288         dev_priv->mm.interruptible = false;
3289         ret = i915_gem_object_wait_rendering(obj, true);
3290         dev_priv->mm.interruptible = was_interruptible;
3291
3292         WARN_ON(ret);
3293 }
3294
3295 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3296 {
3297         struct drm_device *dev = crtc->dev;
3298         struct drm_i915_private *dev_priv = dev->dev_private;
3299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3300         bool pending;
3301
3302         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3303             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3304                 return false;
3305
3306         spin_lock_irq(&dev->event_lock);
3307         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3308         spin_unlock_irq(&dev->event_lock);
3309
3310         return pending;
3311 }
3312
3313 static void intel_update_pipe_size(struct intel_crtc *crtc)
3314 {
3315         struct drm_device *dev = crtc->base.dev;
3316         struct drm_i915_private *dev_priv = dev->dev_private;
3317         const struct drm_display_mode *adjusted_mode;
3318
3319         if (!i915.fastboot)
3320                 return;
3321
3322         /*
3323          * Update pipe size and adjust fitter if needed: the reason for this is
3324          * that in compute_mode_changes we check the native mode (not the pfit
3325          * mode) to see if we can flip rather than do a full mode set. In the
3326          * fastboot case, we'll flip, but if we don't update the pipesrc and
3327          * pfit state, we'll end up with a big fb scanned out into the wrong
3328          * sized surface.
3329          *
3330          * To fix this properly, we need to hoist the checks up into
3331          * compute_mode_changes (or above), check the actual pfit state and
3332          * whether the platform allows pfit disable with pipe active, and only
3333          * then update the pipesrc and pfit state, even on the flip path.
3334          */
3335
3336         adjusted_mode = &crtc->config->base.adjusted_mode;
3337
3338         I915_WRITE(PIPESRC(crtc->pipe),
3339                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3340                    (adjusted_mode->crtc_vdisplay - 1));
3341         if (!crtc->config->pch_pfit.enabled &&
3342             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3343              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3344                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3345                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3346                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3347         }
3348         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3349         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3350 }
3351
3352 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3353 {
3354         struct drm_device *dev = crtc->dev;
3355         struct drm_i915_private *dev_priv = dev->dev_private;
3356         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3357         int pipe = intel_crtc->pipe;
3358         u32 reg, temp;
3359
3360         /* enable normal train */
3361         reg = FDI_TX_CTL(pipe);
3362         temp = I915_READ(reg);
3363         if (IS_IVYBRIDGE(dev)) {
3364                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3365                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3366         } else {
3367                 temp &= ~FDI_LINK_TRAIN_NONE;
3368                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3369         }
3370         I915_WRITE(reg, temp);
3371
3372         reg = FDI_RX_CTL(pipe);
3373         temp = I915_READ(reg);
3374         if (HAS_PCH_CPT(dev)) {
3375                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3376                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3377         } else {
3378                 temp &= ~FDI_LINK_TRAIN_NONE;
3379                 temp |= FDI_LINK_TRAIN_NONE;
3380         }
3381         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3382
3383         /* wait one idle pattern time */
3384         POSTING_READ(reg);
3385         udelay(1000);
3386
3387         /* IVB wants error correction enabled */
3388         if (IS_IVYBRIDGE(dev))
3389                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3390                            FDI_FE_ERRC_ENABLE);
3391 }
3392
3393 /* The FDI link training functions for ILK/Ibexpeak. */
3394 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3395 {
3396         struct drm_device *dev = crtc->dev;
3397         struct drm_i915_private *dev_priv = dev->dev_private;
3398         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399         int pipe = intel_crtc->pipe;
3400         u32 reg, temp, tries;
3401
3402         /* FDI needs bits from pipe first */
3403         assert_pipe_enabled(dev_priv, pipe);
3404
3405         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3406            for train result */
3407         reg = FDI_RX_IMR(pipe);
3408         temp = I915_READ(reg);
3409         temp &= ~FDI_RX_SYMBOL_LOCK;
3410         temp &= ~FDI_RX_BIT_LOCK;
3411         I915_WRITE(reg, temp);
3412         I915_READ(reg);
3413         udelay(150);
3414
3415         /* enable CPU FDI TX and PCH FDI RX */
3416         reg = FDI_TX_CTL(pipe);
3417         temp = I915_READ(reg);
3418         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3419         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3420         temp &= ~FDI_LINK_TRAIN_NONE;
3421         temp |= FDI_LINK_TRAIN_PATTERN_1;
3422         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3423
3424         reg = FDI_RX_CTL(pipe);
3425         temp = I915_READ(reg);
3426         temp &= ~FDI_LINK_TRAIN_NONE;
3427         temp |= FDI_LINK_TRAIN_PATTERN_1;
3428         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3429
3430         POSTING_READ(reg);
3431         udelay(150);
3432
3433         /* Ironlake workaround, enable clock pointer after FDI enable*/
3434         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3435         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3436                    FDI_RX_PHASE_SYNC_POINTER_EN);
3437
3438         reg = FDI_RX_IIR(pipe);
3439         for (tries = 0; tries < 5; tries++) {
3440                 temp = I915_READ(reg);
3441                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3442
3443                 if ((temp & FDI_RX_BIT_LOCK)) {
3444                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3445                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3446                         break;
3447                 }
3448         }
3449         if (tries == 5)
3450                 DRM_ERROR("FDI train 1 fail!\n");
3451
3452         /* Train 2 */
3453         reg = FDI_TX_CTL(pipe);
3454         temp = I915_READ(reg);
3455         temp &= ~FDI_LINK_TRAIN_NONE;
3456         temp |= FDI_LINK_TRAIN_PATTERN_2;
3457         I915_WRITE(reg, temp);
3458
3459         reg = FDI_RX_CTL(pipe);
3460         temp = I915_READ(reg);
3461         temp &= ~FDI_LINK_TRAIN_NONE;
3462         temp |= FDI_LINK_TRAIN_PATTERN_2;
3463         I915_WRITE(reg, temp);
3464
3465         POSTING_READ(reg);
3466         udelay(150);
3467
3468         reg = FDI_RX_IIR(pipe);
3469         for (tries = 0; tries < 5; tries++) {
3470                 temp = I915_READ(reg);
3471                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3472
3473                 if (temp & FDI_RX_SYMBOL_LOCK) {
3474                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3475                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3476                         break;
3477                 }
3478         }
3479         if (tries == 5)
3480                 DRM_ERROR("FDI train 2 fail!\n");
3481
3482         DRM_DEBUG_KMS("FDI train done\n");
3483
3484 }
3485
3486 static const int snb_b_fdi_train_param[] = {
3487         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3488         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3489         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3490         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3491 };
3492
3493 /* The FDI link training functions for SNB/Cougarpoint. */
3494 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3495 {
3496         struct drm_device *dev = crtc->dev;
3497         struct drm_i915_private *dev_priv = dev->dev_private;
3498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3499         int pipe = intel_crtc->pipe;
3500         u32 reg, temp, i, retry;
3501
3502         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3503            for train result */
3504         reg = FDI_RX_IMR(pipe);
3505         temp = I915_READ(reg);
3506         temp &= ~FDI_RX_SYMBOL_LOCK;
3507         temp &= ~FDI_RX_BIT_LOCK;
3508         I915_WRITE(reg, temp);
3509
3510         POSTING_READ(reg);
3511         udelay(150);
3512
3513         /* enable CPU FDI TX and PCH FDI RX */
3514         reg = FDI_TX_CTL(pipe);
3515         temp = I915_READ(reg);
3516         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3517         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3518         temp &= ~FDI_LINK_TRAIN_NONE;
3519         temp |= FDI_LINK_TRAIN_PATTERN_1;
3520         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3521         /* SNB-B */
3522         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3523         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3524
3525         I915_WRITE(FDI_RX_MISC(pipe),
3526                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3527
3528         reg = FDI_RX_CTL(pipe);
3529         temp = I915_READ(reg);
3530         if (HAS_PCH_CPT(dev)) {
3531                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3532                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3533         } else {
3534                 temp &= ~FDI_LINK_TRAIN_NONE;
3535                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3536         }
3537         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3538
3539         POSTING_READ(reg);
3540         udelay(150);
3541
3542         for (i = 0; i < 4; i++) {
3543                 reg = FDI_TX_CTL(pipe);
3544                 temp = I915_READ(reg);
3545                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3546                 temp |= snb_b_fdi_train_param[i];
3547                 I915_WRITE(reg, temp);
3548
3549                 POSTING_READ(reg);
3550                 udelay(500);
3551
3552                 for (retry = 0; retry < 5; retry++) {
3553                         reg = FDI_RX_IIR(pipe);
3554                         temp = I915_READ(reg);
3555                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3556                         if (temp & FDI_RX_BIT_LOCK) {
3557                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3558                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3559                                 break;
3560                         }
3561                         udelay(50);
3562                 }
3563                 if (retry < 5)
3564                         break;
3565         }
3566         if (i == 4)
3567                 DRM_ERROR("FDI train 1 fail!\n");
3568
3569         /* Train 2 */
3570         reg = FDI_TX_CTL(pipe);
3571         temp = I915_READ(reg);
3572         temp &= ~FDI_LINK_TRAIN_NONE;
3573         temp |= FDI_LINK_TRAIN_PATTERN_2;
3574         if (IS_GEN6(dev)) {
3575                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3576                 /* SNB-B */
3577                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3578         }
3579         I915_WRITE(reg, temp);
3580
3581         reg = FDI_RX_CTL(pipe);
3582         temp = I915_READ(reg);
3583         if (HAS_PCH_CPT(dev)) {
3584                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3585                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3586         } else {
3587                 temp &= ~FDI_LINK_TRAIN_NONE;
3588                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3589         }
3590         I915_WRITE(reg, temp);
3591
3592         POSTING_READ(reg);
3593         udelay(150);
3594
3595         for (i = 0; i < 4; i++) {
3596                 reg = FDI_TX_CTL(pipe);
3597                 temp = I915_READ(reg);
3598                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3599                 temp |= snb_b_fdi_train_param[i];
3600                 I915_WRITE(reg, temp);
3601
3602                 POSTING_READ(reg);
3603                 udelay(500);
3604
3605                 for (retry = 0; retry < 5; retry++) {
3606                         reg = FDI_RX_IIR(pipe);
3607                         temp = I915_READ(reg);
3608                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3609                         if (temp & FDI_RX_SYMBOL_LOCK) {
3610                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3611                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3612                                 break;
3613                         }
3614                         udelay(50);
3615                 }
3616                 if (retry < 5)
3617                         break;
3618         }
3619         if (i == 4)
3620                 DRM_ERROR("FDI train 2 fail!\n");
3621
3622         DRM_DEBUG_KMS("FDI train done.\n");
3623 }
3624
3625 /* Manual link training for Ivy Bridge A0 parts */
3626 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3627 {
3628         struct drm_device *dev = crtc->dev;
3629         struct drm_i915_private *dev_priv = dev->dev_private;
3630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631         int pipe = intel_crtc->pipe;
3632         u32 reg, temp, i, j;
3633
3634         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3635            for train result */
3636         reg = FDI_RX_IMR(pipe);
3637         temp = I915_READ(reg);
3638         temp &= ~FDI_RX_SYMBOL_LOCK;
3639         temp &= ~FDI_RX_BIT_LOCK;
3640         I915_WRITE(reg, temp);
3641
3642         POSTING_READ(reg);
3643         udelay(150);
3644
3645         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3646                       I915_READ(FDI_RX_IIR(pipe)));
3647
3648         /* Try each vswing and preemphasis setting twice before moving on */
3649         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3650                 /* disable first in case we need to retry */
3651                 reg = FDI_TX_CTL(pipe);
3652                 temp = I915_READ(reg);
3653                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3654                 temp &= ~FDI_TX_ENABLE;
3655                 I915_WRITE(reg, temp);
3656
3657                 reg = FDI_RX_CTL(pipe);
3658                 temp = I915_READ(reg);
3659                 temp &= ~FDI_LINK_TRAIN_AUTO;
3660                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3661                 temp &= ~FDI_RX_ENABLE;
3662                 I915_WRITE(reg, temp);
3663
3664                 /* enable CPU FDI TX and PCH FDI RX */
3665                 reg = FDI_TX_CTL(pipe);
3666                 temp = I915_READ(reg);
3667                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3668                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3669                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3670                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3671                 temp |= snb_b_fdi_train_param[j/2];
3672                 temp |= FDI_COMPOSITE_SYNC;
3673                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3674
3675                 I915_WRITE(FDI_RX_MISC(pipe),
3676                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3677
3678                 reg = FDI_RX_CTL(pipe);
3679                 temp = I915_READ(reg);
3680                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3681                 temp |= FDI_COMPOSITE_SYNC;
3682                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3683
3684                 POSTING_READ(reg);
3685                 udelay(1); /* should be 0.5us */
3686
3687                 for (i = 0; i < 4; i++) {
3688                         reg = FDI_RX_IIR(pipe);
3689                         temp = I915_READ(reg);
3690                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3691
3692                         if (temp & FDI_RX_BIT_LOCK ||
3693                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3694                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3695                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3696                                               i);
3697                                 break;
3698                         }
3699                         udelay(1); /* should be 0.5us */
3700                 }
3701                 if (i == 4) {
3702                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3703                         continue;
3704                 }
3705
3706                 /* Train 2 */
3707                 reg = FDI_TX_CTL(pipe);
3708                 temp = I915_READ(reg);
3709                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3710                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3711                 I915_WRITE(reg, temp);
3712
3713                 reg = FDI_RX_CTL(pipe);
3714                 temp = I915_READ(reg);
3715                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3716                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3717                 I915_WRITE(reg, temp);
3718
3719                 POSTING_READ(reg);
3720                 udelay(2); /* should be 1.5us */
3721
3722                 for (i = 0; i < 4; i++) {
3723                         reg = FDI_RX_IIR(pipe);
3724                         temp = I915_READ(reg);
3725                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3726
3727                         if (temp & FDI_RX_SYMBOL_LOCK ||
3728                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3729                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3730                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3731                                               i);
3732                                 goto train_done;
3733                         }
3734                         udelay(2); /* should be 1.5us */
3735                 }
3736                 if (i == 4)
3737                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3738         }
3739
3740 train_done:
3741         DRM_DEBUG_KMS("FDI train done.\n");
3742 }
3743
3744 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3745 {
3746         struct drm_device *dev = intel_crtc->base.dev;
3747         struct drm_i915_private *dev_priv = dev->dev_private;
3748         int pipe = intel_crtc->pipe;
3749         u32 reg, temp;
3750
3751
3752         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3753         reg = FDI_RX_CTL(pipe);
3754         temp = I915_READ(reg);
3755         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3756         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3757         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3758         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3759
3760         POSTING_READ(reg);
3761         udelay(200);
3762
3763         /* Switch from Rawclk to PCDclk */
3764         temp = I915_READ(reg);
3765         I915_WRITE(reg, temp | FDI_PCDCLK);
3766
3767         POSTING_READ(reg);
3768         udelay(200);
3769
3770         /* Enable CPU FDI TX PLL, always on for Ironlake */
3771         reg = FDI_TX_CTL(pipe);
3772         temp = I915_READ(reg);
3773         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3774                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3775
3776                 POSTING_READ(reg);
3777                 udelay(100);
3778         }
3779 }
3780
3781 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3782 {
3783         struct drm_device *dev = intel_crtc->base.dev;
3784         struct drm_i915_private *dev_priv = dev->dev_private;
3785         int pipe = intel_crtc->pipe;
3786         u32 reg, temp;
3787
3788         /* Switch from PCDclk to Rawclk */
3789         reg = FDI_RX_CTL(pipe);
3790         temp = I915_READ(reg);
3791         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3792
3793         /* Disable CPU FDI TX PLL */
3794         reg = FDI_TX_CTL(pipe);
3795         temp = I915_READ(reg);
3796         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3797
3798         POSTING_READ(reg);
3799         udelay(100);
3800
3801         reg = FDI_RX_CTL(pipe);
3802         temp = I915_READ(reg);
3803         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3804
3805         /* Wait for the clocks to turn off. */
3806         POSTING_READ(reg);
3807         udelay(100);
3808 }
3809
3810 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3811 {
3812         struct drm_device *dev = crtc->dev;
3813         struct drm_i915_private *dev_priv = dev->dev_private;
3814         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3815         int pipe = intel_crtc->pipe;
3816         u32 reg, temp;
3817
3818         /* disable CPU FDI tx and PCH FDI rx */
3819         reg = FDI_TX_CTL(pipe);
3820         temp = I915_READ(reg);
3821         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3822         POSTING_READ(reg);
3823
3824         reg = FDI_RX_CTL(pipe);
3825         temp = I915_READ(reg);
3826         temp &= ~(0x7 << 16);
3827         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3828         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3829
3830         POSTING_READ(reg);
3831         udelay(100);
3832
3833         /* Ironlake workaround, disable clock pointer after downing FDI */
3834         if (HAS_PCH_IBX(dev))
3835                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3836
3837         /* still set train pattern 1 */
3838         reg = FDI_TX_CTL(pipe);
3839         temp = I915_READ(reg);
3840         temp &= ~FDI_LINK_TRAIN_NONE;
3841         temp |= FDI_LINK_TRAIN_PATTERN_1;
3842         I915_WRITE(reg, temp);
3843
3844         reg = FDI_RX_CTL(pipe);
3845         temp = I915_READ(reg);
3846         if (HAS_PCH_CPT(dev)) {
3847                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3848                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3849         } else {
3850                 temp &= ~FDI_LINK_TRAIN_NONE;
3851                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3852         }
3853         /* BPC in FDI rx is consistent with that in PIPECONF */
3854         temp &= ~(0x07 << 16);
3855         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3856         I915_WRITE(reg, temp);
3857
3858         POSTING_READ(reg);
3859         udelay(100);
3860 }
3861
3862 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3863 {
3864         struct intel_crtc *crtc;
3865
3866         /* Note that we don't need to be called with mode_config.lock here
3867          * as our list of CRTC objects is static for the lifetime of the
3868          * device and so cannot disappear as we iterate. Similarly, we can
3869          * happily treat the predicates as racy, atomic checks as userspace
3870          * cannot claim and pin a new fb without at least acquring the
3871          * struct_mutex and so serialising with us.
3872          */
3873         for_each_intel_crtc(dev, crtc) {
3874                 if (atomic_read(&crtc->unpin_work_count) == 0)
3875                         continue;
3876
3877                 if (crtc->unpin_work)
3878                         intel_wait_for_vblank(dev, crtc->pipe);
3879
3880                 return true;
3881         }
3882
3883         return false;
3884 }
3885
3886 static void page_flip_completed(struct intel_crtc *intel_crtc)
3887 {
3888         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3889         struct intel_unpin_work *work = intel_crtc->unpin_work;
3890
3891         /* ensure that the unpin work is consistent wrt ->pending. */
3892         smp_rmb();
3893         intel_crtc->unpin_work = NULL;
3894
3895         if (work->event)
3896                 drm_send_vblank_event(intel_crtc->base.dev,
3897                                       intel_crtc->pipe,
3898                                       work->event);
3899
3900         drm_crtc_vblank_put(&intel_crtc->base);
3901
3902         wake_up_all(&dev_priv->pending_flip_queue);
3903         queue_work(dev_priv->wq, &work->work);
3904
3905         trace_i915_flip_complete(intel_crtc->plane,
3906                                  work->pending_flip_obj);
3907 }
3908
3909 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3910 {
3911         struct drm_device *dev = crtc->dev;
3912         struct drm_i915_private *dev_priv = dev->dev_private;
3913
3914         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3915         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3916                                        !intel_crtc_has_pending_flip(crtc),
3917                                        60*HZ) == 0)) {
3918                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3919
3920                 spin_lock_irq(&dev->event_lock);
3921                 if (intel_crtc->unpin_work) {
3922                         WARN_ONCE(1, "Removing stuck page flip\n");
3923                         page_flip_completed(intel_crtc);
3924                 }
3925                 spin_unlock_irq(&dev->event_lock);
3926         }
3927
3928         if (crtc->primary->fb) {
3929                 mutex_lock(&dev->struct_mutex);
3930                 intel_finish_fb(crtc->primary->fb);
3931                 mutex_unlock(&dev->struct_mutex);
3932         }
3933 }
3934
3935 /* Program iCLKIP clock to the desired frequency */
3936 static void lpt_program_iclkip(struct drm_crtc *crtc)
3937 {
3938         struct drm_device *dev = crtc->dev;
3939         struct drm_i915_private *dev_priv = dev->dev_private;
3940         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3941         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3942         u32 temp;
3943
3944         mutex_lock(&dev_priv->sb_lock);
3945
3946         /* It is necessary to ungate the pixclk gate prior to programming
3947          * the divisors, and gate it back when it is done.
3948          */
3949         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3950
3951         /* Disable SSCCTL */
3952         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3953                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3954                                 SBI_SSCCTL_DISABLE,
3955                         SBI_ICLK);
3956
3957         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3958         if (clock == 20000) {
3959                 auxdiv = 1;
3960                 divsel = 0x41;
3961                 phaseinc = 0x20;
3962         } else {
3963                 /* The iCLK virtual clock root frequency is in MHz,
3964                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3965                  * divisors, it is necessary to divide one by another, so we
3966                  * convert the virtual clock precision to KHz here for higher
3967                  * precision.
3968                  */
3969                 u32 iclk_virtual_root_freq = 172800 * 1000;
3970                 u32 iclk_pi_range = 64;
3971                 u32 desired_divisor, msb_divisor_value, pi_value;
3972
3973                 desired_divisor = (iclk_virtual_root_freq / clock);
3974                 msb_divisor_value = desired_divisor / iclk_pi_range;
3975                 pi_value = desired_divisor % iclk_pi_range;
3976
3977                 auxdiv = 0;
3978                 divsel = msb_divisor_value - 2;
3979                 phaseinc = pi_value;
3980         }
3981
3982         /* This should not happen with any sane values */
3983         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3984                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3985         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3986                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3987
3988         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3989                         clock,
3990                         auxdiv,
3991                         divsel,
3992                         phasedir,
3993                         phaseinc);
3994
3995         /* Program SSCDIVINTPHASE6 */
3996         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3997         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3998         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3999         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4000         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4001         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4002         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4003         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4004
4005         /* Program SSCAUXDIV */
4006         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4007         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4008         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4009         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4010
4011         /* Enable modulator and associated divider */
4012         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4013         temp &= ~SBI_SSCCTL_DISABLE;
4014         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4015
4016         /* Wait for initialization time */
4017         udelay(24);
4018
4019         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4020
4021         mutex_unlock(&dev_priv->sb_lock);
4022 }
4023
4024 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4025                                                 enum pipe pch_transcoder)
4026 {
4027         struct drm_device *dev = crtc->base.dev;
4028         struct drm_i915_private *dev_priv = dev->dev_private;
4029         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4030
4031         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4032                    I915_READ(HTOTAL(cpu_transcoder)));
4033         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4034                    I915_READ(HBLANK(cpu_transcoder)));
4035         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4036                    I915_READ(HSYNC(cpu_transcoder)));
4037
4038         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4039                    I915_READ(VTOTAL(cpu_transcoder)));
4040         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4041                    I915_READ(VBLANK(cpu_transcoder)));
4042         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4043                    I915_READ(VSYNC(cpu_transcoder)));
4044         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4045                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4046 }
4047
4048 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4049 {
4050         struct drm_i915_private *dev_priv = dev->dev_private;
4051         uint32_t temp;
4052
4053         temp = I915_READ(SOUTH_CHICKEN1);
4054         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4055                 return;
4056
4057         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4058         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4059
4060         temp &= ~FDI_BC_BIFURCATION_SELECT;
4061         if (enable)
4062                 temp |= FDI_BC_BIFURCATION_SELECT;
4063
4064         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4065         I915_WRITE(SOUTH_CHICKEN1, temp);
4066         POSTING_READ(SOUTH_CHICKEN1);
4067 }
4068
4069 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4070 {
4071         struct drm_device *dev = intel_crtc->base.dev;
4072
4073         switch (intel_crtc->pipe) {
4074         case PIPE_A:
4075                 break;
4076         case PIPE_B:
4077                 if (intel_crtc->config->fdi_lanes > 2)
4078                         cpt_set_fdi_bc_bifurcation(dev, false);
4079                 else
4080                         cpt_set_fdi_bc_bifurcation(dev, true);
4081
4082                 break;
4083         case PIPE_C:
4084                 cpt_set_fdi_bc_bifurcation(dev, true);
4085
4086                 break;
4087         default:
4088                 BUG();
4089         }
4090 }
4091
4092 /*
4093  * Enable PCH resources required for PCH ports:
4094  *   - PCH PLLs
4095  *   - FDI training & RX/TX
4096  *   - update transcoder timings
4097  *   - DP transcoding bits
4098  *   - transcoder
4099  */
4100 static void ironlake_pch_enable(struct drm_crtc *crtc)
4101 {
4102         struct drm_device *dev = crtc->dev;
4103         struct drm_i915_private *dev_priv = dev->dev_private;
4104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4105         int pipe = intel_crtc->pipe;
4106         u32 reg, temp;
4107
4108         assert_pch_transcoder_disabled(dev_priv, pipe);
4109
4110         if (IS_IVYBRIDGE(dev))
4111                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4112
4113         /* Write the TU size bits before fdi link training, so that error
4114          * detection works. */
4115         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4116                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4117
4118         /* For PCH output, training FDI link */
4119         dev_priv->display.fdi_link_train(crtc);
4120
4121         /* We need to program the right clock selection before writing the pixel
4122          * mutliplier into the DPLL. */
4123         if (HAS_PCH_CPT(dev)) {
4124                 u32 sel;
4125
4126                 temp = I915_READ(PCH_DPLL_SEL);
4127                 temp |= TRANS_DPLL_ENABLE(pipe);
4128                 sel = TRANS_DPLLB_SEL(pipe);
4129                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4130                         temp |= sel;
4131                 else
4132                         temp &= ~sel;
4133                 I915_WRITE(PCH_DPLL_SEL, temp);
4134         }
4135
4136         /* XXX: pch pll's can be enabled any time before we enable the PCH
4137          * transcoder, and we actually should do this to not upset any PCH
4138          * transcoder that already use the clock when we share it.
4139          *
4140          * Note that enable_shared_dpll tries to do the right thing, but
4141          * get_shared_dpll unconditionally resets the pll - we need that to have
4142          * the right LVDS enable sequence. */
4143         intel_enable_shared_dpll(intel_crtc);
4144
4145         /* set transcoder timing, panel must allow it */
4146         assert_panel_unlocked(dev_priv, pipe);
4147         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4148
4149         intel_fdi_normal_train(crtc);
4150
4151         /* For PCH DP, enable TRANS_DP_CTL */
4152         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4153                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4154                 reg = TRANS_DP_CTL(pipe);
4155                 temp = I915_READ(reg);
4156                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4157                           TRANS_DP_SYNC_MASK |
4158                           TRANS_DP_BPC_MASK);
4159                 temp |= TRANS_DP_OUTPUT_ENABLE;
4160                 temp |= bpc << 9; /* same format but at 11:9 */
4161
4162                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4163                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4164                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4165                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4166
4167                 switch (intel_trans_dp_port_sel(crtc)) {
4168                 case PCH_DP_B:
4169                         temp |= TRANS_DP_PORT_SEL_B;
4170                         break;
4171                 case PCH_DP_C:
4172                         temp |= TRANS_DP_PORT_SEL_C;
4173                         break;
4174                 case PCH_DP_D:
4175                         temp |= TRANS_DP_PORT_SEL_D;
4176                         break;
4177                 default:
4178                         BUG();
4179                 }
4180
4181                 I915_WRITE(reg, temp);
4182         }
4183
4184         ironlake_enable_pch_transcoder(dev_priv, pipe);
4185 }
4186
4187 static void lpt_pch_enable(struct drm_crtc *crtc)
4188 {
4189         struct drm_device *dev = crtc->dev;
4190         struct drm_i915_private *dev_priv = dev->dev_private;
4191         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4192         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4193
4194         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4195
4196         lpt_program_iclkip(crtc);
4197
4198         /* Set transcoder timing. */
4199         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4200
4201         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4202 }
4203
4204 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4205                                                 struct intel_crtc_state *crtc_state)
4206 {
4207         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4208         struct intel_shared_dpll *pll;
4209         struct intel_shared_dpll_config *shared_dpll;
4210         enum intel_dpll_id i;
4211
4212         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4213
4214         if (HAS_PCH_IBX(dev_priv->dev)) {
4215                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4216                 i = (enum intel_dpll_id) crtc->pipe;
4217                 pll = &dev_priv->shared_dplls[i];
4218
4219                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4220                               crtc->base.base.id, pll->name);
4221
4222                 WARN_ON(shared_dpll[i].crtc_mask);
4223
4224                 goto found;
4225         }
4226
4227         if (IS_BROXTON(dev_priv->dev)) {
4228                 /* PLL is attached to port in bxt */
4229                 struct intel_encoder *encoder;
4230                 struct intel_digital_port *intel_dig_port;
4231
4232                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4233                 if (WARN_ON(!encoder))
4234                         return NULL;
4235
4236                 intel_dig_port = enc_to_dig_port(&encoder->base);
4237                 /* 1:1 mapping between ports and PLLs */
4238                 i = (enum intel_dpll_id)intel_dig_port->port;
4239                 pll = &dev_priv->shared_dplls[i];
4240                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4241                         crtc->base.base.id, pll->name);
4242                 WARN_ON(shared_dpll[i].crtc_mask);
4243
4244                 goto found;
4245         }
4246
4247         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4248                 pll = &dev_priv->shared_dplls[i];
4249
4250                 /* Only want to check enabled timings first */
4251                 if (shared_dpll[i].crtc_mask == 0)
4252                         continue;
4253
4254                 if (memcmp(&crtc_state->dpll_hw_state,
4255                            &shared_dpll[i].hw_state,
4256                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4257                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4258                                       crtc->base.base.id, pll->name,
4259                                       shared_dpll[i].crtc_mask,
4260                                       pll->active);
4261                         goto found;
4262                 }
4263         }
4264
4265         /* Ok no matching timings, maybe there's a free one? */
4266         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4267                 pll = &dev_priv->shared_dplls[i];
4268                 if (shared_dpll[i].crtc_mask == 0) {
4269                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4270                                       crtc->base.base.id, pll->name);
4271                         goto found;
4272                 }
4273         }
4274
4275         return NULL;
4276
4277 found:
4278         if (shared_dpll[i].crtc_mask == 0)
4279                 shared_dpll[i].hw_state =
4280                         crtc_state->dpll_hw_state;
4281
4282         crtc_state->shared_dpll = i;
4283         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4284                          pipe_name(crtc->pipe));
4285
4286         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4287
4288         return pll;
4289 }
4290
4291 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4292 {
4293         struct drm_i915_private *dev_priv = to_i915(state->dev);
4294         struct intel_shared_dpll_config *shared_dpll;
4295         struct intel_shared_dpll *pll;
4296         enum intel_dpll_id i;
4297
4298         if (!to_intel_atomic_state(state)->dpll_set)
4299                 return;
4300
4301         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4302         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4303                 pll = &dev_priv->shared_dplls[i];
4304                 pll->config = shared_dpll[i];
4305         }
4306 }
4307
4308 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4309 {
4310         struct drm_i915_private *dev_priv = dev->dev_private;
4311         int dslreg = PIPEDSL(pipe);
4312         u32 temp;
4313
4314         temp = I915_READ(dslreg);
4315         udelay(500);
4316         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4317                 if (wait_for(I915_READ(dslreg) != temp, 5))
4318                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4319         }
4320 }
4321
4322 static int
4323 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4324                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4325                   int src_w, int src_h, int dst_w, int dst_h)
4326 {
4327         struct intel_crtc_scaler_state *scaler_state =
4328                 &crtc_state->scaler_state;
4329         struct intel_crtc *intel_crtc =
4330                 to_intel_crtc(crtc_state->base.crtc);
4331         int need_scaling;
4332
4333         need_scaling = intel_rotation_90_or_270(rotation) ?
4334                 (src_h != dst_w || src_w != dst_h):
4335                 (src_w != dst_w || src_h != dst_h);
4336
4337         /*
4338          * if plane is being disabled or scaler is no more required or force detach
4339          *  - free scaler binded to this plane/crtc
4340          *  - in order to do this, update crtc->scaler_usage
4341          *
4342          * Here scaler state in crtc_state is set free so that
4343          * scaler can be assigned to other user. Actual register
4344          * update to free the scaler is done in plane/panel-fit programming.
4345          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4346          */
4347         if (force_detach || !need_scaling) {
4348                 if (*scaler_id >= 0) {
4349                         scaler_state->scaler_users &= ~(1 << scaler_user);
4350                         scaler_state->scalers[*scaler_id].in_use = 0;
4351
4352                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4353                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4354                                 intel_crtc->pipe, scaler_user, *scaler_id,
4355                                 scaler_state->scaler_users);
4356                         *scaler_id = -1;
4357                 }
4358                 return 0;
4359         }
4360
4361         /* range checks */
4362         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4363                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4364
4365                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4366                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4367                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4368                         "size is out of scaler range\n",
4369                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4370                 return -EINVAL;
4371         }
4372
4373         /* mark this plane as a scaler user in crtc_state */
4374         scaler_state->scaler_users |= (1 << scaler_user);
4375         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4376                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4377                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4378                 scaler_state->scaler_users);
4379
4380         return 0;
4381 }
4382
4383 /**
4384  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4385  *
4386  * @state: crtc's scaler state
4387  *
4388  * Return
4389  *     0 - scaler_usage updated successfully
4390  *    error - requested scaling cannot be supported or other error condition
4391  */
4392 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4393 {
4394         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4395         struct drm_display_mode *adjusted_mode =
4396                 &state->base.adjusted_mode;
4397
4398         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4399                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4400
4401         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4402                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4403                 state->pipe_src_w, state->pipe_src_h,
4404                 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4405 }
4406
4407 /**
4408  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4409  *
4410  * @state: crtc's scaler state
4411  * @plane_state: atomic plane state to update
4412  *
4413  * Return
4414  *     0 - scaler_usage updated successfully
4415  *    error - requested scaling cannot be supported or other error condition
4416  */
4417 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4418                                    struct intel_plane_state *plane_state)
4419 {
4420
4421         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4422         struct intel_plane *intel_plane =
4423                 to_intel_plane(plane_state->base.plane);
4424         struct drm_framebuffer *fb = plane_state->base.fb;
4425         int ret;
4426
4427         bool force_detach = !fb || !plane_state->visible;
4428
4429         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4430                       intel_plane->base.base.id, intel_crtc->pipe,
4431                       drm_plane_index(&intel_plane->base));
4432
4433         ret = skl_update_scaler(crtc_state, force_detach,
4434                                 drm_plane_index(&intel_plane->base),
4435                                 &plane_state->scaler_id,
4436                                 plane_state->base.rotation,
4437                                 drm_rect_width(&plane_state->src) >> 16,
4438                                 drm_rect_height(&plane_state->src) >> 16,
4439                                 drm_rect_width(&plane_state->dst),
4440                                 drm_rect_height(&plane_state->dst));
4441
4442         if (ret || plane_state->scaler_id < 0)
4443                 return ret;
4444
4445         /* check colorkey */
4446         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4447                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4448                               intel_plane->base.base.id);
4449                 return -EINVAL;
4450         }
4451
4452         /* Check src format */
4453         switch (fb->pixel_format) {
4454         case DRM_FORMAT_RGB565:
4455         case DRM_FORMAT_XBGR8888:
4456         case DRM_FORMAT_XRGB8888:
4457         case DRM_FORMAT_ABGR8888:
4458         case DRM_FORMAT_ARGB8888:
4459         case DRM_FORMAT_XRGB2101010:
4460         case DRM_FORMAT_XBGR2101010:
4461         case DRM_FORMAT_YUYV:
4462         case DRM_FORMAT_YVYU:
4463         case DRM_FORMAT_UYVY:
4464         case DRM_FORMAT_VYUY:
4465                 break;
4466         default:
4467                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4468                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4469                 return -EINVAL;
4470         }
4471
4472         return 0;
4473 }
4474
4475 static void skylake_scaler_disable(struct intel_crtc *crtc)
4476 {
4477         int i;
4478
4479         for (i = 0; i < crtc->num_scalers; i++)
4480                 skl_detach_scaler(crtc, i);
4481 }
4482
4483 static void skylake_pfit_enable(struct intel_crtc *crtc)
4484 {
4485         struct drm_device *dev = crtc->base.dev;
4486         struct drm_i915_private *dev_priv = dev->dev_private;
4487         int pipe = crtc->pipe;
4488         struct intel_crtc_scaler_state *scaler_state =
4489                 &crtc->config->scaler_state;
4490
4491         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4492
4493         if (crtc->config->pch_pfit.enabled) {
4494                 int id;
4495
4496                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4497                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4498                         return;
4499                 }
4500
4501                 id = scaler_state->scaler_id;
4502                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4503                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4504                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4505                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4506
4507                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4508         }
4509 }
4510
4511 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4512 {
4513         struct drm_device *dev = crtc->base.dev;
4514         struct drm_i915_private *dev_priv = dev->dev_private;
4515         int pipe = crtc->pipe;
4516
4517         if (crtc->config->pch_pfit.enabled) {
4518                 /* Force use of hard-coded filter coefficients
4519                  * as some pre-programmed values are broken,
4520                  * e.g. x201.
4521                  */
4522                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4523                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4524                                                  PF_PIPE_SEL_IVB(pipe));
4525                 else
4526                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4527                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4528                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4529         }
4530 }
4531
4532 void hsw_enable_ips(struct intel_crtc *crtc)
4533 {
4534         struct drm_device *dev = crtc->base.dev;
4535         struct drm_i915_private *dev_priv = dev->dev_private;
4536
4537         if (!crtc->config->ips_enabled)
4538                 return;
4539
4540         /* We can only enable IPS after we enable a plane and wait for a vblank */
4541         intel_wait_for_vblank(dev, crtc->pipe);
4542
4543         assert_plane_enabled(dev_priv, crtc->plane);
4544         if (IS_BROADWELL(dev)) {
4545                 mutex_lock(&dev_priv->rps.hw_lock);
4546                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4547                 mutex_unlock(&dev_priv->rps.hw_lock);
4548                 /* Quoting Art Runyan: "its not safe to expect any particular
4549                  * value in IPS_CTL bit 31 after enabling IPS through the
4550                  * mailbox." Moreover, the mailbox may return a bogus state,
4551                  * so we need to just enable it and continue on.
4552                  */
4553         } else {
4554                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4555                 /* The bit only becomes 1 in the next vblank, so this wait here
4556                  * is essentially intel_wait_for_vblank. If we don't have this
4557                  * and don't wait for vblanks until the end of crtc_enable, then
4558                  * the HW state readout code will complain that the expected
4559                  * IPS_CTL value is not the one we read. */
4560                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4561                         DRM_ERROR("Timed out waiting for IPS enable\n");
4562         }
4563 }
4564
4565 void hsw_disable_ips(struct intel_crtc *crtc)
4566 {
4567         struct drm_device *dev = crtc->base.dev;
4568         struct drm_i915_private *dev_priv = dev->dev_private;
4569
4570         if (!crtc->config->ips_enabled)
4571                 return;
4572
4573         assert_plane_enabled(dev_priv, crtc->plane);
4574         if (IS_BROADWELL(dev)) {
4575                 mutex_lock(&dev_priv->rps.hw_lock);
4576                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4577                 mutex_unlock(&dev_priv->rps.hw_lock);
4578                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4579                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4580                         DRM_ERROR("Timed out waiting for IPS disable\n");
4581         } else {
4582                 I915_WRITE(IPS_CTL, 0);
4583                 POSTING_READ(IPS_CTL);
4584         }
4585
4586         /* We need to wait for a vblank before we can disable the plane. */
4587         intel_wait_for_vblank(dev, crtc->pipe);
4588 }
4589
4590 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4591 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4592 {
4593         struct drm_device *dev = crtc->dev;
4594         struct drm_i915_private *dev_priv = dev->dev_private;
4595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4596         enum pipe pipe = intel_crtc->pipe;
4597         int palreg = PALETTE(pipe);
4598         int i;
4599         bool reenable_ips = false;
4600
4601         /* The clocks have to be on to load the palette. */
4602         if (!crtc->state->active)
4603                 return;
4604
4605         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4606                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4607                         assert_dsi_pll_enabled(dev_priv);
4608                 else
4609                         assert_pll_enabled(dev_priv, pipe);
4610         }
4611
4612         /* use legacy palette for Ironlake */
4613         if (!HAS_GMCH_DISPLAY(dev))
4614                 palreg = LGC_PALETTE(pipe);
4615
4616         /* Workaround : Do not read or write the pipe palette/gamma data while
4617          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4618          */
4619         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4620             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4621              GAMMA_MODE_MODE_SPLIT)) {
4622                 hsw_disable_ips(intel_crtc);
4623                 reenable_ips = true;
4624         }
4625
4626         for (i = 0; i < 256; i++) {
4627                 I915_WRITE(palreg + 4 * i,
4628                            (intel_crtc->lut_r[i] << 16) |
4629                            (intel_crtc->lut_g[i] << 8) |
4630                            intel_crtc->lut_b[i]);
4631         }
4632
4633         if (reenable_ips)
4634                 hsw_enable_ips(intel_crtc);
4635 }
4636
4637 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4638 {
4639         if (intel_crtc->overlay) {
4640                 struct drm_device *dev = intel_crtc->base.dev;
4641                 struct drm_i915_private *dev_priv = dev->dev_private;
4642
4643                 mutex_lock(&dev->struct_mutex);
4644                 dev_priv->mm.interruptible = false;
4645                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4646                 dev_priv->mm.interruptible = true;
4647                 mutex_unlock(&dev->struct_mutex);
4648         }
4649
4650         /* Let userspace switch the overlay on again. In most cases userspace
4651          * has to recompute where to put it anyway.
4652          */
4653 }
4654
4655 /**
4656  * intel_post_enable_primary - Perform operations after enabling primary plane
4657  * @crtc: the CRTC whose primary plane was just enabled
4658  *
4659  * Performs potentially sleeping operations that must be done after the primary
4660  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4661  * called due to an explicit primary plane update, or due to an implicit
4662  * re-enable that is caused when a sprite plane is updated to no longer
4663  * completely hide the primary plane.
4664  */
4665 static void
4666 intel_post_enable_primary(struct drm_crtc *crtc)
4667 {
4668         struct drm_device *dev = crtc->dev;
4669         struct drm_i915_private *dev_priv = dev->dev_private;
4670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4671         int pipe = intel_crtc->pipe;
4672
4673         /*
4674          * BDW signals flip done immediately if the plane
4675          * is disabled, even if the plane enable is already
4676          * armed to occur at the next vblank :(
4677          */
4678         if (IS_BROADWELL(dev))
4679                 intel_wait_for_vblank(dev, pipe);
4680
4681         /*
4682          * FIXME IPS should be fine as long as one plane is
4683          * enabled, but in practice it seems to have problems
4684          * when going from primary only to sprite only and vice
4685          * versa.
4686          */
4687         hsw_enable_ips(intel_crtc);
4688
4689         /*
4690          * Gen2 reports pipe underruns whenever all planes are disabled.
4691          * So don't enable underrun reporting before at least some planes
4692          * are enabled.
4693          * FIXME: Need to fix the logic to work when we turn off all planes
4694          * but leave the pipe running.
4695          */
4696         if (IS_GEN2(dev))
4697                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4698
4699         /* Underruns don't raise interrupts, so check manually. */
4700         if (HAS_GMCH_DISPLAY(dev))
4701                 i9xx_check_fifo_underruns(dev_priv);
4702 }
4703
4704 /**
4705  * intel_pre_disable_primary - Perform operations before disabling primary plane
4706  * @crtc: the CRTC whose primary plane is to be disabled
4707  *
4708  * Performs potentially sleeping operations that must be done before the
4709  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4710  * be called due to an explicit primary plane update, or due to an implicit
4711  * disable that is caused when a sprite plane completely hides the primary
4712  * plane.
4713  */
4714 static void
4715 intel_pre_disable_primary(struct drm_crtc *crtc)
4716 {
4717         struct drm_device *dev = crtc->dev;
4718         struct drm_i915_private *dev_priv = dev->dev_private;
4719         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4720         int pipe = intel_crtc->pipe;
4721
4722         /*
4723          * Gen2 reports pipe underruns whenever all planes are disabled.
4724          * So diasble underrun reporting before all the planes get disabled.
4725          * FIXME: Need to fix the logic to work when we turn off all planes
4726          * but leave the pipe running.
4727          */
4728         if (IS_GEN2(dev))
4729                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4730
4731         /*
4732          * Vblank time updates from the shadow to live plane control register
4733          * are blocked if the memory self-refresh mode is active at that
4734          * moment. So to make sure the plane gets truly disabled, disable
4735          * first the self-refresh mode. The self-refresh enable bit in turn
4736          * will be checked/applied by the HW only at the next frame start
4737          * event which is after the vblank start event, so we need to have a
4738          * wait-for-vblank between disabling the plane and the pipe.
4739          */
4740         if (HAS_GMCH_DISPLAY(dev)) {
4741                 intel_set_memory_cxsr(dev_priv, false);
4742                 dev_priv->wm.vlv.cxsr = false;
4743                 intel_wait_for_vblank(dev, pipe);
4744         }
4745
4746         /*
4747          * FIXME IPS should be fine as long as one plane is
4748          * enabled, but in practice it seems to have problems
4749          * when going from primary only to sprite only and vice
4750          * versa.
4751          */
4752         hsw_disable_ips(intel_crtc);
4753 }
4754
4755 static void intel_post_plane_update(struct intel_crtc *crtc)
4756 {
4757         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4758         struct drm_device *dev = crtc->base.dev;
4759         struct drm_i915_private *dev_priv = dev->dev_private;
4760         struct drm_plane *plane;
4761
4762         if (atomic->wait_vblank)
4763                 intel_wait_for_vblank(dev, crtc->pipe);
4764
4765         intel_frontbuffer_flip(dev, atomic->fb_bits);
4766
4767         if (atomic->disable_cxsr)
4768                 crtc->wm.cxsr_allowed = true;
4769
4770         if (crtc->atomic.update_wm_post)
4771                 intel_update_watermarks(&crtc->base);
4772
4773         if (atomic->update_fbc)
4774                 intel_fbc_update(dev_priv);
4775
4776         if (atomic->post_enable_primary)
4777                 intel_post_enable_primary(&crtc->base);
4778
4779         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4780                 intel_update_sprite_watermarks(plane, &crtc->base,
4781                                                0, 0, 0, false, false);
4782
4783         memset(atomic, 0, sizeof(*atomic));
4784 }
4785
4786 static void intel_pre_plane_update(struct intel_crtc *crtc)
4787 {
4788         struct drm_device *dev = crtc->base.dev;
4789         struct drm_i915_private *dev_priv = dev->dev_private;
4790         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4791         struct drm_plane *p;
4792
4793         /* Track fb's for any planes being disabled */
4794         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4795                 struct intel_plane *plane = to_intel_plane(p);
4796
4797                 mutex_lock(&dev->struct_mutex);
4798                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4799                                   plane->frontbuffer_bit);
4800                 mutex_unlock(&dev->struct_mutex);
4801         }
4802
4803         if (atomic->wait_for_flips)
4804                 intel_crtc_wait_for_pending_flips(&crtc->base);
4805
4806         if (atomic->disable_fbc)
4807                 intel_fbc_disable_crtc(crtc);
4808
4809         if (crtc->atomic.disable_ips)
4810                 hsw_disable_ips(crtc);
4811
4812         if (atomic->pre_disable_primary)
4813                 intel_pre_disable_primary(&crtc->base);
4814
4815         if (atomic->disable_cxsr) {
4816                 crtc->wm.cxsr_allowed = false;
4817                 intel_set_memory_cxsr(dev_priv, false);
4818         }
4819 }
4820
4821 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4822 {
4823         struct drm_device *dev = crtc->dev;
4824         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4825         struct drm_plane *p;
4826         int pipe = intel_crtc->pipe;
4827
4828         intel_crtc_dpms_overlay_disable(intel_crtc);
4829
4830         drm_for_each_plane_mask(p, dev, plane_mask)
4831                 to_intel_plane(p)->disable_plane(p, crtc);
4832
4833         /*
4834          * FIXME: Once we grow proper nuclear flip support out of this we need
4835          * to compute the mask of flip planes precisely. For the time being
4836          * consider this a flip to a NULL plane.
4837          */
4838         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4839 }
4840
4841 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4842 {
4843         struct drm_device *dev = crtc->dev;
4844         struct drm_i915_private *dev_priv = dev->dev_private;
4845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4846         struct intel_encoder *encoder;
4847         int pipe = intel_crtc->pipe;
4848
4849         if (WARN_ON(intel_crtc->active))
4850                 return;
4851
4852         if (intel_crtc->config->has_pch_encoder)
4853                 intel_prepare_shared_dpll(intel_crtc);
4854
4855         if (intel_crtc->config->has_dp_encoder)
4856                 intel_dp_set_m_n(intel_crtc, M1_N1);
4857
4858         intel_set_pipe_timings(intel_crtc);
4859
4860         if (intel_crtc->config->has_pch_encoder) {
4861                 intel_cpu_transcoder_set_m_n(intel_crtc,
4862                                      &intel_crtc->config->fdi_m_n, NULL);
4863         }
4864
4865         ironlake_set_pipeconf(crtc);
4866
4867         intel_crtc->active = true;
4868
4869         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4870         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4871
4872         for_each_encoder_on_crtc(dev, crtc, encoder)
4873                 if (encoder->pre_enable)
4874                         encoder->pre_enable(encoder);
4875
4876         if (intel_crtc->config->has_pch_encoder) {
4877                 /* Note: FDI PLL enabling _must_ be done before we enable the
4878                  * cpu pipes, hence this is separate from all the other fdi/pch
4879                  * enabling. */
4880                 ironlake_fdi_pll_enable(intel_crtc);
4881         } else {
4882                 assert_fdi_tx_disabled(dev_priv, pipe);
4883                 assert_fdi_rx_disabled(dev_priv, pipe);
4884         }
4885
4886         ironlake_pfit_enable(intel_crtc);
4887
4888         /*
4889          * On ILK+ LUT must be loaded before the pipe is running but with
4890          * clocks enabled
4891          */
4892         intel_crtc_load_lut(crtc);
4893
4894         intel_update_watermarks(crtc);
4895         intel_enable_pipe(intel_crtc);
4896
4897         if (intel_crtc->config->has_pch_encoder)
4898                 ironlake_pch_enable(crtc);
4899
4900         assert_vblank_disabled(crtc);
4901         drm_crtc_vblank_on(crtc);
4902
4903         for_each_encoder_on_crtc(dev, crtc, encoder)
4904                 encoder->enable(encoder);
4905
4906         if (HAS_PCH_CPT(dev))
4907                 cpt_verify_modeset(dev, intel_crtc->pipe);
4908 }
4909
4910 /* IPS only exists on ULT machines and is tied to pipe A. */
4911 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4912 {
4913         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4914 }
4915
4916 static void haswell_crtc_enable(struct drm_crtc *crtc)
4917 {
4918         struct drm_device *dev = crtc->dev;
4919         struct drm_i915_private *dev_priv = dev->dev_private;
4920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4921         struct intel_encoder *encoder;
4922         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4923         struct intel_crtc_state *pipe_config =
4924                 to_intel_crtc_state(crtc->state);
4925
4926         if (WARN_ON(intel_crtc->active))
4927                 return;
4928
4929         if (intel_crtc_to_shared_dpll(intel_crtc))
4930                 intel_enable_shared_dpll(intel_crtc);
4931
4932         if (intel_crtc->config->has_dp_encoder)
4933                 intel_dp_set_m_n(intel_crtc, M1_N1);
4934
4935         intel_set_pipe_timings(intel_crtc);
4936
4937         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4938                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4939                            intel_crtc->config->pixel_multiplier - 1);
4940         }
4941
4942         if (intel_crtc->config->has_pch_encoder) {
4943                 intel_cpu_transcoder_set_m_n(intel_crtc,
4944                                      &intel_crtc->config->fdi_m_n, NULL);
4945         }
4946
4947         haswell_set_pipeconf(crtc);
4948
4949         intel_set_pipe_csc(crtc);
4950
4951         intel_crtc->active = true;
4952
4953         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4954         for_each_encoder_on_crtc(dev, crtc, encoder)
4955                 if (encoder->pre_enable)
4956                         encoder->pre_enable(encoder);
4957
4958         if (intel_crtc->config->has_pch_encoder) {
4959                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4960                                                       true);
4961                 dev_priv->display.fdi_link_train(crtc);
4962         }
4963
4964         intel_ddi_enable_pipe_clock(intel_crtc);
4965
4966         if (INTEL_INFO(dev)->gen == 9)
4967                 skylake_pfit_enable(intel_crtc);
4968         else if (INTEL_INFO(dev)->gen < 9)
4969                 ironlake_pfit_enable(intel_crtc);
4970         else
4971                 MISSING_CASE(INTEL_INFO(dev)->gen);
4972
4973         /*
4974          * On ILK+ LUT must be loaded before the pipe is running but with
4975          * clocks enabled
4976          */
4977         intel_crtc_load_lut(crtc);
4978
4979         intel_ddi_set_pipe_settings(crtc);
4980         intel_ddi_enable_transcoder_func(crtc);
4981
4982         intel_update_watermarks(crtc);
4983         intel_enable_pipe(intel_crtc);
4984
4985         if (intel_crtc->config->has_pch_encoder)
4986                 lpt_pch_enable(crtc);
4987
4988         if (intel_crtc->config->dp_encoder_is_mst)
4989                 intel_ddi_set_vc_payload_alloc(crtc, true);
4990
4991         assert_vblank_disabled(crtc);
4992         drm_crtc_vblank_on(crtc);
4993
4994         for_each_encoder_on_crtc(dev, crtc, encoder) {
4995                 encoder->enable(encoder);
4996                 intel_opregion_notify_encoder(encoder, true);
4997         }
4998
4999         /* If we change the relative order between pipe/planes enabling, we need
5000          * to change the workaround. */
5001         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5002         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5003                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5004                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5005         }
5006 }
5007
5008 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5009 {
5010         struct drm_device *dev = crtc->base.dev;
5011         struct drm_i915_private *dev_priv = dev->dev_private;
5012         int pipe = crtc->pipe;
5013
5014         /* To avoid upsetting the power well on haswell only disable the pfit if
5015          * it's in use. The hw state code will make sure we get this right. */
5016         if (crtc->config->pch_pfit.enabled) {
5017                 I915_WRITE(PF_CTL(pipe), 0);
5018                 I915_WRITE(PF_WIN_POS(pipe), 0);
5019                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5020         }
5021 }
5022
5023 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5024 {
5025         struct drm_device *dev = crtc->dev;
5026         struct drm_i915_private *dev_priv = dev->dev_private;
5027         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5028         struct intel_encoder *encoder;
5029         int pipe = intel_crtc->pipe;
5030         u32 reg, temp;
5031
5032         for_each_encoder_on_crtc(dev, crtc, encoder)
5033                 encoder->disable(encoder);
5034
5035         drm_crtc_vblank_off(crtc);
5036         assert_vblank_disabled(crtc);
5037
5038         if (intel_crtc->config->has_pch_encoder)
5039                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5040
5041         intel_disable_pipe(intel_crtc);
5042
5043         ironlake_pfit_disable(intel_crtc);
5044
5045         if (intel_crtc->config->has_pch_encoder)
5046                 ironlake_fdi_disable(crtc);
5047
5048         for_each_encoder_on_crtc(dev, crtc, encoder)
5049                 if (encoder->post_disable)
5050                         encoder->post_disable(encoder);
5051
5052         if (intel_crtc->config->has_pch_encoder) {
5053                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5054
5055                 if (HAS_PCH_CPT(dev)) {
5056                         /* disable TRANS_DP_CTL */
5057                         reg = TRANS_DP_CTL(pipe);
5058                         temp = I915_READ(reg);
5059                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5060                                   TRANS_DP_PORT_SEL_MASK);
5061                         temp |= TRANS_DP_PORT_SEL_NONE;
5062                         I915_WRITE(reg, temp);
5063
5064                         /* disable DPLL_SEL */
5065                         temp = I915_READ(PCH_DPLL_SEL);
5066                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5067                         I915_WRITE(PCH_DPLL_SEL, temp);
5068                 }
5069
5070                 ironlake_fdi_pll_disable(intel_crtc);
5071         }
5072
5073         intel_crtc->active = false;
5074         intel_update_watermarks(crtc);
5075 }
5076
5077 static void haswell_crtc_disable(struct drm_crtc *crtc)
5078 {
5079         struct drm_device *dev = crtc->dev;
5080         struct drm_i915_private *dev_priv = dev->dev_private;
5081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5082         struct intel_encoder *encoder;
5083         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5084
5085         for_each_encoder_on_crtc(dev, crtc, encoder) {
5086                 intel_opregion_notify_encoder(encoder, false);
5087                 encoder->disable(encoder);
5088         }
5089
5090         drm_crtc_vblank_off(crtc);
5091         assert_vblank_disabled(crtc);
5092
5093         if (intel_crtc->config->has_pch_encoder)
5094                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5095                                                       false);
5096         intel_disable_pipe(intel_crtc);
5097
5098         if (intel_crtc->config->dp_encoder_is_mst)
5099                 intel_ddi_set_vc_payload_alloc(crtc, false);
5100
5101         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5102
5103         if (INTEL_INFO(dev)->gen == 9)
5104                 skylake_scaler_disable(intel_crtc);
5105         else if (INTEL_INFO(dev)->gen < 9)
5106                 ironlake_pfit_disable(intel_crtc);
5107         else
5108                 MISSING_CASE(INTEL_INFO(dev)->gen);
5109
5110         intel_ddi_disable_pipe_clock(intel_crtc);
5111
5112         if (intel_crtc->config->has_pch_encoder) {
5113                 lpt_disable_pch_transcoder(dev_priv);
5114                 intel_ddi_fdi_disable(crtc);
5115         }
5116
5117         for_each_encoder_on_crtc(dev, crtc, encoder)
5118                 if (encoder->post_disable)
5119                         encoder->post_disable(encoder);
5120
5121         intel_crtc->active = false;
5122         intel_update_watermarks(crtc);
5123 }
5124
5125 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5126 {
5127         struct drm_device *dev = crtc->base.dev;
5128         struct drm_i915_private *dev_priv = dev->dev_private;
5129         struct intel_crtc_state *pipe_config = crtc->config;
5130
5131         if (!pipe_config->gmch_pfit.control)
5132                 return;
5133
5134         /*
5135          * The panel fitter should only be adjusted whilst the pipe is disabled,
5136          * according to register description and PRM.
5137          */
5138         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5139         assert_pipe_disabled(dev_priv, crtc->pipe);
5140
5141         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5142         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5143
5144         /* Border color in case we don't scale up to the full screen. Black by
5145          * default, change to something else for debugging. */
5146         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5147 }
5148
5149 static enum intel_display_power_domain port_to_power_domain(enum port port)
5150 {
5151         switch (port) {
5152         case PORT_A:
5153                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5154         case PORT_B:
5155                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5156         case PORT_C:
5157                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5158         case PORT_D:
5159                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5160         case PORT_E:
5161                 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5162         default:
5163                 WARN_ON_ONCE(1);
5164                 return POWER_DOMAIN_PORT_OTHER;
5165         }
5166 }
5167
5168 #define for_each_power_domain(domain, mask)                             \
5169         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5170                 if ((1 << (domain)) & (mask))
5171
5172 enum intel_display_power_domain
5173 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5174 {
5175         struct drm_device *dev = intel_encoder->base.dev;
5176         struct intel_digital_port *intel_dig_port;
5177
5178         switch (intel_encoder->type) {
5179         case INTEL_OUTPUT_UNKNOWN:
5180                 /* Only DDI platforms should ever use this output type */
5181                 WARN_ON_ONCE(!HAS_DDI(dev));
5182         case INTEL_OUTPUT_DISPLAYPORT:
5183         case INTEL_OUTPUT_HDMI:
5184         case INTEL_OUTPUT_EDP:
5185                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5186                 return port_to_power_domain(intel_dig_port->port);
5187         case INTEL_OUTPUT_DP_MST:
5188                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5189                 return port_to_power_domain(intel_dig_port->port);
5190         case INTEL_OUTPUT_ANALOG:
5191                 return POWER_DOMAIN_PORT_CRT;
5192         case INTEL_OUTPUT_DSI:
5193                 return POWER_DOMAIN_PORT_DSI;
5194         default:
5195                 return POWER_DOMAIN_PORT_OTHER;
5196         }
5197 }
5198
5199 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5200 {
5201         struct drm_device *dev = crtc->dev;
5202         struct intel_encoder *intel_encoder;
5203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5204         enum pipe pipe = intel_crtc->pipe;
5205         unsigned long mask;
5206         enum transcoder transcoder;
5207
5208         if (!crtc->state->active)
5209                 return 0;
5210
5211         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5212
5213         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5214         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5215         if (intel_crtc->config->pch_pfit.enabled ||
5216             intel_crtc->config->pch_pfit.force_thru)
5217                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5218
5219         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5220                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5221
5222         return mask;
5223 }
5224
5225 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5226 {
5227         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5228         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5229         enum intel_display_power_domain domain;
5230         unsigned long domains, new_domains, old_domains;
5231
5232         old_domains = intel_crtc->enabled_power_domains;
5233         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5234
5235         domains = new_domains & ~old_domains;
5236
5237         for_each_power_domain(domain, domains)
5238                 intel_display_power_get(dev_priv, domain);
5239
5240         return old_domains & ~new_domains;
5241 }
5242
5243 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5244                                       unsigned long domains)
5245 {
5246         enum intel_display_power_domain domain;
5247
5248         for_each_power_domain(domain, domains)
5249                 intel_display_power_put(dev_priv, domain);
5250 }
5251
5252 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5253 {
5254         struct drm_device *dev = state->dev;
5255         struct drm_i915_private *dev_priv = dev->dev_private;
5256         unsigned long put_domains[I915_MAX_PIPES] = {};
5257         struct drm_crtc_state *crtc_state;
5258         struct drm_crtc *crtc;
5259         int i;
5260
5261         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5262                 if (needs_modeset(crtc->state))
5263                         put_domains[to_intel_crtc(crtc)->pipe] =
5264                                 modeset_get_crtc_power_domains(crtc);
5265         }
5266
5267         if (dev_priv->display.modeset_commit_cdclk) {
5268                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5269
5270                 if (cdclk != dev_priv->cdclk_freq &&
5271                     !WARN_ON(!state->allow_modeset))
5272                         dev_priv->display.modeset_commit_cdclk(state);
5273         }
5274
5275         for (i = 0; i < I915_MAX_PIPES; i++)
5276                 if (put_domains[i])
5277                         modeset_put_power_domains(dev_priv, put_domains[i]);
5278 }
5279
5280 static void intel_update_max_cdclk(struct drm_device *dev)
5281 {
5282         struct drm_i915_private *dev_priv = dev->dev_private;
5283
5284         if (IS_SKYLAKE(dev)) {
5285                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5286
5287                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5288                         dev_priv->max_cdclk_freq = 675000;
5289                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5290                         dev_priv->max_cdclk_freq = 540000;
5291                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5292                         dev_priv->max_cdclk_freq = 450000;
5293                 else
5294                         dev_priv->max_cdclk_freq = 337500;
5295         } else if (IS_BROADWELL(dev))  {
5296                 /*
5297                  * FIXME with extra cooling we can allow
5298                  * 540 MHz for ULX and 675 Mhz for ULT.
5299                  * How can we know if extra cooling is
5300                  * available? PCI ID, VTB, something else?
5301                  */
5302                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5303                         dev_priv->max_cdclk_freq = 450000;
5304                 else if (IS_BDW_ULX(dev))
5305                         dev_priv->max_cdclk_freq = 450000;
5306                 else if (IS_BDW_ULT(dev))
5307                         dev_priv->max_cdclk_freq = 540000;
5308                 else
5309                         dev_priv->max_cdclk_freq = 675000;
5310         } else if (IS_CHERRYVIEW(dev)) {
5311                 dev_priv->max_cdclk_freq = 320000;
5312         } else if (IS_VALLEYVIEW(dev)) {
5313                 dev_priv->max_cdclk_freq = 400000;
5314         } else {
5315                 /* otherwise assume cdclk is fixed */
5316                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5317         }
5318
5319         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5320                          dev_priv->max_cdclk_freq);
5321 }
5322
5323 static void intel_update_cdclk(struct drm_device *dev)
5324 {
5325         struct drm_i915_private *dev_priv = dev->dev_private;
5326
5327         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5328         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5329                          dev_priv->cdclk_freq);
5330
5331         /*
5332          * Program the gmbus_freq based on the cdclk frequency.
5333          * BSpec erroneously claims we should aim for 4MHz, but
5334          * in fact 1MHz is the correct frequency.
5335          */
5336         if (IS_VALLEYVIEW(dev)) {
5337                 /*
5338                  * Program the gmbus_freq based on the cdclk frequency.
5339                  * BSpec erroneously claims we should aim for 4MHz, but
5340                  * in fact 1MHz is the correct frequency.
5341                  */
5342                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5343         }
5344
5345         if (dev_priv->max_cdclk_freq == 0)
5346                 intel_update_max_cdclk(dev);
5347 }
5348
5349 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5350 {
5351         struct drm_i915_private *dev_priv = dev->dev_private;
5352         uint32_t divider;
5353         uint32_t ratio;
5354         uint32_t current_freq;
5355         int ret;
5356
5357         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5358         switch (frequency) {
5359         case 144000:
5360                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5361                 ratio = BXT_DE_PLL_RATIO(60);
5362                 break;
5363         case 288000:
5364                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5365                 ratio = BXT_DE_PLL_RATIO(60);
5366                 break;
5367         case 384000:
5368                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5369                 ratio = BXT_DE_PLL_RATIO(60);
5370                 break;
5371         case 576000:
5372                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5373                 ratio = BXT_DE_PLL_RATIO(60);
5374                 break;
5375         case 624000:
5376                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5377                 ratio = BXT_DE_PLL_RATIO(65);
5378                 break;
5379         case 19200:
5380                 /*
5381                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5382                  * to suppress GCC warning.
5383                  */
5384                 ratio = 0;
5385                 divider = 0;
5386                 break;
5387         default:
5388                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5389
5390                 return;
5391         }
5392
5393         mutex_lock(&dev_priv->rps.hw_lock);
5394         /* Inform power controller of upcoming frequency change */
5395         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5396                                       0x80000000);
5397         mutex_unlock(&dev_priv->rps.hw_lock);
5398
5399         if (ret) {
5400                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5401                           ret, frequency);
5402                 return;
5403         }
5404
5405         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5406         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5407         current_freq = current_freq * 500 + 1000;
5408
5409         /*
5410          * DE PLL has to be disabled when
5411          * - setting to 19.2MHz (bypass, PLL isn't used)
5412          * - before setting to 624MHz (PLL needs toggling)
5413          * - before setting to any frequency from 624MHz (PLL needs toggling)
5414          */
5415         if (frequency == 19200 || frequency == 624000 ||
5416             current_freq == 624000) {
5417                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5418                 /* Timeout 200us */
5419                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5420                              1))
5421                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5422         }
5423
5424         if (frequency != 19200) {
5425                 uint32_t val;
5426
5427                 val = I915_READ(BXT_DE_PLL_CTL);
5428                 val &= ~BXT_DE_PLL_RATIO_MASK;
5429                 val |= ratio;
5430                 I915_WRITE(BXT_DE_PLL_CTL, val);
5431
5432                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5433                 /* Timeout 200us */
5434                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5435                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5436
5437                 val = I915_READ(CDCLK_CTL);
5438                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5439                 val |= divider;
5440                 /*
5441                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5442                  * enable otherwise.
5443                  */
5444                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5445                 if (frequency >= 500000)
5446                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5447
5448                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5449                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5450                 val |= (frequency - 1000) / 500;
5451                 I915_WRITE(CDCLK_CTL, val);
5452         }
5453
5454         mutex_lock(&dev_priv->rps.hw_lock);
5455         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5456                                       DIV_ROUND_UP(frequency, 25000));
5457         mutex_unlock(&dev_priv->rps.hw_lock);
5458
5459         if (ret) {
5460                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5461                           ret, frequency);
5462                 return;
5463         }
5464
5465         intel_update_cdclk(dev);
5466 }
5467
5468 void broxton_init_cdclk(struct drm_device *dev)
5469 {
5470         struct drm_i915_private *dev_priv = dev->dev_private;
5471         uint32_t val;
5472
5473         /*
5474          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5475          * or else the reset will hang because there is no PCH to respond.
5476          * Move the handshake programming to initialization sequence.
5477          * Previously was left up to BIOS.
5478          */
5479         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5480         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5481         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5482
5483         /* Enable PG1 for cdclk */
5484         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5485
5486         /* check if cd clock is enabled */
5487         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5488                 DRM_DEBUG_KMS("Display already initialized\n");
5489                 return;
5490         }
5491
5492         /*
5493          * FIXME:
5494          * - The initial CDCLK needs to be read from VBT.
5495          *   Need to make this change after VBT has changes for BXT.
5496          * - check if setting the max (or any) cdclk freq is really necessary
5497          *   here, it belongs to modeset time
5498          */
5499         broxton_set_cdclk(dev, 624000);
5500
5501         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5502         POSTING_READ(DBUF_CTL);
5503
5504         udelay(10);
5505
5506         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5507                 DRM_ERROR("DBuf power enable timeout!\n");
5508 }
5509
5510 void broxton_uninit_cdclk(struct drm_device *dev)
5511 {
5512         struct drm_i915_private *dev_priv = dev->dev_private;
5513
5514         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5515         POSTING_READ(DBUF_CTL);
5516
5517         udelay(10);
5518
5519         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5520                 DRM_ERROR("DBuf power disable timeout!\n");
5521
5522         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5523         broxton_set_cdclk(dev, 19200);
5524
5525         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5526 }
5527
5528 static const struct skl_cdclk_entry {
5529         unsigned int freq;
5530         unsigned int vco;
5531 } skl_cdclk_frequencies[] = {
5532         { .freq = 308570, .vco = 8640 },
5533         { .freq = 337500, .vco = 8100 },
5534         { .freq = 432000, .vco = 8640 },
5535         { .freq = 450000, .vco = 8100 },
5536         { .freq = 540000, .vco = 8100 },
5537         { .freq = 617140, .vco = 8640 },
5538         { .freq = 675000, .vco = 8100 },
5539 };
5540
5541 static unsigned int skl_cdclk_decimal(unsigned int freq)
5542 {
5543         return (freq - 1000) / 500;
5544 }
5545
5546 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5547 {
5548         unsigned int i;
5549
5550         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5551                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5552
5553                 if (e->freq == freq)
5554                         return e->vco;
5555         }
5556
5557         return 8100;
5558 }
5559
5560 static void
5561 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5562 {
5563         unsigned int min_freq;
5564         u32 val;
5565
5566         /* select the minimum CDCLK before enabling DPLL 0 */
5567         val = I915_READ(CDCLK_CTL);
5568         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5569         val |= CDCLK_FREQ_337_308;
5570
5571         if (required_vco == 8640)
5572                 min_freq = 308570;
5573         else
5574                 min_freq = 337500;
5575
5576         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5577
5578         I915_WRITE(CDCLK_CTL, val);
5579         POSTING_READ(CDCLK_CTL);
5580
5581         /*
5582          * We always enable DPLL0 with the lowest link rate possible, but still
5583          * taking into account the VCO required to operate the eDP panel at the
5584          * desired frequency. The usual DP link rates operate with a VCO of
5585          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5586          * The modeset code is responsible for the selection of the exact link
5587          * rate later on, with the constraint of choosing a frequency that
5588          * works with required_vco.
5589          */
5590         val = I915_READ(DPLL_CTRL1);
5591
5592         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5593                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5594         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5595         if (required_vco == 8640)
5596                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5597                                             SKL_DPLL0);
5598         else
5599                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5600                                             SKL_DPLL0);
5601
5602         I915_WRITE(DPLL_CTRL1, val);
5603         POSTING_READ(DPLL_CTRL1);
5604
5605         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5606
5607         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5608                 DRM_ERROR("DPLL0 not locked\n");
5609 }
5610
5611 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5612 {
5613         int ret;
5614         u32 val;
5615
5616         /* inform PCU we want to change CDCLK */
5617         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5618         mutex_lock(&dev_priv->rps.hw_lock);
5619         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5620         mutex_unlock(&dev_priv->rps.hw_lock);
5621
5622         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5623 }
5624
5625 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5626 {
5627         unsigned int i;
5628
5629         for (i = 0; i < 15; i++) {
5630                 if (skl_cdclk_pcu_ready(dev_priv))
5631                         return true;
5632                 udelay(10);
5633         }
5634
5635         return false;
5636 }
5637
5638 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5639 {
5640         struct drm_device *dev = dev_priv->dev;
5641         u32 freq_select, pcu_ack;
5642
5643         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5644
5645         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5646                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5647                 return;
5648         }
5649
5650         /* set CDCLK_CTL */
5651         switch(freq) {
5652         case 450000:
5653         case 432000:
5654                 freq_select = CDCLK_FREQ_450_432;
5655                 pcu_ack = 1;
5656                 break;
5657         case 540000:
5658                 freq_select = CDCLK_FREQ_540;
5659                 pcu_ack = 2;
5660                 break;
5661         case 308570:
5662         case 337500:
5663         default:
5664                 freq_select = CDCLK_FREQ_337_308;
5665                 pcu_ack = 0;
5666                 break;
5667         case 617140:
5668         case 675000:
5669                 freq_select = CDCLK_FREQ_675_617;
5670                 pcu_ack = 3;
5671                 break;
5672         }
5673
5674         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5675         POSTING_READ(CDCLK_CTL);
5676
5677         /* inform PCU of the change */
5678         mutex_lock(&dev_priv->rps.hw_lock);
5679         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5680         mutex_unlock(&dev_priv->rps.hw_lock);
5681
5682         intel_update_cdclk(dev);
5683 }
5684
5685 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5686 {
5687         /* disable DBUF power */
5688         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5689         POSTING_READ(DBUF_CTL);
5690
5691         udelay(10);
5692
5693         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5694                 DRM_ERROR("DBuf power disable timeout\n");
5695
5696         /* disable DPLL0 */
5697         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5698         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5699                 DRM_ERROR("Couldn't disable DPLL0\n");
5700
5701         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5702 }
5703
5704 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5705 {
5706         u32 val;
5707         unsigned int required_vco;
5708
5709         /* enable PCH reset handshake */
5710         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5711         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5712
5713         /* enable PG1 and Misc I/O */
5714         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5715
5716         /* DPLL0 not enabled (happens on early BIOS versions) */
5717         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5718                 /* enable DPLL0 */
5719                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5720                 skl_dpll0_enable(dev_priv, required_vco);
5721         }
5722
5723         /* set CDCLK to the frequency the BIOS chose */
5724         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5725
5726         /* enable DBUF power */
5727         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5728         POSTING_READ(DBUF_CTL);
5729
5730         udelay(10);
5731
5732         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5733                 DRM_ERROR("DBuf power enable timeout\n");
5734 }
5735
5736 /* returns HPLL frequency in kHz */
5737 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5738 {
5739         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5740
5741         /* Obtain SKU information */
5742         mutex_lock(&dev_priv->sb_lock);
5743         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5744                 CCK_FUSE_HPLL_FREQ_MASK;
5745         mutex_unlock(&dev_priv->sb_lock);
5746
5747         return vco_freq[hpll_freq] * 1000;
5748 }
5749
5750 /* Adjust CDclk dividers to allow high res or save power if possible */
5751 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5752 {
5753         struct drm_i915_private *dev_priv = dev->dev_private;
5754         u32 val, cmd;
5755
5756         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5757                                         != dev_priv->cdclk_freq);
5758
5759         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5760                 cmd = 2;
5761         else if (cdclk == 266667)
5762                 cmd = 1;
5763         else
5764                 cmd = 0;
5765
5766         mutex_lock(&dev_priv->rps.hw_lock);
5767         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5768         val &= ~DSPFREQGUAR_MASK;
5769         val |= (cmd << DSPFREQGUAR_SHIFT);
5770         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5771         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5772                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5773                      50)) {
5774                 DRM_ERROR("timed out waiting for CDclk change\n");
5775         }
5776         mutex_unlock(&dev_priv->rps.hw_lock);
5777
5778         mutex_lock(&dev_priv->sb_lock);
5779
5780         if (cdclk == 400000) {
5781                 u32 divider;
5782
5783                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5784
5785                 /* adjust cdclk divider */
5786                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5787                 val &= ~DISPLAY_FREQUENCY_VALUES;
5788                 val |= divider;
5789                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5790
5791                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5792                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5793                              50))
5794                         DRM_ERROR("timed out waiting for CDclk change\n");
5795         }
5796
5797         /* adjust self-refresh exit latency value */
5798         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5799         val &= ~0x7f;
5800
5801         /*
5802          * For high bandwidth configs, we set a higher latency in the bunit
5803          * so that the core display fetch happens in time to avoid underruns.
5804          */
5805         if (cdclk == 400000)
5806                 val |= 4500 / 250; /* 4.5 usec */
5807         else
5808                 val |= 3000 / 250; /* 3.0 usec */
5809         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5810
5811         mutex_unlock(&dev_priv->sb_lock);
5812
5813         intel_update_cdclk(dev);
5814 }
5815
5816 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5817 {
5818         struct drm_i915_private *dev_priv = dev->dev_private;
5819         u32 val, cmd;
5820
5821         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5822                                                 != dev_priv->cdclk_freq);
5823
5824         switch (cdclk) {
5825         case 333333:
5826         case 320000:
5827         case 266667:
5828         case 200000:
5829                 break;
5830         default:
5831                 MISSING_CASE(cdclk);
5832                 return;
5833         }
5834
5835         /*
5836          * Specs are full of misinformation, but testing on actual
5837          * hardware has shown that we just need to write the desired
5838          * CCK divider into the Punit register.
5839          */
5840         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5841
5842         mutex_lock(&dev_priv->rps.hw_lock);
5843         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5844         val &= ~DSPFREQGUAR_MASK_CHV;
5845         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5846         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5847         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5848                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5849                      50)) {
5850                 DRM_ERROR("timed out waiting for CDclk change\n");
5851         }
5852         mutex_unlock(&dev_priv->rps.hw_lock);
5853
5854         intel_update_cdclk(dev);
5855 }
5856
5857 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5858                                  int max_pixclk)
5859 {
5860         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5861         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5862
5863         /*
5864          * Really only a few cases to deal with, as only 4 CDclks are supported:
5865          *   200MHz
5866          *   267MHz
5867          *   320/333MHz (depends on HPLL freq)
5868          *   400MHz (VLV only)
5869          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5870          * of the lower bin and adjust if needed.
5871          *
5872          * We seem to get an unstable or solid color picture at 200MHz.
5873          * Not sure what's wrong. For now use 200MHz only when all pipes
5874          * are off.
5875          */
5876         if (!IS_CHERRYVIEW(dev_priv) &&
5877             max_pixclk > freq_320*limit/100)
5878                 return 400000;
5879         else if (max_pixclk > 266667*limit/100)
5880                 return freq_320;
5881         else if (max_pixclk > 0)
5882                 return 266667;
5883         else
5884                 return 200000;
5885 }
5886
5887 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5888                               int max_pixclk)
5889 {
5890         /*
5891          * FIXME:
5892          * - remove the guardband, it's not needed on BXT
5893          * - set 19.2MHz bypass frequency if there are no active pipes
5894          */
5895         if (max_pixclk > 576000*9/10)
5896                 return 624000;
5897         else if (max_pixclk > 384000*9/10)
5898                 return 576000;
5899         else if (max_pixclk > 288000*9/10)
5900                 return 384000;
5901         else if (max_pixclk > 144000*9/10)
5902                 return 288000;
5903         else
5904                 return 144000;
5905 }
5906
5907 /* Compute the max pixel clock for new configuration. Uses atomic state if
5908  * that's non-NULL, look at current state otherwise. */
5909 static int intel_mode_max_pixclk(struct drm_device *dev,
5910                                  struct drm_atomic_state *state)
5911 {
5912         struct intel_crtc *intel_crtc;
5913         struct intel_crtc_state *crtc_state;
5914         int max_pixclk = 0;
5915
5916         for_each_intel_crtc(dev, intel_crtc) {
5917                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5918                 if (IS_ERR(crtc_state))
5919                         return PTR_ERR(crtc_state);
5920
5921                 if (!crtc_state->base.enable)
5922                         continue;
5923
5924                 max_pixclk = max(max_pixclk,
5925                                  crtc_state->base.adjusted_mode.crtc_clock);
5926         }
5927
5928         return max_pixclk;
5929 }
5930
5931 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5932 {
5933         struct drm_device *dev = state->dev;
5934         struct drm_i915_private *dev_priv = dev->dev_private;
5935         int max_pixclk = intel_mode_max_pixclk(dev, state);
5936
5937         if (max_pixclk < 0)
5938                 return max_pixclk;
5939
5940         to_intel_atomic_state(state)->cdclk =
5941                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5942
5943         return 0;
5944 }
5945
5946 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5947 {
5948         struct drm_device *dev = state->dev;
5949         struct drm_i915_private *dev_priv = dev->dev_private;
5950         int max_pixclk = intel_mode_max_pixclk(dev, state);
5951
5952         if (max_pixclk < 0)
5953                 return max_pixclk;
5954
5955         to_intel_atomic_state(state)->cdclk =
5956                 broxton_calc_cdclk(dev_priv, max_pixclk);
5957
5958         return 0;
5959 }
5960
5961 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5962 {
5963         unsigned int credits, default_credits;
5964
5965         if (IS_CHERRYVIEW(dev_priv))
5966                 default_credits = PFI_CREDIT(12);
5967         else
5968                 default_credits = PFI_CREDIT(8);
5969
5970         if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5971                 /* CHV suggested value is 31 or 63 */
5972                 if (IS_CHERRYVIEW(dev_priv))
5973                         credits = PFI_CREDIT_63;
5974                 else
5975                         credits = PFI_CREDIT(15);
5976         } else {
5977                 credits = default_credits;
5978         }
5979
5980         /*
5981          * WA - write default credits before re-programming
5982          * FIXME: should we also set the resend bit here?
5983          */
5984         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5985                    default_credits);
5986
5987         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5988                    credits | PFI_CREDIT_RESEND);
5989
5990         /*
5991          * FIXME is this guaranteed to clear
5992          * immediately or should we poll for it?
5993          */
5994         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5995 }
5996
5997 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5998 {
5999         struct drm_device *dev = old_state->dev;
6000         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6001         struct drm_i915_private *dev_priv = dev->dev_private;
6002
6003         /*
6004          * FIXME: We can end up here with all power domains off, yet
6005          * with a CDCLK frequency other than the minimum. To account
6006          * for this take the PIPE-A power domain, which covers the HW
6007          * blocks needed for the following programming. This can be
6008          * removed once it's guaranteed that we get here either with
6009          * the minimum CDCLK set, or the required power domains
6010          * enabled.
6011          */
6012         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6013
6014         if (IS_CHERRYVIEW(dev))
6015                 cherryview_set_cdclk(dev, req_cdclk);
6016         else
6017                 valleyview_set_cdclk(dev, req_cdclk);
6018
6019         vlv_program_pfi_credits(dev_priv);
6020
6021         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6022 }
6023
6024 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6025 {
6026         struct drm_device *dev = crtc->dev;
6027         struct drm_i915_private *dev_priv = to_i915(dev);
6028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6029         struct intel_encoder *encoder;
6030         int pipe = intel_crtc->pipe;
6031         bool is_dsi;
6032
6033         if (WARN_ON(intel_crtc->active))
6034                 return;
6035
6036         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6037
6038         if (!is_dsi) {
6039                 if (IS_CHERRYVIEW(dev))
6040                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6041                 else
6042                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6043         }
6044
6045         if (intel_crtc->config->has_dp_encoder)
6046                 intel_dp_set_m_n(intel_crtc, M1_N1);
6047
6048         intel_set_pipe_timings(intel_crtc);
6049
6050         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6051                 struct drm_i915_private *dev_priv = dev->dev_private;
6052
6053                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6054                 I915_WRITE(CHV_CANVAS(pipe), 0);
6055         }
6056
6057         i9xx_set_pipeconf(intel_crtc);
6058
6059         intel_crtc->active = true;
6060
6061         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6062
6063         for_each_encoder_on_crtc(dev, crtc, encoder)
6064                 if (encoder->pre_pll_enable)
6065                         encoder->pre_pll_enable(encoder);
6066
6067         if (!is_dsi) {
6068                 if (IS_CHERRYVIEW(dev))
6069                         chv_enable_pll(intel_crtc, intel_crtc->config);
6070                 else
6071                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6072         }
6073
6074         for_each_encoder_on_crtc(dev, crtc, encoder)
6075                 if (encoder->pre_enable)
6076                         encoder->pre_enable(encoder);
6077
6078         i9xx_pfit_enable(intel_crtc);
6079
6080         intel_crtc_load_lut(crtc);
6081
6082         intel_enable_pipe(intel_crtc);
6083
6084         assert_vblank_disabled(crtc);
6085         drm_crtc_vblank_on(crtc);
6086
6087         for_each_encoder_on_crtc(dev, crtc, encoder)
6088                 encoder->enable(encoder);
6089 }
6090
6091 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6092 {
6093         struct drm_device *dev = crtc->base.dev;
6094         struct drm_i915_private *dev_priv = dev->dev_private;
6095
6096         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6097         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6098 }
6099
6100 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6101 {
6102         struct drm_device *dev = crtc->dev;
6103         struct drm_i915_private *dev_priv = to_i915(dev);
6104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6105         struct intel_encoder *encoder;
6106         int pipe = intel_crtc->pipe;
6107
6108         if (WARN_ON(intel_crtc->active))
6109                 return;
6110
6111         i9xx_set_pll_dividers(intel_crtc);
6112
6113         if (intel_crtc->config->has_dp_encoder)
6114                 intel_dp_set_m_n(intel_crtc, M1_N1);
6115
6116         intel_set_pipe_timings(intel_crtc);
6117
6118         i9xx_set_pipeconf(intel_crtc);
6119
6120         intel_crtc->active = true;
6121
6122         if (!IS_GEN2(dev))
6123                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6124
6125         for_each_encoder_on_crtc(dev, crtc, encoder)
6126                 if (encoder->pre_enable)
6127                         encoder->pre_enable(encoder);
6128
6129         i9xx_enable_pll(intel_crtc);
6130
6131         i9xx_pfit_enable(intel_crtc);
6132
6133         intel_crtc_load_lut(crtc);
6134
6135         intel_update_watermarks(crtc);
6136         intel_enable_pipe(intel_crtc);
6137
6138         assert_vblank_disabled(crtc);
6139         drm_crtc_vblank_on(crtc);
6140
6141         for_each_encoder_on_crtc(dev, crtc, encoder)
6142                 encoder->enable(encoder);
6143 }
6144
6145 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6146 {
6147         struct drm_device *dev = crtc->base.dev;
6148         struct drm_i915_private *dev_priv = dev->dev_private;
6149
6150         if (!crtc->config->gmch_pfit.control)
6151                 return;
6152
6153         assert_pipe_disabled(dev_priv, crtc->pipe);
6154
6155         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6156                          I915_READ(PFIT_CONTROL));
6157         I915_WRITE(PFIT_CONTROL, 0);
6158 }
6159
6160 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6161 {
6162         struct drm_device *dev = crtc->dev;
6163         struct drm_i915_private *dev_priv = dev->dev_private;
6164         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6165         struct intel_encoder *encoder;
6166         int pipe = intel_crtc->pipe;
6167
6168         /*
6169          * On gen2 planes are double buffered but the pipe isn't, so we must
6170          * wait for planes to fully turn off before disabling the pipe.
6171          * We also need to wait on all gmch platforms because of the
6172          * self-refresh mode constraint explained above.
6173          */
6174         intel_wait_for_vblank(dev, pipe);
6175
6176         for_each_encoder_on_crtc(dev, crtc, encoder)
6177                 encoder->disable(encoder);
6178
6179         drm_crtc_vblank_off(crtc);
6180         assert_vblank_disabled(crtc);
6181
6182         intel_disable_pipe(intel_crtc);
6183
6184         i9xx_pfit_disable(intel_crtc);
6185
6186         for_each_encoder_on_crtc(dev, crtc, encoder)
6187                 if (encoder->post_disable)
6188                         encoder->post_disable(encoder);
6189
6190         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6191                 if (IS_CHERRYVIEW(dev))
6192                         chv_disable_pll(dev_priv, pipe);
6193                 else if (IS_VALLEYVIEW(dev))
6194                         vlv_disable_pll(dev_priv, pipe);
6195                 else
6196                         i9xx_disable_pll(intel_crtc);
6197         }
6198
6199         if (!IS_GEN2(dev))
6200                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6201
6202         intel_crtc->active = false;
6203         intel_update_watermarks(crtc);
6204 }
6205
6206 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6207 {
6208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6209         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6210         enum intel_display_power_domain domain;
6211         unsigned long domains;
6212
6213         if (!intel_crtc->active)
6214                 return;
6215
6216         if (to_intel_plane_state(crtc->primary->state)->visible) {
6217                 intel_crtc_wait_for_pending_flips(crtc);
6218                 intel_pre_disable_primary(crtc);
6219         }
6220
6221         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6222         dev_priv->display.crtc_disable(crtc);
6223         intel_disable_shared_dpll(intel_crtc);
6224
6225         domains = intel_crtc->enabled_power_domains;
6226         for_each_power_domain(domain, domains)
6227                 intel_display_power_put(dev_priv, domain);
6228         intel_crtc->enabled_power_domains = 0;
6229 }
6230
6231 /*
6232  * turn all crtc's off, but do not adjust state
6233  * This has to be paired with a call to intel_modeset_setup_hw_state.
6234  */
6235 int intel_display_suspend(struct drm_device *dev)
6236 {
6237         struct drm_mode_config *config = &dev->mode_config;
6238         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6239         struct drm_atomic_state *state;
6240         struct drm_crtc *crtc;
6241         unsigned crtc_mask = 0;
6242         int ret = 0;
6243
6244         if (WARN_ON(!ctx))
6245                 return 0;
6246
6247         lockdep_assert_held(&ctx->ww_ctx);
6248         state = drm_atomic_state_alloc(dev);
6249         if (WARN_ON(!state))
6250                 return -ENOMEM;
6251
6252         state->acquire_ctx = ctx;
6253         state->allow_modeset = true;
6254
6255         for_each_crtc(dev, crtc) {
6256                 struct drm_crtc_state *crtc_state =
6257                         drm_atomic_get_crtc_state(state, crtc);
6258
6259                 ret = PTR_ERR_OR_ZERO(crtc_state);
6260                 if (ret)
6261                         goto free;
6262
6263                 if (!crtc_state->active)
6264                         continue;
6265
6266                 crtc_state->active = false;
6267                 crtc_mask |= 1 << drm_crtc_index(crtc);
6268         }
6269
6270         if (crtc_mask) {
6271                 ret = drm_atomic_commit(state);
6272
6273                 if (!ret) {
6274                         for_each_crtc(dev, crtc)
6275                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6276                                         crtc->state->active = true;
6277
6278                         return ret;
6279                 }
6280         }
6281
6282 free:
6283         if (ret)
6284                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6285         drm_atomic_state_free(state);
6286         return ret;
6287 }
6288
6289 void intel_encoder_destroy(struct drm_encoder *encoder)
6290 {
6291         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6292
6293         drm_encoder_cleanup(encoder);
6294         kfree(intel_encoder);
6295 }
6296
6297 /* Cross check the actual hw state with our own modeset state tracking (and it's
6298  * internal consistency). */
6299 static void intel_connector_check_state(struct intel_connector *connector)
6300 {
6301         struct drm_crtc *crtc = connector->base.state->crtc;
6302
6303         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6304                       connector->base.base.id,
6305                       connector->base.name);
6306
6307         if (connector->get_hw_state(connector)) {
6308                 struct intel_encoder *encoder = connector->encoder;
6309                 struct drm_connector_state *conn_state = connector->base.state;
6310
6311                 I915_STATE_WARN(!crtc,
6312                          "connector enabled without attached crtc\n");
6313
6314                 if (!crtc)
6315                         return;
6316
6317                 I915_STATE_WARN(!crtc->state->active,
6318                       "connector is active, but attached crtc isn't\n");
6319
6320                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6321                         return;
6322
6323                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6324                         "atomic encoder doesn't match attached encoder\n");
6325
6326                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6327                         "attached encoder crtc differs from connector crtc\n");
6328         } else {
6329                 I915_STATE_WARN(crtc && crtc->state->active,
6330                         "attached crtc is active, but connector isn't\n");
6331                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6332                         "best encoder set without crtc!\n");
6333         }
6334 }
6335
6336 int intel_connector_init(struct intel_connector *connector)
6337 {
6338         struct drm_connector_state *connector_state;
6339
6340         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6341         if (!connector_state)
6342                 return -ENOMEM;
6343
6344         connector->base.state = connector_state;
6345         return 0;
6346 }
6347
6348 struct intel_connector *intel_connector_alloc(void)
6349 {
6350         struct intel_connector *connector;
6351
6352         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6353         if (!connector)
6354                 return NULL;
6355
6356         if (intel_connector_init(connector) < 0) {
6357                 kfree(connector);
6358                 return NULL;
6359         }
6360
6361         return connector;
6362 }
6363
6364 /* Simple connector->get_hw_state implementation for encoders that support only
6365  * one connector and no cloning and hence the encoder state determines the state
6366  * of the connector. */
6367 bool intel_connector_get_hw_state(struct intel_connector *connector)
6368 {
6369         enum pipe pipe = 0;
6370         struct intel_encoder *encoder = connector->encoder;
6371
6372         return encoder->get_hw_state(encoder, &pipe);
6373 }
6374
6375 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6376 {
6377         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6378                 return crtc_state->fdi_lanes;
6379
6380         return 0;
6381 }
6382
6383 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6384                                      struct intel_crtc_state *pipe_config)
6385 {
6386         struct drm_atomic_state *state = pipe_config->base.state;
6387         struct intel_crtc *other_crtc;
6388         struct intel_crtc_state *other_crtc_state;
6389
6390         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6391                       pipe_name(pipe), pipe_config->fdi_lanes);
6392         if (pipe_config->fdi_lanes > 4) {
6393                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6394                               pipe_name(pipe), pipe_config->fdi_lanes);
6395                 return -EINVAL;
6396         }
6397
6398         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6399                 if (pipe_config->fdi_lanes > 2) {
6400                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6401                                       pipe_config->fdi_lanes);
6402                         return -EINVAL;
6403                 } else {
6404                         return 0;
6405                 }
6406         }
6407
6408         if (INTEL_INFO(dev)->num_pipes == 2)
6409                 return 0;
6410
6411         /* Ivybridge 3 pipe is really complicated */
6412         switch (pipe) {
6413         case PIPE_A:
6414                 return 0;
6415         case PIPE_B:
6416                 if (pipe_config->fdi_lanes <= 2)
6417                         return 0;
6418
6419                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6420                 other_crtc_state =
6421                         intel_atomic_get_crtc_state(state, other_crtc);
6422                 if (IS_ERR(other_crtc_state))
6423                         return PTR_ERR(other_crtc_state);
6424
6425                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6426                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6427                                       pipe_name(pipe), pipe_config->fdi_lanes);
6428                         return -EINVAL;
6429                 }
6430                 return 0;
6431         case PIPE_C:
6432                 if (pipe_config->fdi_lanes > 2) {
6433                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6434                                       pipe_name(pipe), pipe_config->fdi_lanes);
6435                         return -EINVAL;
6436                 }
6437
6438                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6439                 other_crtc_state =
6440                         intel_atomic_get_crtc_state(state, other_crtc);
6441                 if (IS_ERR(other_crtc_state))
6442                         return PTR_ERR(other_crtc_state);
6443
6444                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6445                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6446                         return -EINVAL;
6447                 }
6448                 return 0;
6449         default:
6450                 BUG();
6451         }
6452 }
6453
6454 #define RETRY 1
6455 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6456                                        struct intel_crtc_state *pipe_config)
6457 {
6458         struct drm_device *dev = intel_crtc->base.dev;
6459         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6460         int lane, link_bw, fdi_dotclock, ret;
6461         bool needs_recompute = false;
6462
6463 retry:
6464         /* FDI is a binary signal running at ~2.7GHz, encoding
6465          * each output octet as 10 bits. The actual frequency
6466          * is stored as a divider into a 100MHz clock, and the
6467          * mode pixel clock is stored in units of 1KHz.
6468          * Hence the bw of each lane in terms of the mode signal
6469          * is:
6470          */
6471         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6472
6473         fdi_dotclock = adjusted_mode->crtc_clock;
6474
6475         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6476                                            pipe_config->pipe_bpp);
6477
6478         pipe_config->fdi_lanes = lane;
6479
6480         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6481                                link_bw, &pipe_config->fdi_m_n);
6482
6483         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6484                                        intel_crtc->pipe, pipe_config);
6485         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6486                 pipe_config->pipe_bpp -= 2*3;
6487                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6488                               pipe_config->pipe_bpp);
6489                 needs_recompute = true;
6490                 pipe_config->bw_constrained = true;
6491
6492                 goto retry;
6493         }
6494
6495         if (needs_recompute)
6496                 return RETRY;
6497
6498         return ret;
6499 }
6500
6501 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6502                                      struct intel_crtc_state *pipe_config)
6503 {
6504         if (pipe_config->pipe_bpp > 24)
6505                 return false;
6506
6507         /* HSW can handle pixel rate up to cdclk? */
6508         if (IS_HASWELL(dev_priv->dev))
6509                 return true;
6510
6511         /*
6512          * We compare against max which means we must take
6513          * the increased cdclk requirement into account when
6514          * calculating the new cdclk.
6515          *
6516          * Should measure whether using a lower cdclk w/o IPS
6517          */
6518         return ilk_pipe_pixel_rate(pipe_config) <=
6519                 dev_priv->max_cdclk_freq * 95 / 100;
6520 }
6521
6522 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6523                                    struct intel_crtc_state *pipe_config)
6524 {
6525         struct drm_device *dev = crtc->base.dev;
6526         struct drm_i915_private *dev_priv = dev->dev_private;
6527
6528         pipe_config->ips_enabled = i915.enable_ips &&
6529                 hsw_crtc_supports_ips(crtc) &&
6530                 pipe_config_supports_ips(dev_priv, pipe_config);
6531 }
6532
6533 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6534                                      struct intel_crtc_state *pipe_config)
6535 {
6536         struct drm_device *dev = crtc->base.dev;
6537         struct drm_i915_private *dev_priv = dev->dev_private;
6538         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6539
6540         /* FIXME should check pixel clock limits on all platforms */
6541         if (INTEL_INFO(dev)->gen < 4) {
6542                 int clock_limit = dev_priv->max_cdclk_freq;
6543
6544                 /*
6545                  * Enable pixel doubling when the dot clock
6546                  * is > 90% of the (display) core speed.
6547                  *
6548                  * GDG double wide on either pipe,
6549                  * otherwise pipe A only.
6550                  */
6551                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6552                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6553                         clock_limit *= 2;
6554                         pipe_config->double_wide = true;
6555                 }
6556
6557                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6558                         return -EINVAL;
6559         }
6560
6561         /*
6562          * Pipe horizontal size must be even in:
6563          * - DVO ganged mode
6564          * - LVDS dual channel mode
6565          * - Double wide pipe
6566          */
6567         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6568              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6569                 pipe_config->pipe_src_w &= ~1;
6570
6571         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6572          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6573          */
6574         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6575                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6576                 return -EINVAL;
6577
6578         if (HAS_IPS(dev))
6579                 hsw_compute_ips_config(crtc, pipe_config);
6580
6581         if (pipe_config->has_pch_encoder)
6582                 return ironlake_fdi_compute_config(crtc, pipe_config);
6583
6584         return 0;
6585 }
6586
6587 static int skylake_get_display_clock_speed(struct drm_device *dev)
6588 {
6589         struct drm_i915_private *dev_priv = to_i915(dev);
6590         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6591         uint32_t cdctl = I915_READ(CDCLK_CTL);
6592         uint32_t linkrate;
6593
6594         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6595                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6596
6597         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6598                 return 540000;
6599
6600         linkrate = (I915_READ(DPLL_CTRL1) &
6601                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6602
6603         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6604             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6605                 /* vco 8640 */
6606                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6607                 case CDCLK_FREQ_450_432:
6608                         return 432000;
6609                 case CDCLK_FREQ_337_308:
6610                         return 308570;
6611                 case CDCLK_FREQ_675_617:
6612                         return 617140;
6613                 default:
6614                         WARN(1, "Unknown cd freq selection\n");
6615                 }
6616         } else {
6617                 /* vco 8100 */
6618                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6619                 case CDCLK_FREQ_450_432:
6620                         return 450000;
6621                 case CDCLK_FREQ_337_308:
6622                         return 337500;
6623                 case CDCLK_FREQ_675_617:
6624                         return 675000;
6625                 default:
6626                         WARN(1, "Unknown cd freq selection\n");
6627                 }
6628         }
6629
6630         /* error case, do as if DPLL0 isn't enabled */
6631         return 24000;
6632 }
6633
6634 static int broxton_get_display_clock_speed(struct drm_device *dev)
6635 {
6636         struct drm_i915_private *dev_priv = to_i915(dev);
6637         uint32_t cdctl = I915_READ(CDCLK_CTL);
6638         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6639         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6640         int cdclk;
6641
6642         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6643                 return 19200;
6644
6645         cdclk = 19200 * pll_ratio / 2;
6646
6647         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6648         case BXT_CDCLK_CD2X_DIV_SEL_1:
6649                 return cdclk;  /* 576MHz or 624MHz */
6650         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6651                 return cdclk * 2 / 3; /* 384MHz */
6652         case BXT_CDCLK_CD2X_DIV_SEL_2:
6653                 return cdclk / 2; /* 288MHz */
6654         case BXT_CDCLK_CD2X_DIV_SEL_4:
6655                 return cdclk / 4; /* 144MHz */
6656         }
6657
6658         /* error case, do as if DE PLL isn't enabled */
6659         return 19200;
6660 }
6661
6662 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6663 {
6664         struct drm_i915_private *dev_priv = dev->dev_private;
6665         uint32_t lcpll = I915_READ(LCPLL_CTL);
6666         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6667
6668         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6669                 return 800000;
6670         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6671                 return 450000;
6672         else if (freq == LCPLL_CLK_FREQ_450)
6673                 return 450000;
6674         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6675                 return 540000;
6676         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6677                 return 337500;
6678         else
6679                 return 675000;
6680 }
6681
6682 static int haswell_get_display_clock_speed(struct drm_device *dev)
6683 {
6684         struct drm_i915_private *dev_priv = dev->dev_private;
6685         uint32_t lcpll = I915_READ(LCPLL_CTL);
6686         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6687
6688         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6689                 return 800000;
6690         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6691                 return 450000;
6692         else if (freq == LCPLL_CLK_FREQ_450)
6693                 return 450000;
6694         else if (IS_HSW_ULT(dev))
6695                 return 337500;
6696         else
6697                 return 540000;
6698 }
6699
6700 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6701 {
6702         struct drm_i915_private *dev_priv = dev->dev_private;
6703         u32 val;
6704         int divider;
6705
6706         if (dev_priv->hpll_freq == 0)
6707                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6708
6709         mutex_lock(&dev_priv->sb_lock);
6710         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6711         mutex_unlock(&dev_priv->sb_lock);
6712
6713         divider = val & DISPLAY_FREQUENCY_VALUES;
6714
6715         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6716              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6717              "cdclk change in progress\n");
6718
6719         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6720 }
6721
6722 static int ilk_get_display_clock_speed(struct drm_device *dev)
6723 {
6724         return 450000;
6725 }
6726
6727 static int i945_get_display_clock_speed(struct drm_device *dev)
6728 {
6729         return 400000;
6730 }
6731
6732 static int i915_get_display_clock_speed(struct drm_device *dev)
6733 {
6734         return 333333;
6735 }
6736
6737 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6738 {
6739         return 200000;
6740 }
6741
6742 static int pnv_get_display_clock_speed(struct drm_device *dev)
6743 {
6744         u16 gcfgc = 0;
6745
6746         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6747
6748         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6749         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6750                 return 266667;
6751         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6752                 return 333333;
6753         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6754                 return 444444;
6755         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6756                 return 200000;
6757         default:
6758                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6759         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6760                 return 133333;
6761         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6762                 return 166667;
6763         }
6764 }
6765
6766 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6767 {
6768         u16 gcfgc = 0;
6769
6770         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6771
6772         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6773                 return 133333;
6774         else {
6775                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6776                 case GC_DISPLAY_CLOCK_333_MHZ:
6777                         return 333333;
6778                 default:
6779                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6780                         return 190000;
6781                 }
6782         }
6783 }
6784
6785 static int i865_get_display_clock_speed(struct drm_device *dev)
6786 {
6787         return 266667;
6788 }
6789
6790 static int i85x_get_display_clock_speed(struct drm_device *dev)
6791 {
6792         u16 hpllcc = 0;
6793
6794         /*
6795          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6796          * encoding is different :(
6797          * FIXME is this the right way to detect 852GM/852GMV?
6798          */
6799         if (dev->pdev->revision == 0x1)
6800                 return 133333;
6801
6802         pci_bus_read_config_word(dev->pdev->bus,
6803                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6804
6805         /* Assume that the hardware is in the high speed state.  This
6806          * should be the default.
6807          */
6808         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6809         case GC_CLOCK_133_200:
6810         case GC_CLOCK_133_200_2:
6811         case GC_CLOCK_100_200:
6812                 return 200000;
6813         case GC_CLOCK_166_250:
6814                 return 250000;
6815         case GC_CLOCK_100_133:
6816                 return 133333;
6817         case GC_CLOCK_133_266:
6818         case GC_CLOCK_133_266_2:
6819         case GC_CLOCK_166_266:
6820                 return 266667;
6821         }
6822
6823         /* Shouldn't happen */
6824         return 0;
6825 }
6826
6827 static int i830_get_display_clock_speed(struct drm_device *dev)
6828 {
6829         return 133333;
6830 }
6831
6832 static unsigned int intel_hpll_vco(struct drm_device *dev)
6833 {
6834         struct drm_i915_private *dev_priv = dev->dev_private;
6835         static const unsigned int blb_vco[8] = {
6836                 [0] = 3200000,
6837                 [1] = 4000000,
6838                 [2] = 5333333,
6839                 [3] = 4800000,
6840                 [4] = 6400000,
6841         };
6842         static const unsigned int pnv_vco[8] = {
6843                 [0] = 3200000,
6844                 [1] = 4000000,
6845                 [2] = 5333333,
6846                 [3] = 4800000,
6847                 [4] = 2666667,
6848         };
6849         static const unsigned int cl_vco[8] = {
6850                 [0] = 3200000,
6851                 [1] = 4000000,
6852                 [2] = 5333333,
6853                 [3] = 6400000,
6854                 [4] = 3333333,
6855                 [5] = 3566667,
6856                 [6] = 4266667,
6857         };
6858         static const unsigned int elk_vco[8] = {
6859                 [0] = 3200000,
6860                 [1] = 4000000,
6861                 [2] = 5333333,
6862                 [3] = 4800000,
6863         };
6864         static const unsigned int ctg_vco[8] = {
6865                 [0] = 3200000,
6866                 [1] = 4000000,
6867                 [2] = 5333333,
6868                 [3] = 6400000,
6869                 [4] = 2666667,
6870                 [5] = 4266667,
6871         };
6872         const unsigned int *vco_table;
6873         unsigned int vco;
6874         uint8_t tmp = 0;
6875
6876         /* FIXME other chipsets? */
6877         if (IS_GM45(dev))
6878                 vco_table = ctg_vco;
6879         else if (IS_G4X(dev))
6880                 vco_table = elk_vco;
6881         else if (IS_CRESTLINE(dev))
6882                 vco_table = cl_vco;
6883         else if (IS_PINEVIEW(dev))
6884                 vco_table = pnv_vco;
6885         else if (IS_G33(dev))
6886                 vco_table = blb_vco;
6887         else
6888                 return 0;
6889
6890         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6891
6892         vco = vco_table[tmp & 0x7];
6893         if (vco == 0)
6894                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6895         else
6896                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6897
6898         return vco;
6899 }
6900
6901 static int gm45_get_display_clock_speed(struct drm_device *dev)
6902 {
6903         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6904         uint16_t tmp = 0;
6905
6906         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6907
6908         cdclk_sel = (tmp >> 12) & 0x1;
6909
6910         switch (vco) {
6911         case 2666667:
6912         case 4000000:
6913         case 5333333:
6914                 return cdclk_sel ? 333333 : 222222;
6915         case 3200000:
6916                 return cdclk_sel ? 320000 : 228571;
6917         default:
6918                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6919                 return 222222;
6920         }
6921 }
6922
6923 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6924 {
6925         static const uint8_t div_3200[] = { 16, 10,  8 };
6926         static const uint8_t div_4000[] = { 20, 12, 10 };
6927         static const uint8_t div_5333[] = { 24, 16, 14 };
6928         const uint8_t *div_table;
6929         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6930         uint16_t tmp = 0;
6931
6932         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6933
6934         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6935
6936         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6937                 goto fail;
6938
6939         switch (vco) {
6940         case 3200000:
6941                 div_table = div_3200;
6942                 break;
6943         case 4000000:
6944                 div_table = div_4000;
6945                 break;
6946         case 5333333:
6947                 div_table = div_5333;
6948                 break;
6949         default:
6950                 goto fail;
6951         }
6952
6953         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6954
6955 fail:
6956         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6957         return 200000;
6958 }
6959
6960 static int g33_get_display_clock_speed(struct drm_device *dev)
6961 {
6962         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6963         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6964         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6965         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6966         const uint8_t *div_table;
6967         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6968         uint16_t tmp = 0;
6969
6970         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6971
6972         cdclk_sel = (tmp >> 4) & 0x7;
6973
6974         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6975                 goto fail;
6976
6977         switch (vco) {
6978         case 3200000:
6979                 div_table = div_3200;
6980                 break;
6981         case 4000000:
6982                 div_table = div_4000;
6983                 break;
6984         case 4800000:
6985                 div_table = div_4800;
6986                 break;
6987         case 5333333:
6988                 div_table = div_5333;
6989                 break;
6990         default:
6991                 goto fail;
6992         }
6993
6994         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6995
6996 fail:
6997         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6998         return 190476;
6999 }
7000
7001 static void
7002 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7003 {
7004         while (*num > DATA_LINK_M_N_MASK ||
7005                *den > DATA_LINK_M_N_MASK) {
7006                 *num >>= 1;
7007                 *den >>= 1;
7008         }
7009 }
7010
7011 static void compute_m_n(unsigned int m, unsigned int n,
7012                         uint32_t *ret_m, uint32_t *ret_n)
7013 {
7014         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7015         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7016         intel_reduce_m_n_ratio(ret_m, ret_n);
7017 }
7018
7019 void
7020 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7021                        int pixel_clock, int link_clock,
7022                        struct intel_link_m_n *m_n)
7023 {
7024         m_n->tu = 64;
7025
7026         compute_m_n(bits_per_pixel * pixel_clock,
7027                     link_clock * nlanes * 8,
7028                     &m_n->gmch_m, &m_n->gmch_n);
7029
7030         compute_m_n(pixel_clock, link_clock,
7031                     &m_n->link_m, &m_n->link_n);
7032 }
7033
7034 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7035 {
7036         if (i915.panel_use_ssc >= 0)
7037                 return i915.panel_use_ssc != 0;
7038         return dev_priv->vbt.lvds_use_ssc
7039                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7040 }
7041
7042 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7043                            int num_connectors)
7044 {
7045         struct drm_device *dev = crtc_state->base.crtc->dev;
7046         struct drm_i915_private *dev_priv = dev->dev_private;
7047         int refclk;
7048
7049         WARN_ON(!crtc_state->base.state);
7050
7051         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7052                 refclk = 100000;
7053         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7054             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7055                 refclk = dev_priv->vbt.lvds_ssc_freq;
7056                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7057         } else if (!IS_GEN2(dev)) {
7058                 refclk = 96000;
7059         } else {
7060                 refclk = 48000;
7061         }
7062
7063         return refclk;
7064 }
7065
7066 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7067 {
7068         return (1 << dpll->n) << 16 | dpll->m2;
7069 }
7070
7071 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7072 {
7073         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7074 }
7075
7076 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7077                                      struct intel_crtc_state *crtc_state,
7078                                      intel_clock_t *reduced_clock)
7079 {
7080         struct drm_device *dev = crtc->base.dev;
7081         u32 fp, fp2 = 0;
7082
7083         if (IS_PINEVIEW(dev)) {
7084                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7085                 if (reduced_clock)
7086                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7087         } else {
7088                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7089                 if (reduced_clock)
7090                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7091         }
7092
7093         crtc_state->dpll_hw_state.fp0 = fp;
7094
7095         crtc->lowfreq_avail = false;
7096         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7097             reduced_clock) {
7098                 crtc_state->dpll_hw_state.fp1 = fp2;
7099                 crtc->lowfreq_avail = true;
7100         } else {
7101                 crtc_state->dpll_hw_state.fp1 = fp;
7102         }
7103 }
7104
7105 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7106                 pipe)
7107 {
7108         u32 reg_val;
7109
7110         /*
7111          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7112          * and set it to a reasonable value instead.
7113          */
7114         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7115         reg_val &= 0xffffff00;
7116         reg_val |= 0x00000030;
7117         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7118
7119         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7120         reg_val &= 0x8cffffff;
7121         reg_val = 0x8c000000;
7122         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7123
7124         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7125         reg_val &= 0xffffff00;
7126         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7127
7128         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7129         reg_val &= 0x00ffffff;
7130         reg_val |= 0xb0000000;
7131         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7132 }
7133
7134 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7135                                          struct intel_link_m_n *m_n)
7136 {
7137         struct drm_device *dev = crtc->base.dev;
7138         struct drm_i915_private *dev_priv = dev->dev_private;
7139         int pipe = crtc->pipe;
7140
7141         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7142         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7143         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7144         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7145 }
7146
7147 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7148                                          struct intel_link_m_n *m_n,
7149                                          struct intel_link_m_n *m2_n2)
7150 {
7151         struct drm_device *dev = crtc->base.dev;
7152         struct drm_i915_private *dev_priv = dev->dev_private;
7153         int pipe = crtc->pipe;
7154         enum transcoder transcoder = crtc->config->cpu_transcoder;
7155
7156         if (INTEL_INFO(dev)->gen >= 5) {
7157                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7158                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7159                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7160                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7161                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7162                  * for gen < 8) and if DRRS is supported (to make sure the
7163                  * registers are not unnecessarily accessed).
7164                  */
7165                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7166                         crtc->config->has_drrs) {
7167                         I915_WRITE(PIPE_DATA_M2(transcoder),
7168                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7169                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7170                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7171                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7172                 }
7173         } else {
7174                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7175                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7176                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7177                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7178         }
7179 }
7180
7181 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7182 {
7183         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7184
7185         if (m_n == M1_N1) {
7186                 dp_m_n = &crtc->config->dp_m_n;
7187                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7188         } else if (m_n == M2_N2) {
7189
7190                 /*
7191                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7192                  * needs to be programmed into M1_N1.
7193                  */
7194                 dp_m_n = &crtc->config->dp_m2_n2;
7195         } else {
7196                 DRM_ERROR("Unsupported divider value\n");
7197                 return;
7198         }
7199
7200         if (crtc->config->has_pch_encoder)
7201                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7202         else
7203                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7204 }
7205
7206 static void vlv_compute_dpll(struct intel_crtc *crtc,
7207                              struct intel_crtc_state *pipe_config)
7208 {
7209         u32 dpll, dpll_md;
7210
7211         /*
7212          * Enable DPIO clock input. We should never disable the reference
7213          * clock for pipe B, since VGA hotplug / manual detection depends
7214          * on it.
7215          */
7216         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7217                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7218         /* We should never disable this, set it here for state tracking */
7219         if (crtc->pipe == PIPE_B)
7220                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7221         dpll |= DPLL_VCO_ENABLE;
7222         pipe_config->dpll_hw_state.dpll = dpll;
7223
7224         dpll_md = (pipe_config->pixel_multiplier - 1)
7225                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7226         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7227 }
7228
7229 static void vlv_prepare_pll(struct intel_crtc *crtc,
7230                             const struct intel_crtc_state *pipe_config)
7231 {
7232         struct drm_device *dev = crtc->base.dev;
7233         struct drm_i915_private *dev_priv = dev->dev_private;
7234         int pipe = crtc->pipe;
7235         u32 mdiv;
7236         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7237         u32 coreclk, reg_val;
7238
7239         mutex_lock(&dev_priv->sb_lock);
7240
7241         bestn = pipe_config->dpll.n;
7242         bestm1 = pipe_config->dpll.m1;
7243         bestm2 = pipe_config->dpll.m2;
7244         bestp1 = pipe_config->dpll.p1;
7245         bestp2 = pipe_config->dpll.p2;
7246
7247         /* See eDP HDMI DPIO driver vbios notes doc */
7248
7249         /* PLL B needs special handling */
7250         if (pipe == PIPE_B)
7251                 vlv_pllb_recal_opamp(dev_priv, pipe);
7252
7253         /* Set up Tx target for periodic Rcomp update */
7254         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7255
7256         /* Disable target IRef on PLL */
7257         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7258         reg_val &= 0x00ffffff;
7259         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7260
7261         /* Disable fast lock */
7262         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7263
7264         /* Set idtafcrecal before PLL is enabled */
7265         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7266         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7267         mdiv |= ((bestn << DPIO_N_SHIFT));
7268         mdiv |= (1 << DPIO_K_SHIFT);
7269
7270         /*
7271          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7272          * but we don't support that).
7273          * Note: don't use the DAC post divider as it seems unstable.
7274          */
7275         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7276         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7277
7278         mdiv |= DPIO_ENABLE_CALIBRATION;
7279         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7280
7281         /* Set HBR and RBR LPF coefficients */
7282         if (pipe_config->port_clock == 162000 ||
7283             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7284             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7285                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7286                                  0x009f0003);
7287         else
7288                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7289                                  0x00d0000f);
7290
7291         if (pipe_config->has_dp_encoder) {
7292                 /* Use SSC source */
7293                 if (pipe == PIPE_A)
7294                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7295                                          0x0df40000);
7296                 else
7297                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7298                                          0x0df70000);
7299         } else { /* HDMI or VGA */
7300                 /* Use bend source */
7301                 if (pipe == PIPE_A)
7302                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7303                                          0x0df70000);
7304                 else
7305                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7306                                          0x0df40000);
7307         }
7308
7309         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7310         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7311         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7312             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7313                 coreclk |= 0x01000000;
7314         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7315
7316         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7317         mutex_unlock(&dev_priv->sb_lock);
7318 }
7319
7320 static void chv_compute_dpll(struct intel_crtc *crtc,
7321                              struct intel_crtc_state *pipe_config)
7322 {
7323         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7324                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7325                 DPLL_VCO_ENABLE;
7326         if (crtc->pipe != PIPE_A)
7327                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7328
7329         pipe_config->dpll_hw_state.dpll_md =
7330                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7331 }
7332
7333 static void chv_prepare_pll(struct intel_crtc *crtc,
7334                             const struct intel_crtc_state *pipe_config)
7335 {
7336         struct drm_device *dev = crtc->base.dev;
7337         struct drm_i915_private *dev_priv = dev->dev_private;
7338         int pipe = crtc->pipe;
7339         int dpll_reg = DPLL(crtc->pipe);
7340         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7341         u32 loopfilter, tribuf_calcntr;
7342         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7343         u32 dpio_val;
7344         int vco;
7345
7346         bestn = pipe_config->dpll.n;
7347         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7348         bestm1 = pipe_config->dpll.m1;
7349         bestm2 = pipe_config->dpll.m2 >> 22;
7350         bestp1 = pipe_config->dpll.p1;
7351         bestp2 = pipe_config->dpll.p2;
7352         vco = pipe_config->dpll.vco;
7353         dpio_val = 0;
7354         loopfilter = 0;
7355
7356         /*
7357          * Enable Refclk and SSC
7358          */
7359         I915_WRITE(dpll_reg,
7360                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7361
7362         mutex_lock(&dev_priv->sb_lock);
7363
7364         /* p1 and p2 divider */
7365         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7366                         5 << DPIO_CHV_S1_DIV_SHIFT |
7367                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7368                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7369                         1 << DPIO_CHV_K_DIV_SHIFT);
7370
7371         /* Feedback post-divider - m2 */
7372         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7373
7374         /* Feedback refclk divider - n and m1 */
7375         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7376                         DPIO_CHV_M1_DIV_BY_2 |
7377                         1 << DPIO_CHV_N_DIV_SHIFT);
7378
7379         /* M2 fraction division */
7380         if (bestm2_frac)
7381                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7382
7383         /* M2 fraction division enable */
7384         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7385         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7386         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7387         if (bestm2_frac)
7388                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7389         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7390
7391         /* Program digital lock detect threshold */
7392         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7393         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7394                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7395         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7396         if (!bestm2_frac)
7397                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7398         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7399
7400         /* Loop filter */
7401         if (vco == 5400000) {
7402                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7403                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7404                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7405                 tribuf_calcntr = 0x9;
7406         } else if (vco <= 6200000) {
7407                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7408                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7409                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7410                 tribuf_calcntr = 0x9;
7411         } else if (vco <= 6480000) {
7412                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7413                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7414                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7415                 tribuf_calcntr = 0x8;
7416         } else {
7417                 /* Not supported. Apply the same limits as in the max case */
7418                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7419                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7420                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7421                 tribuf_calcntr = 0;
7422         }
7423         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7424
7425         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7426         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7427         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7428         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7429
7430         /* AFC Recal */
7431         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7432                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7433                         DPIO_AFC_RECAL);
7434
7435         mutex_unlock(&dev_priv->sb_lock);
7436 }
7437
7438 /**
7439  * vlv_force_pll_on - forcibly enable just the PLL
7440  * @dev_priv: i915 private structure
7441  * @pipe: pipe PLL to enable
7442  * @dpll: PLL configuration
7443  *
7444  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7445  * in cases where we need the PLL enabled even when @pipe is not going to
7446  * be enabled.
7447  */
7448 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7449                       const struct dpll *dpll)
7450 {
7451         struct intel_crtc *crtc =
7452                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7453         struct intel_crtc_state pipe_config = {
7454                 .base.crtc = &crtc->base,
7455                 .pixel_multiplier = 1,
7456                 .dpll = *dpll,
7457         };
7458
7459         if (IS_CHERRYVIEW(dev)) {
7460                 chv_compute_dpll(crtc, &pipe_config);
7461                 chv_prepare_pll(crtc, &pipe_config);
7462                 chv_enable_pll(crtc, &pipe_config);
7463         } else {
7464                 vlv_compute_dpll(crtc, &pipe_config);
7465                 vlv_prepare_pll(crtc, &pipe_config);
7466                 vlv_enable_pll(crtc, &pipe_config);
7467         }
7468 }
7469
7470 /**
7471  * vlv_force_pll_off - forcibly disable just the PLL
7472  * @dev_priv: i915 private structure
7473  * @pipe: pipe PLL to disable
7474  *
7475  * Disable the PLL for @pipe. To be used in cases where we need
7476  * the PLL enabled even when @pipe is not going to be enabled.
7477  */
7478 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7479 {
7480         if (IS_CHERRYVIEW(dev))
7481                 chv_disable_pll(to_i915(dev), pipe);
7482         else
7483                 vlv_disable_pll(to_i915(dev), pipe);
7484 }
7485
7486 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7487                               struct intel_crtc_state *crtc_state,
7488                               intel_clock_t *reduced_clock,
7489                               int num_connectors)
7490 {
7491         struct drm_device *dev = crtc->base.dev;
7492         struct drm_i915_private *dev_priv = dev->dev_private;
7493         u32 dpll;
7494         bool is_sdvo;
7495         struct dpll *clock = &crtc_state->dpll;
7496
7497         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7498
7499         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7500                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7501
7502         dpll = DPLL_VGA_MODE_DIS;
7503
7504         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7505                 dpll |= DPLLB_MODE_LVDS;
7506         else
7507                 dpll |= DPLLB_MODE_DAC_SERIAL;
7508
7509         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7510                 dpll |= (crtc_state->pixel_multiplier - 1)
7511                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7512         }
7513
7514         if (is_sdvo)
7515                 dpll |= DPLL_SDVO_HIGH_SPEED;
7516
7517         if (crtc_state->has_dp_encoder)
7518                 dpll |= DPLL_SDVO_HIGH_SPEED;
7519
7520         /* compute bitmask from p1 value */
7521         if (IS_PINEVIEW(dev))
7522                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7523         else {
7524                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7525                 if (IS_G4X(dev) && reduced_clock)
7526                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7527         }
7528         switch (clock->p2) {
7529         case 5:
7530                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7531                 break;
7532         case 7:
7533                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7534                 break;
7535         case 10:
7536                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7537                 break;
7538         case 14:
7539                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7540                 break;
7541         }
7542         if (INTEL_INFO(dev)->gen >= 4)
7543                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7544
7545         if (crtc_state->sdvo_tv_clock)
7546                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7547         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7548                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7549                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7550         else
7551                 dpll |= PLL_REF_INPUT_DREFCLK;
7552
7553         dpll |= DPLL_VCO_ENABLE;
7554         crtc_state->dpll_hw_state.dpll = dpll;
7555
7556         if (INTEL_INFO(dev)->gen >= 4) {
7557                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7558                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7559                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7560         }
7561 }
7562
7563 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7564                               struct intel_crtc_state *crtc_state,
7565                               intel_clock_t *reduced_clock,
7566                               int num_connectors)
7567 {
7568         struct drm_device *dev = crtc->base.dev;
7569         struct drm_i915_private *dev_priv = dev->dev_private;
7570         u32 dpll;
7571         struct dpll *clock = &crtc_state->dpll;
7572
7573         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7574
7575         dpll = DPLL_VGA_MODE_DIS;
7576
7577         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7578                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7579         } else {
7580                 if (clock->p1 == 2)
7581                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7582                 else
7583                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7584                 if (clock->p2 == 4)
7585                         dpll |= PLL_P2_DIVIDE_BY_4;
7586         }
7587
7588         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7589                 dpll |= DPLL_DVO_2X_MODE;
7590
7591         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7592                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7593                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7594         else
7595                 dpll |= PLL_REF_INPUT_DREFCLK;
7596
7597         dpll |= DPLL_VCO_ENABLE;
7598         crtc_state->dpll_hw_state.dpll = dpll;
7599 }
7600
7601 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7602 {
7603         struct drm_device *dev = intel_crtc->base.dev;
7604         struct drm_i915_private *dev_priv = dev->dev_private;
7605         enum pipe pipe = intel_crtc->pipe;
7606         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7607         struct drm_display_mode *adjusted_mode =
7608                 &intel_crtc->config->base.adjusted_mode;
7609         uint32_t crtc_vtotal, crtc_vblank_end;
7610         int vsyncshift = 0;
7611
7612         /* We need to be careful not to changed the adjusted mode, for otherwise
7613          * the hw state checker will get angry at the mismatch. */
7614         crtc_vtotal = adjusted_mode->crtc_vtotal;
7615         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7616
7617         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7618                 /* the chip adds 2 halflines automatically */
7619                 crtc_vtotal -= 1;
7620                 crtc_vblank_end -= 1;
7621
7622                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7623                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7624                 else
7625                         vsyncshift = adjusted_mode->crtc_hsync_start -
7626                                 adjusted_mode->crtc_htotal / 2;
7627                 if (vsyncshift < 0)
7628                         vsyncshift += adjusted_mode->crtc_htotal;
7629         }
7630
7631         if (INTEL_INFO(dev)->gen > 3)
7632                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7633
7634         I915_WRITE(HTOTAL(cpu_transcoder),
7635                    (adjusted_mode->crtc_hdisplay - 1) |
7636                    ((adjusted_mode->crtc_htotal - 1) << 16));
7637         I915_WRITE(HBLANK(cpu_transcoder),
7638                    (adjusted_mode->crtc_hblank_start - 1) |
7639                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7640         I915_WRITE(HSYNC(cpu_transcoder),
7641                    (adjusted_mode->crtc_hsync_start - 1) |
7642                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7643
7644         I915_WRITE(VTOTAL(cpu_transcoder),
7645                    (adjusted_mode->crtc_vdisplay - 1) |
7646                    ((crtc_vtotal - 1) << 16));
7647         I915_WRITE(VBLANK(cpu_transcoder),
7648                    (adjusted_mode->crtc_vblank_start - 1) |
7649                    ((crtc_vblank_end - 1) << 16));
7650         I915_WRITE(VSYNC(cpu_transcoder),
7651                    (adjusted_mode->crtc_vsync_start - 1) |
7652                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7653
7654         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7655          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7656          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7657          * bits. */
7658         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7659             (pipe == PIPE_B || pipe == PIPE_C))
7660                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7661
7662         /* pipesrc controls the size that is scaled from, which should
7663          * always be the user's requested size.
7664          */
7665         I915_WRITE(PIPESRC(pipe),
7666                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7667                    (intel_crtc->config->pipe_src_h - 1));
7668 }
7669
7670 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7671                                    struct intel_crtc_state *pipe_config)
7672 {
7673         struct drm_device *dev = crtc->base.dev;
7674         struct drm_i915_private *dev_priv = dev->dev_private;
7675         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7676         uint32_t tmp;
7677
7678         tmp = I915_READ(HTOTAL(cpu_transcoder));
7679         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7680         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7681         tmp = I915_READ(HBLANK(cpu_transcoder));
7682         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7683         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7684         tmp = I915_READ(HSYNC(cpu_transcoder));
7685         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7686         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7687
7688         tmp = I915_READ(VTOTAL(cpu_transcoder));
7689         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7690         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7691         tmp = I915_READ(VBLANK(cpu_transcoder));
7692         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7693         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7694         tmp = I915_READ(VSYNC(cpu_transcoder));
7695         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7696         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7697
7698         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7699                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7700                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7701                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7702         }
7703
7704         tmp = I915_READ(PIPESRC(crtc->pipe));
7705         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7706         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7707
7708         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7709         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7710 }
7711
7712 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7713                                  struct intel_crtc_state *pipe_config)
7714 {
7715         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7716         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7717         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7718         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7719
7720         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7721         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7722         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7723         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7724
7725         mode->flags = pipe_config->base.adjusted_mode.flags;
7726         mode->type = DRM_MODE_TYPE_DRIVER;
7727
7728         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7729         mode->flags |= pipe_config->base.adjusted_mode.flags;
7730
7731         mode->hsync = drm_mode_hsync(mode);
7732         mode->vrefresh = drm_mode_vrefresh(mode);
7733         drm_mode_set_name(mode);
7734 }
7735
7736 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7737 {
7738         struct drm_device *dev = intel_crtc->base.dev;
7739         struct drm_i915_private *dev_priv = dev->dev_private;
7740         uint32_t pipeconf;
7741
7742         pipeconf = 0;
7743
7744         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7745             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7746                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7747
7748         if (intel_crtc->config->double_wide)
7749                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7750
7751         /* only g4x and later have fancy bpc/dither controls */
7752         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7753                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7754                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7755                         pipeconf |= PIPECONF_DITHER_EN |
7756                                     PIPECONF_DITHER_TYPE_SP;
7757
7758                 switch (intel_crtc->config->pipe_bpp) {
7759                 case 18:
7760                         pipeconf |= PIPECONF_6BPC;
7761                         break;
7762                 case 24:
7763                         pipeconf |= PIPECONF_8BPC;
7764                         break;
7765                 case 30:
7766                         pipeconf |= PIPECONF_10BPC;
7767                         break;
7768                 default:
7769                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7770                         BUG();
7771                 }
7772         }
7773
7774         if (HAS_PIPE_CXSR(dev)) {
7775                 if (intel_crtc->lowfreq_avail) {
7776                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7777                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7778                 } else {
7779                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7780                 }
7781         }
7782
7783         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7784                 if (INTEL_INFO(dev)->gen < 4 ||
7785                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7786                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7787                 else
7788                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7789         } else
7790                 pipeconf |= PIPECONF_PROGRESSIVE;
7791
7792         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7793                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7794
7795         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7796         POSTING_READ(PIPECONF(intel_crtc->pipe));
7797 }
7798
7799 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7800                                    struct intel_crtc_state *crtc_state)
7801 {
7802         struct drm_device *dev = crtc->base.dev;
7803         struct drm_i915_private *dev_priv = dev->dev_private;
7804         int refclk, num_connectors = 0;
7805         intel_clock_t clock;
7806         bool ok;
7807         bool is_dsi = false;
7808         struct intel_encoder *encoder;
7809         const intel_limit_t *limit;
7810         struct drm_atomic_state *state = crtc_state->base.state;
7811         struct drm_connector *connector;
7812         struct drm_connector_state *connector_state;
7813         int i;
7814
7815         memset(&crtc_state->dpll_hw_state, 0,
7816                sizeof(crtc_state->dpll_hw_state));
7817
7818         for_each_connector_in_state(state, connector, connector_state, i) {
7819                 if (connector_state->crtc != &crtc->base)
7820                         continue;
7821
7822                 encoder = to_intel_encoder(connector_state->best_encoder);
7823
7824                 switch (encoder->type) {
7825                 case INTEL_OUTPUT_DSI:
7826                         is_dsi = true;
7827                         break;
7828                 default:
7829                         break;
7830                 }
7831
7832                 num_connectors++;
7833         }
7834
7835         if (is_dsi)
7836                 return 0;
7837
7838         if (!crtc_state->clock_set) {
7839                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7840
7841                 /*
7842                  * Returns a set of divisors for the desired target clock with
7843                  * the given refclk, or FALSE.  The returned values represent
7844                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7845                  * 2) / p1 / p2.
7846                  */
7847                 limit = intel_limit(crtc_state, refclk);
7848                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7849                                                  crtc_state->port_clock,
7850                                                  refclk, NULL, &clock);
7851                 if (!ok) {
7852                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7853                         return -EINVAL;
7854                 }
7855
7856                 /* Compat-code for transition, will disappear. */
7857                 crtc_state->dpll.n = clock.n;
7858                 crtc_state->dpll.m1 = clock.m1;
7859                 crtc_state->dpll.m2 = clock.m2;
7860                 crtc_state->dpll.p1 = clock.p1;
7861                 crtc_state->dpll.p2 = clock.p2;
7862         }
7863
7864         if (IS_GEN2(dev)) {
7865                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7866                                   num_connectors);
7867         } else if (IS_CHERRYVIEW(dev)) {
7868                 chv_compute_dpll(crtc, crtc_state);
7869         } else if (IS_VALLEYVIEW(dev)) {
7870                 vlv_compute_dpll(crtc, crtc_state);
7871         } else {
7872                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7873                                   num_connectors);
7874         }
7875
7876         return 0;
7877 }
7878
7879 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7880                                  struct intel_crtc_state *pipe_config)
7881 {
7882         struct drm_device *dev = crtc->base.dev;
7883         struct drm_i915_private *dev_priv = dev->dev_private;
7884         uint32_t tmp;
7885
7886         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7887                 return;
7888
7889         tmp = I915_READ(PFIT_CONTROL);
7890         if (!(tmp & PFIT_ENABLE))
7891                 return;
7892
7893         /* Check whether the pfit is attached to our pipe. */
7894         if (INTEL_INFO(dev)->gen < 4) {
7895                 if (crtc->pipe != PIPE_B)
7896                         return;
7897         } else {
7898                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7899                         return;
7900         }
7901
7902         pipe_config->gmch_pfit.control = tmp;
7903         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7904         if (INTEL_INFO(dev)->gen < 5)
7905                 pipe_config->gmch_pfit.lvds_border_bits =
7906                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7907 }
7908
7909 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7910                                struct intel_crtc_state *pipe_config)
7911 {
7912         struct drm_device *dev = crtc->base.dev;
7913         struct drm_i915_private *dev_priv = dev->dev_private;
7914         int pipe = pipe_config->cpu_transcoder;
7915         intel_clock_t clock;
7916         u32 mdiv;
7917         int refclk = 100000;
7918
7919         /* In case of MIPI DPLL will not even be used */
7920         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7921                 return;
7922
7923         mutex_lock(&dev_priv->sb_lock);
7924         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7925         mutex_unlock(&dev_priv->sb_lock);
7926
7927         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7928         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7929         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7930         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7931         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7932
7933         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7934 }
7935
7936 static void
7937 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7938                               struct intel_initial_plane_config *plane_config)
7939 {
7940         struct drm_device *dev = crtc->base.dev;
7941         struct drm_i915_private *dev_priv = dev->dev_private;
7942         u32 val, base, offset;
7943         int pipe = crtc->pipe, plane = crtc->plane;
7944         int fourcc, pixel_format;
7945         unsigned int aligned_height;
7946         struct drm_framebuffer *fb;
7947         struct intel_framebuffer *intel_fb;
7948
7949         val = I915_READ(DSPCNTR(plane));
7950         if (!(val & DISPLAY_PLANE_ENABLE))
7951                 return;
7952
7953         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7954         if (!intel_fb) {
7955                 DRM_DEBUG_KMS("failed to alloc fb\n");
7956                 return;
7957         }
7958
7959         fb = &intel_fb->base;
7960
7961         if (INTEL_INFO(dev)->gen >= 4) {
7962                 if (val & DISPPLANE_TILED) {
7963                         plane_config->tiling = I915_TILING_X;
7964                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7965                 }
7966         }
7967
7968         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7969         fourcc = i9xx_format_to_fourcc(pixel_format);
7970         fb->pixel_format = fourcc;
7971         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7972
7973         if (INTEL_INFO(dev)->gen >= 4) {
7974                 if (plane_config->tiling)
7975                         offset = I915_READ(DSPTILEOFF(plane));
7976                 else
7977                         offset = I915_READ(DSPLINOFF(plane));
7978                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7979         } else {
7980                 base = I915_READ(DSPADDR(plane));
7981         }
7982         plane_config->base = base;
7983
7984         val = I915_READ(PIPESRC(pipe));
7985         fb->width = ((val >> 16) & 0xfff) + 1;
7986         fb->height = ((val >> 0) & 0xfff) + 1;
7987
7988         val = I915_READ(DSPSTRIDE(pipe));
7989         fb->pitches[0] = val & 0xffffffc0;
7990
7991         aligned_height = intel_fb_align_height(dev, fb->height,
7992                                                fb->pixel_format,
7993                                                fb->modifier[0]);
7994
7995         plane_config->size = fb->pitches[0] * aligned_height;
7996
7997         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7998                       pipe_name(pipe), plane, fb->width, fb->height,
7999                       fb->bits_per_pixel, base, fb->pitches[0],
8000                       plane_config->size);
8001
8002         plane_config->fb = intel_fb;
8003 }
8004
8005 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8006                                struct intel_crtc_state *pipe_config)
8007 {
8008         struct drm_device *dev = crtc->base.dev;
8009         struct drm_i915_private *dev_priv = dev->dev_private;
8010         int pipe = pipe_config->cpu_transcoder;
8011         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8012         intel_clock_t clock;
8013         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8014         int refclk = 100000;
8015
8016         mutex_lock(&dev_priv->sb_lock);
8017         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8018         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8019         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8020         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8021         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8022         mutex_unlock(&dev_priv->sb_lock);
8023
8024         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8025         clock.m2 = (pll_dw0 & 0xff) << 22;
8026         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8027                 clock.m2 |= pll_dw2 & 0x3fffff;
8028         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8029         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8030         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8031
8032         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8033 }
8034
8035 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8036                                  struct intel_crtc_state *pipe_config)
8037 {
8038         struct drm_device *dev = crtc->base.dev;
8039         struct drm_i915_private *dev_priv = dev->dev_private;
8040         uint32_t tmp;
8041
8042         if (!intel_display_power_is_enabled(dev_priv,
8043                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8044                 return false;
8045
8046         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8047         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8048
8049         tmp = I915_READ(PIPECONF(crtc->pipe));
8050         if (!(tmp & PIPECONF_ENABLE))
8051                 return false;
8052
8053         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8054                 switch (tmp & PIPECONF_BPC_MASK) {
8055                 case PIPECONF_6BPC:
8056                         pipe_config->pipe_bpp = 18;
8057                         break;
8058                 case PIPECONF_8BPC:
8059                         pipe_config->pipe_bpp = 24;
8060                         break;
8061                 case PIPECONF_10BPC:
8062                         pipe_config->pipe_bpp = 30;
8063                         break;
8064                 default:
8065                         break;
8066                 }
8067         }
8068
8069         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8070                 pipe_config->limited_color_range = true;
8071
8072         if (INTEL_INFO(dev)->gen < 4)
8073                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8074
8075         intel_get_pipe_timings(crtc, pipe_config);
8076
8077         i9xx_get_pfit_config(crtc, pipe_config);
8078
8079         if (INTEL_INFO(dev)->gen >= 4) {
8080                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8081                 pipe_config->pixel_multiplier =
8082                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8083                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8084                 pipe_config->dpll_hw_state.dpll_md = tmp;
8085         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8086                 tmp = I915_READ(DPLL(crtc->pipe));
8087                 pipe_config->pixel_multiplier =
8088                         ((tmp & SDVO_MULTIPLIER_MASK)
8089                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8090         } else {
8091                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8092                  * port and will be fixed up in the encoder->get_config
8093                  * function. */
8094                 pipe_config->pixel_multiplier = 1;
8095         }
8096         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8097         if (!IS_VALLEYVIEW(dev)) {
8098                 /*
8099                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8100                  * on 830. Filter it out here so that we don't
8101                  * report errors due to that.
8102                  */
8103                 if (IS_I830(dev))
8104                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8105
8106                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8107                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8108         } else {
8109                 /* Mask out read-only status bits. */
8110                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8111                                                      DPLL_PORTC_READY_MASK |
8112                                                      DPLL_PORTB_READY_MASK);
8113         }
8114
8115         if (IS_CHERRYVIEW(dev))
8116                 chv_crtc_clock_get(crtc, pipe_config);
8117         else if (IS_VALLEYVIEW(dev))
8118                 vlv_crtc_clock_get(crtc, pipe_config);
8119         else
8120                 i9xx_crtc_clock_get(crtc, pipe_config);
8121
8122         return true;
8123 }
8124
8125 static void ironlake_init_pch_refclk(struct drm_device *dev)
8126 {
8127         struct drm_i915_private *dev_priv = dev->dev_private;
8128         struct intel_encoder *encoder;
8129         u32 val, final;
8130         bool has_lvds = false;
8131         bool has_cpu_edp = false;
8132         bool has_panel = false;
8133         bool has_ck505 = false;
8134         bool can_ssc = false;
8135
8136         /* We need to take the global config into account */
8137         for_each_intel_encoder(dev, encoder) {
8138                 switch (encoder->type) {
8139                 case INTEL_OUTPUT_LVDS:
8140                         has_panel = true;
8141                         has_lvds = true;
8142                         break;
8143                 case INTEL_OUTPUT_EDP:
8144                         has_panel = true;
8145                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8146                                 has_cpu_edp = true;
8147                         break;
8148                 default:
8149                         break;
8150                 }
8151         }
8152
8153         if (HAS_PCH_IBX(dev)) {
8154                 has_ck505 = dev_priv->vbt.display_clock_mode;
8155                 can_ssc = has_ck505;
8156         } else {
8157                 has_ck505 = false;
8158                 can_ssc = true;
8159         }
8160
8161         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8162                       has_panel, has_lvds, has_ck505);
8163
8164         /* Ironlake: try to setup display ref clock before DPLL
8165          * enabling. This is only under driver's control after
8166          * PCH B stepping, previous chipset stepping should be
8167          * ignoring this setting.
8168          */
8169         val = I915_READ(PCH_DREF_CONTROL);
8170
8171         /* As we must carefully and slowly disable/enable each source in turn,
8172          * compute the final state we want first and check if we need to
8173          * make any changes at all.
8174          */
8175         final = val;
8176         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8177         if (has_ck505)
8178                 final |= DREF_NONSPREAD_CK505_ENABLE;
8179         else
8180                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8181
8182         final &= ~DREF_SSC_SOURCE_MASK;
8183         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8184         final &= ~DREF_SSC1_ENABLE;
8185
8186         if (has_panel) {
8187                 final |= DREF_SSC_SOURCE_ENABLE;
8188
8189                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8190                         final |= DREF_SSC1_ENABLE;
8191
8192                 if (has_cpu_edp) {
8193                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8194                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8195                         else
8196                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8197                 } else
8198                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8199         } else {
8200                 final |= DREF_SSC_SOURCE_DISABLE;
8201                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8202         }
8203
8204         if (final == val)
8205                 return;
8206
8207         /* Always enable nonspread source */
8208         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8209
8210         if (has_ck505)
8211                 val |= DREF_NONSPREAD_CK505_ENABLE;
8212         else
8213                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8214
8215         if (has_panel) {
8216                 val &= ~DREF_SSC_SOURCE_MASK;
8217                 val |= DREF_SSC_SOURCE_ENABLE;
8218
8219                 /* SSC must be turned on before enabling the CPU output  */
8220                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8221                         DRM_DEBUG_KMS("Using SSC on panel\n");
8222                         val |= DREF_SSC1_ENABLE;
8223                 } else
8224                         val &= ~DREF_SSC1_ENABLE;
8225
8226                 /* Get SSC going before enabling the outputs */
8227                 I915_WRITE(PCH_DREF_CONTROL, val);
8228                 POSTING_READ(PCH_DREF_CONTROL);
8229                 udelay(200);
8230
8231                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8232
8233                 /* Enable CPU source on CPU attached eDP */
8234                 if (has_cpu_edp) {
8235                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8236                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8237                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8238                         } else
8239                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8240                 } else
8241                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8242
8243                 I915_WRITE(PCH_DREF_CONTROL, val);
8244                 POSTING_READ(PCH_DREF_CONTROL);
8245                 udelay(200);
8246         } else {
8247                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8248
8249                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8250
8251                 /* Turn off CPU output */
8252                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8253
8254                 I915_WRITE(PCH_DREF_CONTROL, val);
8255                 POSTING_READ(PCH_DREF_CONTROL);
8256                 udelay(200);
8257
8258                 /* Turn off the SSC source */
8259                 val &= ~DREF_SSC_SOURCE_MASK;
8260                 val |= DREF_SSC_SOURCE_DISABLE;
8261
8262                 /* Turn off SSC1 */
8263                 val &= ~DREF_SSC1_ENABLE;
8264
8265                 I915_WRITE(PCH_DREF_CONTROL, val);
8266                 POSTING_READ(PCH_DREF_CONTROL);
8267                 udelay(200);
8268         }
8269
8270         BUG_ON(val != final);
8271 }
8272
8273 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8274 {
8275         uint32_t tmp;
8276
8277         tmp = I915_READ(SOUTH_CHICKEN2);
8278         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8279         I915_WRITE(SOUTH_CHICKEN2, tmp);
8280
8281         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8282                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8283                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8284
8285         tmp = I915_READ(SOUTH_CHICKEN2);
8286         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8287         I915_WRITE(SOUTH_CHICKEN2, tmp);
8288
8289         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8290                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8291                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8292 }
8293
8294 /* WaMPhyProgramming:hsw */
8295 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8296 {
8297         uint32_t tmp;
8298
8299         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8300         tmp &= ~(0xFF << 24);
8301         tmp |= (0x12 << 24);
8302         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8303
8304         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8305         tmp |= (1 << 11);
8306         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8307
8308         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8309         tmp |= (1 << 11);
8310         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8311
8312         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8313         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8314         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8315
8316         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8317         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8318         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8319
8320         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8321         tmp &= ~(7 << 13);
8322         tmp |= (5 << 13);
8323         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8324
8325         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8326         tmp &= ~(7 << 13);
8327         tmp |= (5 << 13);
8328         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8329
8330         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8331         tmp &= ~0xFF;
8332         tmp |= 0x1C;
8333         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8334
8335         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8336         tmp &= ~0xFF;
8337         tmp |= 0x1C;
8338         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8339
8340         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8341         tmp &= ~(0xFF << 16);
8342         tmp |= (0x1C << 16);
8343         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8344
8345         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8346         tmp &= ~(0xFF << 16);
8347         tmp |= (0x1C << 16);
8348         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8349
8350         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8351         tmp |= (1 << 27);
8352         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8353
8354         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8355         tmp |= (1 << 27);
8356         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8357
8358         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8359         tmp &= ~(0xF << 28);
8360         tmp |= (4 << 28);
8361         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8362
8363         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8364         tmp &= ~(0xF << 28);
8365         tmp |= (4 << 28);
8366         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8367 }
8368
8369 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8370  * Programming" based on the parameters passed:
8371  * - Sequence to enable CLKOUT_DP
8372  * - Sequence to enable CLKOUT_DP without spread
8373  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8374  */
8375 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8376                                  bool with_fdi)
8377 {
8378         struct drm_i915_private *dev_priv = dev->dev_private;
8379         uint32_t reg, tmp;
8380
8381         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8382                 with_spread = true;
8383         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8384                  with_fdi, "LP PCH doesn't have FDI\n"))
8385                 with_fdi = false;
8386
8387         mutex_lock(&dev_priv->sb_lock);
8388
8389         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8390         tmp &= ~SBI_SSCCTL_DISABLE;
8391         tmp |= SBI_SSCCTL_PATHALT;
8392         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8393
8394         udelay(24);
8395
8396         if (with_spread) {
8397                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8398                 tmp &= ~SBI_SSCCTL_PATHALT;
8399                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8400
8401                 if (with_fdi) {
8402                         lpt_reset_fdi_mphy(dev_priv);
8403                         lpt_program_fdi_mphy(dev_priv);
8404                 }
8405         }
8406
8407         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8408                SBI_GEN0 : SBI_DBUFF0;
8409         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8410         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8411         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8412
8413         mutex_unlock(&dev_priv->sb_lock);
8414 }
8415
8416 /* Sequence to disable CLKOUT_DP */
8417 static void lpt_disable_clkout_dp(struct drm_device *dev)
8418 {
8419         struct drm_i915_private *dev_priv = dev->dev_private;
8420         uint32_t reg, tmp;
8421
8422         mutex_lock(&dev_priv->sb_lock);
8423
8424         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8425                SBI_GEN0 : SBI_DBUFF0;
8426         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8427         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8428         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8429
8430         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8431         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8432                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8433                         tmp |= SBI_SSCCTL_PATHALT;
8434                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8435                         udelay(32);
8436                 }
8437                 tmp |= SBI_SSCCTL_DISABLE;
8438                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8439         }
8440
8441         mutex_unlock(&dev_priv->sb_lock);
8442 }
8443
8444 static void lpt_init_pch_refclk(struct drm_device *dev)
8445 {
8446         struct intel_encoder *encoder;
8447         bool has_vga = false;
8448
8449         for_each_intel_encoder(dev, encoder) {
8450                 switch (encoder->type) {
8451                 case INTEL_OUTPUT_ANALOG:
8452                         has_vga = true;
8453                         break;
8454                 default:
8455                         break;
8456                 }
8457         }
8458
8459         if (has_vga)
8460                 lpt_enable_clkout_dp(dev, true, true);
8461         else
8462                 lpt_disable_clkout_dp(dev);
8463 }
8464
8465 /*
8466  * Initialize reference clocks when the driver loads
8467  */
8468 void intel_init_pch_refclk(struct drm_device *dev)
8469 {
8470         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8471                 ironlake_init_pch_refclk(dev);
8472         else if (HAS_PCH_LPT(dev))
8473                 lpt_init_pch_refclk(dev);
8474 }
8475
8476 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8477 {
8478         struct drm_device *dev = crtc_state->base.crtc->dev;
8479         struct drm_i915_private *dev_priv = dev->dev_private;
8480         struct drm_atomic_state *state = crtc_state->base.state;
8481         struct drm_connector *connector;
8482         struct drm_connector_state *connector_state;
8483         struct intel_encoder *encoder;
8484         int num_connectors = 0, i;
8485         bool is_lvds = false;
8486
8487         for_each_connector_in_state(state, connector, connector_state, i) {
8488                 if (connector_state->crtc != crtc_state->base.crtc)
8489                         continue;
8490
8491                 encoder = to_intel_encoder(connector_state->best_encoder);
8492
8493                 switch (encoder->type) {
8494                 case INTEL_OUTPUT_LVDS:
8495                         is_lvds = true;
8496                         break;
8497                 default:
8498                         break;
8499                 }
8500                 num_connectors++;
8501         }
8502
8503         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8504                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8505                               dev_priv->vbt.lvds_ssc_freq);
8506                 return dev_priv->vbt.lvds_ssc_freq;
8507         }
8508
8509         return 120000;
8510 }
8511
8512 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8513 {
8514         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8516         int pipe = intel_crtc->pipe;
8517         uint32_t val;
8518
8519         val = 0;
8520
8521         switch (intel_crtc->config->pipe_bpp) {
8522         case 18:
8523                 val |= PIPECONF_6BPC;
8524                 break;
8525         case 24:
8526                 val |= PIPECONF_8BPC;
8527                 break;
8528         case 30:
8529                 val |= PIPECONF_10BPC;
8530                 break;
8531         case 36:
8532                 val |= PIPECONF_12BPC;
8533                 break;
8534         default:
8535                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8536                 BUG();
8537         }
8538
8539         if (intel_crtc->config->dither)
8540                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8541
8542         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8543                 val |= PIPECONF_INTERLACED_ILK;
8544         else
8545                 val |= PIPECONF_PROGRESSIVE;
8546
8547         if (intel_crtc->config->limited_color_range)
8548                 val |= PIPECONF_COLOR_RANGE_SELECT;
8549
8550         I915_WRITE(PIPECONF(pipe), val);
8551         POSTING_READ(PIPECONF(pipe));
8552 }
8553
8554 /*
8555  * Set up the pipe CSC unit.
8556  *
8557  * Currently only full range RGB to limited range RGB conversion
8558  * is supported, but eventually this should handle various
8559  * RGB<->YCbCr scenarios as well.
8560  */
8561 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8562 {
8563         struct drm_device *dev = crtc->dev;
8564         struct drm_i915_private *dev_priv = dev->dev_private;
8565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8566         int pipe = intel_crtc->pipe;
8567         uint16_t coeff = 0x7800; /* 1.0 */
8568
8569         /*
8570          * TODO: Check what kind of values actually come out of the pipe
8571          * with these coeff/postoff values and adjust to get the best
8572          * accuracy. Perhaps we even need to take the bpc value into
8573          * consideration.
8574          */
8575
8576         if (intel_crtc->config->limited_color_range)
8577                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8578
8579         /*
8580          * GY/GU and RY/RU should be the other way around according
8581          * to BSpec, but reality doesn't agree. Just set them up in
8582          * a way that results in the correct picture.
8583          */
8584         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8585         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8586
8587         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8588         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8589
8590         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8591         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8592
8593         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8594         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8595         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8596
8597         if (INTEL_INFO(dev)->gen > 6) {
8598                 uint16_t postoff = 0;
8599
8600                 if (intel_crtc->config->limited_color_range)
8601                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8602
8603                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8604                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8605                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8606
8607                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8608         } else {
8609                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8610
8611                 if (intel_crtc->config->limited_color_range)
8612                         mode |= CSC_BLACK_SCREEN_OFFSET;
8613
8614                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8615         }
8616 }
8617
8618 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8619 {
8620         struct drm_device *dev = crtc->dev;
8621         struct drm_i915_private *dev_priv = dev->dev_private;
8622         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8623         enum pipe pipe = intel_crtc->pipe;
8624         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8625         uint32_t val;
8626
8627         val = 0;
8628
8629         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8630                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8631
8632         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8633                 val |= PIPECONF_INTERLACED_ILK;
8634         else
8635                 val |= PIPECONF_PROGRESSIVE;
8636
8637         I915_WRITE(PIPECONF(cpu_transcoder), val);
8638         POSTING_READ(PIPECONF(cpu_transcoder));
8639
8640         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8641         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8642
8643         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8644                 val = 0;
8645
8646                 switch (intel_crtc->config->pipe_bpp) {
8647                 case 18:
8648                         val |= PIPEMISC_DITHER_6_BPC;
8649                         break;
8650                 case 24:
8651                         val |= PIPEMISC_DITHER_8_BPC;
8652                         break;
8653                 case 30:
8654                         val |= PIPEMISC_DITHER_10_BPC;
8655                         break;
8656                 case 36:
8657                         val |= PIPEMISC_DITHER_12_BPC;
8658                         break;
8659                 default:
8660                         /* Case prevented by pipe_config_set_bpp. */
8661                         BUG();
8662                 }
8663
8664                 if (intel_crtc->config->dither)
8665                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8666
8667                 I915_WRITE(PIPEMISC(pipe), val);
8668         }
8669 }
8670
8671 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8672                                     struct intel_crtc_state *crtc_state,
8673                                     intel_clock_t *clock,
8674                                     bool *has_reduced_clock,
8675                                     intel_clock_t *reduced_clock)
8676 {
8677         struct drm_device *dev = crtc->dev;
8678         struct drm_i915_private *dev_priv = dev->dev_private;
8679         int refclk;
8680         const intel_limit_t *limit;
8681         bool ret;
8682
8683         refclk = ironlake_get_refclk(crtc_state);
8684
8685         /*
8686          * Returns a set of divisors for the desired target clock with the given
8687          * refclk, or FALSE.  The returned values represent the clock equation:
8688          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8689          */
8690         limit = intel_limit(crtc_state, refclk);
8691         ret = dev_priv->display.find_dpll(limit, crtc_state,
8692                                           crtc_state->port_clock,
8693                                           refclk, NULL, clock);
8694         if (!ret)
8695                 return false;
8696
8697         return true;
8698 }
8699
8700 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8701 {
8702         /*
8703          * Account for spread spectrum to avoid
8704          * oversubscribing the link. Max center spread
8705          * is 2.5%; use 5% for safety's sake.
8706          */
8707         u32 bps = target_clock * bpp * 21 / 20;
8708         return DIV_ROUND_UP(bps, link_bw * 8);
8709 }
8710
8711 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8712 {
8713         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8714 }
8715
8716 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8717                                       struct intel_crtc_state *crtc_state,
8718                                       u32 *fp,
8719                                       intel_clock_t *reduced_clock, u32 *fp2)
8720 {
8721         struct drm_crtc *crtc = &intel_crtc->base;
8722         struct drm_device *dev = crtc->dev;
8723         struct drm_i915_private *dev_priv = dev->dev_private;
8724         struct drm_atomic_state *state = crtc_state->base.state;
8725         struct drm_connector *connector;
8726         struct drm_connector_state *connector_state;
8727         struct intel_encoder *encoder;
8728         uint32_t dpll;
8729         int factor, num_connectors = 0, i;
8730         bool is_lvds = false, is_sdvo = false;
8731
8732         for_each_connector_in_state(state, connector, connector_state, i) {
8733                 if (connector_state->crtc != crtc_state->base.crtc)
8734                         continue;
8735
8736                 encoder = to_intel_encoder(connector_state->best_encoder);
8737
8738                 switch (encoder->type) {
8739                 case INTEL_OUTPUT_LVDS:
8740                         is_lvds = true;
8741                         break;
8742                 case INTEL_OUTPUT_SDVO:
8743                 case INTEL_OUTPUT_HDMI:
8744                         is_sdvo = true;
8745                         break;
8746                 default:
8747                         break;
8748                 }
8749
8750                 num_connectors++;
8751         }
8752
8753         /* Enable autotuning of the PLL clock (if permissible) */
8754         factor = 21;
8755         if (is_lvds) {
8756                 if ((intel_panel_use_ssc(dev_priv) &&
8757                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8758                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8759                         factor = 25;
8760         } else if (crtc_state->sdvo_tv_clock)
8761                 factor = 20;
8762
8763         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8764                 *fp |= FP_CB_TUNE;
8765
8766         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8767                 *fp2 |= FP_CB_TUNE;
8768
8769         dpll = 0;
8770
8771         if (is_lvds)
8772                 dpll |= DPLLB_MODE_LVDS;
8773         else
8774                 dpll |= DPLLB_MODE_DAC_SERIAL;
8775
8776         dpll |= (crtc_state->pixel_multiplier - 1)
8777                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8778
8779         if (is_sdvo)
8780                 dpll |= DPLL_SDVO_HIGH_SPEED;
8781         if (crtc_state->has_dp_encoder)
8782                 dpll |= DPLL_SDVO_HIGH_SPEED;
8783
8784         /* compute bitmask from p1 value */
8785         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8786         /* also FPA1 */
8787         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8788
8789         switch (crtc_state->dpll.p2) {
8790         case 5:
8791                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8792                 break;
8793         case 7:
8794                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8795                 break;
8796         case 10:
8797                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8798                 break;
8799         case 14:
8800                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8801                 break;
8802         }
8803
8804         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8805                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8806         else
8807                 dpll |= PLL_REF_INPUT_DREFCLK;
8808
8809         return dpll | DPLL_VCO_ENABLE;
8810 }
8811
8812 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8813                                        struct intel_crtc_state *crtc_state)
8814 {
8815         struct drm_device *dev = crtc->base.dev;
8816         intel_clock_t clock, reduced_clock;
8817         u32 dpll = 0, fp = 0, fp2 = 0;
8818         bool ok, has_reduced_clock = false;
8819         bool is_lvds = false;
8820         struct intel_shared_dpll *pll;
8821
8822         memset(&crtc_state->dpll_hw_state, 0,
8823                sizeof(crtc_state->dpll_hw_state));
8824
8825         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8826
8827         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8828              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8829
8830         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8831                                      &has_reduced_clock, &reduced_clock);
8832         if (!ok && !crtc_state->clock_set) {
8833                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8834                 return -EINVAL;
8835         }
8836         /* Compat-code for transition, will disappear. */
8837         if (!crtc_state->clock_set) {
8838                 crtc_state->dpll.n = clock.n;
8839                 crtc_state->dpll.m1 = clock.m1;
8840                 crtc_state->dpll.m2 = clock.m2;
8841                 crtc_state->dpll.p1 = clock.p1;
8842                 crtc_state->dpll.p2 = clock.p2;
8843         }
8844
8845         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8846         if (crtc_state->has_pch_encoder) {
8847                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8848                 if (has_reduced_clock)
8849                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8850
8851                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8852                                              &fp, &reduced_clock,
8853                                              has_reduced_clock ? &fp2 : NULL);
8854
8855                 crtc_state->dpll_hw_state.dpll = dpll;
8856                 crtc_state->dpll_hw_state.fp0 = fp;
8857                 if (has_reduced_clock)
8858                         crtc_state->dpll_hw_state.fp1 = fp2;
8859                 else
8860                         crtc_state->dpll_hw_state.fp1 = fp;
8861
8862                 pll = intel_get_shared_dpll(crtc, crtc_state);
8863                 if (pll == NULL) {
8864                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8865                                          pipe_name(crtc->pipe));
8866                         return -EINVAL;
8867                 }
8868         }
8869
8870         if (is_lvds && has_reduced_clock)
8871                 crtc->lowfreq_avail = true;
8872         else
8873                 crtc->lowfreq_avail = false;
8874
8875         return 0;
8876 }
8877
8878 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8879                                          struct intel_link_m_n *m_n)
8880 {
8881         struct drm_device *dev = crtc->base.dev;
8882         struct drm_i915_private *dev_priv = dev->dev_private;
8883         enum pipe pipe = crtc->pipe;
8884
8885         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8886         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8887         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8888                 & ~TU_SIZE_MASK;
8889         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8890         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8891                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8892 }
8893
8894 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8895                                          enum transcoder transcoder,
8896                                          struct intel_link_m_n *m_n,
8897                                          struct intel_link_m_n *m2_n2)
8898 {
8899         struct drm_device *dev = crtc->base.dev;
8900         struct drm_i915_private *dev_priv = dev->dev_private;
8901         enum pipe pipe = crtc->pipe;
8902
8903         if (INTEL_INFO(dev)->gen >= 5) {
8904                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8905                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8906                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8907                         & ~TU_SIZE_MASK;
8908                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8909                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8910                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8911                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8912                  * gen < 8) and if DRRS is supported (to make sure the
8913                  * registers are not unnecessarily read).
8914                  */
8915                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8916                         crtc->config->has_drrs) {
8917                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8918                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8919                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8920                                         & ~TU_SIZE_MASK;
8921                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8922                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8923                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8924                 }
8925         } else {
8926                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8927                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8928                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8929                         & ~TU_SIZE_MASK;
8930                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8931                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8932                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8933         }
8934 }
8935
8936 void intel_dp_get_m_n(struct intel_crtc *crtc,
8937                       struct intel_crtc_state *pipe_config)
8938 {
8939         if (pipe_config->has_pch_encoder)
8940                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8941         else
8942                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8943                                              &pipe_config->dp_m_n,
8944                                              &pipe_config->dp_m2_n2);
8945 }
8946
8947 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8948                                         struct intel_crtc_state *pipe_config)
8949 {
8950         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8951                                      &pipe_config->fdi_m_n, NULL);
8952 }
8953
8954 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8955                                     struct intel_crtc_state *pipe_config)
8956 {
8957         struct drm_device *dev = crtc->base.dev;
8958         struct drm_i915_private *dev_priv = dev->dev_private;
8959         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8960         uint32_t ps_ctrl = 0;
8961         int id = -1;
8962         int i;
8963
8964         /* find scaler attached to this pipe */
8965         for (i = 0; i < crtc->num_scalers; i++) {
8966                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8967                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8968                         id = i;
8969                         pipe_config->pch_pfit.enabled = true;
8970                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8971                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8972                         break;
8973                 }
8974         }
8975
8976         scaler_state->scaler_id = id;
8977         if (id >= 0) {
8978                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8979         } else {
8980                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8981         }
8982 }
8983
8984 static void
8985 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8986                                  struct intel_initial_plane_config *plane_config)
8987 {
8988         struct drm_device *dev = crtc->base.dev;
8989         struct drm_i915_private *dev_priv = dev->dev_private;
8990         u32 val, base, offset, stride_mult, tiling;
8991         int pipe = crtc->pipe;
8992         int fourcc, pixel_format;
8993         unsigned int aligned_height;
8994         struct drm_framebuffer *fb;
8995         struct intel_framebuffer *intel_fb;
8996
8997         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8998         if (!intel_fb) {
8999                 DRM_DEBUG_KMS("failed to alloc fb\n");
9000                 return;
9001         }
9002
9003         fb = &intel_fb->base;
9004
9005         val = I915_READ(PLANE_CTL(pipe, 0));
9006         if (!(val & PLANE_CTL_ENABLE))
9007                 goto error;
9008
9009         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9010         fourcc = skl_format_to_fourcc(pixel_format,
9011                                       val & PLANE_CTL_ORDER_RGBX,
9012                                       val & PLANE_CTL_ALPHA_MASK);
9013         fb->pixel_format = fourcc;
9014         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9015
9016         tiling = val & PLANE_CTL_TILED_MASK;
9017         switch (tiling) {
9018         case PLANE_CTL_TILED_LINEAR:
9019                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9020                 break;
9021         case PLANE_CTL_TILED_X:
9022                 plane_config->tiling = I915_TILING_X;
9023                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9024                 break;
9025         case PLANE_CTL_TILED_Y:
9026                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9027                 break;
9028         case PLANE_CTL_TILED_YF:
9029                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9030                 break;
9031         default:
9032                 MISSING_CASE(tiling);
9033                 goto error;
9034         }
9035
9036         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9037         plane_config->base = base;
9038
9039         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9040
9041         val = I915_READ(PLANE_SIZE(pipe, 0));
9042         fb->height = ((val >> 16) & 0xfff) + 1;
9043         fb->width = ((val >> 0) & 0x1fff) + 1;
9044
9045         val = I915_READ(PLANE_STRIDE(pipe, 0));
9046         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9047                                                 fb->pixel_format);
9048         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9049
9050         aligned_height = intel_fb_align_height(dev, fb->height,
9051                                                fb->pixel_format,
9052                                                fb->modifier[0]);
9053
9054         plane_config->size = fb->pitches[0] * aligned_height;
9055
9056         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9057                       pipe_name(pipe), fb->width, fb->height,
9058                       fb->bits_per_pixel, base, fb->pitches[0],
9059                       plane_config->size);
9060
9061         plane_config->fb = intel_fb;
9062         return;
9063
9064 error:
9065         kfree(fb);
9066 }
9067
9068 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9069                                      struct intel_crtc_state *pipe_config)
9070 {
9071         struct drm_device *dev = crtc->base.dev;
9072         struct drm_i915_private *dev_priv = dev->dev_private;
9073         uint32_t tmp;
9074
9075         tmp = I915_READ(PF_CTL(crtc->pipe));
9076
9077         if (tmp & PF_ENABLE) {
9078                 pipe_config->pch_pfit.enabled = true;
9079                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9080                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9081
9082                 /* We currently do not free assignements of panel fitters on
9083                  * ivb/hsw (since we don't use the higher upscaling modes which
9084                  * differentiates them) so just WARN about this case for now. */
9085                 if (IS_GEN7(dev)) {
9086                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9087                                 PF_PIPE_SEL_IVB(crtc->pipe));
9088                 }
9089         }
9090 }
9091
9092 static void
9093 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9094                                   struct intel_initial_plane_config *plane_config)
9095 {
9096         struct drm_device *dev = crtc->base.dev;
9097         struct drm_i915_private *dev_priv = dev->dev_private;
9098         u32 val, base, offset;
9099         int pipe = crtc->pipe;
9100         int fourcc, pixel_format;
9101         unsigned int aligned_height;
9102         struct drm_framebuffer *fb;
9103         struct intel_framebuffer *intel_fb;
9104
9105         val = I915_READ(DSPCNTR(pipe));
9106         if (!(val & DISPLAY_PLANE_ENABLE))
9107                 return;
9108
9109         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9110         if (!intel_fb) {
9111                 DRM_DEBUG_KMS("failed to alloc fb\n");
9112                 return;
9113         }
9114
9115         fb = &intel_fb->base;
9116
9117         if (INTEL_INFO(dev)->gen >= 4) {
9118                 if (val & DISPPLANE_TILED) {
9119                         plane_config->tiling = I915_TILING_X;
9120                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9121                 }
9122         }
9123
9124         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9125         fourcc = i9xx_format_to_fourcc(pixel_format);
9126         fb->pixel_format = fourcc;
9127         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9128
9129         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9130         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9131                 offset = I915_READ(DSPOFFSET(pipe));
9132         } else {
9133                 if (plane_config->tiling)
9134                         offset = I915_READ(DSPTILEOFF(pipe));
9135                 else
9136                         offset = I915_READ(DSPLINOFF(pipe));
9137         }
9138         plane_config->base = base;
9139
9140         val = I915_READ(PIPESRC(pipe));
9141         fb->width = ((val >> 16) & 0xfff) + 1;
9142         fb->height = ((val >> 0) & 0xfff) + 1;
9143
9144         val = I915_READ(DSPSTRIDE(pipe));
9145         fb->pitches[0] = val & 0xffffffc0;
9146
9147         aligned_height = intel_fb_align_height(dev, fb->height,
9148                                                fb->pixel_format,
9149                                                fb->modifier[0]);
9150
9151         plane_config->size = fb->pitches[0] * aligned_height;
9152
9153         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9154                       pipe_name(pipe), fb->width, fb->height,
9155                       fb->bits_per_pixel, base, fb->pitches[0],
9156                       plane_config->size);
9157
9158         plane_config->fb = intel_fb;
9159 }
9160
9161 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9162                                      struct intel_crtc_state *pipe_config)
9163 {
9164         struct drm_device *dev = crtc->base.dev;
9165         struct drm_i915_private *dev_priv = dev->dev_private;
9166         uint32_t tmp;
9167
9168         if (!intel_display_power_is_enabled(dev_priv,
9169                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9170                 return false;
9171
9172         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9173         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9174
9175         tmp = I915_READ(PIPECONF(crtc->pipe));
9176         if (!(tmp & PIPECONF_ENABLE))
9177                 return false;
9178
9179         switch (tmp & PIPECONF_BPC_MASK) {
9180         case PIPECONF_6BPC:
9181                 pipe_config->pipe_bpp = 18;
9182                 break;
9183         case PIPECONF_8BPC:
9184                 pipe_config->pipe_bpp = 24;
9185                 break;
9186         case PIPECONF_10BPC:
9187                 pipe_config->pipe_bpp = 30;
9188                 break;
9189         case PIPECONF_12BPC:
9190                 pipe_config->pipe_bpp = 36;
9191                 break;
9192         default:
9193                 break;
9194         }
9195
9196         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9197                 pipe_config->limited_color_range = true;
9198
9199         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9200                 struct intel_shared_dpll *pll;
9201
9202                 pipe_config->has_pch_encoder = true;
9203
9204                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9205                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9206                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9207
9208                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9209
9210                 if (HAS_PCH_IBX(dev_priv->dev)) {
9211                         pipe_config->shared_dpll =
9212                                 (enum intel_dpll_id) crtc->pipe;
9213                 } else {
9214                         tmp = I915_READ(PCH_DPLL_SEL);
9215                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9216                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9217                         else
9218                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9219                 }
9220
9221                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9222
9223                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9224                                            &pipe_config->dpll_hw_state));
9225
9226                 tmp = pipe_config->dpll_hw_state.dpll;
9227                 pipe_config->pixel_multiplier =
9228                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9229                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9230
9231                 ironlake_pch_clock_get(crtc, pipe_config);
9232         } else {
9233                 pipe_config->pixel_multiplier = 1;
9234         }
9235
9236         intel_get_pipe_timings(crtc, pipe_config);
9237
9238         ironlake_get_pfit_config(crtc, pipe_config);
9239
9240         return true;
9241 }
9242
9243 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9244 {
9245         struct drm_device *dev = dev_priv->dev;
9246         struct intel_crtc *crtc;
9247
9248         for_each_intel_crtc(dev, crtc)
9249                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9250                      pipe_name(crtc->pipe));
9251
9252         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9253         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9254         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9255         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9256         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9257         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9258              "CPU PWM1 enabled\n");
9259         if (IS_HASWELL(dev))
9260                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9261                      "CPU PWM2 enabled\n");
9262         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9263              "PCH PWM1 enabled\n");
9264         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9265              "Utility pin enabled\n");
9266         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9267
9268         /*
9269          * In theory we can still leave IRQs enabled, as long as only the HPD
9270          * interrupts remain enabled. We used to check for that, but since it's
9271          * gen-specific and since we only disable LCPLL after we fully disable
9272          * the interrupts, the check below should be enough.
9273          */
9274         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9275 }
9276
9277 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9278 {
9279         struct drm_device *dev = dev_priv->dev;
9280
9281         if (IS_HASWELL(dev))
9282                 return I915_READ(D_COMP_HSW);
9283         else
9284                 return I915_READ(D_COMP_BDW);
9285 }
9286
9287 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9288 {
9289         struct drm_device *dev = dev_priv->dev;
9290
9291         if (IS_HASWELL(dev)) {
9292                 mutex_lock(&dev_priv->rps.hw_lock);
9293                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9294                                             val))
9295                         DRM_ERROR("Failed to write to D_COMP\n");
9296                 mutex_unlock(&dev_priv->rps.hw_lock);
9297         } else {
9298                 I915_WRITE(D_COMP_BDW, val);
9299                 POSTING_READ(D_COMP_BDW);
9300         }
9301 }
9302
9303 /*
9304  * This function implements pieces of two sequences from BSpec:
9305  * - Sequence for display software to disable LCPLL
9306  * - Sequence for display software to allow package C8+
9307  * The steps implemented here are just the steps that actually touch the LCPLL
9308  * register. Callers should take care of disabling all the display engine
9309  * functions, doing the mode unset, fixing interrupts, etc.
9310  */
9311 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9312                               bool switch_to_fclk, bool allow_power_down)
9313 {
9314         uint32_t val;
9315
9316         assert_can_disable_lcpll(dev_priv);
9317
9318         val = I915_READ(LCPLL_CTL);
9319
9320         if (switch_to_fclk) {
9321                 val |= LCPLL_CD_SOURCE_FCLK;
9322                 I915_WRITE(LCPLL_CTL, val);
9323
9324                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9325                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9326                         DRM_ERROR("Switching to FCLK failed\n");
9327
9328                 val = I915_READ(LCPLL_CTL);
9329         }
9330
9331         val |= LCPLL_PLL_DISABLE;
9332         I915_WRITE(LCPLL_CTL, val);
9333         POSTING_READ(LCPLL_CTL);
9334
9335         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9336                 DRM_ERROR("LCPLL still locked\n");
9337
9338         val = hsw_read_dcomp(dev_priv);
9339         val |= D_COMP_COMP_DISABLE;
9340         hsw_write_dcomp(dev_priv, val);
9341         ndelay(100);
9342
9343         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9344                      1))
9345                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9346
9347         if (allow_power_down) {
9348                 val = I915_READ(LCPLL_CTL);
9349                 val |= LCPLL_POWER_DOWN_ALLOW;
9350                 I915_WRITE(LCPLL_CTL, val);
9351                 POSTING_READ(LCPLL_CTL);
9352         }
9353 }
9354
9355 /*
9356  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9357  * source.
9358  */
9359 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9360 {
9361         uint32_t val;
9362
9363         val = I915_READ(LCPLL_CTL);
9364
9365         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9366                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9367                 return;
9368
9369         /*
9370          * Make sure we're not on PC8 state before disabling PC8, otherwise
9371          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9372          */
9373         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9374
9375         if (val & LCPLL_POWER_DOWN_ALLOW) {
9376                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9377                 I915_WRITE(LCPLL_CTL, val);
9378                 POSTING_READ(LCPLL_CTL);
9379         }
9380
9381         val = hsw_read_dcomp(dev_priv);
9382         val |= D_COMP_COMP_FORCE;
9383         val &= ~D_COMP_COMP_DISABLE;
9384         hsw_write_dcomp(dev_priv, val);
9385
9386         val = I915_READ(LCPLL_CTL);
9387         val &= ~LCPLL_PLL_DISABLE;
9388         I915_WRITE(LCPLL_CTL, val);
9389
9390         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9391                 DRM_ERROR("LCPLL not locked yet\n");
9392
9393         if (val & LCPLL_CD_SOURCE_FCLK) {
9394                 val = I915_READ(LCPLL_CTL);
9395                 val &= ~LCPLL_CD_SOURCE_FCLK;
9396                 I915_WRITE(LCPLL_CTL, val);
9397
9398                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9399                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9400                         DRM_ERROR("Switching back to LCPLL failed\n");
9401         }
9402
9403         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9404         intel_update_cdclk(dev_priv->dev);
9405 }
9406
9407 /*
9408  * Package states C8 and deeper are really deep PC states that can only be
9409  * reached when all the devices on the system allow it, so even if the graphics
9410  * device allows PC8+, it doesn't mean the system will actually get to these
9411  * states. Our driver only allows PC8+ when going into runtime PM.
9412  *
9413  * The requirements for PC8+ are that all the outputs are disabled, the power
9414  * well is disabled and most interrupts are disabled, and these are also
9415  * requirements for runtime PM. When these conditions are met, we manually do
9416  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9417  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9418  * hang the machine.
9419  *
9420  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9421  * the state of some registers, so when we come back from PC8+ we need to
9422  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9423  * need to take care of the registers kept by RC6. Notice that this happens even
9424  * if we don't put the device in PCI D3 state (which is what currently happens
9425  * because of the runtime PM support).
9426  *
9427  * For more, read "Display Sequences for Package C8" on the hardware
9428  * documentation.
9429  */
9430 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9431 {
9432         struct drm_device *dev = dev_priv->dev;
9433         uint32_t val;
9434
9435         DRM_DEBUG_KMS("Enabling package C8+\n");
9436
9437         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9438                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9439                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9440                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9441         }
9442
9443         lpt_disable_clkout_dp(dev);
9444         hsw_disable_lcpll(dev_priv, true, true);
9445 }
9446
9447 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9448 {
9449         struct drm_device *dev = dev_priv->dev;
9450         uint32_t val;
9451
9452         DRM_DEBUG_KMS("Disabling package C8+\n");
9453
9454         hsw_restore_lcpll(dev_priv);
9455         lpt_init_pch_refclk(dev);
9456
9457         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9458                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9459                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9460                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9461         }
9462
9463         intel_prepare_ddi(dev);
9464 }
9465
9466 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9467 {
9468         struct drm_device *dev = old_state->dev;
9469         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9470
9471         broxton_set_cdclk(dev, req_cdclk);
9472 }
9473
9474 /* compute the max rate for new configuration */
9475 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9476 {
9477         struct intel_crtc *intel_crtc;
9478         struct intel_crtc_state *crtc_state;
9479         int max_pixel_rate = 0;
9480
9481         for_each_intel_crtc(state->dev, intel_crtc) {
9482                 int pixel_rate;
9483
9484                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9485                 if (IS_ERR(crtc_state))
9486                         return PTR_ERR(crtc_state);
9487
9488                 if (!crtc_state->base.enable)
9489                         continue;
9490
9491                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9492
9493                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9494                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9495                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9496
9497                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9498         }
9499
9500         return max_pixel_rate;
9501 }
9502
9503 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9504 {
9505         struct drm_i915_private *dev_priv = dev->dev_private;
9506         uint32_t val, data;
9507         int ret;
9508
9509         if (WARN((I915_READ(LCPLL_CTL) &
9510                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9511                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9512                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9513                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9514                  "trying to change cdclk frequency with cdclk not enabled\n"))
9515                 return;
9516
9517         mutex_lock(&dev_priv->rps.hw_lock);
9518         ret = sandybridge_pcode_write(dev_priv,
9519                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9520         mutex_unlock(&dev_priv->rps.hw_lock);
9521         if (ret) {
9522                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9523                 return;
9524         }
9525
9526         val = I915_READ(LCPLL_CTL);
9527         val |= LCPLL_CD_SOURCE_FCLK;
9528         I915_WRITE(LCPLL_CTL, val);
9529
9530         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9531                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9532                 DRM_ERROR("Switching to FCLK failed\n");
9533
9534         val = I915_READ(LCPLL_CTL);
9535         val &= ~LCPLL_CLK_FREQ_MASK;
9536
9537         switch (cdclk) {
9538         case 450000:
9539                 val |= LCPLL_CLK_FREQ_450;
9540                 data = 0;
9541                 break;
9542         case 540000:
9543                 val |= LCPLL_CLK_FREQ_54O_BDW;
9544                 data = 1;
9545                 break;
9546         case 337500:
9547                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9548                 data = 2;
9549                 break;
9550         case 675000:
9551                 val |= LCPLL_CLK_FREQ_675_BDW;
9552                 data = 3;
9553                 break;
9554         default:
9555                 WARN(1, "invalid cdclk frequency\n");
9556                 return;
9557         }
9558
9559         I915_WRITE(LCPLL_CTL, val);
9560
9561         val = I915_READ(LCPLL_CTL);
9562         val &= ~LCPLL_CD_SOURCE_FCLK;
9563         I915_WRITE(LCPLL_CTL, val);
9564
9565         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9566                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9567                 DRM_ERROR("Switching back to LCPLL failed\n");
9568
9569         mutex_lock(&dev_priv->rps.hw_lock);
9570         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9571         mutex_unlock(&dev_priv->rps.hw_lock);
9572
9573         intel_update_cdclk(dev);
9574
9575         WARN(cdclk != dev_priv->cdclk_freq,
9576              "cdclk requested %d kHz but got %d kHz\n",
9577              cdclk, dev_priv->cdclk_freq);
9578 }
9579
9580 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9581 {
9582         struct drm_i915_private *dev_priv = to_i915(state->dev);
9583         int max_pixclk = ilk_max_pixel_rate(state);
9584         int cdclk;
9585
9586         /*
9587          * FIXME should also account for plane ratio
9588          * once 64bpp pixel formats are supported.
9589          */
9590         if (max_pixclk > 540000)
9591                 cdclk = 675000;
9592         else if (max_pixclk > 450000)
9593                 cdclk = 540000;
9594         else if (max_pixclk > 337500)
9595                 cdclk = 450000;
9596         else
9597                 cdclk = 337500;
9598
9599         /*
9600          * FIXME move the cdclk caclulation to
9601          * compute_config() so we can fail gracegully.
9602          */
9603         if (cdclk > dev_priv->max_cdclk_freq) {
9604                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9605                           cdclk, dev_priv->max_cdclk_freq);
9606                 cdclk = dev_priv->max_cdclk_freq;
9607         }
9608
9609         to_intel_atomic_state(state)->cdclk = cdclk;
9610
9611         return 0;
9612 }
9613
9614 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9615 {
9616         struct drm_device *dev = old_state->dev;
9617         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9618
9619         broadwell_set_cdclk(dev, req_cdclk);
9620 }
9621
9622 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9623                                       struct intel_crtc_state *crtc_state)
9624 {
9625         if (!intel_ddi_pll_select(crtc, crtc_state))
9626                 return -EINVAL;
9627
9628         crtc->lowfreq_avail = false;
9629
9630         return 0;
9631 }
9632
9633 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9634                                 enum port port,
9635                                 struct intel_crtc_state *pipe_config)
9636 {
9637         switch (port) {
9638         case PORT_A:
9639                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9640                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9641                 break;
9642         case PORT_B:
9643                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9644                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9645                 break;
9646         case PORT_C:
9647                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9648                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9649                 break;
9650         default:
9651                 DRM_ERROR("Incorrect port type\n");
9652         }
9653 }
9654
9655 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9656                                 enum port port,
9657                                 struct intel_crtc_state *pipe_config)
9658 {
9659         u32 temp, dpll_ctl1;
9660
9661         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9662         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9663
9664         switch (pipe_config->ddi_pll_sel) {
9665         case SKL_DPLL0:
9666                 /*
9667                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9668                  * of the shared DPLL framework and thus needs to be read out
9669                  * separately
9670                  */
9671                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9672                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9673                 break;
9674         case SKL_DPLL1:
9675                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9676                 break;
9677         case SKL_DPLL2:
9678                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9679                 break;
9680         case SKL_DPLL3:
9681                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9682                 break;
9683         }
9684 }
9685
9686 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9687                                 enum port port,
9688                                 struct intel_crtc_state *pipe_config)
9689 {
9690         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9691
9692         switch (pipe_config->ddi_pll_sel) {
9693         case PORT_CLK_SEL_WRPLL1:
9694                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9695                 break;
9696         case PORT_CLK_SEL_WRPLL2:
9697                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9698                 break;
9699         }
9700 }
9701
9702 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9703                                        struct intel_crtc_state *pipe_config)
9704 {
9705         struct drm_device *dev = crtc->base.dev;
9706         struct drm_i915_private *dev_priv = dev->dev_private;
9707         struct intel_shared_dpll *pll;
9708         enum port port;
9709         uint32_t tmp;
9710
9711         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9712
9713         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9714
9715         if (IS_SKYLAKE(dev))
9716                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9717         else if (IS_BROXTON(dev))
9718                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9719         else
9720                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9721
9722         if (pipe_config->shared_dpll >= 0) {
9723                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9724
9725                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9726                                            &pipe_config->dpll_hw_state));
9727         }
9728
9729         /*
9730          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9731          * DDI E. So just check whether this pipe is wired to DDI E and whether
9732          * the PCH transcoder is on.
9733          */
9734         if (INTEL_INFO(dev)->gen < 9 &&
9735             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9736                 pipe_config->has_pch_encoder = true;
9737
9738                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9739                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9740                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9741
9742                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9743         }
9744 }
9745
9746 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9747                                     struct intel_crtc_state *pipe_config)
9748 {
9749         struct drm_device *dev = crtc->base.dev;
9750         struct drm_i915_private *dev_priv = dev->dev_private;
9751         enum intel_display_power_domain pfit_domain;
9752         uint32_t tmp;
9753
9754         if (!intel_display_power_is_enabled(dev_priv,
9755                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9756                 return false;
9757
9758         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9759         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9760
9761         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9762         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9763                 enum pipe trans_edp_pipe;
9764                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9765                 default:
9766                         WARN(1, "unknown pipe linked to edp transcoder\n");
9767                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9768                 case TRANS_DDI_EDP_INPUT_A_ON:
9769                         trans_edp_pipe = PIPE_A;
9770                         break;
9771                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9772                         trans_edp_pipe = PIPE_B;
9773                         break;
9774                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9775                         trans_edp_pipe = PIPE_C;
9776                         break;
9777                 }
9778
9779                 if (trans_edp_pipe == crtc->pipe)
9780                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9781         }
9782
9783         if (!intel_display_power_is_enabled(dev_priv,
9784                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9785                 return false;
9786
9787         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9788         if (!(tmp & PIPECONF_ENABLE))
9789                 return false;
9790
9791         haswell_get_ddi_port_state(crtc, pipe_config);
9792
9793         intel_get_pipe_timings(crtc, pipe_config);
9794
9795         if (INTEL_INFO(dev)->gen >= 9) {
9796                 skl_init_scalers(dev, crtc, pipe_config);
9797         }
9798
9799         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9800
9801         if (INTEL_INFO(dev)->gen >= 9) {
9802                 pipe_config->scaler_state.scaler_id = -1;
9803                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9804         }
9805
9806         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9807                 if (INTEL_INFO(dev)->gen == 9)
9808                         skylake_get_pfit_config(crtc, pipe_config);
9809                 else if (INTEL_INFO(dev)->gen < 9)
9810                         ironlake_get_pfit_config(crtc, pipe_config);
9811                 else
9812                         MISSING_CASE(INTEL_INFO(dev)->gen);
9813         }
9814
9815         if (IS_HASWELL(dev))
9816                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9817                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9818
9819         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9820                 pipe_config->pixel_multiplier =
9821                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9822         } else {
9823                 pipe_config->pixel_multiplier = 1;
9824         }
9825
9826         return true;
9827 }
9828
9829 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9830 {
9831         struct drm_device *dev = crtc->dev;
9832         struct drm_i915_private *dev_priv = dev->dev_private;
9833         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9834         uint32_t cntl = 0, size = 0;
9835
9836         if (base) {
9837                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9838                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9839                 unsigned int stride = roundup_pow_of_two(width) * 4;
9840
9841                 switch (stride) {
9842                 default:
9843                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9844                                   width, stride);
9845                         stride = 256;
9846                         /* fallthrough */
9847                 case 256:
9848                 case 512:
9849                 case 1024:
9850                 case 2048:
9851                         break;
9852                 }
9853
9854                 cntl |= CURSOR_ENABLE |
9855                         CURSOR_GAMMA_ENABLE |
9856                         CURSOR_FORMAT_ARGB |
9857                         CURSOR_STRIDE(stride);
9858
9859                 size = (height << 12) | width;
9860         }
9861
9862         if (intel_crtc->cursor_cntl != 0 &&
9863             (intel_crtc->cursor_base != base ||
9864              intel_crtc->cursor_size != size ||
9865              intel_crtc->cursor_cntl != cntl)) {
9866                 /* On these chipsets we can only modify the base/size/stride
9867                  * whilst the cursor is disabled.
9868                  */
9869                 I915_WRITE(_CURACNTR, 0);
9870                 POSTING_READ(_CURACNTR);
9871                 intel_crtc->cursor_cntl = 0;
9872         }
9873
9874         if (intel_crtc->cursor_base != base) {
9875                 I915_WRITE(_CURABASE, base);
9876                 intel_crtc->cursor_base = base;
9877         }
9878
9879         if (intel_crtc->cursor_size != size) {
9880                 I915_WRITE(CURSIZE, size);
9881                 intel_crtc->cursor_size = size;
9882         }
9883
9884         if (intel_crtc->cursor_cntl != cntl) {
9885                 I915_WRITE(_CURACNTR, cntl);
9886                 POSTING_READ(_CURACNTR);
9887                 intel_crtc->cursor_cntl = cntl;
9888         }
9889 }
9890
9891 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9892 {
9893         struct drm_device *dev = crtc->dev;
9894         struct drm_i915_private *dev_priv = dev->dev_private;
9895         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9896         int pipe = intel_crtc->pipe;
9897         uint32_t cntl;
9898
9899         cntl = 0;
9900         if (base) {
9901                 cntl = MCURSOR_GAMMA_ENABLE;
9902                 switch (intel_crtc->base.cursor->state->crtc_w) {
9903                         case 64:
9904                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9905                                 break;
9906                         case 128:
9907                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9908                                 break;
9909                         case 256:
9910                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9911                                 break;
9912                         default:
9913                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9914                                 return;
9915                 }
9916                 cntl |= pipe << 28; /* Connect to correct pipe */
9917
9918                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9919                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9920         }
9921
9922         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9923                 cntl |= CURSOR_ROTATE_180;
9924
9925         if (intel_crtc->cursor_cntl != cntl) {
9926                 I915_WRITE(CURCNTR(pipe), cntl);
9927                 POSTING_READ(CURCNTR(pipe));
9928                 intel_crtc->cursor_cntl = cntl;
9929         }
9930
9931         /* and commit changes on next vblank */
9932         I915_WRITE(CURBASE(pipe), base);
9933         POSTING_READ(CURBASE(pipe));
9934
9935         intel_crtc->cursor_base = base;
9936 }
9937
9938 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9939 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9940                                      bool on)
9941 {
9942         struct drm_device *dev = crtc->dev;
9943         struct drm_i915_private *dev_priv = dev->dev_private;
9944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9945         int pipe = intel_crtc->pipe;
9946         int x = crtc->cursor_x;
9947         int y = crtc->cursor_y;
9948         u32 base = 0, pos = 0;
9949
9950         if (on)
9951                 base = intel_crtc->cursor_addr;
9952
9953         if (x >= intel_crtc->config->pipe_src_w)
9954                 base = 0;
9955
9956         if (y >= intel_crtc->config->pipe_src_h)
9957                 base = 0;
9958
9959         if (x < 0) {
9960                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9961                         base = 0;
9962
9963                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9964                 x = -x;
9965         }
9966         pos |= x << CURSOR_X_SHIFT;
9967
9968         if (y < 0) {
9969                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9970                         base = 0;
9971
9972                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9973                 y = -y;
9974         }
9975         pos |= y << CURSOR_Y_SHIFT;
9976
9977         if (base == 0 && intel_crtc->cursor_base == 0)
9978                 return;
9979
9980         I915_WRITE(CURPOS(pipe), pos);
9981
9982         /* ILK+ do this automagically */
9983         if (HAS_GMCH_DISPLAY(dev) &&
9984             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9985                 base += (intel_crtc->base.cursor->state->crtc_h *
9986                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9987         }
9988
9989         if (IS_845G(dev) || IS_I865G(dev))
9990                 i845_update_cursor(crtc, base);
9991         else
9992                 i9xx_update_cursor(crtc, base);
9993 }
9994
9995 static bool cursor_size_ok(struct drm_device *dev,
9996                            uint32_t width, uint32_t height)
9997 {
9998         if (width == 0 || height == 0)
9999                 return false;
10000
10001         /*
10002          * 845g/865g are special in that they are only limited by
10003          * the width of their cursors, the height is arbitrary up to
10004          * the precision of the register. Everything else requires
10005          * square cursors, limited to a few power-of-two sizes.
10006          */
10007         if (IS_845G(dev) || IS_I865G(dev)) {
10008                 if ((width & 63) != 0)
10009                         return false;
10010
10011                 if (width > (IS_845G(dev) ? 64 : 512))
10012                         return false;
10013
10014                 if (height > 1023)
10015                         return false;
10016         } else {
10017                 switch (width | height) {
10018                 case 256:
10019                 case 128:
10020                         if (IS_GEN2(dev))
10021                                 return false;
10022                 case 64:
10023                         break;
10024                 default:
10025                         return false;
10026                 }
10027         }
10028
10029         return true;
10030 }
10031
10032 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10033                                  u16 *blue, uint32_t start, uint32_t size)
10034 {
10035         int end = (start + size > 256) ? 256 : start + size, i;
10036         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10037
10038         for (i = start; i < end; i++) {
10039                 intel_crtc->lut_r[i] = red[i] >> 8;
10040                 intel_crtc->lut_g[i] = green[i] >> 8;
10041                 intel_crtc->lut_b[i] = blue[i] >> 8;
10042         }
10043
10044         intel_crtc_load_lut(crtc);
10045 }
10046
10047 /* VESA 640x480x72Hz mode to set on the pipe */
10048 static struct drm_display_mode load_detect_mode = {
10049         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10050                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10051 };
10052
10053 struct drm_framebuffer *
10054 __intel_framebuffer_create(struct drm_device *dev,
10055                            struct drm_mode_fb_cmd2 *mode_cmd,
10056                            struct drm_i915_gem_object *obj)
10057 {
10058         struct intel_framebuffer *intel_fb;
10059         int ret;
10060
10061         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10062         if (!intel_fb) {
10063                 drm_gem_object_unreference(&obj->base);
10064                 return ERR_PTR(-ENOMEM);
10065         }
10066
10067         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10068         if (ret)
10069                 goto err;
10070
10071         return &intel_fb->base;
10072 err:
10073         drm_gem_object_unreference(&obj->base);
10074         kfree(intel_fb);
10075
10076         return ERR_PTR(ret);
10077 }
10078
10079 static struct drm_framebuffer *
10080 intel_framebuffer_create(struct drm_device *dev,
10081                          struct drm_mode_fb_cmd2 *mode_cmd,
10082                          struct drm_i915_gem_object *obj)
10083 {
10084         struct drm_framebuffer *fb;
10085         int ret;
10086
10087         ret = i915_mutex_lock_interruptible(dev);
10088         if (ret)
10089                 return ERR_PTR(ret);
10090         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10091         mutex_unlock(&dev->struct_mutex);
10092
10093         return fb;
10094 }
10095
10096 static u32
10097 intel_framebuffer_pitch_for_width(int width, int bpp)
10098 {
10099         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10100         return ALIGN(pitch, 64);
10101 }
10102
10103 static u32
10104 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10105 {
10106         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10107         return PAGE_ALIGN(pitch * mode->vdisplay);
10108 }
10109
10110 static struct drm_framebuffer *
10111 intel_framebuffer_create_for_mode(struct drm_device *dev,
10112                                   struct drm_display_mode *mode,
10113                                   int depth, int bpp)
10114 {
10115         struct drm_i915_gem_object *obj;
10116         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10117
10118         obj = i915_gem_alloc_object(dev,
10119                                     intel_framebuffer_size_for_mode(mode, bpp));
10120         if (obj == NULL)
10121                 return ERR_PTR(-ENOMEM);
10122
10123         mode_cmd.width = mode->hdisplay;
10124         mode_cmd.height = mode->vdisplay;
10125         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10126                                                                 bpp);
10127         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10128
10129         return intel_framebuffer_create(dev, &mode_cmd, obj);
10130 }
10131
10132 static struct drm_framebuffer *
10133 mode_fits_in_fbdev(struct drm_device *dev,
10134                    struct drm_display_mode *mode)
10135 {
10136 #ifdef CONFIG_DRM_FBDEV_EMULATION
10137         struct drm_i915_private *dev_priv = dev->dev_private;
10138         struct drm_i915_gem_object *obj;
10139         struct drm_framebuffer *fb;
10140
10141         if (!dev_priv->fbdev)
10142                 return NULL;
10143
10144         if (!dev_priv->fbdev->fb)
10145                 return NULL;
10146
10147         obj = dev_priv->fbdev->fb->obj;
10148         BUG_ON(!obj);
10149
10150         fb = &dev_priv->fbdev->fb->base;
10151         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10152                                                                fb->bits_per_pixel))
10153                 return NULL;
10154
10155         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10156                 return NULL;
10157
10158         return fb;
10159 #else
10160         return NULL;
10161 #endif
10162 }
10163
10164 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10165                                            struct drm_crtc *crtc,
10166                                            struct drm_display_mode *mode,
10167                                            struct drm_framebuffer *fb,
10168                                            int x, int y)
10169 {
10170         struct drm_plane_state *plane_state;
10171         int hdisplay, vdisplay;
10172         int ret;
10173
10174         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10175         if (IS_ERR(plane_state))
10176                 return PTR_ERR(plane_state);
10177
10178         if (mode)
10179                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10180         else
10181                 hdisplay = vdisplay = 0;
10182
10183         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10184         if (ret)
10185                 return ret;
10186         drm_atomic_set_fb_for_plane(plane_state, fb);
10187         plane_state->crtc_x = 0;
10188         plane_state->crtc_y = 0;
10189         plane_state->crtc_w = hdisplay;
10190         plane_state->crtc_h = vdisplay;
10191         plane_state->src_x = x << 16;
10192         plane_state->src_y = y << 16;
10193         plane_state->src_w = hdisplay << 16;
10194         plane_state->src_h = vdisplay << 16;
10195
10196         return 0;
10197 }
10198
10199 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10200                                 struct drm_display_mode *mode,
10201                                 struct intel_load_detect_pipe *old,
10202                                 struct drm_modeset_acquire_ctx *ctx)
10203 {
10204         struct intel_crtc *intel_crtc;
10205         struct intel_encoder *intel_encoder =
10206                 intel_attached_encoder(connector);
10207         struct drm_crtc *possible_crtc;
10208         struct drm_encoder *encoder = &intel_encoder->base;
10209         struct drm_crtc *crtc = NULL;
10210         struct drm_device *dev = encoder->dev;
10211         struct drm_framebuffer *fb;
10212         struct drm_mode_config *config = &dev->mode_config;
10213         struct drm_atomic_state *state = NULL;
10214         struct drm_connector_state *connector_state;
10215         struct intel_crtc_state *crtc_state;
10216         int ret, i = -1;
10217
10218         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10219                       connector->base.id, connector->name,
10220                       encoder->base.id, encoder->name);
10221
10222 retry:
10223         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10224         if (ret)
10225                 goto fail;
10226
10227         /*
10228          * Algorithm gets a little messy:
10229          *
10230          *   - if the connector already has an assigned crtc, use it (but make
10231          *     sure it's on first)
10232          *
10233          *   - try to find the first unused crtc that can drive this connector,
10234          *     and use that if we find one
10235          */
10236
10237         /* See if we already have a CRTC for this connector */
10238         if (encoder->crtc) {
10239                 crtc = encoder->crtc;
10240
10241                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10242                 if (ret)
10243                         goto fail;
10244                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10245                 if (ret)
10246                         goto fail;
10247
10248                 old->dpms_mode = connector->dpms;
10249                 old->load_detect_temp = false;
10250
10251                 /* Make sure the crtc and connector are running */
10252                 if (connector->dpms != DRM_MODE_DPMS_ON)
10253                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10254
10255                 return true;
10256         }
10257
10258         /* Find an unused one (if possible) */
10259         for_each_crtc(dev, possible_crtc) {
10260                 i++;
10261                 if (!(encoder->possible_crtcs & (1 << i)))
10262                         continue;
10263                 if (possible_crtc->state->enable)
10264                         continue;
10265
10266                 crtc = possible_crtc;
10267                 break;
10268         }
10269
10270         /*
10271          * If we didn't find an unused CRTC, don't use any.
10272          */
10273         if (!crtc) {
10274                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10275                 goto fail;
10276         }
10277
10278         ret = drm_modeset_lock(&crtc->mutex, ctx);
10279         if (ret)
10280                 goto fail;
10281         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10282         if (ret)
10283                 goto fail;
10284
10285         intel_crtc = to_intel_crtc(crtc);
10286         old->dpms_mode = connector->dpms;
10287         old->load_detect_temp = true;
10288         old->release_fb = NULL;
10289
10290         state = drm_atomic_state_alloc(dev);
10291         if (!state)
10292                 return false;
10293
10294         state->acquire_ctx = ctx;
10295
10296         connector_state = drm_atomic_get_connector_state(state, connector);
10297         if (IS_ERR(connector_state)) {
10298                 ret = PTR_ERR(connector_state);
10299                 goto fail;
10300         }
10301
10302         connector_state->crtc = crtc;
10303         connector_state->best_encoder = &intel_encoder->base;
10304
10305         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10306         if (IS_ERR(crtc_state)) {
10307                 ret = PTR_ERR(crtc_state);
10308                 goto fail;
10309         }
10310
10311         crtc_state->base.active = crtc_state->base.enable = true;
10312
10313         if (!mode)
10314                 mode = &load_detect_mode;
10315
10316         /* We need a framebuffer large enough to accommodate all accesses
10317          * that the plane may generate whilst we perform load detection.
10318          * We can not rely on the fbcon either being present (we get called
10319          * during its initialisation to detect all boot displays, or it may
10320          * not even exist) or that it is large enough to satisfy the
10321          * requested mode.
10322          */
10323         fb = mode_fits_in_fbdev(dev, mode);
10324         if (fb == NULL) {
10325                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10326                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10327                 old->release_fb = fb;
10328         } else
10329                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10330         if (IS_ERR(fb)) {
10331                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10332                 goto fail;
10333         }
10334
10335         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10336         if (ret)
10337                 goto fail;
10338
10339         drm_mode_copy(&crtc_state->base.mode, mode);
10340
10341         if (drm_atomic_commit(state)) {
10342                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10343                 if (old->release_fb)
10344                         old->release_fb->funcs->destroy(old->release_fb);
10345                 goto fail;
10346         }
10347         crtc->primary->crtc = crtc;
10348
10349         /* let the connector get through one full cycle before testing */
10350         intel_wait_for_vblank(dev, intel_crtc->pipe);
10351         return true;
10352
10353 fail:
10354         drm_atomic_state_free(state);
10355         state = NULL;
10356
10357         if (ret == -EDEADLK) {
10358                 drm_modeset_backoff(ctx);
10359                 goto retry;
10360         }
10361
10362         return false;
10363 }
10364
10365 void intel_release_load_detect_pipe(struct drm_connector *connector,
10366                                     struct intel_load_detect_pipe *old,
10367                                     struct drm_modeset_acquire_ctx *ctx)
10368 {
10369         struct drm_device *dev = connector->dev;
10370         struct intel_encoder *intel_encoder =
10371                 intel_attached_encoder(connector);
10372         struct drm_encoder *encoder = &intel_encoder->base;
10373         struct drm_crtc *crtc = encoder->crtc;
10374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10375         struct drm_atomic_state *state;
10376         struct drm_connector_state *connector_state;
10377         struct intel_crtc_state *crtc_state;
10378         int ret;
10379
10380         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10381                       connector->base.id, connector->name,
10382                       encoder->base.id, encoder->name);
10383
10384         if (old->load_detect_temp) {
10385                 state = drm_atomic_state_alloc(dev);
10386                 if (!state)
10387                         goto fail;
10388
10389                 state->acquire_ctx = ctx;
10390
10391                 connector_state = drm_atomic_get_connector_state(state, connector);
10392                 if (IS_ERR(connector_state))
10393                         goto fail;
10394
10395                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10396                 if (IS_ERR(crtc_state))
10397                         goto fail;
10398
10399                 connector_state->best_encoder = NULL;
10400                 connector_state->crtc = NULL;
10401
10402                 crtc_state->base.enable = crtc_state->base.active = false;
10403
10404                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10405                                                       0, 0);
10406                 if (ret)
10407                         goto fail;
10408
10409                 ret = drm_atomic_commit(state);
10410                 if (ret)
10411                         goto fail;
10412
10413                 if (old->release_fb) {
10414                         drm_framebuffer_unregister_private(old->release_fb);
10415                         drm_framebuffer_unreference(old->release_fb);
10416                 }
10417
10418                 return;
10419         }
10420
10421         /* Switch crtc and encoder back off if necessary */
10422         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10423                 connector->funcs->dpms(connector, old->dpms_mode);
10424
10425         return;
10426 fail:
10427         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10428         drm_atomic_state_free(state);
10429 }
10430
10431 static int i9xx_pll_refclk(struct drm_device *dev,
10432                            const struct intel_crtc_state *pipe_config)
10433 {
10434         struct drm_i915_private *dev_priv = dev->dev_private;
10435         u32 dpll = pipe_config->dpll_hw_state.dpll;
10436
10437         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10438                 return dev_priv->vbt.lvds_ssc_freq;
10439         else if (HAS_PCH_SPLIT(dev))
10440                 return 120000;
10441         else if (!IS_GEN2(dev))
10442                 return 96000;
10443         else
10444                 return 48000;
10445 }
10446
10447 /* Returns the clock of the currently programmed mode of the given pipe. */
10448 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10449                                 struct intel_crtc_state *pipe_config)
10450 {
10451         struct drm_device *dev = crtc->base.dev;
10452         struct drm_i915_private *dev_priv = dev->dev_private;
10453         int pipe = pipe_config->cpu_transcoder;
10454         u32 dpll = pipe_config->dpll_hw_state.dpll;
10455         u32 fp;
10456         intel_clock_t clock;
10457         int port_clock;
10458         int refclk = i9xx_pll_refclk(dev, pipe_config);
10459
10460         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10461                 fp = pipe_config->dpll_hw_state.fp0;
10462         else
10463                 fp = pipe_config->dpll_hw_state.fp1;
10464
10465         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10466         if (IS_PINEVIEW(dev)) {
10467                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10468                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10469         } else {
10470                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10471                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10472         }
10473
10474         if (!IS_GEN2(dev)) {
10475                 if (IS_PINEVIEW(dev))
10476                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10477                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10478                 else
10479                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10480                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10481
10482                 switch (dpll & DPLL_MODE_MASK) {
10483                 case DPLLB_MODE_DAC_SERIAL:
10484                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10485                                 5 : 10;
10486                         break;
10487                 case DPLLB_MODE_LVDS:
10488                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10489                                 7 : 14;
10490                         break;
10491                 default:
10492                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10493                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10494                         return;
10495                 }
10496
10497                 if (IS_PINEVIEW(dev))
10498                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10499                 else
10500                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10501         } else {
10502                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10503                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10504
10505                 if (is_lvds) {
10506                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10507                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10508
10509                         if (lvds & LVDS_CLKB_POWER_UP)
10510                                 clock.p2 = 7;
10511                         else
10512                                 clock.p2 = 14;
10513                 } else {
10514                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10515                                 clock.p1 = 2;
10516                         else {
10517                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10518                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10519                         }
10520                         if (dpll & PLL_P2_DIVIDE_BY_4)
10521                                 clock.p2 = 4;
10522                         else
10523                                 clock.p2 = 2;
10524                 }
10525
10526                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10527         }
10528
10529         /*
10530          * This value includes pixel_multiplier. We will use
10531          * port_clock to compute adjusted_mode.crtc_clock in the
10532          * encoder's get_config() function.
10533          */
10534         pipe_config->port_clock = port_clock;
10535 }
10536
10537 int intel_dotclock_calculate(int link_freq,
10538                              const struct intel_link_m_n *m_n)
10539 {
10540         /*
10541          * The calculation for the data clock is:
10542          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10543          * But we want to avoid losing precison if possible, so:
10544          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10545          *
10546          * and the link clock is simpler:
10547          * link_clock = (m * link_clock) / n
10548          */
10549
10550         if (!m_n->link_n)
10551                 return 0;
10552
10553         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10554 }
10555
10556 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10557                                    struct intel_crtc_state *pipe_config)
10558 {
10559         struct drm_device *dev = crtc->base.dev;
10560
10561         /* read out port_clock from the DPLL */
10562         i9xx_crtc_clock_get(crtc, pipe_config);
10563
10564         /*
10565          * This value does not include pixel_multiplier.
10566          * We will check that port_clock and adjusted_mode.crtc_clock
10567          * agree once we know their relationship in the encoder's
10568          * get_config() function.
10569          */
10570         pipe_config->base.adjusted_mode.crtc_clock =
10571                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10572                                          &pipe_config->fdi_m_n);
10573 }
10574
10575 /** Returns the currently programmed mode of the given pipe. */
10576 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10577                                              struct drm_crtc *crtc)
10578 {
10579         struct drm_i915_private *dev_priv = dev->dev_private;
10580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10581         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10582         struct drm_display_mode *mode;
10583         struct intel_crtc_state pipe_config;
10584         int htot = I915_READ(HTOTAL(cpu_transcoder));
10585         int hsync = I915_READ(HSYNC(cpu_transcoder));
10586         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10587         int vsync = I915_READ(VSYNC(cpu_transcoder));
10588         enum pipe pipe = intel_crtc->pipe;
10589
10590         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10591         if (!mode)
10592                 return NULL;
10593
10594         /*
10595          * Construct a pipe_config sufficient for getting the clock info
10596          * back out of crtc_clock_get.
10597          *
10598          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10599          * to use a real value here instead.
10600          */
10601         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10602         pipe_config.pixel_multiplier = 1;
10603         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10604         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10605         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10606         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10607
10608         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10609         mode->hdisplay = (htot & 0xffff) + 1;
10610         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10611         mode->hsync_start = (hsync & 0xffff) + 1;
10612         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10613         mode->vdisplay = (vtot & 0xffff) + 1;
10614         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10615         mode->vsync_start = (vsync & 0xffff) + 1;
10616         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10617
10618         drm_mode_set_name(mode);
10619
10620         return mode;
10621 }
10622
10623 void intel_mark_busy(struct drm_device *dev)
10624 {
10625         struct drm_i915_private *dev_priv = dev->dev_private;
10626
10627         if (dev_priv->mm.busy)
10628                 return;
10629
10630         intel_runtime_pm_get(dev_priv);
10631         i915_update_gfx_val(dev_priv);
10632         if (INTEL_INFO(dev)->gen >= 6)
10633                 gen6_rps_busy(dev_priv);
10634         dev_priv->mm.busy = true;
10635 }
10636
10637 void intel_mark_idle(struct drm_device *dev)
10638 {
10639         struct drm_i915_private *dev_priv = dev->dev_private;
10640
10641         if (!dev_priv->mm.busy)
10642                 return;
10643
10644         dev_priv->mm.busy = false;
10645
10646         if (INTEL_INFO(dev)->gen >= 6)
10647                 gen6_rps_idle(dev->dev_private);
10648
10649         intel_runtime_pm_put(dev_priv);
10650 }
10651
10652 static void intel_crtc_destroy(struct drm_crtc *crtc)
10653 {
10654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10655         struct drm_device *dev = crtc->dev;
10656         struct intel_unpin_work *work;
10657
10658         spin_lock_irq(&dev->event_lock);
10659         work = intel_crtc->unpin_work;
10660         intel_crtc->unpin_work = NULL;
10661         spin_unlock_irq(&dev->event_lock);
10662
10663         if (work) {
10664                 cancel_work_sync(&work->work);
10665                 kfree(work);
10666         }
10667
10668         drm_crtc_cleanup(crtc);
10669
10670         kfree(intel_crtc);
10671 }
10672
10673 static void intel_unpin_work_fn(struct work_struct *__work)
10674 {
10675         struct intel_unpin_work *work =
10676                 container_of(__work, struct intel_unpin_work, work);
10677         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10678         struct drm_device *dev = crtc->base.dev;
10679         struct drm_plane *primary = crtc->base.primary;
10680
10681         mutex_lock(&dev->struct_mutex);
10682         intel_unpin_fb_obj(work->old_fb, primary->state);
10683         drm_gem_object_unreference(&work->pending_flip_obj->base);
10684
10685         if (work->flip_queued_req)
10686                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10687         mutex_unlock(&dev->struct_mutex);
10688
10689         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10690         drm_framebuffer_unreference(work->old_fb);
10691
10692         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10693         atomic_dec(&crtc->unpin_work_count);
10694
10695         kfree(work);
10696 }
10697
10698 static void do_intel_finish_page_flip(struct drm_device *dev,
10699                                       struct drm_crtc *crtc)
10700 {
10701         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10702         struct intel_unpin_work *work;
10703         unsigned long flags;
10704
10705         /* Ignore early vblank irqs */
10706         if (intel_crtc == NULL)
10707                 return;
10708
10709         /*
10710          * This is called both by irq handlers and the reset code (to complete
10711          * lost pageflips) so needs the full irqsave spinlocks.
10712          */
10713         spin_lock_irqsave(&dev->event_lock, flags);
10714         work = intel_crtc->unpin_work;
10715
10716         /* Ensure we don't miss a work->pending update ... */
10717         smp_rmb();
10718
10719         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10720                 spin_unlock_irqrestore(&dev->event_lock, flags);
10721                 return;
10722         }
10723
10724         page_flip_completed(intel_crtc);
10725
10726         spin_unlock_irqrestore(&dev->event_lock, flags);
10727 }
10728
10729 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10730 {
10731         struct drm_i915_private *dev_priv = dev->dev_private;
10732         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10733
10734         do_intel_finish_page_flip(dev, crtc);
10735 }
10736
10737 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10738 {
10739         struct drm_i915_private *dev_priv = dev->dev_private;
10740         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10741
10742         do_intel_finish_page_flip(dev, crtc);
10743 }
10744
10745 /* Is 'a' after or equal to 'b'? */
10746 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10747 {
10748         return !((a - b) & 0x80000000);
10749 }
10750
10751 static bool page_flip_finished(struct intel_crtc *crtc)
10752 {
10753         struct drm_device *dev = crtc->base.dev;
10754         struct drm_i915_private *dev_priv = dev->dev_private;
10755
10756         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10757             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10758                 return true;
10759
10760         /*
10761          * The relevant registers doen't exist on pre-ctg.
10762          * As the flip done interrupt doesn't trigger for mmio
10763          * flips on gmch platforms, a flip count check isn't
10764          * really needed there. But since ctg has the registers,
10765          * include it in the check anyway.
10766          */
10767         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10768                 return true;
10769
10770         /*
10771          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10772          * used the same base address. In that case the mmio flip might
10773          * have completed, but the CS hasn't even executed the flip yet.
10774          *
10775          * A flip count check isn't enough as the CS might have updated
10776          * the base address just after start of vblank, but before we
10777          * managed to process the interrupt. This means we'd complete the
10778          * CS flip too soon.
10779          *
10780          * Combining both checks should get us a good enough result. It may
10781          * still happen that the CS flip has been executed, but has not
10782          * yet actually completed. But in case the base address is the same
10783          * anyway, we don't really care.
10784          */
10785         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10786                 crtc->unpin_work->gtt_offset &&
10787                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10788                                     crtc->unpin_work->flip_count);
10789 }
10790
10791 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10792 {
10793         struct drm_i915_private *dev_priv = dev->dev_private;
10794         struct intel_crtc *intel_crtc =
10795                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10796         unsigned long flags;
10797
10798
10799         /*
10800          * This is called both by irq handlers and the reset code (to complete
10801          * lost pageflips) so needs the full irqsave spinlocks.
10802          *
10803          * NB: An MMIO update of the plane base pointer will also
10804          * generate a page-flip completion irq, i.e. every modeset
10805          * is also accompanied by a spurious intel_prepare_page_flip().
10806          */
10807         spin_lock_irqsave(&dev->event_lock, flags);
10808         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10809                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10810         spin_unlock_irqrestore(&dev->event_lock, flags);
10811 }
10812
10813 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10814 {
10815         /* Ensure that the work item is consistent when activating it ... */
10816         smp_wmb();
10817         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10818         /* and that it is marked active as soon as the irq could fire. */
10819         smp_wmb();
10820 }
10821
10822 static int intel_gen2_queue_flip(struct drm_device *dev,
10823                                  struct drm_crtc *crtc,
10824                                  struct drm_framebuffer *fb,
10825                                  struct drm_i915_gem_object *obj,
10826                                  struct drm_i915_gem_request *req,
10827                                  uint32_t flags)
10828 {
10829         struct intel_engine_cs *ring = req->ring;
10830         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10831         u32 flip_mask;
10832         int ret;
10833
10834         ret = intel_ring_begin(req, 6);
10835         if (ret)
10836                 return ret;
10837
10838         /* Can't queue multiple flips, so wait for the previous
10839          * one to finish before executing the next.
10840          */
10841         if (intel_crtc->plane)
10842                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10843         else
10844                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10845         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10846         intel_ring_emit(ring, MI_NOOP);
10847         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10848                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10849         intel_ring_emit(ring, fb->pitches[0]);
10850         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10851         intel_ring_emit(ring, 0); /* aux display base address, unused */
10852
10853         intel_mark_page_flip_active(intel_crtc);
10854         return 0;
10855 }
10856
10857 static int intel_gen3_queue_flip(struct drm_device *dev,
10858                                  struct drm_crtc *crtc,
10859                                  struct drm_framebuffer *fb,
10860                                  struct drm_i915_gem_object *obj,
10861                                  struct drm_i915_gem_request *req,
10862                                  uint32_t flags)
10863 {
10864         struct intel_engine_cs *ring = req->ring;
10865         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10866         u32 flip_mask;
10867         int ret;
10868
10869         ret = intel_ring_begin(req, 6);
10870         if (ret)
10871                 return ret;
10872
10873         if (intel_crtc->plane)
10874                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10875         else
10876                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10877         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10878         intel_ring_emit(ring, MI_NOOP);
10879         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10880                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10881         intel_ring_emit(ring, fb->pitches[0]);
10882         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10883         intel_ring_emit(ring, MI_NOOP);
10884
10885         intel_mark_page_flip_active(intel_crtc);
10886         return 0;
10887 }
10888
10889 static int intel_gen4_queue_flip(struct drm_device *dev,
10890                                  struct drm_crtc *crtc,
10891                                  struct drm_framebuffer *fb,
10892                                  struct drm_i915_gem_object *obj,
10893                                  struct drm_i915_gem_request *req,
10894                                  uint32_t flags)
10895 {
10896         struct intel_engine_cs *ring = req->ring;
10897         struct drm_i915_private *dev_priv = dev->dev_private;
10898         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10899         uint32_t pf, pipesrc;
10900         int ret;
10901
10902         ret = intel_ring_begin(req, 4);
10903         if (ret)
10904                 return ret;
10905
10906         /* i965+ uses the linear or tiled offsets from the
10907          * Display Registers (which do not change across a page-flip)
10908          * so we need only reprogram the base address.
10909          */
10910         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10911                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10912         intel_ring_emit(ring, fb->pitches[0]);
10913         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10914                         obj->tiling_mode);
10915
10916         /* XXX Enabling the panel-fitter across page-flip is so far
10917          * untested on non-native modes, so ignore it for now.
10918          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10919          */
10920         pf = 0;
10921         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10922         intel_ring_emit(ring, pf | pipesrc);
10923
10924         intel_mark_page_flip_active(intel_crtc);
10925         return 0;
10926 }
10927
10928 static int intel_gen6_queue_flip(struct drm_device *dev,
10929                                  struct drm_crtc *crtc,
10930                                  struct drm_framebuffer *fb,
10931                                  struct drm_i915_gem_object *obj,
10932                                  struct drm_i915_gem_request *req,
10933                                  uint32_t flags)
10934 {
10935         struct intel_engine_cs *ring = req->ring;
10936         struct drm_i915_private *dev_priv = dev->dev_private;
10937         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10938         uint32_t pf, pipesrc;
10939         int ret;
10940
10941         ret = intel_ring_begin(req, 4);
10942         if (ret)
10943                 return ret;
10944
10945         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10946                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10947         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10948         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10949
10950         /* Contrary to the suggestions in the documentation,
10951          * "Enable Panel Fitter" does not seem to be required when page
10952          * flipping with a non-native mode, and worse causes a normal
10953          * modeset to fail.
10954          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10955          */
10956         pf = 0;
10957         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10958         intel_ring_emit(ring, pf | pipesrc);
10959
10960         intel_mark_page_flip_active(intel_crtc);
10961         return 0;
10962 }
10963
10964 static int intel_gen7_queue_flip(struct drm_device *dev,
10965                                  struct drm_crtc *crtc,
10966                                  struct drm_framebuffer *fb,
10967                                  struct drm_i915_gem_object *obj,
10968                                  struct drm_i915_gem_request *req,
10969                                  uint32_t flags)
10970 {
10971         struct intel_engine_cs *ring = req->ring;
10972         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10973         uint32_t plane_bit = 0;
10974         int len, ret;
10975
10976         switch (intel_crtc->plane) {
10977         case PLANE_A:
10978                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10979                 break;
10980         case PLANE_B:
10981                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10982                 break;
10983         case PLANE_C:
10984                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10985                 break;
10986         default:
10987                 WARN_ONCE(1, "unknown plane in flip command\n");
10988                 return -ENODEV;
10989         }
10990
10991         len = 4;
10992         if (ring->id == RCS) {
10993                 len += 6;
10994                 /*
10995                  * On Gen 8, SRM is now taking an extra dword to accommodate
10996                  * 48bits addresses, and we need a NOOP for the batch size to
10997                  * stay even.
10998                  */
10999                 if (IS_GEN8(dev))
11000                         len += 2;
11001         }
11002
11003         /*
11004          * BSpec MI_DISPLAY_FLIP for IVB:
11005          * "The full packet must be contained within the same cache line."
11006          *
11007          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11008          * cacheline, if we ever start emitting more commands before
11009          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11010          * then do the cacheline alignment, and finally emit the
11011          * MI_DISPLAY_FLIP.
11012          */
11013         ret = intel_ring_cacheline_align(req);
11014         if (ret)
11015                 return ret;
11016
11017         ret = intel_ring_begin(req, len);
11018         if (ret)
11019                 return ret;
11020
11021         /* Unmask the flip-done completion message. Note that the bspec says that
11022          * we should do this for both the BCS and RCS, and that we must not unmask
11023          * more than one flip event at any time (or ensure that one flip message
11024          * can be sent by waiting for flip-done prior to queueing new flips).
11025          * Experimentation says that BCS works despite DERRMR masking all
11026          * flip-done completion events and that unmasking all planes at once
11027          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11028          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11029          */
11030         if (ring->id == RCS) {
11031                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11032                 intel_ring_emit(ring, DERRMR);
11033                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11034                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11035                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11036                 if (IS_GEN8(dev))
11037                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11038                                               MI_SRM_LRM_GLOBAL_GTT);
11039                 else
11040                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11041                                               MI_SRM_LRM_GLOBAL_GTT);
11042                 intel_ring_emit(ring, DERRMR);
11043                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11044                 if (IS_GEN8(dev)) {
11045                         intel_ring_emit(ring, 0);
11046                         intel_ring_emit(ring, MI_NOOP);
11047                 }
11048         }
11049
11050         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11051         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11052         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11053         intel_ring_emit(ring, (MI_NOOP));
11054
11055         intel_mark_page_flip_active(intel_crtc);
11056         return 0;
11057 }
11058
11059 static bool use_mmio_flip(struct intel_engine_cs *ring,
11060                           struct drm_i915_gem_object *obj)
11061 {
11062         /*
11063          * This is not being used for older platforms, because
11064          * non-availability of flip done interrupt forces us to use
11065          * CS flips. Older platforms derive flip done using some clever
11066          * tricks involving the flip_pending status bits and vblank irqs.
11067          * So using MMIO flips there would disrupt this mechanism.
11068          */
11069
11070         if (ring == NULL)
11071                 return true;
11072
11073         if (INTEL_INFO(ring->dev)->gen < 5)
11074                 return false;
11075
11076         if (i915.use_mmio_flip < 0)
11077                 return false;
11078         else if (i915.use_mmio_flip > 0)
11079                 return true;
11080         else if (i915.enable_execlists)
11081                 return true;
11082         else
11083                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11084 }
11085
11086 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11087 {
11088         struct drm_device *dev = intel_crtc->base.dev;
11089         struct drm_i915_private *dev_priv = dev->dev_private;
11090         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11091         const enum pipe pipe = intel_crtc->pipe;
11092         u32 ctl, stride;
11093
11094         ctl = I915_READ(PLANE_CTL(pipe, 0));
11095         ctl &= ~PLANE_CTL_TILED_MASK;
11096         switch (fb->modifier[0]) {
11097         case DRM_FORMAT_MOD_NONE:
11098                 break;
11099         case I915_FORMAT_MOD_X_TILED:
11100                 ctl |= PLANE_CTL_TILED_X;
11101                 break;
11102         case I915_FORMAT_MOD_Y_TILED:
11103                 ctl |= PLANE_CTL_TILED_Y;
11104                 break;
11105         case I915_FORMAT_MOD_Yf_TILED:
11106                 ctl |= PLANE_CTL_TILED_YF;
11107                 break;
11108         default:
11109                 MISSING_CASE(fb->modifier[0]);
11110         }
11111
11112         /*
11113          * The stride is either expressed as a multiple of 64 bytes chunks for
11114          * linear buffers or in number of tiles for tiled buffers.
11115          */
11116         stride = fb->pitches[0] /
11117                  intel_fb_stride_alignment(dev, fb->modifier[0],
11118                                            fb->pixel_format);
11119
11120         /*
11121          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11122          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11123          */
11124         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11125         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11126
11127         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11128         POSTING_READ(PLANE_SURF(pipe, 0));
11129 }
11130
11131 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11132 {
11133         struct drm_device *dev = intel_crtc->base.dev;
11134         struct drm_i915_private *dev_priv = dev->dev_private;
11135         struct intel_framebuffer *intel_fb =
11136                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11137         struct drm_i915_gem_object *obj = intel_fb->obj;
11138         u32 dspcntr;
11139         u32 reg;
11140
11141         reg = DSPCNTR(intel_crtc->plane);
11142         dspcntr = I915_READ(reg);
11143
11144         if (obj->tiling_mode != I915_TILING_NONE)
11145                 dspcntr |= DISPPLANE_TILED;
11146         else
11147                 dspcntr &= ~DISPPLANE_TILED;
11148
11149         I915_WRITE(reg, dspcntr);
11150
11151         I915_WRITE(DSPSURF(intel_crtc->plane),
11152                    intel_crtc->unpin_work->gtt_offset);
11153         POSTING_READ(DSPSURF(intel_crtc->plane));
11154
11155 }
11156
11157 /*
11158  * XXX: This is the temporary way to update the plane registers until we get
11159  * around to using the usual plane update functions for MMIO flips
11160  */
11161 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11162 {
11163         struct drm_device *dev = intel_crtc->base.dev;
11164         u32 start_vbl_count;
11165
11166         intel_mark_page_flip_active(intel_crtc);
11167
11168         intel_pipe_update_start(intel_crtc, &start_vbl_count);
11169
11170         if (INTEL_INFO(dev)->gen >= 9)
11171                 skl_do_mmio_flip(intel_crtc);
11172         else
11173                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11174                 ilk_do_mmio_flip(intel_crtc);
11175
11176         intel_pipe_update_end(intel_crtc, start_vbl_count);
11177 }
11178
11179 static void intel_mmio_flip_work_func(struct work_struct *work)
11180 {
11181         struct intel_mmio_flip *mmio_flip =
11182                 container_of(work, struct intel_mmio_flip, work);
11183
11184         if (mmio_flip->req)
11185                 WARN_ON(__i915_wait_request(mmio_flip->req,
11186                                             mmio_flip->crtc->reset_counter,
11187                                             false, NULL,
11188                                             &mmio_flip->i915->rps.mmioflips));
11189
11190         intel_do_mmio_flip(mmio_flip->crtc);
11191
11192         i915_gem_request_unreference__unlocked(mmio_flip->req);
11193         kfree(mmio_flip);
11194 }
11195
11196 static int intel_queue_mmio_flip(struct drm_device *dev,
11197                                  struct drm_crtc *crtc,
11198                                  struct drm_framebuffer *fb,
11199                                  struct drm_i915_gem_object *obj,
11200                                  struct intel_engine_cs *ring,
11201                                  uint32_t flags)
11202 {
11203         struct intel_mmio_flip *mmio_flip;
11204
11205         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11206         if (mmio_flip == NULL)
11207                 return -ENOMEM;
11208
11209         mmio_flip->i915 = to_i915(dev);
11210         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11211         mmio_flip->crtc = to_intel_crtc(crtc);
11212
11213         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11214         schedule_work(&mmio_flip->work);
11215
11216         return 0;
11217 }
11218
11219 static int intel_default_queue_flip(struct drm_device *dev,
11220                                     struct drm_crtc *crtc,
11221                                     struct drm_framebuffer *fb,
11222                                     struct drm_i915_gem_object *obj,
11223                                     struct drm_i915_gem_request *req,
11224                                     uint32_t flags)
11225 {
11226         return -ENODEV;
11227 }
11228
11229 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11230                                          struct drm_crtc *crtc)
11231 {
11232         struct drm_i915_private *dev_priv = dev->dev_private;
11233         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11234         struct intel_unpin_work *work = intel_crtc->unpin_work;
11235         u32 addr;
11236
11237         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11238                 return true;
11239
11240         if (!work->enable_stall_check)
11241                 return false;
11242
11243         if (work->flip_ready_vblank == 0) {
11244                 if (work->flip_queued_req &&
11245                     !i915_gem_request_completed(work->flip_queued_req, true))
11246                         return false;
11247
11248                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11249         }
11250
11251         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11252                 return false;
11253
11254         /* Potential stall - if we see that the flip has happened,
11255          * assume a missed interrupt. */
11256         if (INTEL_INFO(dev)->gen >= 4)
11257                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11258         else
11259                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11260
11261         /* There is a potential issue here with a false positive after a flip
11262          * to the same address. We could address this by checking for a
11263          * non-incrementing frame counter.
11264          */
11265         return addr == work->gtt_offset;
11266 }
11267
11268 void intel_check_page_flip(struct drm_device *dev, int pipe)
11269 {
11270         struct drm_i915_private *dev_priv = dev->dev_private;
11271         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11273         struct intel_unpin_work *work;
11274
11275         WARN_ON(!in_interrupt());
11276
11277         if (crtc == NULL)
11278                 return;
11279
11280         spin_lock(&dev->event_lock);
11281         work = intel_crtc->unpin_work;
11282         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11283                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11284                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11285                 page_flip_completed(intel_crtc);
11286                 work = NULL;
11287         }
11288         if (work != NULL &&
11289             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11290                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11291         spin_unlock(&dev->event_lock);
11292 }
11293
11294 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11295                                 struct drm_framebuffer *fb,
11296                                 struct drm_pending_vblank_event *event,
11297                                 uint32_t page_flip_flags)
11298 {
11299         struct drm_device *dev = crtc->dev;
11300         struct drm_i915_private *dev_priv = dev->dev_private;
11301         struct drm_framebuffer *old_fb = crtc->primary->fb;
11302         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11303         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11304         struct drm_plane *primary = crtc->primary;
11305         enum pipe pipe = intel_crtc->pipe;
11306         struct intel_unpin_work *work;
11307         struct intel_engine_cs *ring;
11308         bool mmio_flip;
11309         struct drm_i915_gem_request *request = NULL;
11310         int ret;
11311
11312         /*
11313          * drm_mode_page_flip_ioctl() should already catch this, but double
11314          * check to be safe.  In the future we may enable pageflipping from
11315          * a disabled primary plane.
11316          */
11317         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11318                 return -EBUSY;
11319
11320         /* Can't change pixel format via MI display flips. */
11321         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11322                 return -EINVAL;
11323
11324         /*
11325          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11326          * Note that pitch changes could also affect these register.
11327          */
11328         if (INTEL_INFO(dev)->gen > 3 &&
11329             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11330              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11331                 return -EINVAL;
11332
11333         if (i915_terminally_wedged(&dev_priv->gpu_error))
11334                 goto out_hang;
11335
11336         work = kzalloc(sizeof(*work), GFP_KERNEL);
11337         if (work == NULL)
11338                 return -ENOMEM;
11339
11340         work->event = event;
11341         work->crtc = crtc;
11342         work->old_fb = old_fb;
11343         INIT_WORK(&work->work, intel_unpin_work_fn);
11344
11345         ret = drm_crtc_vblank_get(crtc);
11346         if (ret)
11347                 goto free_work;
11348
11349         /* We borrow the event spin lock for protecting unpin_work */
11350         spin_lock_irq(&dev->event_lock);
11351         if (intel_crtc->unpin_work) {
11352                 /* Before declaring the flip queue wedged, check if
11353                  * the hardware completed the operation behind our backs.
11354                  */
11355                 if (__intel_pageflip_stall_check(dev, crtc)) {
11356                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11357                         page_flip_completed(intel_crtc);
11358                 } else {
11359                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11360                         spin_unlock_irq(&dev->event_lock);
11361
11362                         drm_crtc_vblank_put(crtc);
11363                         kfree(work);
11364                         return -EBUSY;
11365                 }
11366         }
11367         intel_crtc->unpin_work = work;
11368         spin_unlock_irq(&dev->event_lock);
11369
11370         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11371                 flush_workqueue(dev_priv->wq);
11372
11373         /* Reference the objects for the scheduled work. */
11374         drm_framebuffer_reference(work->old_fb);
11375         drm_gem_object_reference(&obj->base);
11376
11377         crtc->primary->fb = fb;
11378         update_state_fb(crtc->primary);
11379
11380         work->pending_flip_obj = obj;
11381
11382         ret = i915_mutex_lock_interruptible(dev);
11383         if (ret)
11384                 goto cleanup;
11385
11386         atomic_inc(&intel_crtc->unpin_work_count);
11387         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11388
11389         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11390                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11391
11392         if (IS_VALLEYVIEW(dev)) {
11393                 ring = &dev_priv->ring[BCS];
11394                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11395                         /* vlv: DISPLAY_FLIP fails to change tiling */
11396                         ring = NULL;
11397         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11398                 ring = &dev_priv->ring[BCS];
11399         } else if (INTEL_INFO(dev)->gen >= 7) {
11400                 ring = i915_gem_request_get_ring(obj->last_write_req);
11401                 if (ring == NULL || ring->id != RCS)
11402                         ring = &dev_priv->ring[BCS];
11403         } else {
11404                 ring = &dev_priv->ring[RCS];
11405         }
11406
11407         mmio_flip = use_mmio_flip(ring, obj);
11408
11409         /* When using CS flips, we want to emit semaphores between rings.
11410          * However, when using mmio flips we will create a task to do the
11411          * synchronisation, so all we want here is to pin the framebuffer
11412          * into the display plane and skip any waits.
11413          */
11414         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11415                                          crtc->primary->state,
11416                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11417         if (ret)
11418                 goto cleanup_pending;
11419
11420         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11421                                                   + intel_crtc->dspaddr_offset;
11422
11423         if (mmio_flip) {
11424                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11425                                             page_flip_flags);
11426                 if (ret)
11427                         goto cleanup_unpin;
11428
11429                 i915_gem_request_assign(&work->flip_queued_req,
11430                                         obj->last_write_req);
11431         } else {
11432                 if (!request) {
11433                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11434                         if (ret)
11435                                 goto cleanup_unpin;
11436                 }
11437
11438                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11439                                                    page_flip_flags);
11440                 if (ret)
11441                         goto cleanup_unpin;
11442
11443                 i915_gem_request_assign(&work->flip_queued_req, request);
11444         }
11445
11446         if (request)
11447                 i915_add_request_no_flush(request);
11448
11449         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11450         work->enable_stall_check = true;
11451
11452         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11453                           to_intel_plane(primary)->frontbuffer_bit);
11454         mutex_unlock(&dev->struct_mutex);
11455
11456         intel_fbc_disable_crtc(intel_crtc);
11457         intel_frontbuffer_flip_prepare(dev,
11458                                        to_intel_plane(primary)->frontbuffer_bit);
11459
11460         trace_i915_flip_request(intel_crtc->plane, obj);
11461
11462         return 0;
11463
11464 cleanup_unpin:
11465         intel_unpin_fb_obj(fb, crtc->primary->state);
11466 cleanup_pending:
11467         if (request)
11468                 i915_gem_request_cancel(request);
11469         atomic_dec(&intel_crtc->unpin_work_count);
11470         mutex_unlock(&dev->struct_mutex);
11471 cleanup:
11472         crtc->primary->fb = old_fb;
11473         update_state_fb(crtc->primary);
11474
11475         drm_gem_object_unreference_unlocked(&obj->base);
11476         drm_framebuffer_unreference(work->old_fb);
11477
11478         spin_lock_irq(&dev->event_lock);
11479         intel_crtc->unpin_work = NULL;
11480         spin_unlock_irq(&dev->event_lock);
11481
11482         drm_crtc_vblank_put(crtc);
11483 free_work:
11484         kfree(work);
11485
11486         if (ret == -EIO) {
11487                 struct drm_atomic_state *state;
11488                 struct drm_plane_state *plane_state;
11489
11490 out_hang:
11491                 state = drm_atomic_state_alloc(dev);
11492                 if (!state)
11493                         return -ENOMEM;
11494                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11495
11496 retry:
11497                 plane_state = drm_atomic_get_plane_state(state, primary);
11498                 ret = PTR_ERR_OR_ZERO(plane_state);
11499                 if (!ret) {
11500                         drm_atomic_set_fb_for_plane(plane_state, fb);
11501
11502                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11503                         if (!ret)
11504                                 ret = drm_atomic_commit(state);
11505                 }
11506
11507                 if (ret == -EDEADLK) {
11508                         drm_modeset_backoff(state->acquire_ctx);
11509                         drm_atomic_state_clear(state);
11510                         goto retry;
11511                 }
11512
11513                 if (ret)
11514                         drm_atomic_state_free(state);
11515
11516                 if (ret == 0 && event) {
11517                         spin_lock_irq(&dev->event_lock);
11518                         drm_send_vblank_event(dev, pipe, event);
11519                         spin_unlock_irq(&dev->event_lock);
11520                 }
11521         }
11522         return ret;
11523 }
11524
11525
11526 /**
11527  * intel_wm_need_update - Check whether watermarks need updating
11528  * @plane: drm plane
11529  * @state: new plane state
11530  *
11531  * Check current plane state versus the new one to determine whether
11532  * watermarks need to be recalculated.
11533  *
11534  * Returns true or false.
11535  */
11536 static bool intel_wm_need_update(struct drm_plane *plane,
11537                                  struct drm_plane_state *state)
11538 {
11539         /* Update watermarks on tiling changes. */
11540         if (!plane->state->fb || !state->fb ||
11541             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11542             plane->state->rotation != state->rotation)
11543                 return true;
11544
11545         if (plane->state->crtc_w != state->crtc_w)
11546                 return true;
11547
11548         return false;
11549 }
11550
11551 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11552                                     struct drm_plane_state *plane_state)
11553 {
11554         struct drm_crtc *crtc = crtc_state->crtc;
11555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11556         struct drm_plane *plane = plane_state->plane;
11557         struct drm_device *dev = crtc->dev;
11558         struct drm_i915_private *dev_priv = dev->dev_private;
11559         struct intel_plane_state *old_plane_state =
11560                 to_intel_plane_state(plane->state);
11561         int idx = intel_crtc->base.base.id, ret;
11562         int i = drm_plane_index(plane);
11563         bool mode_changed = needs_modeset(crtc_state);
11564         bool was_crtc_enabled = crtc->state->active;
11565         bool is_crtc_enabled = crtc_state->active;
11566
11567         bool turn_off, turn_on, visible, was_visible;
11568         struct drm_framebuffer *fb = plane_state->fb;
11569
11570         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11571             plane->type != DRM_PLANE_TYPE_CURSOR) {
11572                 ret = skl_update_scaler_plane(
11573                         to_intel_crtc_state(crtc_state),
11574                         to_intel_plane_state(plane_state));
11575                 if (ret)
11576                         return ret;
11577         }
11578
11579         /*
11580          * Disabling a plane is always okay; we just need to update
11581          * fb tracking in a special way since cleanup_fb() won't
11582          * get called by the plane helpers.
11583          */
11584         if (old_plane_state->base.fb && !fb)
11585                 intel_crtc->atomic.disabled_planes |= 1 << i;
11586
11587         was_visible = old_plane_state->visible;
11588         visible = to_intel_plane_state(plane_state)->visible;
11589
11590         if (!was_crtc_enabled && WARN_ON(was_visible))
11591                 was_visible = false;
11592
11593         if (!is_crtc_enabled && WARN_ON(visible))
11594                 visible = false;
11595
11596         if (!was_visible && !visible)
11597                 return 0;
11598
11599         turn_off = was_visible && (!visible || mode_changed);
11600         turn_on = visible && (!was_visible || mode_changed);
11601
11602         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11603                          plane->base.id, fb ? fb->base.id : -1);
11604
11605         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11606                          plane->base.id, was_visible, visible,
11607                          turn_off, turn_on, mode_changed);
11608
11609         if (turn_on) {
11610                 intel_crtc->atomic.update_wm_pre = true;
11611                 /* must disable cxsr around plane enable/disable */
11612                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11613                         intel_crtc->atomic.disable_cxsr = true;
11614                         /* to potentially re-enable cxsr */
11615                         intel_crtc->atomic.wait_vblank = true;
11616                         intel_crtc->atomic.update_wm_post = true;
11617                 }
11618         } else if (turn_off) {
11619                 intel_crtc->atomic.update_wm_post = true;
11620                 /* must disable cxsr around plane enable/disable */
11621                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11622                         if (is_crtc_enabled)
11623                                 intel_crtc->atomic.wait_vblank = true;
11624                         intel_crtc->atomic.disable_cxsr = true;
11625                 }
11626         } else if (intel_wm_need_update(plane, plane_state)) {
11627                 intel_crtc->atomic.update_wm_pre = true;
11628         }
11629
11630         if (visible)
11631                 intel_crtc->atomic.fb_bits |=
11632                         to_intel_plane(plane)->frontbuffer_bit;
11633
11634         switch (plane->type) {
11635         case DRM_PLANE_TYPE_PRIMARY:
11636                 intel_crtc->atomic.wait_for_flips = true;
11637                 intel_crtc->atomic.pre_disable_primary = turn_off;
11638                 intel_crtc->atomic.post_enable_primary = turn_on;
11639
11640                 if (turn_off) {
11641                         /*
11642                          * FIXME: Actually if we will still have any other
11643                          * plane enabled on the pipe we could let IPS enabled
11644                          * still, but for now lets consider that when we make
11645                          * primary invisible by setting DSPCNTR to 0 on
11646                          * update_primary_plane function IPS needs to be
11647                          * disable.
11648                          */
11649                         intel_crtc->atomic.disable_ips = true;
11650
11651                         intel_crtc->atomic.disable_fbc = true;
11652                 }
11653
11654                 /*
11655                  * FBC does not work on some platforms for rotated
11656                  * planes, so disable it when rotation is not 0 and
11657                  * update it when rotation is set back to 0.
11658                  *
11659                  * FIXME: This is redundant with the fbc update done in
11660                  * the primary plane enable function except that that
11661                  * one is done too late. We eventually need to unify
11662                  * this.
11663                  */
11664
11665                 if (visible &&
11666                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11667                     dev_priv->fbc.crtc == intel_crtc &&
11668                     plane_state->rotation != BIT(DRM_ROTATE_0))
11669                         intel_crtc->atomic.disable_fbc = true;
11670
11671                 /*
11672                  * BDW signals flip done immediately if the plane
11673                  * is disabled, even if the plane enable is already
11674                  * armed to occur at the next vblank :(
11675                  */
11676                 if (turn_on && IS_BROADWELL(dev))
11677                         intel_crtc->atomic.wait_vblank = true;
11678
11679                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11680                 break;
11681         case DRM_PLANE_TYPE_CURSOR:
11682                 break;
11683         case DRM_PLANE_TYPE_OVERLAY:
11684                 if (turn_off && !mode_changed) {
11685                         intel_crtc->atomic.wait_vblank = true;
11686                         intel_crtc->atomic.update_sprite_watermarks |=
11687                                 1 << i;
11688                 }
11689         }
11690         return 0;
11691 }
11692
11693 static bool encoders_cloneable(const struct intel_encoder *a,
11694                                const struct intel_encoder *b)
11695 {
11696         /* masks could be asymmetric, so check both ways */
11697         return a == b || (a->cloneable & (1 << b->type) &&
11698                           b->cloneable & (1 << a->type));
11699 }
11700
11701 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11702                                          struct intel_crtc *crtc,
11703                                          struct intel_encoder *encoder)
11704 {
11705         struct intel_encoder *source_encoder;
11706         struct drm_connector *connector;
11707         struct drm_connector_state *connector_state;
11708         int i;
11709
11710         for_each_connector_in_state(state, connector, connector_state, i) {
11711                 if (connector_state->crtc != &crtc->base)
11712                         continue;
11713
11714                 source_encoder =
11715                         to_intel_encoder(connector_state->best_encoder);
11716                 if (!encoders_cloneable(encoder, source_encoder))
11717                         return false;
11718         }
11719
11720         return true;
11721 }
11722
11723 static bool check_encoder_cloning(struct drm_atomic_state *state,
11724                                   struct intel_crtc *crtc)
11725 {
11726         struct intel_encoder *encoder;
11727         struct drm_connector *connector;
11728         struct drm_connector_state *connector_state;
11729         int i;
11730
11731         for_each_connector_in_state(state, connector, connector_state, i) {
11732                 if (connector_state->crtc != &crtc->base)
11733                         continue;
11734
11735                 encoder = to_intel_encoder(connector_state->best_encoder);
11736                 if (!check_single_encoder_cloning(state, crtc, encoder))
11737                         return false;
11738         }
11739
11740         return true;
11741 }
11742
11743 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11744                                    struct drm_crtc_state *crtc_state)
11745 {
11746         struct drm_device *dev = crtc->dev;
11747         struct drm_i915_private *dev_priv = dev->dev_private;
11748         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11749         struct intel_crtc_state *pipe_config =
11750                 to_intel_crtc_state(crtc_state);
11751         struct drm_atomic_state *state = crtc_state->state;
11752         int ret;
11753         bool mode_changed = needs_modeset(crtc_state);
11754
11755         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11756                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11757                 return -EINVAL;
11758         }
11759
11760         if (mode_changed && !crtc_state->active)
11761                 intel_crtc->atomic.update_wm_post = true;
11762
11763         if (mode_changed && crtc_state->enable &&
11764             dev_priv->display.crtc_compute_clock &&
11765             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11766                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11767                                                            pipe_config);
11768                 if (ret)
11769                         return ret;
11770         }
11771
11772         ret = 0;
11773         if (INTEL_INFO(dev)->gen >= 9) {
11774                 if (mode_changed)
11775                         ret = skl_update_scaler_crtc(pipe_config);
11776
11777                 if (!ret)
11778                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11779                                                          pipe_config);
11780         }
11781
11782         return ret;
11783 }
11784
11785 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11786         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11787         .load_lut = intel_crtc_load_lut,
11788         .atomic_begin = intel_begin_crtc_commit,
11789         .atomic_flush = intel_finish_crtc_commit,
11790         .atomic_check = intel_crtc_atomic_check,
11791 };
11792
11793 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11794 {
11795         struct intel_connector *connector;
11796
11797         for_each_intel_connector(dev, connector) {
11798                 if (connector->base.encoder) {
11799                         connector->base.state->best_encoder =
11800                                 connector->base.encoder;
11801                         connector->base.state->crtc =
11802                                 connector->base.encoder->crtc;
11803                 } else {
11804                         connector->base.state->best_encoder = NULL;
11805                         connector->base.state->crtc = NULL;
11806                 }
11807         }
11808 }
11809
11810 static void
11811 connected_sink_compute_bpp(struct intel_connector *connector,
11812                            struct intel_crtc_state *pipe_config)
11813 {
11814         int bpp = pipe_config->pipe_bpp;
11815
11816         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11817                 connector->base.base.id,
11818                 connector->base.name);
11819
11820         /* Don't use an invalid EDID bpc value */
11821         if (connector->base.display_info.bpc &&
11822             connector->base.display_info.bpc * 3 < bpp) {
11823                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11824                               bpp, connector->base.display_info.bpc*3);
11825                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11826         }
11827
11828         /* Clamp bpp to 8 on screens without EDID 1.4 */
11829         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11830                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11831                               bpp);
11832                 pipe_config->pipe_bpp = 24;
11833         }
11834 }
11835
11836 static int
11837 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11838                           struct intel_crtc_state *pipe_config)
11839 {
11840         struct drm_device *dev = crtc->base.dev;
11841         struct drm_atomic_state *state;
11842         struct drm_connector *connector;
11843         struct drm_connector_state *connector_state;
11844         int bpp, i;
11845
11846         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11847                 bpp = 10*3;
11848         else if (INTEL_INFO(dev)->gen >= 5)
11849                 bpp = 12*3;
11850         else
11851                 bpp = 8*3;
11852
11853
11854         pipe_config->pipe_bpp = bpp;
11855
11856         state = pipe_config->base.state;
11857
11858         /* Clamp display bpp to EDID value */
11859         for_each_connector_in_state(state, connector, connector_state, i) {
11860                 if (connector_state->crtc != &crtc->base)
11861                         continue;
11862
11863                 connected_sink_compute_bpp(to_intel_connector(connector),
11864                                            pipe_config);
11865         }
11866
11867         return bpp;
11868 }
11869
11870 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11871 {
11872         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11873                         "type: 0x%x flags: 0x%x\n",
11874                 mode->crtc_clock,
11875                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11876                 mode->crtc_hsync_end, mode->crtc_htotal,
11877                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11878                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11879 }
11880
11881 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11882                                    struct intel_crtc_state *pipe_config,
11883                                    const char *context)
11884 {
11885         struct drm_device *dev = crtc->base.dev;
11886         struct drm_plane *plane;
11887         struct intel_plane *intel_plane;
11888         struct intel_plane_state *state;
11889         struct drm_framebuffer *fb;
11890
11891         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11892                       context, pipe_config, pipe_name(crtc->pipe));
11893
11894         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11895         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11896                       pipe_config->pipe_bpp, pipe_config->dither);
11897         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11898                       pipe_config->has_pch_encoder,
11899                       pipe_config->fdi_lanes,
11900                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11901                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11902                       pipe_config->fdi_m_n.tu);
11903         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11904                       pipe_config->has_dp_encoder,
11905                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11906                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11907                       pipe_config->dp_m_n.tu);
11908
11909         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11910                       pipe_config->has_dp_encoder,
11911                       pipe_config->dp_m2_n2.gmch_m,
11912                       pipe_config->dp_m2_n2.gmch_n,
11913                       pipe_config->dp_m2_n2.link_m,
11914                       pipe_config->dp_m2_n2.link_n,
11915                       pipe_config->dp_m2_n2.tu);
11916
11917         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11918                       pipe_config->has_audio,
11919                       pipe_config->has_infoframe);
11920
11921         DRM_DEBUG_KMS("requested mode:\n");
11922         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11923         DRM_DEBUG_KMS("adjusted mode:\n");
11924         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11925         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11926         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11927         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11928                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11929         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11930                       crtc->num_scalers,
11931                       pipe_config->scaler_state.scaler_users,
11932                       pipe_config->scaler_state.scaler_id);
11933         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11934                       pipe_config->gmch_pfit.control,
11935                       pipe_config->gmch_pfit.pgm_ratios,
11936                       pipe_config->gmch_pfit.lvds_border_bits);
11937         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11938                       pipe_config->pch_pfit.pos,
11939                       pipe_config->pch_pfit.size,
11940                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11941         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11942         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11943
11944         if (IS_BROXTON(dev)) {
11945                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11946                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11947                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11948                               pipe_config->ddi_pll_sel,
11949                               pipe_config->dpll_hw_state.ebb0,
11950                               pipe_config->dpll_hw_state.ebb4,
11951                               pipe_config->dpll_hw_state.pll0,
11952                               pipe_config->dpll_hw_state.pll1,
11953                               pipe_config->dpll_hw_state.pll2,
11954                               pipe_config->dpll_hw_state.pll3,
11955                               pipe_config->dpll_hw_state.pll6,
11956                               pipe_config->dpll_hw_state.pll8,
11957                               pipe_config->dpll_hw_state.pll9,
11958                               pipe_config->dpll_hw_state.pll10,
11959                               pipe_config->dpll_hw_state.pcsdw12);
11960         } else if (IS_SKYLAKE(dev)) {
11961                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11962                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11963                               pipe_config->ddi_pll_sel,
11964                               pipe_config->dpll_hw_state.ctrl1,
11965                               pipe_config->dpll_hw_state.cfgcr1,
11966                               pipe_config->dpll_hw_state.cfgcr2);
11967         } else if (HAS_DDI(dev)) {
11968                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11969                               pipe_config->ddi_pll_sel,
11970                               pipe_config->dpll_hw_state.wrpll);
11971         } else {
11972                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11973                               "fp0: 0x%x, fp1: 0x%x\n",
11974                               pipe_config->dpll_hw_state.dpll,
11975                               pipe_config->dpll_hw_state.dpll_md,
11976                               pipe_config->dpll_hw_state.fp0,
11977                               pipe_config->dpll_hw_state.fp1);
11978         }
11979
11980         DRM_DEBUG_KMS("planes on this crtc\n");
11981         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11982                 intel_plane = to_intel_plane(plane);
11983                 if (intel_plane->pipe != crtc->pipe)
11984                         continue;
11985
11986                 state = to_intel_plane_state(plane->state);
11987                 fb = state->base.fb;
11988                 if (!fb) {
11989                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11990                                 "disabled, scaler_id = %d\n",
11991                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11992                                 plane->base.id, intel_plane->pipe,
11993                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11994                                 drm_plane_index(plane), state->scaler_id);
11995                         continue;
11996                 }
11997
11998                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11999                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12000                         plane->base.id, intel_plane->pipe,
12001                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12002                         drm_plane_index(plane));
12003                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12004                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12005                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12006                         state->scaler_id,
12007                         state->src.x1 >> 16, state->src.y1 >> 16,
12008                         drm_rect_width(&state->src) >> 16,
12009                         drm_rect_height(&state->src) >> 16,
12010                         state->dst.x1, state->dst.y1,
12011                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12012         }
12013 }
12014
12015 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12016 {
12017         struct drm_device *dev = state->dev;
12018         struct intel_encoder *encoder;
12019         struct drm_connector *connector;
12020         struct drm_connector_state *connector_state;
12021         unsigned int used_ports = 0;
12022         int i;
12023
12024         /*
12025          * Walk the connector list instead of the encoder
12026          * list to detect the problem on ddi platforms
12027          * where there's just one encoder per digital port.
12028          */
12029         for_each_connector_in_state(state, connector, connector_state, i) {
12030                 if (!connector_state->best_encoder)
12031                         continue;
12032
12033                 encoder = to_intel_encoder(connector_state->best_encoder);
12034
12035                 WARN_ON(!connector_state->crtc);
12036
12037                 switch (encoder->type) {
12038                         unsigned int port_mask;
12039                 case INTEL_OUTPUT_UNKNOWN:
12040                         if (WARN_ON(!HAS_DDI(dev)))
12041                                 break;
12042                 case INTEL_OUTPUT_DISPLAYPORT:
12043                 case INTEL_OUTPUT_HDMI:
12044                 case INTEL_OUTPUT_EDP:
12045                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12046
12047                         /* the same port mustn't appear more than once */
12048                         if (used_ports & port_mask)
12049                                 return false;
12050
12051                         used_ports |= port_mask;
12052                 default:
12053                         break;
12054                 }
12055         }
12056
12057         return true;
12058 }
12059
12060 static void
12061 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12062 {
12063         struct drm_crtc_state tmp_state;
12064         struct intel_crtc_scaler_state scaler_state;
12065         struct intel_dpll_hw_state dpll_hw_state;
12066         enum intel_dpll_id shared_dpll;
12067         uint32_t ddi_pll_sel;
12068         bool force_thru;
12069
12070         /* FIXME: before the switch to atomic started, a new pipe_config was
12071          * kzalloc'd. Code that depends on any field being zero should be
12072          * fixed, so that the crtc_state can be safely duplicated. For now,
12073          * only fields that are know to not cause problems are preserved. */
12074
12075         tmp_state = crtc_state->base;
12076         scaler_state = crtc_state->scaler_state;
12077         shared_dpll = crtc_state->shared_dpll;
12078         dpll_hw_state = crtc_state->dpll_hw_state;
12079         ddi_pll_sel = crtc_state->ddi_pll_sel;
12080         force_thru = crtc_state->pch_pfit.force_thru;
12081
12082         memset(crtc_state, 0, sizeof *crtc_state);
12083
12084         crtc_state->base = tmp_state;
12085         crtc_state->scaler_state = scaler_state;
12086         crtc_state->shared_dpll = shared_dpll;
12087         crtc_state->dpll_hw_state = dpll_hw_state;
12088         crtc_state->ddi_pll_sel = ddi_pll_sel;
12089         crtc_state->pch_pfit.force_thru = force_thru;
12090 }
12091
12092 static int
12093 intel_modeset_pipe_config(struct drm_crtc *crtc,
12094                           struct intel_crtc_state *pipe_config)
12095 {
12096         struct drm_atomic_state *state = pipe_config->base.state;
12097         struct intel_encoder *encoder;
12098         struct drm_connector *connector;
12099         struct drm_connector_state *connector_state;
12100         int base_bpp, ret = -EINVAL;
12101         int i;
12102         bool retry = true;
12103
12104         clear_intel_crtc_state(pipe_config);
12105
12106         pipe_config->cpu_transcoder =
12107                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12108
12109         /*
12110          * Sanitize sync polarity flags based on requested ones. If neither
12111          * positive or negative polarity is requested, treat this as meaning
12112          * negative polarity.
12113          */
12114         if (!(pipe_config->base.adjusted_mode.flags &
12115               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12116                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12117
12118         if (!(pipe_config->base.adjusted_mode.flags &
12119               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12120                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12121
12122         /* Compute a starting value for pipe_config->pipe_bpp taking the source
12123          * plane pixel format and any sink constraints into account. Returns the
12124          * source plane bpp so that dithering can be selected on mismatches
12125          * after encoders and crtc also have had their say. */
12126         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12127                                              pipe_config);
12128         if (base_bpp < 0)
12129                 goto fail;
12130
12131         /*
12132          * Determine the real pipe dimensions. Note that stereo modes can
12133          * increase the actual pipe size due to the frame doubling and
12134          * insertion of additional space for blanks between the frame. This
12135          * is stored in the crtc timings. We use the requested mode to do this
12136          * computation to clearly distinguish it from the adjusted mode, which
12137          * can be changed by the connectors in the below retry loop.
12138          */
12139         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12140                                &pipe_config->pipe_src_w,
12141                                &pipe_config->pipe_src_h);
12142
12143 encoder_retry:
12144         /* Ensure the port clock defaults are reset when retrying. */
12145         pipe_config->port_clock = 0;
12146         pipe_config->pixel_multiplier = 1;
12147
12148         /* Fill in default crtc timings, allow encoders to overwrite them. */
12149         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12150                               CRTC_STEREO_DOUBLE);
12151
12152         /* Pass our mode to the connectors and the CRTC to give them a chance to
12153          * adjust it according to limitations or connector properties, and also
12154          * a chance to reject the mode entirely.
12155          */
12156         for_each_connector_in_state(state, connector, connector_state, i) {
12157                 if (connector_state->crtc != crtc)
12158                         continue;
12159
12160                 encoder = to_intel_encoder(connector_state->best_encoder);
12161
12162                 if (!(encoder->compute_config(encoder, pipe_config))) {
12163                         DRM_DEBUG_KMS("Encoder config failure\n");
12164                         goto fail;
12165                 }
12166         }
12167
12168         /* Set default port clock if not overwritten by the encoder. Needs to be
12169          * done afterwards in case the encoder adjusts the mode. */
12170         if (!pipe_config->port_clock)
12171                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12172                         * pipe_config->pixel_multiplier;
12173
12174         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12175         if (ret < 0) {
12176                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12177                 goto fail;
12178         }
12179
12180         if (ret == RETRY) {
12181                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12182                         ret = -EINVAL;
12183                         goto fail;
12184                 }
12185
12186                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12187                 retry = false;
12188                 goto encoder_retry;
12189         }
12190
12191         /* Dithering seems to not pass-through bits correctly when it should, so
12192          * only enable it on 6bpc panels. */
12193         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12194         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12195                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12196
12197 fail:
12198         return ret;
12199 }
12200
12201 static void
12202 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12203 {
12204         struct drm_crtc *crtc;
12205         struct drm_crtc_state *crtc_state;
12206         int i;
12207
12208         /* Double check state. */
12209         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12210                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12211
12212                 /* Update hwmode for vblank functions */
12213                 if (crtc->state->active)
12214                         crtc->hwmode = crtc->state->adjusted_mode;
12215                 else
12216                         crtc->hwmode.crtc_clock = 0;
12217         }
12218 }
12219
12220 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12221 {
12222         int diff;
12223
12224         if (clock1 == clock2)
12225                 return true;
12226
12227         if (!clock1 || !clock2)
12228                 return false;
12229
12230         diff = abs(clock1 - clock2);
12231
12232         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12233                 return true;
12234
12235         return false;
12236 }
12237
12238 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12239         list_for_each_entry((intel_crtc), \
12240                             &(dev)->mode_config.crtc_list, \
12241                             base.head) \
12242                 if (mask & (1 <<(intel_crtc)->pipe))
12243
12244
12245 static bool
12246 intel_compare_m_n(unsigned int m, unsigned int n,
12247                   unsigned int m2, unsigned int n2,
12248                   bool exact)
12249 {
12250         if (m == m2 && n == n2)
12251                 return true;
12252
12253         if (exact || !m || !n || !m2 || !n2)
12254                 return false;
12255
12256         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12257
12258         if (m > m2) {
12259                 while (m > m2) {
12260                         m2 <<= 1;
12261                         n2 <<= 1;
12262                 }
12263         } else if (m < m2) {
12264                 while (m < m2) {
12265                         m <<= 1;
12266                         n <<= 1;
12267                 }
12268         }
12269
12270         return m == m2 && n == n2;
12271 }
12272
12273 static bool
12274 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12275                        struct intel_link_m_n *m2_n2,
12276                        bool adjust)
12277 {
12278         if (m_n->tu == m2_n2->tu &&
12279             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12280                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12281             intel_compare_m_n(m_n->link_m, m_n->link_n,
12282                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12283                 if (adjust)
12284                         *m2_n2 = *m_n;
12285
12286                 return true;
12287         }
12288
12289         return false;
12290 }
12291
12292 static bool
12293 intel_pipe_config_compare(struct drm_device *dev,
12294                           struct intel_crtc_state *current_config,
12295                           struct intel_crtc_state *pipe_config,
12296                           bool adjust)
12297 {
12298         bool ret = true;
12299
12300 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12301         do { \
12302                 if (!adjust) \
12303                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12304                 else \
12305                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12306         } while (0)
12307
12308 #define PIPE_CONF_CHECK_X(name) \
12309         if (current_config->name != pipe_config->name) { \
12310                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12311                           "(expected 0x%08x, found 0x%08x)\n", \
12312                           current_config->name, \
12313                           pipe_config->name); \
12314                 ret = false; \
12315         }
12316
12317 #define PIPE_CONF_CHECK_I(name) \
12318         if (current_config->name != pipe_config->name) { \
12319                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12320                           "(expected %i, found %i)\n", \
12321                           current_config->name, \
12322                           pipe_config->name); \
12323                 ret = false; \
12324         }
12325
12326 #define PIPE_CONF_CHECK_M_N(name) \
12327         if (!intel_compare_link_m_n(&current_config->name, \
12328                                     &pipe_config->name,\
12329                                     adjust)) { \
12330                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12331                           "(expected tu %i gmch %i/%i link %i/%i, " \
12332                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12333                           current_config->name.tu, \
12334                           current_config->name.gmch_m, \
12335                           current_config->name.gmch_n, \
12336                           current_config->name.link_m, \
12337                           current_config->name.link_n, \
12338                           pipe_config->name.tu, \
12339                           pipe_config->name.gmch_m, \
12340                           pipe_config->name.gmch_n, \
12341                           pipe_config->name.link_m, \
12342                           pipe_config->name.link_n); \
12343                 ret = false; \
12344         }
12345
12346 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12347         if (!intel_compare_link_m_n(&current_config->name, \
12348                                     &pipe_config->name, adjust) && \
12349             !intel_compare_link_m_n(&current_config->alt_name, \
12350                                     &pipe_config->name, adjust)) { \
12351                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12352                           "(expected tu %i gmch %i/%i link %i/%i, " \
12353                           "or tu %i gmch %i/%i link %i/%i, " \
12354                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12355                           current_config->name.tu, \
12356                           current_config->name.gmch_m, \
12357                           current_config->name.gmch_n, \
12358                           current_config->name.link_m, \
12359                           current_config->name.link_n, \
12360                           current_config->alt_name.tu, \
12361                           current_config->alt_name.gmch_m, \
12362                           current_config->alt_name.gmch_n, \
12363                           current_config->alt_name.link_m, \
12364                           current_config->alt_name.link_n, \
12365                           pipe_config->name.tu, \
12366                           pipe_config->name.gmch_m, \
12367                           pipe_config->name.gmch_n, \
12368                           pipe_config->name.link_m, \
12369                           pipe_config->name.link_n); \
12370                 ret = false; \
12371         }
12372
12373 /* This is required for BDW+ where there is only one set of registers for
12374  * switching between high and low RR.
12375  * This macro can be used whenever a comparison has to be made between one
12376  * hw state and multiple sw state variables.
12377  */
12378 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12379         if ((current_config->name != pipe_config->name) && \
12380                 (current_config->alt_name != pipe_config->name)) { \
12381                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12382                                   "(expected %i or %i, found %i)\n", \
12383                                   current_config->name, \
12384                                   current_config->alt_name, \
12385                                   pipe_config->name); \
12386                         ret = false; \
12387         }
12388
12389 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12390         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12391                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12392                           "(expected %i, found %i)\n", \
12393                           current_config->name & (mask), \
12394                           pipe_config->name & (mask)); \
12395                 ret = false; \
12396         }
12397
12398 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12399         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12400                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12401                           "(expected %i, found %i)\n", \
12402                           current_config->name, \
12403                           pipe_config->name); \
12404                 ret = false; \
12405         }
12406
12407 #define PIPE_CONF_QUIRK(quirk)  \
12408         ((current_config->quirks | pipe_config->quirks) & (quirk))
12409
12410         PIPE_CONF_CHECK_I(cpu_transcoder);
12411
12412         PIPE_CONF_CHECK_I(has_pch_encoder);
12413         PIPE_CONF_CHECK_I(fdi_lanes);
12414         PIPE_CONF_CHECK_M_N(fdi_m_n);
12415
12416         PIPE_CONF_CHECK_I(has_dp_encoder);
12417
12418         if (INTEL_INFO(dev)->gen < 8) {
12419                 PIPE_CONF_CHECK_M_N(dp_m_n);
12420
12421                 PIPE_CONF_CHECK_I(has_drrs);
12422                 if (current_config->has_drrs)
12423                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12424         } else
12425                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12426
12427         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12428         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12429         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12430         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12431         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12432         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12433
12434         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12435         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12436         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12437         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12438         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12439         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12440
12441         PIPE_CONF_CHECK_I(pixel_multiplier);
12442         PIPE_CONF_CHECK_I(has_hdmi_sink);
12443         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12444             IS_VALLEYVIEW(dev))
12445                 PIPE_CONF_CHECK_I(limited_color_range);
12446         PIPE_CONF_CHECK_I(has_infoframe);
12447
12448         PIPE_CONF_CHECK_I(has_audio);
12449
12450         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12451                               DRM_MODE_FLAG_INTERLACE);
12452
12453         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12454                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12455                                       DRM_MODE_FLAG_PHSYNC);
12456                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12457                                       DRM_MODE_FLAG_NHSYNC);
12458                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12459                                       DRM_MODE_FLAG_PVSYNC);
12460                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12461                                       DRM_MODE_FLAG_NVSYNC);
12462         }
12463
12464         PIPE_CONF_CHECK_I(pipe_src_w);
12465         PIPE_CONF_CHECK_I(pipe_src_h);
12466
12467         PIPE_CONF_CHECK_I(gmch_pfit.control);
12468         /* pfit ratios are autocomputed by the hw on gen4+ */
12469         if (INTEL_INFO(dev)->gen < 4)
12470                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12471         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12472
12473         PIPE_CONF_CHECK_I(pch_pfit.enabled);
12474         if (current_config->pch_pfit.enabled) {
12475                 PIPE_CONF_CHECK_I(pch_pfit.pos);
12476                 PIPE_CONF_CHECK_I(pch_pfit.size);
12477         }
12478
12479         PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12480
12481         /* BDW+ don't expose a synchronous way to read the state */
12482         if (IS_HASWELL(dev))
12483                 PIPE_CONF_CHECK_I(ips_enabled);
12484
12485         PIPE_CONF_CHECK_I(double_wide);
12486
12487         PIPE_CONF_CHECK_X(ddi_pll_sel);
12488
12489         PIPE_CONF_CHECK_I(shared_dpll);
12490         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12491         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12492         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12493         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12494         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12495         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12496         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12497         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12498
12499         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12500                 PIPE_CONF_CHECK_I(pipe_bpp);
12501
12502         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12503         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12504
12505 #undef PIPE_CONF_CHECK_X
12506 #undef PIPE_CONF_CHECK_I
12507 #undef PIPE_CONF_CHECK_I_ALT
12508 #undef PIPE_CONF_CHECK_FLAGS
12509 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12510 #undef PIPE_CONF_QUIRK
12511 #undef INTEL_ERR_OR_DBG_KMS
12512
12513         return ret;
12514 }
12515
12516 static void check_wm_state(struct drm_device *dev)
12517 {
12518         struct drm_i915_private *dev_priv = dev->dev_private;
12519         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12520         struct intel_crtc *intel_crtc;
12521         int plane;
12522
12523         if (INTEL_INFO(dev)->gen < 9)
12524                 return;
12525
12526         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12527         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12528
12529         for_each_intel_crtc(dev, intel_crtc) {
12530                 struct skl_ddb_entry *hw_entry, *sw_entry;
12531                 const enum pipe pipe = intel_crtc->pipe;
12532
12533                 if (!intel_crtc->active)
12534                         continue;
12535
12536                 /* planes */
12537                 for_each_plane(dev_priv, pipe, plane) {
12538                         hw_entry = &hw_ddb.plane[pipe][plane];
12539                         sw_entry = &sw_ddb->plane[pipe][plane];
12540
12541                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12542                                 continue;
12543
12544                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12545                                   "(expected (%u,%u), found (%u,%u))\n",
12546                                   pipe_name(pipe), plane + 1,
12547                                   sw_entry->start, sw_entry->end,
12548                                   hw_entry->start, hw_entry->end);
12549                 }
12550
12551                 /* cursor */
12552                 hw_entry = &hw_ddb.cursor[pipe];
12553                 sw_entry = &sw_ddb->cursor[pipe];
12554
12555                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12556                         continue;
12557
12558                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12559                           "(expected (%u,%u), found (%u,%u))\n",
12560                           pipe_name(pipe),
12561                           sw_entry->start, sw_entry->end,
12562                           hw_entry->start, hw_entry->end);
12563         }
12564 }
12565
12566 static void
12567 check_connector_state(struct drm_device *dev,
12568                       struct drm_atomic_state *old_state)
12569 {
12570         struct drm_connector_state *old_conn_state;
12571         struct drm_connector *connector;
12572         int i;
12573
12574         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12575                 struct drm_encoder *encoder = connector->encoder;
12576                 struct drm_connector_state *state = connector->state;
12577
12578                 /* This also checks the encoder/connector hw state with the
12579                  * ->get_hw_state callbacks. */
12580                 intel_connector_check_state(to_intel_connector(connector));
12581
12582                 I915_STATE_WARN(state->best_encoder != encoder,
12583                      "connector's atomic encoder doesn't match legacy encoder\n");
12584         }
12585 }
12586
12587 static void
12588 check_encoder_state(struct drm_device *dev)
12589 {
12590         struct intel_encoder *encoder;
12591         struct intel_connector *connector;
12592
12593         for_each_intel_encoder(dev, encoder) {
12594                 bool enabled = false;
12595                 enum pipe pipe;
12596
12597                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12598                               encoder->base.base.id,
12599                               encoder->base.name);
12600
12601                 for_each_intel_connector(dev, connector) {
12602                         if (connector->base.state->best_encoder != &encoder->base)
12603                                 continue;
12604                         enabled = true;
12605
12606                         I915_STATE_WARN(connector->base.state->crtc !=
12607                                         encoder->base.crtc,
12608                              "connector's crtc doesn't match encoder crtc\n");
12609                 }
12610
12611                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12612                      "encoder's enabled state mismatch "
12613                      "(expected %i, found %i)\n",
12614                      !!encoder->base.crtc, enabled);
12615
12616                 if (!encoder->base.crtc) {
12617                         bool active;
12618
12619                         active = encoder->get_hw_state(encoder, &pipe);
12620                         I915_STATE_WARN(active,
12621                              "encoder detached but still enabled on pipe %c.\n",
12622                              pipe_name(pipe));
12623                 }
12624         }
12625 }
12626
12627 static void
12628 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12629 {
12630         struct drm_i915_private *dev_priv = dev->dev_private;
12631         struct intel_encoder *encoder;
12632         struct drm_crtc_state *old_crtc_state;
12633         struct drm_crtc *crtc;
12634         int i;
12635
12636         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12637                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12638                 struct intel_crtc_state *pipe_config, *sw_config;
12639                 bool active;
12640
12641                 if (!needs_modeset(crtc->state))
12642                         continue;
12643
12644                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12645                 pipe_config = to_intel_crtc_state(old_crtc_state);
12646                 memset(pipe_config, 0, sizeof(*pipe_config));
12647                 pipe_config->base.crtc = crtc;
12648                 pipe_config->base.state = old_state;
12649
12650                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12651                               crtc->base.id);
12652
12653                 active = dev_priv->display.get_pipe_config(intel_crtc,
12654                                                            pipe_config);
12655
12656                 /* hw state is inconsistent with the pipe quirk */
12657                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12658                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12659                         active = crtc->state->active;
12660
12661                 I915_STATE_WARN(crtc->state->active != active,
12662                      "crtc active state doesn't match with hw state "
12663                      "(expected %i, found %i)\n", crtc->state->active, active);
12664
12665                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12666                      "transitional active state does not match atomic hw state "
12667                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12668
12669                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12670                         enum pipe pipe;
12671
12672                         active = encoder->get_hw_state(encoder, &pipe);
12673                         I915_STATE_WARN(active != crtc->state->active,
12674                                 "[ENCODER:%i] active %i with crtc active %i\n",
12675                                 encoder->base.base.id, active, crtc->state->active);
12676
12677                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12678                                         "Encoder connected to wrong pipe %c\n",
12679                                         pipe_name(pipe));
12680
12681                         if (active)
12682                                 encoder->get_config(encoder, pipe_config);
12683                 }
12684
12685                 if (!crtc->state->active)
12686                         continue;
12687
12688                 sw_config = to_intel_crtc_state(crtc->state);
12689                 if (!intel_pipe_config_compare(dev, sw_config,
12690                                                pipe_config, false)) {
12691                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12692                         intel_dump_pipe_config(intel_crtc, pipe_config,
12693                                                "[hw state]");
12694                         intel_dump_pipe_config(intel_crtc, sw_config,
12695                                                "[sw state]");
12696                 }
12697         }
12698 }
12699
12700 static void
12701 check_shared_dpll_state(struct drm_device *dev)
12702 {
12703         struct drm_i915_private *dev_priv = dev->dev_private;
12704         struct intel_crtc *crtc;
12705         struct intel_dpll_hw_state dpll_hw_state;
12706         int i;
12707
12708         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12709                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12710                 int enabled_crtcs = 0, active_crtcs = 0;
12711                 bool active;
12712
12713                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12714
12715                 DRM_DEBUG_KMS("%s\n", pll->name);
12716
12717                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12718
12719                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12720                      "more active pll users than references: %i vs %i\n",
12721                      pll->active, hweight32(pll->config.crtc_mask));
12722                 I915_STATE_WARN(pll->active && !pll->on,
12723                      "pll in active use but not on in sw tracking\n");
12724                 I915_STATE_WARN(pll->on && !pll->active,
12725                      "pll in on but not on in use in sw tracking\n");
12726                 I915_STATE_WARN(pll->on != active,
12727                      "pll on state mismatch (expected %i, found %i)\n",
12728                      pll->on, active);
12729
12730                 for_each_intel_crtc(dev, crtc) {
12731                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12732                                 enabled_crtcs++;
12733                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12734                                 active_crtcs++;
12735                 }
12736                 I915_STATE_WARN(pll->active != active_crtcs,
12737                      "pll active crtcs mismatch (expected %i, found %i)\n",
12738                      pll->active, active_crtcs);
12739                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12740                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12741                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12742
12743                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12744                                        sizeof(dpll_hw_state)),
12745                      "pll hw state mismatch\n");
12746         }
12747 }
12748
12749 static void
12750 intel_modeset_check_state(struct drm_device *dev,
12751                           struct drm_atomic_state *old_state)
12752 {
12753         check_wm_state(dev);
12754         check_connector_state(dev, old_state);
12755         check_encoder_state(dev);
12756         check_crtc_state(dev, old_state);
12757         check_shared_dpll_state(dev);
12758 }
12759
12760 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12761                                      int dotclock)
12762 {
12763         /*
12764          * FDI already provided one idea for the dotclock.
12765          * Yell if the encoder disagrees.
12766          */
12767         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12768              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12769              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12770 }
12771
12772 static void update_scanline_offset(struct intel_crtc *crtc)
12773 {
12774         struct drm_device *dev = crtc->base.dev;
12775
12776         /*
12777          * The scanline counter increments at the leading edge of hsync.
12778          *
12779          * On most platforms it starts counting from vtotal-1 on the
12780          * first active line. That means the scanline counter value is
12781          * always one less than what we would expect. Ie. just after
12782          * start of vblank, which also occurs at start of hsync (on the
12783          * last active line), the scanline counter will read vblank_start-1.
12784          *
12785          * On gen2 the scanline counter starts counting from 1 instead
12786          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12787          * to keep the value positive), instead of adding one.
12788          *
12789          * On HSW+ the behaviour of the scanline counter depends on the output
12790          * type. For DP ports it behaves like most other platforms, but on HDMI
12791          * there's an extra 1 line difference. So we need to add two instead of
12792          * one to the value.
12793          */
12794         if (IS_GEN2(dev)) {
12795                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12796                 int vtotal;
12797
12798                 vtotal = mode->crtc_vtotal;
12799                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12800                         vtotal /= 2;
12801
12802                 crtc->scanline_offset = vtotal - 1;
12803         } else if (HAS_DDI(dev) &&
12804                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12805                 crtc->scanline_offset = 2;
12806         } else
12807                 crtc->scanline_offset = 1;
12808 }
12809
12810 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12811 {
12812         struct drm_device *dev = state->dev;
12813         struct drm_i915_private *dev_priv = to_i915(dev);
12814         struct intel_shared_dpll_config *shared_dpll = NULL;
12815         struct intel_crtc *intel_crtc;
12816         struct intel_crtc_state *intel_crtc_state;
12817         struct drm_crtc *crtc;
12818         struct drm_crtc_state *crtc_state;
12819         int i;
12820
12821         if (!dev_priv->display.crtc_compute_clock)
12822                 return;
12823
12824         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12825                 int dpll;
12826
12827                 intel_crtc = to_intel_crtc(crtc);
12828                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12829                 dpll = intel_crtc_state->shared_dpll;
12830
12831                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12832                         continue;
12833
12834                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12835
12836                 if (!shared_dpll)
12837                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12838
12839                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12840         }
12841 }
12842
12843 /*
12844  * This implements the workaround described in the "notes" section of the mode
12845  * set sequence documentation. When going from no pipes or single pipe to
12846  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12847  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12848  */
12849 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12850 {
12851         struct drm_crtc_state *crtc_state;
12852         struct intel_crtc *intel_crtc;
12853         struct drm_crtc *crtc;
12854         struct intel_crtc_state *first_crtc_state = NULL;
12855         struct intel_crtc_state *other_crtc_state = NULL;
12856         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12857         int i;
12858
12859         /* look at all crtc's that are going to be enabled in during modeset */
12860         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12861                 intel_crtc = to_intel_crtc(crtc);
12862
12863                 if (!crtc_state->active || !needs_modeset(crtc_state))
12864                         continue;
12865
12866                 if (first_crtc_state) {
12867                         other_crtc_state = to_intel_crtc_state(crtc_state);
12868                         break;
12869                 } else {
12870                         first_crtc_state = to_intel_crtc_state(crtc_state);
12871                         first_pipe = intel_crtc->pipe;
12872                 }
12873         }
12874
12875         /* No workaround needed? */
12876         if (!first_crtc_state)
12877                 return 0;
12878
12879         /* w/a possibly needed, check how many crtc's are already enabled. */
12880         for_each_intel_crtc(state->dev, intel_crtc) {
12881                 struct intel_crtc_state *pipe_config;
12882
12883                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12884                 if (IS_ERR(pipe_config))
12885                         return PTR_ERR(pipe_config);
12886
12887                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12888
12889                 if (!pipe_config->base.active ||
12890                     needs_modeset(&pipe_config->base))
12891                         continue;
12892
12893                 /* 2 or more enabled crtcs means no need for w/a */
12894                 if (enabled_pipe != INVALID_PIPE)
12895                         return 0;
12896
12897                 enabled_pipe = intel_crtc->pipe;
12898         }
12899
12900         if (enabled_pipe != INVALID_PIPE)
12901                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12902         else if (other_crtc_state)
12903                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12904
12905         return 0;
12906 }
12907
12908 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12909 {
12910         struct drm_crtc *crtc;
12911         struct drm_crtc_state *crtc_state;
12912         int ret = 0;
12913
12914         /* add all active pipes to the state */
12915         for_each_crtc(state->dev, crtc) {
12916                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12917                 if (IS_ERR(crtc_state))
12918                         return PTR_ERR(crtc_state);
12919
12920                 if (!crtc_state->active || needs_modeset(crtc_state))
12921                         continue;
12922
12923                 crtc_state->mode_changed = true;
12924
12925                 ret = drm_atomic_add_affected_connectors(state, crtc);
12926                 if (ret)
12927                         break;
12928
12929                 ret = drm_atomic_add_affected_planes(state, crtc);
12930                 if (ret)
12931                         break;
12932         }
12933
12934         return ret;
12935 }
12936
12937
12938 static int intel_modeset_checks(struct drm_atomic_state *state)
12939 {
12940         struct drm_device *dev = state->dev;
12941         struct drm_i915_private *dev_priv = dev->dev_private;
12942         int ret;
12943
12944         if (!check_digital_port_conflicts(state)) {
12945                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12946                 return -EINVAL;
12947         }
12948
12949         /*
12950          * See if the config requires any additional preparation, e.g.
12951          * to adjust global state with pipes off.  We need to do this
12952          * here so we can get the modeset_pipe updated config for the new
12953          * mode set on this crtc.  For other crtcs we need to use the
12954          * adjusted_mode bits in the crtc directly.
12955          */
12956         if (dev_priv->display.modeset_calc_cdclk) {
12957                 unsigned int cdclk;
12958
12959                 ret = dev_priv->display.modeset_calc_cdclk(state);
12960
12961                 cdclk = to_intel_atomic_state(state)->cdclk;
12962                 if (!ret && cdclk != dev_priv->cdclk_freq)
12963                         ret = intel_modeset_all_pipes(state);
12964
12965                 if (ret < 0)
12966                         return ret;
12967         } else
12968                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
12969
12970         intel_modeset_clear_plls(state);
12971
12972         if (IS_HASWELL(dev))
12973                 return haswell_mode_set_planes_workaround(state);
12974
12975         return 0;
12976 }
12977
12978 /**
12979  * intel_atomic_check - validate state object
12980  * @dev: drm device
12981  * @state: state to validate
12982  */
12983 static int intel_atomic_check(struct drm_device *dev,
12984                               struct drm_atomic_state *state)
12985 {
12986         struct drm_crtc *crtc;
12987         struct drm_crtc_state *crtc_state;
12988         int ret, i;
12989         bool any_ms = false;
12990
12991         ret = drm_atomic_helper_check_modeset(dev, state);
12992         if (ret)
12993                 return ret;
12994
12995         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12996                 struct intel_crtc_state *pipe_config =
12997                         to_intel_crtc_state(crtc_state);
12998
12999                 /* Catch I915_MODE_FLAG_INHERITED */
13000                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13001                         crtc_state->mode_changed = true;
13002
13003                 if (!crtc_state->enable) {
13004                         if (needs_modeset(crtc_state))
13005                                 any_ms = true;
13006                         continue;
13007                 }
13008
13009                 if (!needs_modeset(crtc_state))
13010                         continue;
13011
13012                 /* FIXME: For only active_changed we shouldn't need to do any
13013                  * state recomputation at all. */
13014
13015                 ret = drm_atomic_add_affected_connectors(state, crtc);
13016                 if (ret)
13017                         return ret;
13018
13019                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13020                 if (ret)
13021                         return ret;
13022
13023                 if (i915.fastboot &&
13024                     intel_pipe_config_compare(state->dev,
13025                                         to_intel_crtc_state(crtc->state),
13026                                         pipe_config, true)) {
13027                         crtc_state->mode_changed = false;
13028                 }
13029
13030                 if (needs_modeset(crtc_state)) {
13031                         any_ms = true;
13032
13033                         ret = drm_atomic_add_affected_planes(state, crtc);
13034                         if (ret)
13035                                 return ret;
13036                 }
13037
13038                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13039                                        needs_modeset(crtc_state) ?
13040                                        "[modeset]" : "[fastset]");
13041         }
13042
13043         if (any_ms) {
13044                 ret = intel_modeset_checks(state);
13045
13046                 if (ret)
13047                         return ret;
13048         } else
13049                 to_intel_atomic_state(state)->cdclk =
13050                         to_i915(state->dev)->cdclk_freq;
13051
13052         return drm_atomic_helper_check_planes(state->dev, state);
13053 }
13054
13055 /**
13056  * intel_atomic_commit - commit validated state object
13057  * @dev: DRM device
13058  * @state: the top-level driver state object
13059  * @async: asynchronous commit
13060  *
13061  * This function commits a top-level state object that has been validated
13062  * with drm_atomic_helper_check().
13063  *
13064  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13065  * we can only handle plane-related operations and do not yet support
13066  * asynchronous commit.
13067  *
13068  * RETURNS
13069  * Zero for success or -errno.
13070  */
13071 static int intel_atomic_commit(struct drm_device *dev,
13072                                struct drm_atomic_state *state,
13073                                bool async)
13074 {
13075         struct drm_i915_private *dev_priv = dev->dev_private;
13076         struct drm_crtc *crtc;
13077         struct drm_crtc_state *crtc_state;
13078         int ret = 0;
13079         int i;
13080         bool any_ms = false;
13081
13082         if (async) {
13083                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13084                 return -EINVAL;
13085         }
13086
13087         ret = drm_atomic_helper_prepare_planes(dev, state);
13088         if (ret)
13089                 return ret;
13090
13091         drm_atomic_helper_swap_state(dev, state);
13092
13093         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13094                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13095
13096                 if (!needs_modeset(crtc->state))
13097                         continue;
13098
13099                 any_ms = true;
13100                 intel_pre_plane_update(intel_crtc);
13101
13102                 if (crtc_state->active) {
13103                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13104                         dev_priv->display.crtc_disable(crtc);
13105                         intel_crtc->active = false;
13106                         intel_disable_shared_dpll(intel_crtc);
13107                 }
13108         }
13109
13110         /* Only after disabling all output pipelines that will be changed can we
13111          * update the the output configuration. */
13112         intel_modeset_update_crtc_state(state);
13113
13114         if (any_ms) {
13115                 intel_shared_dpll_commit(state);
13116
13117                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13118                 modeset_update_crtc_power_domains(state);
13119         }
13120
13121         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13122         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13123                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13124                 bool modeset = needs_modeset(crtc->state);
13125
13126                 if (modeset && crtc->state->active) {
13127                         update_scanline_offset(to_intel_crtc(crtc));
13128                         dev_priv->display.crtc_enable(crtc);
13129                 }
13130
13131                 if (!modeset)
13132                         intel_pre_plane_update(intel_crtc);
13133
13134                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13135                 intel_post_plane_update(intel_crtc);
13136         }
13137
13138         /* FIXME: add subpixel order */
13139
13140         drm_atomic_helper_wait_for_vblanks(dev, state);
13141         drm_atomic_helper_cleanup_planes(dev, state);
13142
13143         if (any_ms)
13144                 intel_modeset_check_state(dev, state);
13145
13146         drm_atomic_state_free(state);
13147
13148         return 0;
13149 }
13150
13151 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13152 {
13153         struct drm_device *dev = crtc->dev;
13154         struct drm_atomic_state *state;
13155         struct drm_crtc_state *crtc_state;
13156         int ret;
13157
13158         state = drm_atomic_state_alloc(dev);
13159         if (!state) {
13160                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13161                               crtc->base.id);
13162                 return;
13163         }
13164
13165         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13166
13167 retry:
13168         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13169         ret = PTR_ERR_OR_ZERO(crtc_state);
13170         if (!ret) {
13171                 if (!crtc_state->active)
13172                         goto out;
13173
13174                 crtc_state->mode_changed = true;
13175                 ret = drm_atomic_commit(state);
13176         }
13177
13178         if (ret == -EDEADLK) {
13179                 drm_atomic_state_clear(state);
13180                 drm_modeset_backoff(state->acquire_ctx);
13181                 goto retry;
13182         }
13183
13184         if (ret)
13185 out:
13186                 drm_atomic_state_free(state);
13187 }
13188
13189 #undef for_each_intel_crtc_masked
13190
13191 static const struct drm_crtc_funcs intel_crtc_funcs = {
13192         .gamma_set = intel_crtc_gamma_set,
13193         .set_config = drm_atomic_helper_set_config,
13194         .destroy = intel_crtc_destroy,
13195         .page_flip = intel_crtc_page_flip,
13196         .atomic_duplicate_state = intel_crtc_duplicate_state,
13197         .atomic_destroy_state = intel_crtc_destroy_state,
13198 };
13199
13200 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13201                                       struct intel_shared_dpll *pll,
13202                                       struct intel_dpll_hw_state *hw_state)
13203 {
13204         uint32_t val;
13205
13206         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13207                 return false;
13208
13209         val = I915_READ(PCH_DPLL(pll->id));
13210         hw_state->dpll = val;
13211         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13212         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13213
13214         return val & DPLL_VCO_ENABLE;
13215 }
13216
13217 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13218                                   struct intel_shared_dpll *pll)
13219 {
13220         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13221         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13222 }
13223
13224 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13225                                 struct intel_shared_dpll *pll)
13226 {
13227         /* PCH refclock must be enabled first */
13228         ibx_assert_pch_refclk_enabled(dev_priv);
13229
13230         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13231
13232         /* Wait for the clocks to stabilize. */
13233         POSTING_READ(PCH_DPLL(pll->id));
13234         udelay(150);
13235
13236         /* The pixel multiplier can only be updated once the
13237          * DPLL is enabled and the clocks are stable.
13238          *
13239          * So write it again.
13240          */
13241         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13242         POSTING_READ(PCH_DPLL(pll->id));
13243         udelay(200);
13244 }
13245
13246 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13247                                  struct intel_shared_dpll *pll)
13248 {
13249         struct drm_device *dev = dev_priv->dev;
13250         struct intel_crtc *crtc;
13251
13252         /* Make sure no transcoder isn't still depending on us. */
13253         for_each_intel_crtc(dev, crtc) {
13254                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13255                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13256         }
13257
13258         I915_WRITE(PCH_DPLL(pll->id), 0);
13259         POSTING_READ(PCH_DPLL(pll->id));
13260         udelay(200);
13261 }
13262
13263 static char *ibx_pch_dpll_names[] = {
13264         "PCH DPLL A",
13265         "PCH DPLL B",
13266 };
13267
13268 static void ibx_pch_dpll_init(struct drm_device *dev)
13269 {
13270         struct drm_i915_private *dev_priv = dev->dev_private;
13271         int i;
13272
13273         dev_priv->num_shared_dpll = 2;
13274
13275         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13276                 dev_priv->shared_dplls[i].id = i;
13277                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13278                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13279                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13280                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13281                 dev_priv->shared_dplls[i].get_hw_state =
13282                         ibx_pch_dpll_get_hw_state;
13283         }
13284 }
13285
13286 static void intel_shared_dpll_init(struct drm_device *dev)
13287 {
13288         struct drm_i915_private *dev_priv = dev->dev_private;
13289
13290         intel_update_cdclk(dev);
13291
13292         if (HAS_DDI(dev))
13293                 intel_ddi_pll_init(dev);
13294         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13295                 ibx_pch_dpll_init(dev);
13296         else
13297                 dev_priv->num_shared_dpll = 0;
13298
13299         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13300 }
13301
13302 /**
13303  * intel_prepare_plane_fb - Prepare fb for usage on plane
13304  * @plane: drm plane to prepare for
13305  * @fb: framebuffer to prepare for presentation
13306  *
13307  * Prepares a framebuffer for usage on a display plane.  Generally this
13308  * involves pinning the underlying object and updating the frontbuffer tracking
13309  * bits.  Some older platforms need special physical address handling for
13310  * cursor planes.
13311  *
13312  * Returns 0 on success, negative error code on failure.
13313  */
13314 int
13315 intel_prepare_plane_fb(struct drm_plane *plane,
13316                        struct drm_framebuffer *fb,
13317                        const struct drm_plane_state *new_state)
13318 {
13319         struct drm_device *dev = plane->dev;
13320         struct intel_plane *intel_plane = to_intel_plane(plane);
13321         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13322         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13323         int ret = 0;
13324
13325         if (!obj)
13326                 return 0;
13327
13328         mutex_lock(&dev->struct_mutex);
13329
13330         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13331             INTEL_INFO(dev)->cursor_needs_physical) {
13332                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13333                 ret = i915_gem_object_attach_phys(obj, align);
13334                 if (ret)
13335                         DRM_DEBUG_KMS("failed to attach phys object\n");
13336         } else {
13337                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13338         }
13339
13340         if (ret == 0)
13341                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13342
13343         mutex_unlock(&dev->struct_mutex);
13344
13345         return ret;
13346 }
13347
13348 /**
13349  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13350  * @plane: drm plane to clean up for
13351  * @fb: old framebuffer that was on plane
13352  *
13353  * Cleans up a framebuffer that has just been removed from a plane.
13354  */
13355 void
13356 intel_cleanup_plane_fb(struct drm_plane *plane,
13357                        struct drm_framebuffer *fb,
13358                        const struct drm_plane_state *old_state)
13359 {
13360         struct drm_device *dev = plane->dev;
13361         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13362
13363         if (WARN_ON(!obj))
13364                 return;
13365
13366         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13367             !INTEL_INFO(dev)->cursor_needs_physical) {
13368                 mutex_lock(&dev->struct_mutex);
13369                 intel_unpin_fb_obj(fb, old_state);
13370                 mutex_unlock(&dev->struct_mutex);
13371         }
13372 }
13373
13374 int
13375 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13376 {
13377         int max_scale;
13378         struct drm_device *dev;
13379         struct drm_i915_private *dev_priv;
13380         int crtc_clock, cdclk;
13381
13382         if (!intel_crtc || !crtc_state)
13383                 return DRM_PLANE_HELPER_NO_SCALING;
13384
13385         dev = intel_crtc->base.dev;
13386         dev_priv = dev->dev_private;
13387         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13388         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13389
13390         if (!crtc_clock || !cdclk)
13391                 return DRM_PLANE_HELPER_NO_SCALING;
13392
13393         /*
13394          * skl max scale is lower of:
13395          *    close to 3 but not 3, -1 is for that purpose
13396          *            or
13397          *    cdclk/crtc_clock
13398          */
13399         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13400
13401         return max_scale;
13402 }
13403
13404 static int
13405 intel_check_primary_plane(struct drm_plane *plane,
13406                           struct intel_crtc_state *crtc_state,
13407                           struct intel_plane_state *state)
13408 {
13409         struct drm_crtc *crtc = state->base.crtc;
13410         struct drm_framebuffer *fb = state->base.fb;
13411         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13412         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13413         bool can_position = false;
13414
13415         /* use scaler when colorkey is not required */
13416         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13417             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13418                 min_scale = 1;
13419                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13420                 can_position = true;
13421         }
13422
13423         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13424                                              &state->dst, &state->clip,
13425                                              min_scale, max_scale,
13426                                              can_position, true,
13427                                              &state->visible);
13428 }
13429
13430 static void
13431 intel_commit_primary_plane(struct drm_plane *plane,
13432                            struct intel_plane_state *state)
13433 {
13434         struct drm_crtc *crtc = state->base.crtc;
13435         struct drm_framebuffer *fb = state->base.fb;
13436         struct drm_device *dev = plane->dev;
13437         struct drm_i915_private *dev_priv = dev->dev_private;
13438         struct intel_crtc *intel_crtc;
13439         struct drm_rect *src = &state->src;
13440
13441         crtc = crtc ? crtc : plane->crtc;
13442         intel_crtc = to_intel_crtc(crtc);
13443
13444         plane->fb = fb;
13445         crtc->x = src->x1 >> 16;
13446         crtc->y = src->y1 >> 16;
13447
13448         if (!crtc->state->active)
13449                 return;
13450
13451         if (state->visible)
13452                 /* FIXME: kill this fastboot hack */
13453                 intel_update_pipe_size(intel_crtc);
13454
13455         dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13456 }
13457
13458 static void
13459 intel_disable_primary_plane(struct drm_plane *plane,
13460                             struct drm_crtc *crtc)
13461 {
13462         struct drm_device *dev = plane->dev;
13463         struct drm_i915_private *dev_priv = dev->dev_private;
13464
13465         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13466 }
13467
13468 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13469                                     struct drm_crtc_state *old_crtc_state)
13470 {
13471         struct drm_device *dev = crtc->dev;
13472         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13473
13474         if (intel_crtc->atomic.update_wm_pre)
13475                 intel_update_watermarks(crtc);
13476
13477         /* Perform vblank evasion around commit operation */
13478         if (crtc->state->active)
13479                 intel_pipe_update_start(intel_crtc, &intel_crtc->start_vbl_count);
13480
13481         if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13482                 skl_detach_scalers(intel_crtc);
13483 }
13484
13485 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13486                                      struct drm_crtc_state *old_crtc_state)
13487 {
13488         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13489
13490         if (crtc->state->active)
13491                 intel_pipe_update_end(intel_crtc, intel_crtc->start_vbl_count);
13492 }
13493
13494 /**
13495  * intel_plane_destroy - destroy a plane
13496  * @plane: plane to destroy
13497  *
13498  * Common destruction function for all types of planes (primary, cursor,
13499  * sprite).
13500  */
13501 void intel_plane_destroy(struct drm_plane *plane)
13502 {
13503         struct intel_plane *intel_plane = to_intel_plane(plane);
13504         drm_plane_cleanup(plane);
13505         kfree(intel_plane);
13506 }
13507
13508 const struct drm_plane_funcs intel_plane_funcs = {
13509         .update_plane = drm_atomic_helper_update_plane,
13510         .disable_plane = drm_atomic_helper_disable_plane,
13511         .destroy = intel_plane_destroy,
13512         .set_property = drm_atomic_helper_plane_set_property,
13513         .atomic_get_property = intel_plane_atomic_get_property,
13514         .atomic_set_property = intel_plane_atomic_set_property,
13515         .atomic_duplicate_state = intel_plane_duplicate_state,
13516         .atomic_destroy_state = intel_plane_destroy_state,
13517
13518 };
13519
13520 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13521                                                     int pipe)
13522 {
13523         struct intel_plane *primary;
13524         struct intel_plane_state *state;
13525         const uint32_t *intel_primary_formats;
13526         unsigned int num_formats;
13527
13528         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13529         if (primary == NULL)
13530                 return NULL;
13531
13532         state = intel_create_plane_state(&primary->base);
13533         if (!state) {
13534                 kfree(primary);
13535                 return NULL;
13536         }
13537         primary->base.state = &state->base;
13538
13539         primary->can_scale = false;
13540         primary->max_downscale = 1;
13541         if (INTEL_INFO(dev)->gen >= 9) {
13542                 primary->can_scale = true;
13543                 state->scaler_id = -1;
13544         }
13545         primary->pipe = pipe;
13546         primary->plane = pipe;
13547         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13548         primary->check_plane = intel_check_primary_plane;
13549         primary->commit_plane = intel_commit_primary_plane;
13550         primary->disable_plane = intel_disable_primary_plane;
13551         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13552                 primary->plane = !pipe;
13553
13554         if (INTEL_INFO(dev)->gen >= 9) {
13555                 intel_primary_formats = skl_primary_formats;
13556                 num_formats = ARRAY_SIZE(skl_primary_formats);
13557         } else if (INTEL_INFO(dev)->gen >= 4) {
13558                 intel_primary_formats = i965_primary_formats;
13559                 num_formats = ARRAY_SIZE(i965_primary_formats);
13560         } else {
13561                 intel_primary_formats = i8xx_primary_formats;
13562                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13563         }
13564
13565         drm_universal_plane_init(dev, &primary->base, 0,
13566                                  &intel_plane_funcs,
13567                                  intel_primary_formats, num_formats,
13568                                  DRM_PLANE_TYPE_PRIMARY);
13569
13570         if (INTEL_INFO(dev)->gen >= 4)
13571                 intel_create_rotation_property(dev, primary);
13572
13573         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13574
13575         return &primary->base;
13576 }
13577
13578 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13579 {
13580         if (!dev->mode_config.rotation_property) {
13581                 unsigned long flags = BIT(DRM_ROTATE_0) |
13582                         BIT(DRM_ROTATE_180);
13583
13584                 if (INTEL_INFO(dev)->gen >= 9)
13585                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13586
13587                 dev->mode_config.rotation_property =
13588                         drm_mode_create_rotation_property(dev, flags);
13589         }
13590         if (dev->mode_config.rotation_property)
13591                 drm_object_attach_property(&plane->base.base,
13592                                 dev->mode_config.rotation_property,
13593                                 plane->base.state->rotation);
13594 }
13595
13596 static int
13597 intel_check_cursor_plane(struct drm_plane *plane,
13598                          struct intel_crtc_state *crtc_state,
13599                          struct intel_plane_state *state)
13600 {
13601         struct drm_crtc *crtc = crtc_state->base.crtc;
13602         struct drm_framebuffer *fb = state->base.fb;
13603         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13604         unsigned stride;
13605         int ret;
13606
13607         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13608                                             &state->dst, &state->clip,
13609                                             DRM_PLANE_HELPER_NO_SCALING,
13610                                             DRM_PLANE_HELPER_NO_SCALING,
13611                                             true, true, &state->visible);
13612         if (ret)
13613                 return ret;
13614
13615         /* if we want to turn off the cursor ignore width and height */
13616         if (!obj)
13617                 return 0;
13618
13619         /* Check for which cursor types we support */
13620         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13621                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13622                           state->base.crtc_w, state->base.crtc_h);
13623                 return -EINVAL;
13624         }
13625
13626         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13627         if (obj->base.size < stride * state->base.crtc_h) {
13628                 DRM_DEBUG_KMS("buffer is too small\n");
13629                 return -ENOMEM;
13630         }
13631
13632         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13633                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13634                 return -EINVAL;
13635         }
13636
13637         return 0;
13638 }
13639
13640 static void
13641 intel_disable_cursor_plane(struct drm_plane *plane,
13642                            struct drm_crtc *crtc)
13643 {
13644         intel_crtc_update_cursor(crtc, false);
13645 }
13646
13647 static void
13648 intel_commit_cursor_plane(struct drm_plane *plane,
13649                           struct intel_plane_state *state)
13650 {
13651         struct drm_crtc *crtc = state->base.crtc;
13652         struct drm_device *dev = plane->dev;
13653         struct intel_crtc *intel_crtc;
13654         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13655         uint32_t addr;
13656
13657         crtc = crtc ? crtc : plane->crtc;
13658         intel_crtc = to_intel_crtc(crtc);
13659
13660         plane->fb = state->base.fb;
13661         crtc->cursor_x = state->base.crtc_x;
13662         crtc->cursor_y = state->base.crtc_y;
13663
13664         if (intel_crtc->cursor_bo == obj)
13665                 goto update;
13666
13667         if (!obj)
13668                 addr = 0;
13669         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13670                 addr = i915_gem_obj_ggtt_offset(obj);
13671         else
13672                 addr = obj->phys_handle->busaddr;
13673
13674         intel_crtc->cursor_addr = addr;
13675         intel_crtc->cursor_bo = obj;
13676
13677 update:
13678         if (crtc->state->active)
13679                 intel_crtc_update_cursor(crtc, state->visible);
13680 }
13681
13682 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13683                                                    int pipe)
13684 {
13685         struct intel_plane *cursor;
13686         struct intel_plane_state *state;
13687
13688         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13689         if (cursor == NULL)
13690                 return NULL;
13691
13692         state = intel_create_plane_state(&cursor->base);
13693         if (!state) {
13694                 kfree(cursor);
13695                 return NULL;
13696         }
13697         cursor->base.state = &state->base;
13698
13699         cursor->can_scale = false;
13700         cursor->max_downscale = 1;
13701         cursor->pipe = pipe;
13702         cursor->plane = pipe;
13703         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13704         cursor->check_plane = intel_check_cursor_plane;
13705         cursor->commit_plane = intel_commit_cursor_plane;
13706         cursor->disable_plane = intel_disable_cursor_plane;
13707
13708         drm_universal_plane_init(dev, &cursor->base, 0,
13709                                  &intel_plane_funcs,
13710                                  intel_cursor_formats,
13711                                  ARRAY_SIZE(intel_cursor_formats),
13712                                  DRM_PLANE_TYPE_CURSOR);
13713
13714         if (INTEL_INFO(dev)->gen >= 4) {
13715                 if (!dev->mode_config.rotation_property)
13716                         dev->mode_config.rotation_property =
13717                                 drm_mode_create_rotation_property(dev,
13718                                                         BIT(DRM_ROTATE_0) |
13719                                                         BIT(DRM_ROTATE_180));
13720                 if (dev->mode_config.rotation_property)
13721                         drm_object_attach_property(&cursor->base.base,
13722                                 dev->mode_config.rotation_property,
13723                                 state->base.rotation);
13724         }
13725
13726         if (INTEL_INFO(dev)->gen >=9)
13727                 state->scaler_id = -1;
13728
13729         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13730
13731         return &cursor->base;
13732 }
13733
13734 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13735         struct intel_crtc_state *crtc_state)
13736 {
13737         int i;
13738         struct intel_scaler *intel_scaler;
13739         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13740
13741         for (i = 0; i < intel_crtc->num_scalers; i++) {
13742                 intel_scaler = &scaler_state->scalers[i];
13743                 intel_scaler->in_use = 0;
13744                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13745         }
13746
13747         scaler_state->scaler_id = -1;
13748 }
13749
13750 static void intel_crtc_init(struct drm_device *dev, int pipe)
13751 {
13752         struct drm_i915_private *dev_priv = dev->dev_private;
13753         struct intel_crtc *intel_crtc;
13754         struct intel_crtc_state *crtc_state = NULL;
13755         struct drm_plane *primary = NULL;
13756         struct drm_plane *cursor = NULL;
13757         int i, ret;
13758
13759         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13760         if (intel_crtc == NULL)
13761                 return;
13762
13763         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13764         if (!crtc_state)
13765                 goto fail;
13766         intel_crtc->config = crtc_state;
13767         intel_crtc->base.state = &crtc_state->base;
13768         crtc_state->base.crtc = &intel_crtc->base;
13769
13770         /* initialize shared scalers */
13771         if (INTEL_INFO(dev)->gen >= 9) {
13772                 if (pipe == PIPE_C)
13773                         intel_crtc->num_scalers = 1;
13774                 else
13775                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13776
13777                 skl_init_scalers(dev, intel_crtc, crtc_state);
13778         }
13779
13780         primary = intel_primary_plane_create(dev, pipe);
13781         if (!primary)
13782                 goto fail;
13783
13784         cursor = intel_cursor_plane_create(dev, pipe);
13785         if (!cursor)
13786                 goto fail;
13787
13788         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13789                                         cursor, &intel_crtc_funcs);
13790         if (ret)
13791                 goto fail;
13792
13793         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13794         for (i = 0; i < 256; i++) {
13795                 intel_crtc->lut_r[i] = i;
13796                 intel_crtc->lut_g[i] = i;
13797                 intel_crtc->lut_b[i] = i;
13798         }
13799
13800         /*
13801          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13802          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13803          */
13804         intel_crtc->pipe = pipe;
13805         intel_crtc->plane = pipe;
13806         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13807                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13808                 intel_crtc->plane = !pipe;
13809         }
13810
13811         intel_crtc->cursor_base = ~0;
13812         intel_crtc->cursor_cntl = ~0;
13813         intel_crtc->cursor_size = ~0;
13814
13815         intel_crtc->wm.cxsr_allowed = true;
13816
13817         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13818                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13819         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13820         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13821
13822         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13823
13824         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13825         return;
13826
13827 fail:
13828         if (primary)
13829                 drm_plane_cleanup(primary);
13830         if (cursor)
13831                 drm_plane_cleanup(cursor);
13832         kfree(crtc_state);
13833         kfree(intel_crtc);
13834 }
13835
13836 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13837 {
13838         struct drm_encoder *encoder = connector->base.encoder;
13839         struct drm_device *dev = connector->base.dev;
13840
13841         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13842
13843         if (!encoder || WARN_ON(!encoder->crtc))
13844                 return INVALID_PIPE;
13845
13846         return to_intel_crtc(encoder->crtc)->pipe;
13847 }
13848
13849 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13850                                 struct drm_file *file)
13851 {
13852         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13853         struct drm_crtc *drmmode_crtc;
13854         struct intel_crtc *crtc;
13855
13856         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13857
13858         if (!drmmode_crtc) {
13859                 DRM_ERROR("no such CRTC id\n");
13860                 return -ENOENT;
13861         }
13862
13863         crtc = to_intel_crtc(drmmode_crtc);
13864         pipe_from_crtc_id->pipe = crtc->pipe;
13865
13866         return 0;
13867 }
13868
13869 static int intel_encoder_clones(struct intel_encoder *encoder)
13870 {
13871         struct drm_device *dev = encoder->base.dev;
13872         struct intel_encoder *source_encoder;
13873         int index_mask = 0;
13874         int entry = 0;
13875
13876         for_each_intel_encoder(dev, source_encoder) {
13877                 if (encoders_cloneable(encoder, source_encoder))
13878                         index_mask |= (1 << entry);
13879
13880                 entry++;
13881         }
13882
13883         return index_mask;
13884 }
13885
13886 static bool has_edp_a(struct drm_device *dev)
13887 {
13888         struct drm_i915_private *dev_priv = dev->dev_private;
13889
13890         if (!IS_MOBILE(dev))
13891                 return false;
13892
13893         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13894                 return false;
13895
13896         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13897                 return false;
13898
13899         return true;
13900 }
13901
13902 static bool intel_crt_present(struct drm_device *dev)
13903 {
13904         struct drm_i915_private *dev_priv = dev->dev_private;
13905
13906         if (INTEL_INFO(dev)->gen >= 9)
13907                 return false;
13908
13909         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13910                 return false;
13911
13912         if (IS_CHERRYVIEW(dev))
13913                 return false;
13914
13915         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13916                 return false;
13917
13918         return true;
13919 }
13920
13921 static void intel_setup_outputs(struct drm_device *dev)
13922 {
13923         struct drm_i915_private *dev_priv = dev->dev_private;
13924         struct intel_encoder *encoder;
13925         bool dpd_is_edp = false;
13926
13927         intel_lvds_init(dev);
13928
13929         if (intel_crt_present(dev))
13930                 intel_crt_init(dev);
13931
13932         if (IS_BROXTON(dev)) {
13933                 /*
13934                  * FIXME: Broxton doesn't support port detection via the
13935                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13936                  * detect the ports.
13937                  */
13938                 intel_ddi_init(dev, PORT_A);
13939                 intel_ddi_init(dev, PORT_B);
13940                 intel_ddi_init(dev, PORT_C);
13941         } else if (HAS_DDI(dev)) {
13942                 int found;
13943
13944                 /*
13945                  * Haswell uses DDI functions to detect digital outputs.
13946                  * On SKL pre-D0 the strap isn't connected, so we assume
13947                  * it's there.
13948                  */
13949                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13950                 /* WaIgnoreDDIAStrap: skl */
13951                 if (found || IS_SKYLAKE(dev))
13952                         intel_ddi_init(dev, PORT_A);
13953
13954                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13955                  * register */
13956                 found = I915_READ(SFUSE_STRAP);
13957
13958                 if (found & SFUSE_STRAP_DDIB_DETECTED)
13959                         intel_ddi_init(dev, PORT_B);
13960                 if (found & SFUSE_STRAP_DDIC_DETECTED)
13961                         intel_ddi_init(dev, PORT_C);
13962                 if (found & SFUSE_STRAP_DDID_DETECTED)
13963                         intel_ddi_init(dev, PORT_D);
13964                 /*
13965                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13966                  */
13967                 if (IS_SKYLAKE(dev) &&
13968                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13969                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13970                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13971                         intel_ddi_init(dev, PORT_E);
13972
13973         } else if (HAS_PCH_SPLIT(dev)) {
13974                 int found;
13975                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13976
13977                 if (has_edp_a(dev))
13978                         intel_dp_init(dev, DP_A, PORT_A);
13979
13980                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13981                         /* PCH SDVOB multiplex with HDMIB */
13982                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
13983                         if (!found)
13984                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13985                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13986                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
13987                 }
13988
13989                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13990                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13991
13992                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13993                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13994
13995                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13996                         intel_dp_init(dev, PCH_DP_C, PORT_C);
13997
13998                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13999                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14000         } else if (IS_VALLEYVIEW(dev)) {
14001                 /*
14002                  * The DP_DETECTED bit is the latched state of the DDC
14003                  * SDA pin at boot. However since eDP doesn't require DDC
14004                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14005                  * eDP ports may have been muxed to an alternate function.
14006                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14007                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14008                  * detect eDP ports.
14009                  */
14010                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14011                     !intel_dp_is_edp(dev, PORT_B))
14012                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14013                                         PORT_B);
14014                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14015                     intel_dp_is_edp(dev, PORT_B))
14016                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14017
14018                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14019                     !intel_dp_is_edp(dev, PORT_C))
14020                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14021                                         PORT_C);
14022                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14023                     intel_dp_is_edp(dev, PORT_C))
14024                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14025
14026                 if (IS_CHERRYVIEW(dev)) {
14027                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14028                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14029                                                 PORT_D);
14030                         /* eDP not supported on port D, so don't check VBT */
14031                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14032                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14033                 }
14034
14035                 intel_dsi_init(dev);
14036         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14037                 bool found = false;
14038
14039                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14040                         DRM_DEBUG_KMS("probing SDVOB\n");
14041                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14042                         if (!found && IS_G4X(dev)) {
14043                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14044                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14045                         }
14046
14047                         if (!found && IS_G4X(dev))
14048                                 intel_dp_init(dev, DP_B, PORT_B);
14049                 }
14050
14051                 /* Before G4X SDVOC doesn't have its own detect register */
14052
14053                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14054                         DRM_DEBUG_KMS("probing SDVOC\n");
14055                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14056                 }
14057
14058                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14059
14060                         if (IS_G4X(dev)) {
14061                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14062                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14063                         }
14064                         if (IS_G4X(dev))
14065                                 intel_dp_init(dev, DP_C, PORT_C);
14066                 }
14067
14068                 if (IS_G4X(dev) &&
14069                     (I915_READ(DP_D) & DP_DETECTED))
14070                         intel_dp_init(dev, DP_D, PORT_D);
14071         } else if (IS_GEN2(dev))
14072                 intel_dvo_init(dev);
14073
14074         if (SUPPORTS_TV(dev))
14075                 intel_tv_init(dev);
14076
14077         intel_psr_init(dev);
14078
14079         for_each_intel_encoder(dev, encoder) {
14080                 encoder->base.possible_crtcs = encoder->crtc_mask;
14081                 encoder->base.possible_clones =
14082                         intel_encoder_clones(encoder);
14083         }
14084
14085         intel_init_pch_refclk(dev);
14086
14087         drm_helper_move_panel_connectors_to_head(dev);
14088 }
14089
14090 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14091 {
14092         struct drm_device *dev = fb->dev;
14093         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14094
14095         drm_framebuffer_cleanup(fb);
14096         mutex_lock(&dev->struct_mutex);
14097         WARN_ON(!intel_fb->obj->framebuffer_references--);
14098         drm_gem_object_unreference(&intel_fb->obj->base);
14099         mutex_unlock(&dev->struct_mutex);
14100         kfree(intel_fb);
14101 }
14102
14103 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14104                                                 struct drm_file *file,
14105                                                 unsigned int *handle)
14106 {
14107         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14108         struct drm_i915_gem_object *obj = intel_fb->obj;
14109
14110         return drm_gem_handle_create(file, &obj->base, handle);
14111 }
14112
14113 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14114                                         struct drm_file *file,
14115                                         unsigned flags, unsigned color,
14116                                         struct drm_clip_rect *clips,
14117                                         unsigned num_clips)
14118 {
14119         struct drm_device *dev = fb->dev;
14120         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14121         struct drm_i915_gem_object *obj = intel_fb->obj;
14122
14123         mutex_lock(&dev->struct_mutex);
14124         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14125         mutex_unlock(&dev->struct_mutex);
14126
14127         return 0;
14128 }
14129
14130 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14131         .destroy = intel_user_framebuffer_destroy,
14132         .create_handle = intel_user_framebuffer_create_handle,
14133         .dirty = intel_user_framebuffer_dirty,
14134 };
14135
14136 static
14137 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14138                          uint32_t pixel_format)
14139 {
14140         u32 gen = INTEL_INFO(dev)->gen;
14141
14142         if (gen >= 9) {
14143                 /* "The stride in bytes must not exceed the of the size of 8K
14144                  *  pixels and 32K bytes."
14145                  */
14146                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14147         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14148                 return 32*1024;
14149         } else if (gen >= 4) {
14150                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14151                         return 16*1024;
14152                 else
14153                         return 32*1024;
14154         } else if (gen >= 3) {
14155                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14156                         return 8*1024;
14157                 else
14158                         return 16*1024;
14159         } else {
14160                 /* XXX DSPC is limited to 4k tiled */
14161                 return 8*1024;
14162         }
14163 }
14164
14165 static int intel_framebuffer_init(struct drm_device *dev,
14166                                   struct intel_framebuffer *intel_fb,
14167                                   struct drm_mode_fb_cmd2 *mode_cmd,
14168                                   struct drm_i915_gem_object *obj)
14169 {
14170         unsigned int aligned_height;
14171         int ret;
14172         u32 pitch_limit, stride_alignment;
14173
14174         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14175
14176         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14177                 /* Enforce that fb modifier and tiling mode match, but only for
14178                  * X-tiled. This is needed for FBC. */
14179                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14180                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14181                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14182                         return -EINVAL;
14183                 }
14184         } else {
14185                 if (obj->tiling_mode == I915_TILING_X)
14186                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14187                 else if (obj->tiling_mode == I915_TILING_Y) {
14188                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14189                         return -EINVAL;
14190                 }
14191         }
14192
14193         /* Passed in modifier sanity checking. */
14194         switch (mode_cmd->modifier[0]) {
14195         case I915_FORMAT_MOD_Y_TILED:
14196         case I915_FORMAT_MOD_Yf_TILED:
14197                 if (INTEL_INFO(dev)->gen < 9) {
14198                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14199                                   mode_cmd->modifier[0]);
14200                         return -EINVAL;
14201                 }
14202         case DRM_FORMAT_MOD_NONE:
14203         case I915_FORMAT_MOD_X_TILED:
14204                 break;
14205         default:
14206                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14207                           mode_cmd->modifier[0]);
14208                 return -EINVAL;
14209         }
14210
14211         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14212                                                      mode_cmd->pixel_format);
14213         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14214                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14215                           mode_cmd->pitches[0], stride_alignment);
14216                 return -EINVAL;
14217         }
14218
14219         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14220                                            mode_cmd->pixel_format);
14221         if (mode_cmd->pitches[0] > pitch_limit) {
14222                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14223                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14224                           "tiled" : "linear",
14225                           mode_cmd->pitches[0], pitch_limit);
14226                 return -EINVAL;
14227         }
14228
14229         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14230             mode_cmd->pitches[0] != obj->stride) {
14231                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14232                           mode_cmd->pitches[0], obj->stride);
14233                 return -EINVAL;
14234         }
14235
14236         /* Reject formats not supported by any plane early. */
14237         switch (mode_cmd->pixel_format) {
14238         case DRM_FORMAT_C8:
14239         case DRM_FORMAT_RGB565:
14240         case DRM_FORMAT_XRGB8888:
14241         case DRM_FORMAT_ARGB8888:
14242                 break;
14243         case DRM_FORMAT_XRGB1555:
14244                 if (INTEL_INFO(dev)->gen > 3) {
14245                         DRM_DEBUG("unsupported pixel format: %s\n",
14246                                   drm_get_format_name(mode_cmd->pixel_format));
14247                         return -EINVAL;
14248                 }
14249                 break;
14250         case DRM_FORMAT_ABGR8888:
14251                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14252                         DRM_DEBUG("unsupported pixel format: %s\n",
14253                                   drm_get_format_name(mode_cmd->pixel_format));
14254                         return -EINVAL;
14255                 }
14256                 break;
14257         case DRM_FORMAT_XBGR8888:
14258         case DRM_FORMAT_XRGB2101010:
14259         case DRM_FORMAT_XBGR2101010:
14260                 if (INTEL_INFO(dev)->gen < 4) {
14261                         DRM_DEBUG("unsupported pixel format: %s\n",
14262                                   drm_get_format_name(mode_cmd->pixel_format));
14263                         return -EINVAL;
14264                 }
14265                 break;
14266         case DRM_FORMAT_ABGR2101010:
14267                 if (!IS_VALLEYVIEW(dev)) {
14268                         DRM_DEBUG("unsupported pixel format: %s\n",
14269                                   drm_get_format_name(mode_cmd->pixel_format));
14270                         return -EINVAL;
14271                 }
14272                 break;
14273         case DRM_FORMAT_YUYV:
14274         case DRM_FORMAT_UYVY:
14275         case DRM_FORMAT_YVYU:
14276         case DRM_FORMAT_VYUY:
14277                 if (INTEL_INFO(dev)->gen < 5) {
14278                         DRM_DEBUG("unsupported pixel format: %s\n",
14279                                   drm_get_format_name(mode_cmd->pixel_format));
14280                         return -EINVAL;
14281                 }
14282                 break;
14283         default:
14284                 DRM_DEBUG("unsupported pixel format: %s\n",
14285                           drm_get_format_name(mode_cmd->pixel_format));
14286                 return -EINVAL;
14287         }
14288
14289         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14290         if (mode_cmd->offsets[0] != 0)
14291                 return -EINVAL;
14292
14293         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14294                                                mode_cmd->pixel_format,
14295                                                mode_cmd->modifier[0]);
14296         /* FIXME drm helper for size checks (especially planar formats)? */
14297         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14298                 return -EINVAL;
14299
14300         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14301         intel_fb->obj = obj;
14302         intel_fb->obj->framebuffer_references++;
14303
14304         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14305         if (ret) {
14306                 DRM_ERROR("framebuffer init failed %d\n", ret);
14307                 return ret;
14308         }
14309
14310         return 0;
14311 }
14312
14313 static struct drm_framebuffer *
14314 intel_user_framebuffer_create(struct drm_device *dev,
14315                               struct drm_file *filp,
14316                               struct drm_mode_fb_cmd2 *mode_cmd)
14317 {
14318         struct drm_i915_gem_object *obj;
14319
14320         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14321                                                 mode_cmd->handles[0]));
14322         if (&obj->base == NULL)
14323                 return ERR_PTR(-ENOENT);
14324
14325         return intel_framebuffer_create(dev, mode_cmd, obj);
14326 }
14327
14328 #ifndef CONFIG_DRM_FBDEV_EMULATION
14329 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14330 {
14331 }
14332 #endif
14333
14334 static const struct drm_mode_config_funcs intel_mode_funcs = {
14335         .fb_create = intel_user_framebuffer_create,
14336         .output_poll_changed = intel_fbdev_output_poll_changed,
14337         .atomic_check = intel_atomic_check,
14338         .atomic_commit = intel_atomic_commit,
14339         .atomic_state_alloc = intel_atomic_state_alloc,
14340         .atomic_state_clear = intel_atomic_state_clear,
14341 };
14342
14343 /* Set up chip specific display functions */
14344 static void intel_init_display(struct drm_device *dev)
14345 {
14346         struct drm_i915_private *dev_priv = dev->dev_private;
14347
14348         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14349                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14350         else if (IS_CHERRYVIEW(dev))
14351                 dev_priv->display.find_dpll = chv_find_best_dpll;
14352         else if (IS_VALLEYVIEW(dev))
14353                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14354         else if (IS_PINEVIEW(dev))
14355                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14356         else
14357                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14358
14359         if (INTEL_INFO(dev)->gen >= 9) {
14360                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14361                 dev_priv->display.get_initial_plane_config =
14362                         skylake_get_initial_plane_config;
14363                 dev_priv->display.crtc_compute_clock =
14364                         haswell_crtc_compute_clock;
14365                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14366                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14367                 dev_priv->display.update_primary_plane =
14368                         skylake_update_primary_plane;
14369         } else if (HAS_DDI(dev)) {
14370                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14371                 dev_priv->display.get_initial_plane_config =
14372                         ironlake_get_initial_plane_config;
14373                 dev_priv->display.crtc_compute_clock =
14374                         haswell_crtc_compute_clock;
14375                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14376                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14377                 dev_priv->display.update_primary_plane =
14378                         ironlake_update_primary_plane;
14379         } else if (HAS_PCH_SPLIT(dev)) {
14380                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14381                 dev_priv->display.get_initial_plane_config =
14382                         ironlake_get_initial_plane_config;
14383                 dev_priv->display.crtc_compute_clock =
14384                         ironlake_crtc_compute_clock;
14385                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14386                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14387                 dev_priv->display.update_primary_plane =
14388                         ironlake_update_primary_plane;
14389         } else if (IS_VALLEYVIEW(dev)) {
14390                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14391                 dev_priv->display.get_initial_plane_config =
14392                         i9xx_get_initial_plane_config;
14393                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14394                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14395                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14396                 dev_priv->display.update_primary_plane =
14397                         i9xx_update_primary_plane;
14398         } else {
14399                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14400                 dev_priv->display.get_initial_plane_config =
14401                         i9xx_get_initial_plane_config;
14402                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14403                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14404                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14405                 dev_priv->display.update_primary_plane =
14406                         i9xx_update_primary_plane;
14407         }
14408
14409         /* Returns the core display clock speed */
14410         if (IS_SKYLAKE(dev))
14411                 dev_priv->display.get_display_clock_speed =
14412                         skylake_get_display_clock_speed;
14413         else if (IS_BROXTON(dev))
14414                 dev_priv->display.get_display_clock_speed =
14415                         broxton_get_display_clock_speed;
14416         else if (IS_BROADWELL(dev))
14417                 dev_priv->display.get_display_clock_speed =
14418                         broadwell_get_display_clock_speed;
14419         else if (IS_HASWELL(dev))
14420                 dev_priv->display.get_display_clock_speed =
14421                         haswell_get_display_clock_speed;
14422         else if (IS_VALLEYVIEW(dev))
14423                 dev_priv->display.get_display_clock_speed =
14424                         valleyview_get_display_clock_speed;
14425         else if (IS_GEN5(dev))
14426                 dev_priv->display.get_display_clock_speed =
14427                         ilk_get_display_clock_speed;
14428         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14429                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14430                 dev_priv->display.get_display_clock_speed =
14431                         i945_get_display_clock_speed;
14432         else if (IS_GM45(dev))
14433                 dev_priv->display.get_display_clock_speed =
14434                         gm45_get_display_clock_speed;
14435         else if (IS_CRESTLINE(dev))
14436                 dev_priv->display.get_display_clock_speed =
14437                         i965gm_get_display_clock_speed;
14438         else if (IS_PINEVIEW(dev))
14439                 dev_priv->display.get_display_clock_speed =
14440                         pnv_get_display_clock_speed;
14441         else if (IS_G33(dev) || IS_G4X(dev))
14442                 dev_priv->display.get_display_clock_speed =
14443                         g33_get_display_clock_speed;
14444         else if (IS_I915G(dev))
14445                 dev_priv->display.get_display_clock_speed =
14446                         i915_get_display_clock_speed;
14447         else if (IS_I945GM(dev) || IS_845G(dev))
14448                 dev_priv->display.get_display_clock_speed =
14449                         i9xx_misc_get_display_clock_speed;
14450         else if (IS_PINEVIEW(dev))
14451                 dev_priv->display.get_display_clock_speed =
14452                         pnv_get_display_clock_speed;
14453         else if (IS_I915GM(dev))
14454                 dev_priv->display.get_display_clock_speed =
14455                         i915gm_get_display_clock_speed;
14456         else if (IS_I865G(dev))
14457                 dev_priv->display.get_display_clock_speed =
14458                         i865_get_display_clock_speed;
14459         else if (IS_I85X(dev))
14460                 dev_priv->display.get_display_clock_speed =
14461                         i85x_get_display_clock_speed;
14462         else { /* 830 */
14463                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14464                 dev_priv->display.get_display_clock_speed =
14465                         i830_get_display_clock_speed;
14466         }
14467
14468         if (IS_GEN5(dev)) {
14469                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14470         } else if (IS_GEN6(dev)) {
14471                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14472         } else if (IS_IVYBRIDGE(dev)) {
14473                 /* FIXME: detect B0+ stepping and use auto training */
14474                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14475         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14476                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14477                 if (IS_BROADWELL(dev)) {
14478                         dev_priv->display.modeset_commit_cdclk =
14479                                 broadwell_modeset_commit_cdclk;
14480                         dev_priv->display.modeset_calc_cdclk =
14481                                 broadwell_modeset_calc_cdclk;
14482                 }
14483         } else if (IS_VALLEYVIEW(dev)) {
14484                 dev_priv->display.modeset_commit_cdclk =
14485                         valleyview_modeset_commit_cdclk;
14486                 dev_priv->display.modeset_calc_cdclk =
14487                         valleyview_modeset_calc_cdclk;
14488         } else if (IS_BROXTON(dev)) {
14489                 dev_priv->display.modeset_commit_cdclk =
14490                         broxton_modeset_commit_cdclk;
14491                 dev_priv->display.modeset_calc_cdclk =
14492                         broxton_modeset_calc_cdclk;
14493         }
14494
14495         switch (INTEL_INFO(dev)->gen) {
14496         case 2:
14497                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14498                 break;
14499
14500         case 3:
14501                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14502                 break;
14503
14504         case 4:
14505         case 5:
14506                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14507                 break;
14508
14509         case 6:
14510                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14511                 break;
14512         case 7:
14513         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14514                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14515                 break;
14516         case 9:
14517                 /* Drop through - unsupported since execlist only. */
14518         default:
14519                 /* Default just returns -ENODEV to indicate unsupported */
14520                 dev_priv->display.queue_flip = intel_default_queue_flip;
14521         }
14522
14523         intel_panel_init_backlight_funcs(dev);
14524
14525         mutex_init(&dev_priv->pps_mutex);
14526 }
14527
14528 /*
14529  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14530  * resume, or other times.  This quirk makes sure that's the case for
14531  * affected systems.
14532  */
14533 static void quirk_pipea_force(struct drm_device *dev)
14534 {
14535         struct drm_i915_private *dev_priv = dev->dev_private;
14536
14537         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14538         DRM_INFO("applying pipe a force quirk\n");
14539 }
14540
14541 static void quirk_pipeb_force(struct drm_device *dev)
14542 {
14543         struct drm_i915_private *dev_priv = dev->dev_private;
14544
14545         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14546         DRM_INFO("applying pipe b force quirk\n");
14547 }
14548
14549 /*
14550  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14551  */
14552 static void quirk_ssc_force_disable(struct drm_device *dev)
14553 {
14554         struct drm_i915_private *dev_priv = dev->dev_private;
14555         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14556         DRM_INFO("applying lvds SSC disable quirk\n");
14557 }
14558
14559 /*
14560  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14561  * brightness value
14562  */
14563 static void quirk_invert_brightness(struct drm_device *dev)
14564 {
14565         struct drm_i915_private *dev_priv = dev->dev_private;
14566         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14567         DRM_INFO("applying inverted panel brightness quirk\n");
14568 }
14569
14570 /* Some VBT's incorrectly indicate no backlight is present */
14571 static void quirk_backlight_present(struct drm_device *dev)
14572 {
14573         struct drm_i915_private *dev_priv = dev->dev_private;
14574         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14575         DRM_INFO("applying backlight present quirk\n");
14576 }
14577
14578 struct intel_quirk {
14579         int device;
14580         int subsystem_vendor;
14581         int subsystem_device;
14582         void (*hook)(struct drm_device *dev);
14583 };
14584
14585 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14586 struct intel_dmi_quirk {
14587         void (*hook)(struct drm_device *dev);
14588         const struct dmi_system_id (*dmi_id_list)[];
14589 };
14590
14591 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14592 {
14593         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14594         return 1;
14595 }
14596
14597 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14598         {
14599                 .dmi_id_list = &(const struct dmi_system_id[]) {
14600                         {
14601                                 .callback = intel_dmi_reverse_brightness,
14602                                 .ident = "NCR Corporation",
14603                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14604                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14605                                 },
14606                         },
14607                         { }  /* terminating entry */
14608                 },
14609                 .hook = quirk_invert_brightness,
14610         },
14611 };
14612
14613 static struct intel_quirk intel_quirks[] = {
14614         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14615         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14616
14617         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14618         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14619
14620         /* 830 needs to leave pipe A & dpll A up */
14621         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14622
14623         /* 830 needs to leave pipe B & dpll B up */
14624         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14625
14626         /* Lenovo U160 cannot use SSC on LVDS */
14627         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14628
14629         /* Sony Vaio Y cannot use SSC on LVDS */
14630         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14631
14632         /* Acer Aspire 5734Z must invert backlight brightness */
14633         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14634
14635         /* Acer/eMachines G725 */
14636         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14637
14638         /* Acer/eMachines e725 */
14639         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14640
14641         /* Acer/Packard Bell NCL20 */
14642         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14643
14644         /* Acer Aspire 4736Z */
14645         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14646
14647         /* Acer Aspire 5336 */
14648         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14649
14650         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14651         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14652
14653         /* Acer C720 Chromebook (Core i3 4005U) */
14654         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14655
14656         /* Apple Macbook 2,1 (Core 2 T7400) */
14657         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14658
14659         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14660         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14661
14662         /* HP Chromebook 14 (Celeron 2955U) */
14663         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14664
14665         /* Dell Chromebook 11 */
14666         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14667 };
14668
14669 static void intel_init_quirks(struct drm_device *dev)
14670 {
14671         struct pci_dev *d = dev->pdev;
14672         int i;
14673
14674         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14675                 struct intel_quirk *q = &intel_quirks[i];
14676
14677                 if (d->device == q->device &&
14678                     (d->subsystem_vendor == q->subsystem_vendor ||
14679                      q->subsystem_vendor == PCI_ANY_ID) &&
14680                     (d->subsystem_device == q->subsystem_device ||
14681                      q->subsystem_device == PCI_ANY_ID))
14682                         q->hook(dev);
14683         }
14684         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14685                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14686                         intel_dmi_quirks[i].hook(dev);
14687         }
14688 }
14689
14690 /* Disable the VGA plane that we never use */
14691 static void i915_disable_vga(struct drm_device *dev)
14692 {
14693         struct drm_i915_private *dev_priv = dev->dev_private;
14694         u8 sr1;
14695         u32 vga_reg = i915_vgacntrl_reg(dev);
14696
14697         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14698         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14699         outb(SR01, VGA_SR_INDEX);
14700         sr1 = inb(VGA_SR_DATA);
14701         outb(sr1 | 1<<5, VGA_SR_DATA);
14702         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14703         udelay(300);
14704
14705         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14706         POSTING_READ(vga_reg);
14707 }
14708
14709 void intel_modeset_init_hw(struct drm_device *dev)
14710 {
14711         intel_update_cdclk(dev);
14712         intel_prepare_ddi(dev);
14713         intel_init_clock_gating(dev);
14714         intel_enable_gt_powersave(dev);
14715 }
14716
14717 void intel_modeset_init(struct drm_device *dev)
14718 {
14719         struct drm_i915_private *dev_priv = dev->dev_private;
14720         int sprite, ret;
14721         enum pipe pipe;
14722         struct intel_crtc *crtc;
14723
14724         drm_mode_config_init(dev);
14725
14726         dev->mode_config.min_width = 0;
14727         dev->mode_config.min_height = 0;
14728
14729         dev->mode_config.preferred_depth = 24;
14730         dev->mode_config.prefer_shadow = 1;
14731
14732         dev->mode_config.allow_fb_modifiers = true;
14733
14734         dev->mode_config.funcs = &intel_mode_funcs;
14735
14736         intel_init_quirks(dev);
14737
14738         intel_init_pm(dev);
14739
14740         if (INTEL_INFO(dev)->num_pipes == 0)
14741                 return;
14742
14743         /*
14744          * There may be no VBT; and if the BIOS enabled SSC we can
14745          * just keep using it to avoid unnecessary flicker.  Whereas if the
14746          * BIOS isn't using it, don't assume it will work even if the VBT
14747          * indicates as much.
14748          */
14749         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14750                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14751                                             DREF_SSC1_ENABLE);
14752
14753                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14754                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14755                                      bios_lvds_use_ssc ? "en" : "dis",
14756                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14757                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14758                 }
14759         }
14760
14761         intel_init_display(dev);
14762         intel_init_audio(dev);
14763
14764         if (IS_GEN2(dev)) {
14765                 dev->mode_config.max_width = 2048;
14766                 dev->mode_config.max_height = 2048;
14767         } else if (IS_GEN3(dev)) {
14768                 dev->mode_config.max_width = 4096;
14769                 dev->mode_config.max_height = 4096;
14770         } else {
14771                 dev->mode_config.max_width = 8192;
14772                 dev->mode_config.max_height = 8192;
14773         }
14774
14775         if (IS_845G(dev) || IS_I865G(dev)) {
14776                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14777                 dev->mode_config.cursor_height = 1023;
14778         } else if (IS_GEN2(dev)) {
14779                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14780                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14781         } else {
14782                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14783                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14784         }
14785
14786         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14787
14788         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14789                       INTEL_INFO(dev)->num_pipes,
14790                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14791
14792         for_each_pipe(dev_priv, pipe) {
14793                 intel_crtc_init(dev, pipe);
14794                 for_each_sprite(dev_priv, pipe, sprite) {
14795                         ret = intel_plane_init(dev, pipe, sprite);
14796                         if (ret)
14797                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14798                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14799                 }
14800         }
14801
14802         intel_init_dpio(dev);
14803
14804         intel_shared_dpll_init(dev);
14805
14806         /* Just disable it once at startup */
14807         i915_disable_vga(dev);
14808         intel_setup_outputs(dev);
14809
14810         /* Just in case the BIOS is doing something questionable. */
14811         intel_fbc_disable(dev_priv);
14812
14813         drm_modeset_lock_all(dev);
14814         intel_modeset_setup_hw_state(dev);
14815         drm_modeset_unlock_all(dev);
14816
14817         for_each_intel_crtc(dev, crtc) {
14818                 struct intel_initial_plane_config plane_config = {};
14819
14820                 if (!crtc->active)
14821                         continue;
14822
14823                 /*
14824                  * Note that reserving the BIOS fb up front prevents us
14825                  * from stuffing other stolen allocations like the ring
14826                  * on top.  This prevents some ugliness at boot time, and
14827                  * can even allow for smooth boot transitions if the BIOS
14828                  * fb is large enough for the active pipe configuration.
14829                  */
14830                 dev_priv->display.get_initial_plane_config(crtc,
14831                                                            &plane_config);
14832
14833                 /*
14834                  * If the fb is shared between multiple heads, we'll
14835                  * just get the first one.
14836                  */
14837                 intel_find_initial_plane_obj(crtc, &plane_config);
14838         }
14839 }
14840
14841 static void intel_enable_pipe_a(struct drm_device *dev)
14842 {
14843         struct intel_connector *connector;
14844         struct drm_connector *crt = NULL;
14845         struct intel_load_detect_pipe load_detect_temp;
14846         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14847
14848         /* We can't just switch on the pipe A, we need to set things up with a
14849          * proper mode and output configuration. As a gross hack, enable pipe A
14850          * by enabling the load detect pipe once. */
14851         for_each_intel_connector(dev, connector) {
14852                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14853                         crt = &connector->base;
14854                         break;
14855                 }
14856         }
14857
14858         if (!crt)
14859                 return;
14860
14861         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14862                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14863 }
14864
14865 static bool
14866 intel_check_plane_mapping(struct intel_crtc *crtc)
14867 {
14868         struct drm_device *dev = crtc->base.dev;
14869         struct drm_i915_private *dev_priv = dev->dev_private;
14870         u32 reg, val;
14871
14872         if (INTEL_INFO(dev)->num_pipes == 1)
14873                 return true;
14874
14875         reg = DSPCNTR(!crtc->plane);
14876         val = I915_READ(reg);
14877
14878         if ((val & DISPLAY_PLANE_ENABLE) &&
14879             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14880                 return false;
14881
14882         return true;
14883 }
14884
14885 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14886 {
14887         struct drm_device *dev = crtc->base.dev;
14888         struct drm_i915_private *dev_priv = dev->dev_private;
14889         struct intel_encoder *encoder;
14890         u32 reg;
14891         bool enable;
14892
14893         /* Clear any frame start delays used for debugging left by the BIOS */
14894         reg = PIPECONF(crtc->config->cpu_transcoder);
14895         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14896
14897         /* restore vblank interrupts to correct state */
14898         drm_crtc_vblank_reset(&crtc->base);
14899         if (crtc->active) {
14900                 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
14901                 update_scanline_offset(crtc);
14902                 drm_crtc_vblank_on(&crtc->base);
14903         }
14904
14905         /* We need to sanitize the plane -> pipe mapping first because this will
14906          * disable the crtc (and hence change the state) if it is wrong. Note
14907          * that gen4+ has a fixed plane -> pipe mapping.  */
14908         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14909                 bool plane;
14910
14911                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14912                               crtc->base.base.id);
14913
14914                 /* Pipe has the wrong plane attached and the plane is active.
14915                  * Temporarily change the plane mapping and disable everything
14916                  * ...  */
14917                 plane = crtc->plane;
14918                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14919                 crtc->plane = !plane;
14920                 intel_crtc_disable_noatomic(&crtc->base);
14921                 crtc->plane = plane;
14922         }
14923
14924         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14925             crtc->pipe == PIPE_A && !crtc->active) {
14926                 /* BIOS forgot to enable pipe A, this mostly happens after
14927                  * resume. Force-enable the pipe to fix this, the update_dpms
14928                  * call below we restore the pipe to the right state, but leave
14929                  * the required bits on. */
14930                 intel_enable_pipe_a(dev);
14931         }
14932
14933         /* Adjust the state of the output pipe according to whether we
14934          * have active connectors/encoders. */
14935         enable = false;
14936         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14937                 enable = true;
14938                 break;
14939         }
14940
14941         if (!enable)
14942                 intel_crtc_disable_noatomic(&crtc->base);
14943
14944         if (crtc->active != crtc->base.state->active) {
14945
14946                 /* This can happen either due to bugs in the get_hw_state
14947                  * functions or because of calls to intel_crtc_disable_noatomic,
14948                  * or because the pipe is force-enabled due to the
14949                  * pipe A quirk. */
14950                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14951                               crtc->base.base.id,
14952                               crtc->base.state->enable ? "enabled" : "disabled",
14953                               crtc->active ? "enabled" : "disabled");
14954
14955                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
14956                 crtc->base.state->active = crtc->active;
14957                 crtc->base.enabled = crtc->active;
14958
14959                 /* Because we only establish the connector -> encoder ->
14960                  * crtc links if something is active, this means the
14961                  * crtc is now deactivated. Break the links. connector
14962                  * -> encoder links are only establish when things are
14963                  *  actually up, hence no need to break them. */
14964                 WARN_ON(crtc->active);
14965
14966                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14967                         encoder->base.crtc = NULL;
14968         }
14969
14970         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14971                 /*
14972                  * We start out with underrun reporting disabled to avoid races.
14973                  * For correct bookkeeping mark this on active crtcs.
14974                  *
14975                  * Also on gmch platforms we dont have any hardware bits to
14976                  * disable the underrun reporting. Which means we need to start
14977                  * out with underrun reporting disabled also on inactive pipes,
14978                  * since otherwise we'll complain about the garbage we read when
14979                  * e.g. coming up after runtime pm.
14980                  *
14981                  * No protection against concurrent access is required - at
14982                  * worst a fifo underrun happens which also sets this to false.
14983                  */
14984                 crtc->cpu_fifo_underrun_disabled = true;
14985                 crtc->pch_fifo_underrun_disabled = true;
14986         }
14987 }
14988
14989 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14990 {
14991         struct intel_connector *connector;
14992         struct drm_device *dev = encoder->base.dev;
14993         bool active = false;
14994
14995         /* We need to check both for a crtc link (meaning that the
14996          * encoder is active and trying to read from a pipe) and the
14997          * pipe itself being active. */
14998         bool has_active_crtc = encoder->base.crtc &&
14999                 to_intel_crtc(encoder->base.crtc)->active;
15000
15001         for_each_intel_connector(dev, connector) {
15002                 if (connector->base.encoder != &encoder->base)
15003                         continue;
15004
15005                 active = true;
15006                 break;
15007         }
15008
15009         if (active && !has_active_crtc) {
15010                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15011                               encoder->base.base.id,
15012                               encoder->base.name);
15013
15014                 /* Connector is active, but has no active pipe. This is
15015                  * fallout from our resume register restoring. Disable
15016                  * the encoder manually again. */
15017                 if (encoder->base.crtc) {
15018                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15019                                       encoder->base.base.id,
15020                                       encoder->base.name);
15021                         encoder->disable(encoder);
15022                         if (encoder->post_disable)
15023                                 encoder->post_disable(encoder);
15024                 }
15025                 encoder->base.crtc = NULL;
15026
15027                 /* Inconsistent output/port/pipe state happens presumably due to
15028                  * a bug in one of the get_hw_state functions. Or someplace else
15029                  * in our code, like the register restore mess on resume. Clamp
15030                  * things to off as a safer default. */
15031                 for_each_intel_connector(dev, connector) {
15032                         if (connector->encoder != encoder)
15033                                 continue;
15034                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15035                         connector->base.encoder = NULL;
15036                 }
15037         }
15038         /* Enabled encoders without active connectors will be fixed in
15039          * the crtc fixup. */
15040 }
15041
15042 void i915_redisable_vga_power_on(struct drm_device *dev)
15043 {
15044         struct drm_i915_private *dev_priv = dev->dev_private;
15045         u32 vga_reg = i915_vgacntrl_reg(dev);
15046
15047         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15048                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15049                 i915_disable_vga(dev);
15050         }
15051 }
15052
15053 void i915_redisable_vga(struct drm_device *dev)
15054 {
15055         struct drm_i915_private *dev_priv = dev->dev_private;
15056
15057         /* This function can be called both from intel_modeset_setup_hw_state or
15058          * at a very early point in our resume sequence, where the power well
15059          * structures are not yet restored. Since this function is at a very
15060          * paranoid "someone might have enabled VGA while we were not looking"
15061          * level, just check if the power well is enabled instead of trying to
15062          * follow the "don't touch the power well if we don't need it" policy
15063          * the rest of the driver uses. */
15064         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15065                 return;
15066
15067         i915_redisable_vga_power_on(dev);
15068 }
15069
15070 static bool primary_get_hw_state(struct intel_crtc *crtc)
15071 {
15072         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15073
15074         return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15075 }
15076
15077 static void readout_plane_state(struct intel_crtc *crtc,
15078                                 struct intel_crtc_state *crtc_state)
15079 {
15080         struct intel_plane *p;
15081         struct intel_plane_state *plane_state;
15082         bool active = crtc_state->base.active;
15083
15084         for_each_intel_plane(crtc->base.dev, p) {
15085                 if (crtc->pipe != p->pipe)
15086                         continue;
15087
15088                 plane_state = to_intel_plane_state(p->base.state);
15089
15090                 if (p->base.type == DRM_PLANE_TYPE_PRIMARY) {
15091                         plane_state->visible = primary_get_hw_state(crtc);
15092                         if (plane_state->visible)
15093                                 crtc->base.state->plane_mask |=
15094                                         1 << drm_plane_index(&p->base);
15095                 } else {
15096                         if (active)
15097                                 p->disable_plane(&p->base, &crtc->base);
15098
15099                         plane_state->visible = false;
15100                 }
15101         }
15102 }
15103
15104 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15105 {
15106         struct drm_i915_private *dev_priv = dev->dev_private;
15107         enum pipe pipe;
15108         struct intel_crtc *crtc;
15109         struct intel_encoder *encoder;
15110         struct intel_connector *connector;
15111         int i;
15112
15113         for_each_intel_crtc(dev, crtc) {
15114                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15115                 memset(crtc->config, 0, sizeof(*crtc->config));
15116                 crtc->config->base.crtc = &crtc->base;
15117
15118                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15119                                                                  crtc->config);
15120
15121                 crtc->base.state->active = crtc->active;
15122                 crtc->base.enabled = crtc->active;
15123
15124                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15125                 if (crtc->base.state->active) {
15126                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15127                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15128                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15129
15130                         /*
15131                          * The initial mode needs to be set in order to keep
15132                          * the atomic core happy. It wants a valid mode if the
15133                          * crtc's enabled, so we do the above call.
15134                          *
15135                          * At this point some state updated by the connectors
15136                          * in their ->detect() callback has not run yet, so
15137                          * no recalculation can be done yet.
15138                          *
15139                          * Even if we could do a recalculation and modeset
15140                          * right now it would cause a double modeset if
15141                          * fbdev or userspace chooses a different initial mode.
15142                          *
15143                          * If that happens, someone indicated they wanted a
15144                          * mode change, which means it's safe to do a full
15145                          * recalculation.
15146                          */
15147                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15148                 }
15149
15150                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15151                 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15152
15153                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15154                               crtc->base.base.id,
15155                               crtc->active ? "enabled" : "disabled");
15156         }
15157
15158         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15159                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15160
15161                 pll->on = pll->get_hw_state(dev_priv, pll,
15162                                             &pll->config.hw_state);
15163                 pll->active = 0;
15164                 pll->config.crtc_mask = 0;
15165                 for_each_intel_crtc(dev, crtc) {
15166                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15167                                 pll->active++;
15168                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15169                         }
15170                 }
15171
15172                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15173                               pll->name, pll->config.crtc_mask, pll->on);
15174
15175                 if (pll->config.crtc_mask)
15176                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15177         }
15178
15179         for_each_intel_encoder(dev, encoder) {
15180                 pipe = 0;
15181
15182                 if (encoder->get_hw_state(encoder, &pipe)) {
15183                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15184                         encoder->base.crtc = &crtc->base;
15185                         encoder->get_config(encoder, crtc->config);
15186                 } else {
15187                         encoder->base.crtc = NULL;
15188                 }
15189
15190                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15191                               encoder->base.base.id,
15192                               encoder->base.name,
15193                               encoder->base.crtc ? "enabled" : "disabled",
15194                               pipe_name(pipe));
15195         }
15196
15197         for_each_intel_connector(dev, connector) {
15198                 if (connector->get_hw_state(connector)) {
15199                         connector->base.dpms = DRM_MODE_DPMS_ON;
15200                         connector->base.encoder = &connector->encoder->base;
15201                 } else {
15202                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15203                         connector->base.encoder = NULL;
15204                 }
15205                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15206                               connector->base.base.id,
15207                               connector->base.name,
15208                               connector->base.encoder ? "enabled" : "disabled");
15209         }
15210 }
15211
15212 /* Scan out the current hw modeset state,
15213  * and sanitizes it to the current state
15214  */
15215 static void
15216 intel_modeset_setup_hw_state(struct drm_device *dev)
15217 {
15218         struct drm_i915_private *dev_priv = dev->dev_private;
15219         enum pipe pipe;
15220         struct intel_crtc *crtc;
15221         struct intel_encoder *encoder;
15222         int i;
15223
15224         intel_modeset_readout_hw_state(dev);
15225
15226         /* HW state is read out, now we need to sanitize this mess. */
15227         for_each_intel_encoder(dev, encoder) {
15228                 intel_sanitize_encoder(encoder);
15229         }
15230
15231         for_each_pipe(dev_priv, pipe) {
15232                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15233                 intel_sanitize_crtc(crtc);
15234                 intel_dump_pipe_config(crtc, crtc->config,
15235                                        "[setup_hw_state]");
15236         }
15237
15238         intel_modeset_update_connector_atomic_state(dev);
15239
15240         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15241                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15242
15243                 if (!pll->on || pll->active)
15244                         continue;
15245
15246                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15247
15248                 pll->disable(dev_priv, pll);
15249                 pll->on = false;
15250         }
15251
15252         if (IS_VALLEYVIEW(dev))
15253                 vlv_wm_get_hw_state(dev);
15254         else if (IS_GEN9(dev))
15255                 skl_wm_get_hw_state(dev);
15256         else if (HAS_PCH_SPLIT(dev))
15257                 ilk_wm_get_hw_state(dev);
15258
15259         for_each_intel_crtc(dev, crtc) {
15260                 unsigned long put_domains;
15261
15262                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15263                 if (WARN_ON(put_domains))
15264                         modeset_put_power_domains(dev_priv, put_domains);
15265         }
15266         intel_display_set_init_power(dev_priv, false);
15267 }
15268
15269 void intel_display_resume(struct drm_device *dev)
15270 {
15271         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15272         struct intel_connector *conn;
15273         struct intel_plane *plane;
15274         struct drm_crtc *crtc;
15275         int ret;
15276
15277         if (!state)
15278                 return;
15279
15280         state->acquire_ctx = dev->mode_config.acquire_ctx;
15281
15282         /* preserve complete old state, including dpll */
15283         intel_atomic_get_shared_dpll_state(state);
15284
15285         for_each_crtc(dev, crtc) {
15286                 struct drm_crtc_state *crtc_state =
15287                         drm_atomic_get_crtc_state(state, crtc);
15288
15289                 ret = PTR_ERR_OR_ZERO(crtc_state);
15290                 if (ret)
15291                         goto err;
15292
15293                 /* force a restore */
15294                 crtc_state->mode_changed = true;
15295         }
15296
15297         for_each_intel_plane(dev, plane) {
15298                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15299                 if (ret)
15300                         goto err;
15301         }
15302
15303         for_each_intel_connector(dev, conn) {
15304                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15305                 if (ret)
15306                         goto err;
15307         }
15308
15309         intel_modeset_setup_hw_state(dev);
15310
15311         i915_redisable_vga(dev);
15312         ret = drm_atomic_commit(state);
15313         if (!ret)
15314                 return;
15315
15316 err:
15317         DRM_ERROR("Restoring old state failed with %i\n", ret);
15318         drm_atomic_state_free(state);
15319 }
15320
15321 void intel_modeset_gem_init(struct drm_device *dev)
15322 {
15323         struct drm_crtc *c;
15324         struct drm_i915_gem_object *obj;
15325         int ret;
15326
15327         mutex_lock(&dev->struct_mutex);
15328         intel_init_gt_powersave(dev);
15329         mutex_unlock(&dev->struct_mutex);
15330
15331         intel_modeset_init_hw(dev);
15332
15333         intel_setup_overlay(dev);
15334
15335         /*
15336          * Make sure any fbs we allocated at startup are properly
15337          * pinned & fenced.  When we do the allocation it's too early
15338          * for this.
15339          */
15340         for_each_crtc(dev, c) {
15341                 obj = intel_fb_obj(c->primary->fb);
15342                 if (obj == NULL)
15343                         continue;
15344
15345                 mutex_lock(&dev->struct_mutex);
15346                 ret = intel_pin_and_fence_fb_obj(c->primary,
15347                                                  c->primary->fb,
15348                                                  c->primary->state,
15349                                                  NULL, NULL);
15350                 mutex_unlock(&dev->struct_mutex);
15351                 if (ret) {
15352                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15353                                   to_intel_crtc(c)->pipe);
15354                         drm_framebuffer_unreference(c->primary->fb);
15355                         c->primary->fb = NULL;
15356                         c->primary->crtc = c->primary->state->crtc = NULL;
15357                         update_state_fb(c->primary);
15358                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15359                 }
15360         }
15361
15362         intel_backlight_register(dev);
15363 }
15364
15365 void intel_connector_unregister(struct intel_connector *intel_connector)
15366 {
15367         struct drm_connector *connector = &intel_connector->base;
15368
15369         intel_panel_destroy_backlight(connector);
15370         drm_connector_unregister(connector);
15371 }
15372
15373 void intel_modeset_cleanup(struct drm_device *dev)
15374 {
15375         struct drm_i915_private *dev_priv = dev->dev_private;
15376         struct drm_connector *connector;
15377
15378         intel_disable_gt_powersave(dev);
15379
15380         intel_backlight_unregister(dev);
15381
15382         /*
15383          * Interrupts and polling as the first thing to avoid creating havoc.
15384          * Too much stuff here (turning of connectors, ...) would
15385          * experience fancy races otherwise.
15386          */
15387         intel_irq_uninstall(dev_priv);
15388
15389         /*
15390          * Due to the hpd irq storm handling the hotplug work can re-arm the
15391          * poll handlers. Hence disable polling after hpd handling is shut down.
15392          */
15393         drm_kms_helper_poll_fini(dev);
15394
15395         intel_unregister_dsm_handler();
15396
15397         intel_fbc_disable(dev_priv);
15398
15399         /* flush any delayed tasks or pending work */
15400         flush_scheduled_work();
15401
15402         /* destroy the backlight and sysfs files before encoders/connectors */
15403         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15404                 struct intel_connector *intel_connector;
15405
15406                 intel_connector = to_intel_connector(connector);
15407                 intel_connector->unregister(intel_connector);
15408         }
15409
15410         drm_mode_config_cleanup(dev);
15411
15412         intel_cleanup_overlay(dev);
15413
15414         mutex_lock(&dev->struct_mutex);
15415         intel_cleanup_gt_powersave(dev);
15416         mutex_unlock(&dev->struct_mutex);
15417 }
15418
15419 /*
15420  * Return which encoder is currently attached for connector.
15421  */
15422 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15423 {
15424         return &intel_attached_encoder(connector)->base;
15425 }
15426
15427 void intel_connector_attach_encoder(struct intel_connector *connector,
15428                                     struct intel_encoder *encoder)
15429 {
15430         connector->encoder = encoder;
15431         drm_mode_connector_attach_encoder(&connector->base,
15432                                           &encoder->base);
15433 }
15434
15435 /*
15436  * set vga decode state - true == enable VGA decode
15437  */
15438 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15439 {
15440         struct drm_i915_private *dev_priv = dev->dev_private;
15441         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15442         u16 gmch_ctrl;
15443
15444         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15445                 DRM_ERROR("failed to read control word\n");
15446                 return -EIO;
15447         }
15448
15449         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15450                 return 0;
15451
15452         if (state)
15453                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15454         else
15455                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15456
15457         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15458                 DRM_ERROR("failed to write control word\n");
15459                 return -EIO;
15460         }
15461
15462         return 0;
15463 }
15464
15465 struct intel_display_error_state {
15466
15467         u32 power_well_driver;
15468
15469         int num_transcoders;
15470
15471         struct intel_cursor_error_state {
15472                 u32 control;
15473                 u32 position;
15474                 u32 base;
15475                 u32 size;
15476         } cursor[I915_MAX_PIPES];
15477
15478         struct intel_pipe_error_state {
15479                 bool power_domain_on;
15480                 u32 source;
15481                 u32 stat;
15482         } pipe[I915_MAX_PIPES];
15483
15484         struct intel_plane_error_state {
15485                 u32 control;
15486                 u32 stride;
15487                 u32 size;
15488                 u32 pos;
15489                 u32 addr;
15490                 u32 surface;
15491                 u32 tile_offset;
15492         } plane[I915_MAX_PIPES];
15493
15494         struct intel_transcoder_error_state {
15495                 bool power_domain_on;
15496                 enum transcoder cpu_transcoder;
15497
15498                 u32 conf;
15499
15500                 u32 htotal;
15501                 u32 hblank;
15502                 u32 hsync;
15503                 u32 vtotal;
15504                 u32 vblank;
15505                 u32 vsync;
15506         } transcoder[4];
15507 };
15508
15509 struct intel_display_error_state *
15510 intel_display_capture_error_state(struct drm_device *dev)
15511 {
15512         struct drm_i915_private *dev_priv = dev->dev_private;
15513         struct intel_display_error_state *error;
15514         int transcoders[] = {
15515                 TRANSCODER_A,
15516                 TRANSCODER_B,
15517                 TRANSCODER_C,
15518                 TRANSCODER_EDP,
15519         };
15520         int i;
15521
15522         if (INTEL_INFO(dev)->num_pipes == 0)
15523                 return NULL;
15524
15525         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15526         if (error == NULL)
15527                 return NULL;
15528
15529         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15530                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15531
15532         for_each_pipe(dev_priv, i) {
15533                 error->pipe[i].power_domain_on =
15534                         __intel_display_power_is_enabled(dev_priv,
15535                                                          POWER_DOMAIN_PIPE(i));
15536                 if (!error->pipe[i].power_domain_on)
15537                         continue;
15538
15539                 error->cursor[i].control = I915_READ(CURCNTR(i));
15540                 error->cursor[i].position = I915_READ(CURPOS(i));
15541                 error->cursor[i].base = I915_READ(CURBASE(i));
15542
15543                 error->plane[i].control = I915_READ(DSPCNTR(i));
15544                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15545                 if (INTEL_INFO(dev)->gen <= 3) {
15546                         error->plane[i].size = I915_READ(DSPSIZE(i));
15547                         error->plane[i].pos = I915_READ(DSPPOS(i));
15548                 }
15549                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15550                         error->plane[i].addr = I915_READ(DSPADDR(i));
15551                 if (INTEL_INFO(dev)->gen >= 4) {
15552                         error->plane[i].surface = I915_READ(DSPSURF(i));
15553                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15554                 }
15555
15556                 error->pipe[i].source = I915_READ(PIPESRC(i));
15557
15558                 if (HAS_GMCH_DISPLAY(dev))
15559                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15560         }
15561
15562         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15563         if (HAS_DDI(dev_priv->dev))
15564                 error->num_transcoders++; /* Account for eDP. */
15565
15566         for (i = 0; i < error->num_transcoders; i++) {
15567                 enum transcoder cpu_transcoder = transcoders[i];
15568
15569                 error->transcoder[i].power_domain_on =
15570                         __intel_display_power_is_enabled(dev_priv,
15571                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15572                 if (!error->transcoder[i].power_domain_on)
15573                         continue;
15574
15575                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15576
15577                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15578                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15579                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15580                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15581                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15582                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15583                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15584         }
15585
15586         return error;
15587 }
15588
15589 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15590
15591 void
15592 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15593                                 struct drm_device *dev,
15594                                 struct intel_display_error_state *error)
15595 {
15596         struct drm_i915_private *dev_priv = dev->dev_private;
15597         int i;
15598
15599         if (!error)
15600                 return;
15601
15602         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15603         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15604                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15605                            error->power_well_driver);
15606         for_each_pipe(dev_priv, i) {
15607                 err_printf(m, "Pipe [%d]:\n", i);
15608                 err_printf(m, "  Power: %s\n",
15609                            error->pipe[i].power_domain_on ? "on" : "off");
15610                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15611                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15612
15613                 err_printf(m, "Plane [%d]:\n", i);
15614                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15615                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15616                 if (INTEL_INFO(dev)->gen <= 3) {
15617                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15618                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15619                 }
15620                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15621                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15622                 if (INTEL_INFO(dev)->gen >= 4) {
15623                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15624                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15625                 }
15626
15627                 err_printf(m, "Cursor [%d]:\n", i);
15628                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15629                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15630                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15631         }
15632
15633         for (i = 0; i < error->num_transcoders; i++) {
15634                 err_printf(m, "CPU transcoder: %c\n",
15635                            transcoder_name(error->transcoder[i].cpu_transcoder));
15636                 err_printf(m, "  Power: %s\n",
15637                            error->transcoder[i].power_domain_on ? "on" : "off");
15638                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15639                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15640                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15641                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15642                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15643                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15644                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15645         }
15646 }
15647
15648 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15649 {
15650         struct intel_crtc *crtc;
15651
15652         for_each_intel_crtc(dev, crtc) {
15653                 struct intel_unpin_work *work;
15654
15655                 spin_lock_irq(&dev->event_lock);
15656
15657                 work = crtc->unpin_work;
15658
15659                 if (work && work->event &&
15660                     work->event->base.file_priv == file) {
15661                         kfree(work->event);
15662                         work->event = NULL;
15663                 }
15664
15665                 spin_unlock_irq(&dev->event_lock);
15666         }
15667 }