drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/drm_fb_helper.h>
  34 #include "intel_drv.h"
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include <linux/pci.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/acpi.h>
  41 #include <linux/pnp.h>
  42 #include <linux/vga_switcheroo.h>
  43 #include <linux/slab.h>
  44 #include <acpi/video.h>
  45
  46 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  47
  48 #define BEGIN_LP_RING(n) \
  49         intel_ring_begin(LP_RING(dev_priv), (n))
  50
  51 #define OUT_RING(x) \
  52         intel_ring_emit(LP_RING(dev_priv), x)
  53
  54 #define ADVANCE_LP_RING() \
  55         __intel_ring_advance(LP_RING(dev_priv))
  56
  57 /**
  58  * Lock test for when it's just for synchronization of ring access.
  59  *
  60  * In that case, we don't need to do it when GEM is initialized as nobody else
  61  * has access to the ring.
  62  */
  63 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
  64         if (LP_RING(dev->dev_private)->obj == NULL)                     \
  65                 LOCK_TEST_WITH_RETURN(dev, file);                       \
  66 } while (0)
  67
  68 static inline u32
  69 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
  70 {
  71         if (I915_NEED_GFX_HWS(dev_priv->dev))
  72                 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
  73         else
  74                 return intel_read_status_page(LP_RING(dev_priv), reg);
  75 }
  76
  77 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
  78 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  79 #define I915_BREADCRUMB_INDEX           0x21
  80
  81 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  82 {
  83         drm_i915_private_t *dev_priv = dev->dev_private;
  84         struct drm_i915_master_private *master_priv;
  85
  86         /*
  87          * The dri breadcrumb update races against the drm master disappearing.
  88          * Instead of trying to fix this (this is by far not the only ums issue)
  89          * just don't do the update in kms mode.
  90          */
  91         if (drm_core_check_feature(dev, DRIVER_MODESET))
  92                 return;
  93
  94         if (dev->primary->master) {
  95                 master_priv = dev->primary->master->driver_priv;
  96                 if (master_priv->sarea_priv)
  97                         master_priv->sarea_priv->last_dispatch =
  98                                 READ_BREADCRUMB(dev_priv);
  99         }
 100 }
 101
 102 static void i915_write_hws_pga(struct drm_device *dev)
 103 {
 104         drm_i915_private_t *dev_priv = dev->dev_private;
 105         u32 addr;
 106
 107         addr = dev_priv->status_page_dmah->busaddr;
 108         if (INTEL_INFO(dev)->gen >= 4)
 109                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 110         I915_WRITE(HWS_PGA, addr);
 111 }
 112
 113 /**
 114  * Frees the hardware status page, whether it's a physical address or a virtual
 115  * address set up by the X Server.
 116  */
 117 static void i915_free_hws(struct drm_device *dev)
 118 {
 119         drm_i915_private_t *dev_priv = dev->dev_private;
 120         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 121
 122         if (dev_priv->status_page_dmah) {
 123                 drm_pci_free(dev, dev_priv->status_page_dmah);
 124                 dev_priv->status_page_dmah = NULL;
 125         }
 126
 127         if (ring->status_page.gfx_addr) {
 128                 ring->status_page.gfx_addr = 0;
 129                 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
 130         }
 131
 132         /* Need to rewrite hardware status page */
 133         I915_WRITE(HWS_PGA, 0x1ffff000);
 134 }
 135
 136 void i915_kernel_lost_context(struct drm_device * dev)
 137 {
 138         drm_i915_private_t *dev_priv = dev->dev_private;
 139         struct drm_i915_master_private *master_priv;
 140         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 141
 142         /*
 143          * We should never lose context on the ring with modesetting
 144          * as we don't expose it to userspace
 145          */
 146         if (drm_core_check_feature(dev, DRIVER_MODESET))
 147                 return;
 148
 149         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 150         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 151         ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
 152         if (ring->space < 0)
 153                 ring->space += ring->size;
 154
 155         if (!dev->primary->master)
 156                 return;
 157
 158         master_priv = dev->primary->master->driver_priv;
 159         if (ring->head == ring->tail && master_priv->sarea_priv)
 160                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 161 }
 162
 163 static int i915_dma_cleanup(struct drm_device * dev)
 164 {
 165         drm_i915_private_t *dev_priv = dev->dev_private;
 166         int i;
 167
 168         /* Make sure interrupts are disabled here because the uninstall ioctl
 169          * may not have been called from userspace and after dev_private
 170          * is freed, it's too late.
 171          */
 172         if (dev->irq_enabled)
 173                 drm_irq_uninstall(dev);
 174
 175         mutex_lock(&dev->struct_mutex);
 176         for (i = 0; i < I915_NUM_RINGS; i++)
 177                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 178         mutex_unlock(&dev->struct_mutex);
 179
 180         /* Clear the HWS virtual address at teardown */
 181         if (I915_NEED_GFX_HWS(dev))
 182                 i915_free_hws(dev);
 183
 184         return 0;
 185 }
 186
 187 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 188 {
 189         drm_i915_private_t *dev_priv = dev->dev_private;
 190         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 191         int ret;
 192
 193         master_priv->sarea = drm_getsarea(dev);
 194         if (master_priv->sarea) {
 195                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 196                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 197         } else {
 198                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 199         }
 200
 201         if (init->ring_size != 0) {
 202                 if (LP_RING(dev_priv)->obj != NULL) {
 203                         i915_dma_cleanup(dev);
 204                         DRM_ERROR("Client tried to initialize ringbuffer in "
 205                                   "GEM mode\n");
 206                         return -EINVAL;
 207                 }
 208
 209                 ret = intel_render_ring_init_dri(dev,
 210                                                  init->ring_start,
 211                                                  init->ring_size);
 212                 if (ret) {
 213                         i915_dma_cleanup(dev);
 214                         return ret;
 215                 }
 216         }
 217
 218         dev_priv->dri1.cpp = init->cpp;
 219         dev_priv->dri1.back_offset = init->back_offset;
 220         dev_priv->dri1.front_offset = init->front_offset;
 221         dev_priv->dri1.current_page = 0;
 222         if (master_priv->sarea_priv)
 223                 master_priv->sarea_priv->pf_current_page = 0;
 224
 225         /* Allow hardware batchbuffers unless told otherwise.
 226          */
 227         dev_priv->dri1.allow_batchbuffer = 1;
 228
 229         return 0;
 230 }
 231
 232 static int i915_dma_resume(struct drm_device * dev)
 233 {
 234         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 235         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 236
 237         DRM_DEBUG_DRIVER("%s\n", __func__);
 238
 239         if (ring->virtual_start == NULL) {
 240                 DRM_ERROR("can not ioremap virtual address for"
 241                           " ring buffer\n");
 242                 return -ENOMEM;
 243         }
 244
 245         /* Program Hardware Status Page */
 246         if (!ring->status_page.page_addr) {
 247                 DRM_ERROR("Can not find hardware status page\n");
 248                 return -EINVAL;
 249         }
 250         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 251                                 ring->status_page.page_addr);
 252         if (ring->status_page.gfx_addr != 0)
 253                 intel_ring_setup_status_page(ring);
 254         else
 255                 i915_write_hws_pga(dev);
 256
 257         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 258
 259         return 0;
 260 }
 261
 262 static int i915_dma_init(struct drm_device *dev, void *data,
 263                          struct drm_file *file_priv)
 264 {
 265         drm_i915_init_t *init = data;
 266         int retcode = 0;
 267
 268         if (drm_core_check_feature(dev, DRIVER_MODESET))
 269                 return -ENODEV;
 270
 271         switch (init->func) {
 272         case I915_INIT_DMA:
 273                 retcode = i915_initialize(dev, init);
 274                 break;
 275         case I915_CLEANUP_DMA:
 276                 retcode = i915_dma_cleanup(dev);
 277                 break;
 278         case I915_RESUME_DMA:
 279                 retcode = i915_dma_resume(dev);
 280                 break;
 281         default:
 282                 retcode = -EINVAL;
 283                 break;
 284         }
 285
 286         return retcode;
 287 }
 288
 289 /* Implement basically the same security restrictions as hardware does
 290  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 291  *
 292  * Most of the calculations below involve calculating the size of a
 293  * particular instruction.  It's important to get the size right as
 294  * that tells us where the next instruction to check is.  Any illegal
 295  * instruction detected will be given a size of zero, which is a
 296  * signal to abort the rest of the buffer.
 297  */
 298 static int validate_cmd(int cmd)
 299 {
 300         switch (((cmd >> 29) & 0x7)) {
 301         case 0x0:
 302                 switch ((cmd >> 23) & 0x3f) {
 303                 case 0x0:
 304                         return 1;       /* MI_NOOP */
 305                 case 0x4:
 306                         return 1;       /* MI_FLUSH */
 307                 default:
 308                         return 0;       /* disallow everything else */
 309                 }
 310                 break;
 311         case 0x1:
 312                 return 0;       /* reserved */
 313         case 0x2:
 314                 return (cmd & 0xff) + 2;        /* 2d commands */
 315         case 0x3:
 316                 if (((cmd >> 24) & 0x1f) <= 0x18)
 317                         return 1;
 318
 319                 switch ((cmd >> 24) & 0x1f) {
 320                 case 0x1c:
 321                         return 1;
 322                 case 0x1d:
 323                         switch ((cmd >> 16) & 0xff) {
 324                         case 0x3:
 325                                 return (cmd & 0x1f) + 2;
 326                         case 0x4:
 327                                 return (cmd & 0xf) + 2;
 328                         default:
 329                                 return (cmd & 0xffff) + 2;
 330                         }
 331                 case 0x1e:
 332                         if (cmd & (1 << 23))
 333                                 return (cmd & 0xffff) + 1;
 334                         else
 335                                 return 1;
 336                 case 0x1f:
 337                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 338                                 return (cmd & 0x1ffff) + 2;
 339                         else if (cmd & (1 << 17))       /* indirect random */
 340                                 if ((cmd & 0xffff) == 0)
 341                                         return 0;       /* unknown length, too hard */
 342                                 else
 343                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 344                         else
 345                                 return 2;       /* indirect sequential */
 346                 default:
 347                         return 0;
 348                 }
 349         default:
 350                 return 0;
 351         }
 352
 353         return 0;
 354 }
 355
 356 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 357 {
 358         drm_i915_private_t *dev_priv = dev->dev_private;
 359         int i, ret;
 360
 361         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 362                 return -EINVAL;
 363
 364         for (i = 0; i < dwords;) {
 365                 int sz = validate_cmd(buffer[i]);
 366                 if (sz == 0 || i + sz > dwords)
 367                         return -EINVAL;
 368                 i += sz;
 369         }
 370
 371         ret = BEGIN_LP_RING((dwords+1)&~1);
 372         if (ret)
 373                 return ret;
 374
 375         for (i = 0; i < dwords; i++)
 376                 OUT_RING(buffer[i]);
 377         if (dwords & 1)
 378                 OUT_RING(0);
 379
 380         ADVANCE_LP_RING();
 381
 382         return 0;
 383 }
 384
 385 int
 386 i915_emit_box(struct drm_device *dev,
 387               struct drm_clip_rect *box,
 388               int DR1, int DR4)
 389 {
 390         struct drm_i915_private *dev_priv = dev->dev_private;
 391         int ret;
 392
 393         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 394             box->y2 <= 0 || box->x2 <= 0) {
 395                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 396                           box->x1, box->y1, box->x2, box->y2);
 397                 return -EINVAL;
 398         }
 399
 400         if (INTEL_INFO(dev)->gen >= 4) {
 401                 ret = BEGIN_LP_RING(4);
 402                 if (ret)
 403                         return ret;
 404
 405                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 406                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 407                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 408                 OUT_RING(DR4);
 409         } else {
 410                 ret = BEGIN_LP_RING(6);
 411                 if (ret)
 412                         return ret;
 413
 414                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 415                 OUT_RING(DR1);
 416                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 417                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 418                 OUT_RING(DR4);
 419                 OUT_RING(0);
 420         }
 421         ADVANCE_LP_RING();
 422
 423         return 0;
 424 }
 425
 426 /* XXX: Emitting the counter should really be moved to part of the IRQ
 427  * emit. For now, do it in both places:
 428  */
 429
 430 static void i915_emit_breadcrumb(struct drm_device *dev)
 431 {
 432         drm_i915_private_t *dev_priv = dev->dev_private;
 433         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 434
 435         dev_priv->dri1.counter++;
 436         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 437                 dev_priv->dri1.counter = 0;
 438         if (master_priv->sarea_priv)
 439                 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 440
 441         if (BEGIN_LP_RING(4) == 0) {
 442                 OUT_RING(MI_STORE_DWORD_INDEX);
 443                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 444                 OUT_RING(dev_priv->dri1.counter);
 445                 OUT_RING(0);
 446                 ADVANCE_LP_RING();
 447         }
 448 }
 449
 450 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 451                                    drm_i915_cmdbuffer_t *cmd,
 452                                    struct drm_clip_rect *cliprects,
 453                                    void *cmdbuf)
 454 {
 455         int nbox = cmd->num_cliprects;
 456         int i = 0, count, ret;
 457
 458         if (cmd->sz & 0x3) {
 459                 DRM_ERROR("alignment");
 460                 return -EINVAL;
 461         }
 462
 463         i915_kernel_lost_context(dev);
 464
 465         count = nbox ? nbox : 1;
 466
 467         for (i = 0; i < count; i++) {
 468                 if (i < nbox) {
 469                         ret = i915_emit_box(dev, &cliprects[i],
 470                                             cmd->DR1, cmd->DR4);
 471                         if (ret)
 472                                 return ret;
 473                 }
 474
 475                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 476                 if (ret)
 477                         return ret;
 478         }
 479
 480         i915_emit_breadcrumb(dev);
 481         return 0;
 482 }
 483
 484 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 485                                      drm_i915_batchbuffer_t * batch,
 486                                      struct drm_clip_rect *cliprects)
 487 {
 488         struct drm_i915_private *dev_priv = dev->dev_private;
 489         int nbox = batch->num_cliprects;
 490         int i, count, ret;
 491
 492         if ((batch->start | batch->used) & 0x7) {
 493                 DRM_ERROR("alignment");
 494                 return -EINVAL;
 495         }
 496
 497         i915_kernel_lost_context(dev);
 498
 499         count = nbox ? nbox : 1;
 500         for (i = 0; i < count; i++) {
 501                 if (i < nbox) {
 502                         ret = i915_emit_box(dev, &cliprects[i],
 503                                             batch->DR1, batch->DR4);
 504                         if (ret)
 505                                 return ret;
 506                 }
 507
 508                 if (!IS_I830(dev) && !IS_845G(dev)) {
 509                         ret = BEGIN_LP_RING(2);
 510                         if (ret)
 511                                 return ret;
 512
 513                         if (INTEL_INFO(dev)->gen >= 4) {
 514                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 515                                 OUT_RING(batch->start);
 516                         } else {
 517                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 518                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 519                         }
 520                 } else {
 521                         ret = BEGIN_LP_RING(4);
 522                         if (ret)
 523                                 return ret;
 524
 525                         OUT_RING(MI_BATCH_BUFFER);
 526                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 527                         OUT_RING(batch->start + batch->used - 4);
 528                         OUT_RING(0);
 529                 }
 530                 ADVANCE_LP_RING();
 531         }
 532
 533
 534         if (IS_G4X(dev) || IS_GEN5(dev)) {
 535                 if (BEGIN_LP_RING(2) == 0) {
 536                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 537                         OUT_RING(MI_NOOP);
 538                         ADVANCE_LP_RING();
 539                 }
 540         }
 541
 542         i915_emit_breadcrumb(dev);
 543         return 0;
 544 }
 545
 546 static int i915_dispatch_flip(struct drm_device * dev)
 547 {
 548         drm_i915_private_t *dev_priv = dev->dev_private;
 549         struct drm_i915_master_private *master_priv =
 550                 dev->primary->master->driver_priv;
 551         int ret;
 552
 553         if (!master_priv->sarea_priv)
 554                 return -EINVAL;
 555
 556         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 557                           __func__,
 558                          dev_priv->dri1.current_page,
 559                          master_priv->sarea_priv->pf_current_page);
 560
 561         i915_kernel_lost_context(dev);
 562
 563         ret = BEGIN_LP_RING(10);
 564         if (ret)
 565                 return ret;
 566
 567         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 568         OUT_RING(0);
 569
 570         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 571         OUT_RING(0);
 572         if (dev_priv->dri1.current_page == 0) {
 573                 OUT_RING(dev_priv->dri1.back_offset);
 574                 dev_priv->dri1.current_page = 1;
 575         } else {
 576                 OUT_RING(dev_priv->dri1.front_offset);
 577                 dev_priv->dri1.current_page = 0;
 578         }
 579         OUT_RING(0);
 580
 581         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 582         OUT_RING(0);
 583
 584         ADVANCE_LP_RING();
 585
 586         master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 587
 588         if (BEGIN_LP_RING(4) == 0) {
 589                 OUT_RING(MI_STORE_DWORD_INDEX);
 590                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 591                 OUT_RING(dev_priv->dri1.counter);
 592                 OUT_RING(0);
 593                 ADVANCE_LP_RING();
 594         }
 595
 596         master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 597         return 0;
 598 }
 599
 600 static int i915_quiescent(struct drm_device *dev)
 601 {
 602         i915_kernel_lost_context(dev);
 603         return intel_ring_idle(LP_RING(dev->dev_private));
 604 }
 605
 606 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 607                             struct drm_file *file_priv)
 608 {
 609         int ret;
 610
 611         if (drm_core_check_feature(dev, DRIVER_MODESET))
 612                 return -ENODEV;
 613
 614         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 615
 616         mutex_lock(&dev->struct_mutex);
 617         ret = i915_quiescent(dev);
 618         mutex_unlock(&dev->struct_mutex);
 619
 620         return ret;
 621 }
 622
 623 static int i915_batchbuffer(struct drm_device *dev, void *data,
 624                             struct drm_file *file_priv)
 625 {
 626         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 627         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 628         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 629             master_priv->sarea_priv;
 630         drm_i915_batchbuffer_t *batch = data;
 631         int ret;
 632         struct drm_clip_rect *cliprects = NULL;
 633
 634         if (drm_core_check_feature(dev, DRIVER_MODESET))
 635                 return -ENODEV;
 636
 637         if (!dev_priv->dri1.allow_batchbuffer) {
 638                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 639                 return -EINVAL;
 640         }
 641
 642         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 643                         batch->start, batch->used, batch->num_cliprects);
 644
 645         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 646
 647         if (batch->num_cliprects < 0)
 648                 return -EINVAL;
 649
 650         if (batch->num_cliprects) {
 651                 cliprects = kcalloc(batch->num_cliprects,
 652                                     sizeof(*cliprects),
 653                                     GFP_KERNEL);
 654                 if (cliprects == NULL)
 655                         return -ENOMEM;
 656
 657                 ret = copy_from_user(cliprects, batch->cliprects,
 658                                      batch->num_cliprects *
 659                                      sizeof(struct drm_clip_rect));
 660                 if (ret != 0) {
 661                         ret = -EFAULT;
 662                         goto fail_free;
 663                 }
 664         }
 665
 666         mutex_lock(&dev->struct_mutex);
 667         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 668         mutex_unlock(&dev->struct_mutex);
 669
 670         if (sarea_priv)
 671                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 672
 673 fail_free:
 674         kfree(cliprects);
 675
 676         return ret;
 677 }
 678
 679 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 680                           struct drm_file *file_priv)
 681 {
 682         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 683         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 684         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 685             master_priv->sarea_priv;
 686         drm_i915_cmdbuffer_t *cmdbuf = data;
 687         struct drm_clip_rect *cliprects = NULL;
 688         void *batch_data;
 689         int ret;
 690
 691         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 692                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 693
 694         if (drm_core_check_feature(dev, DRIVER_MODESET))
 695                 return -ENODEV;
 696
 697         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 698
 699         if (cmdbuf->num_cliprects < 0)
 700                 return -EINVAL;
 701
 702         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 703         if (batch_data == NULL)
 704                 return -ENOMEM;
 705
 706         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 707         if (ret != 0) {
 708                 ret = -EFAULT;
 709                 goto fail_batch_free;
 710         }
 711
 712         if (cmdbuf->num_cliprects) {
 713                 cliprects = kcalloc(cmdbuf->num_cliprects,
 714                                     sizeof(*cliprects), GFP_KERNEL);
 715                 if (cliprects == NULL) {
 716                         ret = -ENOMEM;
 717                         goto fail_batch_free;
 718                 }
 719
 720                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 721                                      cmdbuf->num_cliprects *
 722                                      sizeof(struct drm_clip_rect));
 723                 if (ret != 0) {
 724                         ret = -EFAULT;
 725                         goto fail_clip_free;
 726                 }
 727         }
 728
 729         mutex_lock(&dev->struct_mutex);
 730         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 731         mutex_unlock(&dev->struct_mutex);
 732         if (ret) {
 733                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 734                 goto fail_clip_free;
 735         }
 736
 737         if (sarea_priv)
 738                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 739
 740 fail_clip_free:
 741         kfree(cliprects);
 742 fail_batch_free:
 743         kfree(batch_data);
 744
 745         return ret;
 746 }
 747
 748 static int i915_emit_irq(struct drm_device * dev)
 749 {
 750         drm_i915_private_t *dev_priv = dev->dev_private;
 751         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 752
 753         i915_kernel_lost_context(dev);
 754
 755         DRM_DEBUG_DRIVER("\n");
 756
 757         dev_priv->dri1.counter++;
 758         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 759                 dev_priv->dri1.counter = 1;
 760         if (master_priv->sarea_priv)
 761                 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 762
 763         if (BEGIN_LP_RING(4) == 0) {
 764                 OUT_RING(MI_STORE_DWORD_INDEX);
 765                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 766                 OUT_RING(dev_priv->dri1.counter);
 767                 OUT_RING(MI_USER_INTERRUPT);
 768                 ADVANCE_LP_RING();
 769         }
 770
 771         return dev_priv->dri1.counter;
 772 }
 773
 774 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 775 {
 776         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 777         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 778         int ret = 0;
 779         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 780
 781         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 782                   READ_BREADCRUMB(dev_priv));
 783
 784         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 785                 if (master_priv->sarea_priv)
 786                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 787                 return 0;
 788         }
 789
 790         if (master_priv->sarea_priv)
 791                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 792
 793         if (ring->irq_get(ring)) {
 794                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
 795                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 796                 ring->irq_put(ring);
 797         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 798                 ret = -EBUSY;
 799
 800         if (ret == -EBUSY) {
 801                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 802                           READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
 803         }
 804
 805         return ret;
 806 }
 807
 808 /* Needs the lock as it touches the ring.
 809  */
 810 static int i915_irq_emit(struct drm_device *dev, void *data,
 811                          struct drm_file *file_priv)
 812 {
 813         drm_i915_private_t *dev_priv = dev->dev_private;
 814         drm_i915_irq_emit_t *emit = data;
 815         int result;
 816
 817         if (drm_core_check_feature(dev, DRIVER_MODESET))
 818                 return -ENODEV;
 819
 820         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 821                 DRM_ERROR("called with no initialization\n");
 822                 return -EINVAL;
 823         }
 824
 825         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 826
 827         mutex_lock(&dev->struct_mutex);
 828         result = i915_emit_irq(dev);
 829         mutex_unlock(&dev->struct_mutex);
 830
 831         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 832                 DRM_ERROR("copy_to_user\n");
 833                 return -EFAULT;
 834         }
 835
 836         return 0;
 837 }
 838
 839 /* Doesn't need the hardware lock.
 840  */
 841 static int i915_irq_wait(struct drm_device *dev, void *data,
 842                          struct drm_file *file_priv)
 843 {
 844         drm_i915_private_t *dev_priv = dev->dev_private;
 845         drm_i915_irq_wait_t *irqwait = data;
 846
 847         if (drm_core_check_feature(dev, DRIVER_MODESET))
 848                 return -ENODEV;
 849
 850         if (!dev_priv) {
 851                 DRM_ERROR("called with no initialization\n");
 852                 return -EINVAL;
 853         }
 854
 855         return i915_wait_irq(dev, irqwait->irq_seq);
 856 }
 857
 858 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 859                          struct drm_file *file_priv)
 860 {
 861         drm_i915_private_t *dev_priv = dev->dev_private;
 862         drm_i915_vblank_pipe_t *pipe = data;
 863
 864         if (drm_core_check_feature(dev, DRIVER_MODESET))
 865                 return -ENODEV;
 866
 867         if (!dev_priv) {
 868                 DRM_ERROR("called with no initialization\n");
 869                 return -EINVAL;
 870         }
 871
 872         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 873
 874         return 0;
 875 }
 876
 877 /**
 878  * Schedule buffer swap at given vertical blank.
 879  */
 880 static int i915_vblank_swap(struct drm_device *dev, void *data,
 881                      struct drm_file *file_priv)
 882 {
 883         /* The delayed swap mechanism was fundamentally racy, and has been
 884          * removed.  The model was that the client requested a delayed flip/swap
 885          * from the kernel, then waited for vblank before continuing to perform
 886          * rendering.  The problem was that the kernel might wake the client
 887          * up before it dispatched the vblank swap (since the lock has to be
 888          * held while touching the ringbuffer), in which case the client would
 889          * clear and start the next frame before the swap occurred, and
 890          * flicker would occur in addition to likely missing the vblank.
 891          *
 892          * In the absence of this ioctl, userland falls back to a correct path
 893          * of waiting for a vblank, then dispatching the swap on its own.
 894          * Context switching to userland and back is plenty fast enough for
 895          * meeting the requirements of vblank swapping.
 896          */
 897         return -EINVAL;
 898 }
 899
 900 static int i915_flip_bufs(struct drm_device *dev, void *data,
 901                           struct drm_file *file_priv)
 902 {
 903         int ret;
 904
 905         if (drm_core_check_feature(dev, DRIVER_MODESET))
 906                 return -ENODEV;
 907
 908         DRM_DEBUG_DRIVER("%s\n", __func__);
 909
 910         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 911
 912         mutex_lock(&dev->struct_mutex);
 913         ret = i915_dispatch_flip(dev);
 914         mutex_unlock(&dev->struct_mutex);
 915
 916         return ret;
 917 }
 918
 919 static int i915_getparam(struct drm_device *dev, void *data,
 920                          struct drm_file *file_priv)
 921 {
 922         drm_i915_private_t *dev_priv = dev->dev_private;
 923         drm_i915_getparam_t *param = data;
 924         int value;
 925
 926         if (!dev_priv) {
 927                 DRM_ERROR("called with no initialization\n");
 928                 return -EINVAL;
 929         }
 930
 931         switch (param->param) {
 932         case I915_PARAM_IRQ_ACTIVE:
 933                 value = dev->pdev->irq ? 1 : 0;
 934                 break;
 935         case I915_PARAM_ALLOW_BATCHBUFFER:
 936                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 937                 break;
 938         case I915_PARAM_LAST_DISPATCH:
 939                 value = READ_BREADCRUMB(dev_priv);
 940                 break;
 941         case I915_PARAM_CHIPSET_ID:
 942                 value = dev->pdev->device;
 943                 break;
 944         case I915_PARAM_HAS_GEM:
 945                 value = 1;
 946                 break;
 947         case I915_PARAM_NUM_FENCES_AVAIL:
 948                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 949                 break;
 950         case I915_PARAM_HAS_OVERLAY:
 951                 value = dev_priv->overlay ? 1 : 0;
 952                 break;
 953         case I915_PARAM_HAS_PAGEFLIPPING:
 954                 value = 1;
 955                 break;
 956         case I915_PARAM_HAS_EXECBUF2:
 957                 /* depends on GEM */
 958                 value = 1;
 959                 break;
 960         case I915_PARAM_HAS_BSD:
 961                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 962                 break;
 963         case I915_PARAM_HAS_BLT:
 964                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 965                 break;
 966         case I915_PARAM_HAS_VEBOX:
 967                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
 968                 break;
 969         case I915_PARAM_HAS_RELAXED_FENCING:
 970                 value = 1;
 971                 break;
 972         case I915_PARAM_HAS_COHERENT_RINGS:
 973                 value = 1;
 974                 break;
 975         case I915_PARAM_HAS_EXEC_CONSTANTS:
 976                 value = INTEL_INFO(dev)->gen >= 4;
 977                 break;
 978         case I915_PARAM_HAS_RELAXED_DELTA:
 979                 value = 1;
 980                 break;
 981         case I915_PARAM_HAS_GEN7_SOL_RESET:
 982                 value = 1;
 983                 break;
 984         case I915_PARAM_HAS_LLC:
 985                 value = HAS_LLC(dev);
 986                 break;
 987         case I915_PARAM_HAS_WT:
 988                 value = HAS_WT(dev);
 989                 break;
 990         case I915_PARAM_HAS_ALIASING_PPGTT:
 991                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
 992                 break;
 993         case I915_PARAM_HAS_WAIT_TIMEOUT:
 994                 value = 1;
 995                 break;
 996         case I915_PARAM_HAS_SEMAPHORES:
 997                 value = i915_semaphore_is_enabled(dev);
 998                 break;
 999         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
1000                 value = 1;
1001                 break;
1002         case I915_PARAM_HAS_SECURE_BATCHES:
1003                 value = capable(CAP_SYS_ADMIN);
1004                 break;
1005         case I915_PARAM_HAS_PINNED_BATCHES:
1006                 value = 1;
1007                 break;
1008         case I915_PARAM_HAS_EXEC_NO_RELOC:
1009                 value = 1;
1010                 break;
1011         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1012                 value = 1;
1013                 break;
1014         default:
1015                 DRM_DEBUG("Unknown parameter %d\n", param->param);
1016                 return -EINVAL;
1017         }
1018
1019         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1020                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1021                 return -EFAULT;
1022         }
1023
1024         return 0;
1025 }
1026
1027 static int i915_setparam(struct drm_device *dev, void *data,
1028                          struct drm_file *file_priv)
1029 {
1030         drm_i915_private_t *dev_priv = dev->dev_private;
1031         drm_i915_setparam_t *param = data;
1032
1033         if (!dev_priv) {
1034                 DRM_ERROR("called with no initialization\n");
1035                 return -EINVAL;
1036         }
1037
1038         switch (param->param) {
1039         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1040                 break;
1041         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1042                 break;
1043         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1044                 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1045                 break;
1046         case I915_SETPARAM_NUM_USED_FENCES:
1047                 if (param->value > dev_priv->num_fence_regs ||
1048                     param->value < 0)
1049                         return -EINVAL;
1050                 /* Userspace can use first N regs */
1051                 dev_priv->fence_reg_start = param->value;
1052                 break;
1053         default:
1054                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1055                                         param->param);
1056                 return -EINVAL;
1057         }
1058
1059         return 0;
1060 }
1061
1062 static int i915_set_status_page(struct drm_device *dev, void *data,
1063                                 struct drm_file *file_priv)
1064 {
1065         drm_i915_private_t *dev_priv = dev->dev_private;
1066         drm_i915_hws_addr_t *hws = data;
1067         struct intel_ring_buffer *ring;
1068
1069         if (drm_core_check_feature(dev, DRIVER_MODESET))
1070                 return -ENODEV;
1071
1072         if (!I915_NEED_GFX_HWS(dev))
1073                 return -EINVAL;
1074
1075         if (!dev_priv) {
1076                 DRM_ERROR("called with no initialization\n");
1077                 return -EINVAL;
1078         }
1079
1080         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1081                 WARN(1, "tried to set status page when mode setting active\n");
1082                 return 0;
1083         }
1084
1085         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1086
1087         ring = LP_RING(dev_priv);
1088         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1089
1090         dev_priv->dri1.gfx_hws_cpu_addr =
1091                 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1092         if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1093                 i915_dma_cleanup(dev);
1094                 ring->status_page.gfx_addr = 0;
1095                 DRM_ERROR("can not ioremap virtual address for"
1096                                 " G33 hw status page\n");
1097                 return -ENOMEM;
1098         }
1099
1100         memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1101         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1102
1103         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1104                          ring->status_page.gfx_addr);
1105         DRM_DEBUG_DRIVER("load hws at %p\n",
1106                          ring->status_page.page_addr);
1107         return 0;
1108 }
1109
1110 static int i915_get_bridge_dev(struct drm_device *dev)
1111 {
1112         struct drm_i915_private *dev_priv = dev->dev_private;
1113
1114         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1115         if (!dev_priv->bridge_dev) {
1116                 DRM_ERROR("bridge device not found\n");
1117                 return -1;
1118         }
1119         return 0;
1120 }
1121
1122 #define MCHBAR_I915 0x44
1123 #define MCHBAR_I965 0x48
1124 #define MCHBAR_SIZE (4*4096)
1125
1126 #define DEVEN_REG 0x54
1127 #define   DEVEN_MCHBAR_EN (1 << 28)
1128
1129 /* Allocate space for the MCH regs if needed, return nonzero on error */
1130 static int
1131 intel_alloc_mchbar_resource(struct drm_device *dev)
1132 {
1133         drm_i915_private_t *dev_priv = dev->dev_private;
1134         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1135         u32 temp_lo, temp_hi = 0;
1136         u64 mchbar_addr;
1137         int ret;
1138
1139         if (INTEL_INFO(dev)->gen >= 4)
1140                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1141         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1142         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1143
1144         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1145 #ifdef CONFIG_PNP
1146         if (mchbar_addr &&
1147             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1148                 return 0;
1149 #endif
1150
1151         /* Get some space for it */
1152         dev_priv->mch_res.name = "i915 MCHBAR";
1153         dev_priv->mch_res.flags = IORESOURCE_MEM;
1154         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1155                                      &dev_priv->mch_res,
1156                                      MCHBAR_SIZE, MCHBAR_SIZE,
1157                                      PCIBIOS_MIN_MEM,
1158                                      0, pcibios_align_resource,
1159                                      dev_priv->bridge_dev);
1160         if (ret) {
1161                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1162                 dev_priv->mch_res.start = 0;
1163                 return ret;
1164         }
1165
1166         if (INTEL_INFO(dev)->gen >= 4)
1167                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1168                                        upper_32_bits(dev_priv->mch_res.start));
1169
1170         pci_write_config_dword(dev_priv->bridge_dev, reg,
1171                                lower_32_bits(dev_priv->mch_res.start));
1172         return 0;
1173 }
1174
1175 /* Setup MCHBAR if possible, return true if we should disable it again */
1176 static void
1177 intel_setup_mchbar(struct drm_device *dev)
1178 {
1179         drm_i915_private_t *dev_priv = dev->dev_private;
1180         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1181         u32 temp;
1182         bool enabled;
1183
1184         dev_priv->mchbar_need_disable = false;
1185
1186         if (IS_I915G(dev) || IS_I915GM(dev)) {
1187                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1188                 enabled = !!(temp & DEVEN_MCHBAR_EN);
1189         } else {
1190                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1191                 enabled = temp & 1;
1192         }
1193
1194         /* If it's already enabled, don't have to do anything */
1195         if (enabled)
1196                 return;
1197
1198         if (intel_alloc_mchbar_resource(dev))
1199                 return;
1200
1201         dev_priv->mchbar_need_disable = true;
1202
1203         /* Space is allocated or reserved, so enable it. */
1204         if (IS_I915G(dev) || IS_I915GM(dev)) {
1205                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1206                                        temp | DEVEN_MCHBAR_EN);
1207         } else {
1208                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1209                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1210         }
1211 }
1212
1213 static void
1214 intel_teardown_mchbar(struct drm_device *dev)
1215 {
1216         drm_i915_private_t *dev_priv = dev->dev_private;
1217         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1218         u32 temp;
1219
1220         if (dev_priv->mchbar_need_disable) {
1221                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1222                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1223                         temp &= ~DEVEN_MCHBAR_EN;
1224                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1225                 } else {
1226                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1227                         temp &= ~1;
1228                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1229                 }
1230         }
1231
1232         if (dev_priv->mch_res.start)
1233                 release_resource(&dev_priv->mch_res);
1234 }
1235
1236 /* true = enable decode, false = disable decoder */
1237 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1238 {
1239         struct drm_device *dev = cookie;
1240
1241         intel_modeset_vga_set_state(dev, state);
1242         if (state)
1243                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1244                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1245         else
1246                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1247 }
1248
1249 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1250 {
1251         struct drm_device *dev = pci_get_drvdata(pdev);
1252         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1253         if (state == VGA_SWITCHEROO_ON) {
1254                 pr_info("switched on\n");
1255                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1256                 /* i915 resume handler doesn't set to D0 */
1257                 pci_set_power_state(dev->pdev, PCI_D0);
1258                 i915_resume(dev);
1259                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1260         } else {
1261                 pr_err("switched off\n");
1262                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1263                 i915_suspend(dev, pmm);
1264                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1265         }
1266 }
1267
1268 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1269 {
1270         struct drm_device *dev = pci_get_drvdata(pdev);
1271         bool can_switch;
1272
1273         spin_lock(&dev->count_lock);
1274         can_switch = (dev->open_count == 0);
1275         spin_unlock(&dev->count_lock);
1276         return can_switch;
1277 }
1278
1279 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1280         .set_gpu_state = i915_switcheroo_set_state,
1281         .reprobe = NULL,
1282         .can_switch = i915_switcheroo_can_switch,
1283 };
1284
1285 static int i915_load_modeset_init(struct drm_device *dev)
1286 {
1287         struct drm_i915_private *dev_priv = dev->dev_private;
1288         int ret;
1289
1290         ret = intel_parse_bios(dev);
1291         if (ret)
1292                 DRM_INFO("failed to find VBIOS tables\n");
1293
1294         /* If we have > 1 VGA cards, then we need to arbitrate access
1295          * to the common VGA resources.
1296          *
1297          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1298          * then we do not take part in VGA arbitration and the
1299          * vga_client_register() fails with -ENODEV.
1300          */
1301         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1302         if (ret && ret != -ENODEV)
1303                 goto out;
1304
1305         intel_register_dsm_handler();
1306
1307         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
1308         if (ret)
1309                 goto cleanup_vga_client;
1310
1311         /* Initialise stolen first so that we may reserve preallocated
1312          * objects for the BIOS to KMS transition.
1313          */
1314         ret = i915_gem_init_stolen(dev);
1315         if (ret)
1316                 goto cleanup_vga_switcheroo;
1317
1318         ret = drm_irq_install(dev);
1319         if (ret)
1320                 goto cleanup_gem_stolen;
1321
1322         intel_power_domains_init_hw(dev);
1323
1324         /* Important: The output setup functions called by modeset_init need
1325          * working irqs for e.g. gmbus and dp aux transfers. */
1326         intel_modeset_init(dev);
1327
1328         ret = i915_gem_init(dev);
1329         if (ret)
1330                 goto cleanup_power;
1331
1332         INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1333
1334         intel_modeset_gem_init(dev);
1335
1336         /* Always safe in the mode setting case. */
1337         /* FIXME: do pre/post-mode set stuff in core KMS code */
1338         dev->vblank_disable_allowed = true;
1339         if (INTEL_INFO(dev)->num_pipes == 0) {
1340                 intel_display_power_put(dev, POWER_DOMAIN_VGA);
1341                 return 0;
1342         }
1343
1344         ret = intel_fbdev_init(dev);
1345         if (ret)
1346                 goto cleanup_gem;
1347
1348         /* Only enable hotplug handling once the fbdev is fully set up. */
1349         intel_hpd_init(dev);
1350
1351         /*
1352          * Some ports require correctly set-up hpd registers for detection to
1353          * work properly (leading to ghost connected connector status), e.g. VGA
1354          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1355          * irqs are fully enabled. Now we should scan for the initial config
1356          * only once hotplug handling is enabled, but due to screwed-up locking
1357          * around kms/fbdev init we can't protect the fdbev initial config
1358          * scanning against hotplug events. Hence do this first and ignore the
1359          * tiny window where we will loose hotplug notifactions.
1360          */
1361         intel_fbdev_initial_config(dev);
1362
1363         /* Only enable hotplug handling once the fbdev is fully set up. */
1364         dev_priv->enable_hotplug_processing = true;
1365
1366         drm_kms_helper_poll_init(dev);
1367
1368         return 0;
1369
1370 cleanup_gem:
1371         mutex_lock(&dev->struct_mutex);
1372         i915_gem_cleanup_ringbuffer(dev);
1373         i915_gem_context_fini(dev);
1374         mutex_unlock(&dev->struct_mutex);
1375         i915_gem_cleanup_aliasing_ppgtt(dev);
1376         drm_mm_takedown(&dev_priv->gtt.base.mm);
1377 cleanup_power:
1378         intel_display_power_put(dev, POWER_DOMAIN_VGA);
1379         drm_irq_uninstall(dev);
1380 cleanup_gem_stolen:
1381         i915_gem_cleanup_stolen(dev);
1382 cleanup_vga_switcheroo:
1383         vga_switcheroo_unregister_client(dev->pdev);
1384 cleanup_vga_client:
1385         vga_client_register(dev->pdev, NULL, NULL, NULL);
1386 out:
1387         return ret;
1388 }
1389
1390 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1391 {
1392         struct drm_i915_master_private *master_priv;
1393
1394         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1395         if (!master_priv)
1396                 return -ENOMEM;
1397
1398         master->driver_priv = master_priv;
1399         return 0;
1400 }
1401
1402 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1403 {
1404         struct drm_i915_master_private *master_priv = master->driver_priv;
1405
1406         if (!master_priv)
1407                 return;
1408
1409         kfree(master_priv);
1410
1411         master->driver_priv = NULL;
1412 }
1413
1414 #ifdef CONFIG_DRM_I915_FBDEV
1415 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1416 {
1417         struct apertures_struct *ap;
1418         struct pci_dev *pdev = dev_priv->dev->pdev;
1419         bool primary;
1420
1421         ap = alloc_apertures(1);
1422         if (!ap)
1423                 return;
1424
1425         ap->ranges[0].base = dev_priv->gtt.mappable_base;
1426         ap->ranges[0].size = dev_priv->gtt.mappable_end;
1427
1428         primary =
1429                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1430
1431         remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1432
1433         kfree(ap);
1434 }
1435 #else
1436 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1437 {
1438 }
1439 #endif
1440
1441 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1442 {
1443         const struct intel_device_info *info = dev_priv->info;
1444
1445 #define PRINT_S(name) "%s"
1446 #define SEP_EMPTY
1447 #define PRINT_FLAG(name) info->name ? #name "," : ""
1448 #define SEP_COMMA ,
1449         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1450                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
1451                          info->gen,
1452                          dev_priv->dev->pdev->device,
1453                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
1454 #undef PRINT_S
1455 #undef SEP_EMPTY
1456 #undef PRINT_FLAG
1457 #undef SEP_COMMA
1458 }
1459
1460 /**
1461  * i915_driver_load - setup chip and create an initial config
1462  * @dev: DRM device
1463  * @flags: startup flags
1464  *
1465  * The driver load routine has to do several things:
1466  *   - drive output discovery via intel_modeset_init()
1467  *   - initialize the memory manager
1468  *   - allocate initial config memory
1469  *   - setup the DRM framebuffer with the allocated memory
1470  */
1471 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1472 {
1473         struct drm_i915_private *dev_priv;
1474         struct intel_device_info *info;
1475         int ret = 0, mmio_bar, mmio_size;
1476         uint32_t aperture_size;
1477
1478         info = (struct intel_device_info *) flags;
1479
1480         /* Refuse to load on gen6+ without kms enabled. */
1481         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
1482                 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
1483                 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
1484                 return -ENODEV;
1485         }
1486
1487         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1488         if (dev_priv == NULL)
1489                 return -ENOMEM;
1490
1491         dev->dev_private = (void *)dev_priv;
1492         dev_priv->dev = dev;
1493         dev_priv->info = info;
1494
1495         spin_lock_init(&dev_priv->irq_lock);
1496         spin_lock_init(&dev_priv->gpu_error.lock);
1497         spin_lock_init(&dev_priv->backlight.lock);
1498         spin_lock_init(&dev_priv->uncore.lock);
1499         spin_lock_init(&dev_priv->mm.object_stat_lock);
1500         mutex_init(&dev_priv->dpio_lock);
1501         mutex_init(&dev_priv->modeset_restore_lock);
1502
1503         intel_pm_setup(dev);
1504
1505         intel_display_crc_init(dev);
1506
1507         i915_dump_device_info(dev_priv);
1508
1509         /* Not all pre-production machines fall into this category, only the
1510          * very first ones. Almost everything should work, except for maybe
1511          * suspend/resume. And we don't implement workarounds that affect only
1512          * pre-production machines. */
1513         if (IS_HSW_EARLY_SDV(dev))
1514                 DRM_INFO("This is an early pre-production Haswell machine. "
1515                          "It may not be fully functional.\n");
1516
1517         if (i915_get_bridge_dev(dev)) {
1518                 ret = -EIO;
1519                 goto free_priv;
1520         }
1521
1522         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1523         /* Before gen4, the registers and the GTT are behind different BARs.
1524          * However, from gen4 onwards, the registers and the GTT are shared
1525          * in the same BAR, so we want to restrict this ioremap from
1526          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1527          * the register BAR remains the same size for all the earlier
1528          * generations up to Ironlake.
1529          */
1530         if (info->gen < 5)
1531                 mmio_size = 512*1024;
1532         else
1533                 mmio_size = 2*1024*1024;
1534
1535         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1536         if (!dev_priv->regs) {
1537                 DRM_ERROR("failed to map registers\n");
1538                 ret = -EIO;
1539                 goto put_bridge;
1540         }
1541
1542         intel_uncore_early_sanitize(dev);
1543
1544         /* This must be called before any calls to HAS_PCH_* */
1545         intel_detect_pch(dev);
1546
1547         intel_uncore_init(dev);
1548
1549         ret = i915_gem_gtt_init(dev);
1550         if (ret)
1551                 goto out_regs;
1552
1553         if (drm_core_check_feature(dev, DRIVER_MODESET))
1554                 i915_kick_out_firmware_fb(dev_priv);
1555
1556         pci_set_master(dev->pdev);
1557
1558         /* overlay on gen2 is broken and can't address above 1G */
1559         if (IS_GEN2(dev))
1560                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1561
1562         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1563          * using 32bit addressing, overwriting memory if HWS is located
1564          * above 4GB.
1565          *
1566          * The documentation also mentions an issue with undefined
1567          * behaviour if any general state is accessed within a page above 4GB,
1568          * which also needs to be handled carefully.
1569          */
1570         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1571                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1572
1573         aperture_size = dev_priv->gtt.mappable_end;
1574
1575         dev_priv->gtt.mappable =
1576                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1577                                      aperture_size);
1578         if (dev_priv->gtt.mappable == NULL) {
1579                 ret = -EIO;
1580                 goto out_gtt;
1581         }
1582
1583         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
1584                                               aperture_size);
1585
1586         /* The i915 workqueue is primarily used for batched retirement of
1587          * requests (and thus managing bo) once the task has been completed
1588          * by the GPU. i915_gem_retire_requests() is called directly when we
1589          * need high-priority retirement, such as waiting for an explicit
1590          * bo.
1591          *
1592          * It is also used for periodic low-priority events, such as
1593          * idle-timers and recording error state.
1594          *
1595          * All tasks on the workqueue are expected to acquire the dev mutex
1596          * so there is no point in running more than one instance of the
1597          * workqueue at any time.  Use an ordered one.
1598          */
1599         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1600         if (dev_priv->wq == NULL) {
1601                 DRM_ERROR("Failed to create our workqueue.\n");
1602                 ret = -ENOMEM;
1603                 goto out_mtrrfree;
1604         }
1605
1606         intel_irq_init(dev);
1607         intel_uncore_sanitize(dev);
1608
1609         /* Try to make sure MCHBAR is enabled before poking at it */
1610         intel_setup_mchbar(dev);
1611         intel_setup_gmbus(dev);
1612         intel_opregion_setup(dev);
1613
1614         intel_setup_bios(dev);
1615
1616         i915_gem_load(dev);
1617
1618         /* On the 945G/GM, the chipset reports the MSI capability on the
1619          * integrated graphics even though the support isn't actually there
1620          * according to the published specs.  It doesn't appear to function
1621          * correctly in testing on 945G.
1622          * This may be a side effect of MSI having been made available for PEG
1623          * and the registers being closely associated.
1624          *
1625          * According to chipset errata, on the 965GM, MSI interrupts may
1626          * be lost or delayed, but we use them anyways to avoid
1627          * stuck interrupts on some machines.
1628          */
1629         if (!IS_I945G(dev) && !IS_I945GM(dev))
1630                 pci_enable_msi(dev->pdev);
1631
1632         dev_priv->num_plane = 1;
1633         if (IS_VALLEYVIEW(dev))
1634                 dev_priv->num_plane = 2;
1635
1636         if (INTEL_INFO(dev)->num_pipes) {
1637                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1638                 if (ret)
1639                         goto out_gem_unload;
1640         }
1641
1642         if (HAS_POWER_WELL(dev))
1643                 intel_power_domains_init(dev);
1644
1645         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1646                 ret = i915_load_modeset_init(dev);
1647                 if (ret < 0) {
1648                         DRM_ERROR("failed to init modeset\n");
1649                         goto out_power_well;
1650                 }
1651         } else {
1652                 /* Start out suspended in ums mode. */
1653                 dev_priv->ums.mm_suspended = 1;
1654         }
1655
1656         i915_setup_sysfs(dev);
1657
1658         if (INTEL_INFO(dev)->num_pipes) {
1659                 /* Must be done after probing outputs */
1660                 intel_opregion_init(dev);
1661                 acpi_video_register();
1662         }
1663
1664         if (IS_GEN5(dev))
1665                 intel_gpu_ips_init(dev_priv);
1666
1667         return 0;
1668
1669 out_power_well:
1670         if (HAS_POWER_WELL(dev))
1671                 intel_power_domains_remove(dev);
1672         drm_vblank_cleanup(dev);
1673 out_gem_unload:
1674         if (dev_priv->mm.inactive_shrinker.scan_objects)
1675                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1676
1677         if (dev->pdev->msi_enabled)
1678                 pci_disable_msi(dev->pdev);
1679
1680         intel_teardown_gmbus(dev);
1681         intel_teardown_mchbar(dev);
1682         destroy_workqueue(dev_priv->wq);
1683 out_mtrrfree:
1684         arch_phys_wc_del(dev_priv->gtt.mtrr);
1685         io_mapping_free(dev_priv->gtt.mappable);
1686 out_gtt:
1687         list_del(&dev_priv->gtt.base.global_link);
1688         drm_mm_takedown(&dev_priv->gtt.base.mm);
1689         dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1690 out_regs:
1691         intel_uncore_fini(dev);
1692         pci_iounmap(dev->pdev, dev_priv->regs);
1693 put_bridge:
1694         pci_dev_put(dev_priv->bridge_dev);
1695 free_priv:
1696         if (dev_priv->slab)
1697                 kmem_cache_destroy(dev_priv->slab);
1698         kfree(dev_priv);
1699         return ret;
1700 }
1701
1702 int i915_driver_unload(struct drm_device *dev)
1703 {
1704         struct drm_i915_private *dev_priv = dev->dev_private;
1705         int ret;
1706
1707         intel_gpu_ips_teardown();
1708
1709         if (HAS_POWER_WELL(dev)) {
1710                 /* The i915.ko module is still not prepared to be loaded when
1711                  * the power well is not enabled, so just enable it in case
1712                  * we're going to unload/reload. */
1713                 intel_display_set_init_power(dev, true);
1714                 intel_power_domains_remove(dev);
1715         }
1716
1717         i915_teardown_sysfs(dev);
1718
1719         if (dev_priv->mm.inactive_shrinker.scan_objects)
1720                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1721
1722         ret = i915_gem_suspend(dev);
1723         if (ret)
1724                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1725
1726         io_mapping_free(dev_priv->gtt.mappable);
1727         arch_phys_wc_del(dev_priv->gtt.mtrr);
1728
1729         acpi_video_unregister();
1730
1731         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1732                 intel_fbdev_fini(dev);
1733                 intel_modeset_cleanup(dev);
1734                 cancel_work_sync(&dev_priv->console_resume_work);
1735
1736                 /*
1737                  * free the memory space allocated for the child device
1738                  * config parsed from VBT
1739                  */
1740                 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1741                         kfree(dev_priv->vbt.child_dev);
1742                         dev_priv->vbt.child_dev = NULL;
1743                         dev_priv->vbt.child_dev_num = 0;
1744                 }
1745
1746                 vga_switcheroo_unregister_client(dev->pdev);
1747                 vga_client_register(dev->pdev, NULL, NULL, NULL);
1748         }
1749
1750         /* Free error state after interrupts are fully disabled. */
1751         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1752         cancel_work_sync(&dev_priv->gpu_error.work);
1753         i915_destroy_error_state(dev);
1754
1755         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
1756
1757         if (dev->pdev->msi_enabled)
1758                 pci_disable_msi(dev->pdev);
1759
1760         intel_opregion_fini(dev);
1761
1762         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1763                 /* Flush any outstanding unpin_work. */
1764                 flush_workqueue(dev_priv->wq);
1765
1766                 mutex_lock(&dev->struct_mutex);
1767                 i915_gem_free_all_phys_object(dev);
1768                 i915_gem_cleanup_ringbuffer(dev);
1769                 i915_gem_context_fini(dev);
1770                 mutex_unlock(&dev->struct_mutex);
1771                 i915_gem_cleanup_aliasing_ppgtt(dev);
1772                 i915_gem_cleanup_stolen(dev);
1773
1774                 if (!I915_NEED_GFX_HWS(dev))
1775                         i915_free_hws(dev);
1776         }
1777
1778         list_del(&dev_priv->gtt.base.global_link);
1779         WARN_ON(!list_empty(&dev_priv->vm_list));
1780         drm_mm_takedown(&dev_priv->gtt.base.mm);
1781
1782         drm_vblank_cleanup(dev);
1783
1784         intel_teardown_gmbus(dev);
1785         intel_teardown_mchbar(dev);
1786
1787         destroy_workqueue(dev_priv->wq);
1788         pm_qos_remove_request(&dev_priv->pm_qos);
1789
1790         dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1791
1792         intel_uncore_fini(dev);
1793         if (dev_priv->regs != NULL)
1794                 pci_iounmap(dev->pdev, dev_priv->regs);
1795
1796         if (dev_priv->slab)
1797                 kmem_cache_destroy(dev_priv->slab);
1798
1799         pci_dev_put(dev_priv->bridge_dev);
1800         kfree(dev->dev_private);
1801
1802         return 0;
1803 }
1804
1805 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1806 {
1807         int ret;
1808
1809         ret = i915_gem_open(dev, file);
1810         if (ret)
1811                 return ret;
1812
1813         return 0;
1814 }
1815
1816 /**
1817  * i915_driver_lastclose - clean up after all DRM clients have exited
1818  * @dev: DRM device
1819  *
1820  * Take care of cleaning up after all DRM clients have exited.  In the
1821  * mode setting case, we want to restore the kernel's initial mode (just
1822  * in case the last client left us in a bad state).
1823  *
1824  * Additionally, in the non-mode setting case, we'll tear down the GTT
1825  * and DMA structures, since the kernel won't be using them, and clea
1826  * up any GEM state.
1827  */
1828 void i915_driver_lastclose(struct drm_device * dev)
1829 {
1830         drm_i915_private_t *dev_priv = dev->dev_private;
1831
1832         /* On gen6+ we refuse to init without kms enabled, but then the drm core
1833          * goes right around and calls lastclose. Check for this and don't clean
1834          * up anything. */
1835         if (!dev_priv)
1836                 return;
1837
1838         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1839                 intel_fbdev_restore_mode(dev);
1840                 vga_switcheroo_process_delayed_switch();
1841                 return;
1842         }
1843
1844         i915_gem_lastclose(dev);
1845
1846         i915_dma_cleanup(dev);
1847 }
1848
1849 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1850 {
1851         mutex_lock(&dev->struct_mutex);
1852         i915_gem_context_close(dev, file_priv);
1853         i915_gem_release(dev, file_priv);
1854         mutex_unlock(&dev->struct_mutex);
1855 }
1856
1857 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1858 {
1859         struct drm_i915_file_private *file_priv = file->driver_priv;
1860
1861         kfree(file_priv);
1862 }
1863
1864 const struct drm_ioctl_desc i915_ioctls[] = {
1865         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1866         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1867         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1868         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1869         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1870         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1871         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1872         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1873         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1874         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1875         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1876         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1877         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1878         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1879         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
1880         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1881         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1882         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1883         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1884         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1885         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1886         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1887         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1888         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1889         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1890         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1891         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1892         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1893         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1894         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1895         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1896         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1897         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1898         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1899         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1900         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1901         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1902         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1903         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1904         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1905         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1906         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1907         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1908         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1909         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1910         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1911         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1912         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1913 };
1914
1915 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1916
1917 /*
1918  * This is really ugly: Because old userspace abused the linux agp interface to
1919  * manage the gtt, we need to claim that all intel devices are agp.  For
1920  * otherwise the drm core refuses to initialize the agp support code.
1921  */
1922 int i915_driver_device_is_agp(struct drm_device * dev)
1923 {
1924         return 1;
1925 }