drivers/gpu/drm/i2c/tda998x_drv.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/component.h>
  19 #include <linux/hdmi.h>
  20 #include <linux/module.h>
  21 #include <linux/irq.h>
  22 #include <sound/asoundef.h>
  23
  24 #include <drm/drmP.h>
  25 #include <drm/drm_crtc_helper.h>
  26 #include <drm/drm_encoder_slave.h>
  27 #include <drm/drm_edid.h>
  28 #include <drm/i2c/tda998x.h>
  29
  30 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
  31
  32 struct tda998x_priv {
  33         struct i2c_client *cec;
  34         struct i2c_client *hdmi;
  35         struct mutex mutex;
  36         struct delayed_work dwork;
  37         uint16_t rev;
  38         uint8_t current_page;
  39         int dpms;
  40         bool is_hdmi_sink;
  41         u8 vip_cntrl_0;
  42         u8 vip_cntrl_1;
  43         u8 vip_cntrl_2;
  44         struct tda998x_encoder_params params;
  45
  46         wait_queue_head_t wq_edid;
  47         volatile int wq_edid_wait;
  48         struct drm_encoder *encoder;
  49 };
  50
  51 #define to_tda998x_priv(x)  ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv)
  52
  53 /* The TDA9988 series of devices use a paged register scheme.. to simplify
  54  * things we encode the page # in upper bits of the register #.  To read/
  55  * write a given register, we need to make sure CURPAGE register is set
  56  * appropriately.  Which implies reads/writes are not atomic.  Fun!
  57  */
  58
  59 #define REG(page, addr) (((page) << 8) | (addr))
  60 #define REG2ADDR(reg)   ((reg) & 0xff)
  61 #define REG2PAGE(reg)   (((reg) >> 8) & 0xff)
  62
  63 #define REG_CURPAGE               0xff                /* write */
  64
  65
  66 /* Page 00h: General Control */
  67 #define REG_VERSION_LSB           REG(0x00, 0x00)     /* read */
  68 #define REG_MAIN_CNTRL0           REG(0x00, 0x01)     /* read/write */
  69 # define MAIN_CNTRL0_SR           (1 << 0)
  70 # define MAIN_CNTRL0_DECS         (1 << 1)
  71 # define MAIN_CNTRL0_DEHS         (1 << 2)
  72 # define MAIN_CNTRL0_CECS         (1 << 3)
  73 # define MAIN_CNTRL0_CEHS         (1 << 4)
  74 # define MAIN_CNTRL0_SCALER       (1 << 7)
  75 #define REG_VERSION_MSB           REG(0x00, 0x02)     /* read */
  76 #define REG_SOFTRESET             REG(0x00, 0x0a)     /* write */
  77 # define SOFTRESET_AUDIO          (1 << 0)
  78 # define SOFTRESET_I2C_MASTER     (1 << 1)
  79 #define REG_DDC_DISABLE           REG(0x00, 0x0b)     /* read/write */
  80 #define REG_CCLK_ON               REG(0x00, 0x0c)     /* read/write */
  81 #define REG_I2C_MASTER            REG(0x00, 0x0d)     /* read/write */
  82 # define I2C_MASTER_DIS_MM        (1 << 0)
  83 # define I2C_MASTER_DIS_FILT      (1 << 1)
  84 # define I2C_MASTER_APP_STRT_LAT  (1 << 2)
  85 #define REG_FEAT_POWERDOWN        REG(0x00, 0x0e)     /* read/write */
  86 # define FEAT_POWERDOWN_SPDIF     (1 << 3)
  87 #define REG_INT_FLAGS_0           REG(0x00, 0x0f)     /* read/write */
  88 #define REG_INT_FLAGS_1           REG(0x00, 0x10)     /* read/write */
  89 #define REG_INT_FLAGS_2           REG(0x00, 0x11)     /* read/write */
  90 # define INT_FLAGS_2_EDID_BLK_RD  (1 << 1)
  91 #define REG_ENA_ACLK              REG(0x00, 0x16)     /* read/write */
  92 #define REG_ENA_VP_0              REG(0x00, 0x18)     /* read/write */
  93 #define REG_ENA_VP_1              REG(0x00, 0x19)     /* read/write */
  94 #define REG_ENA_VP_2              REG(0x00, 0x1a)     /* read/write */
  95 #define REG_ENA_AP                REG(0x00, 0x1e)     /* read/write */
  96 #define REG_VIP_CNTRL_0           REG(0x00, 0x20)     /* write */
  97 # define VIP_CNTRL_0_MIRR_A       (1 << 7)
  98 # define VIP_CNTRL_0_SWAP_A(x)    (((x) & 7) << 4)
  99 # define VIP_CNTRL_0_MIRR_B       (1 << 3)
 100 # define VIP_CNTRL_0_SWAP_B(x)    (((x) & 7) << 0)
 101 #define REG_VIP_CNTRL_1           REG(0x00, 0x21)     /* write */
 102 # define VIP_CNTRL_1_MIRR_C       (1 << 7)
 103 # define VIP_CNTRL_1_SWAP_C(x)    (((x) & 7) << 4)
 104 # define VIP_CNTRL_1_MIRR_D       (1 << 3)
 105 # define VIP_CNTRL_1_SWAP_D(x)    (((x) & 7) << 0)
 106 #define REG_VIP_CNTRL_2           REG(0x00, 0x22)     /* write */
 107 # define VIP_CNTRL_2_MIRR_E       (1 << 7)
 108 # define VIP_CNTRL_2_SWAP_E(x)    (((x) & 7) << 4)
 109 # define VIP_CNTRL_2_MIRR_F       (1 << 3)
 110 # define VIP_CNTRL_2_SWAP_F(x)    (((x) & 7) << 0)
 111 #define REG_VIP_CNTRL_3           REG(0x00, 0x23)     /* write */
 112 # define VIP_CNTRL_3_X_TGL        (1 << 0)
 113 # define VIP_CNTRL_3_H_TGL        (1 << 1)
 114 # define VIP_CNTRL_3_V_TGL        (1 << 2)
 115 # define VIP_CNTRL_3_EMB          (1 << 3)
 116 # define VIP_CNTRL_3_SYNC_DE      (1 << 4)
 117 # define VIP_CNTRL_3_SYNC_HS      (1 << 5)
 118 # define VIP_CNTRL_3_DE_INT       (1 << 6)
 119 # define VIP_CNTRL_3_EDGE         (1 << 7)
 120 #define REG_VIP_CNTRL_4           REG(0x00, 0x24)     /* write */
 121 # define VIP_CNTRL_4_BLC(x)       (((x) & 3) << 0)
 122 # define VIP_CNTRL_4_BLANKIT(x)   (((x) & 3) << 2)
 123 # define VIP_CNTRL_4_CCIR656      (1 << 4)
 124 # define VIP_CNTRL_4_656_ALT      (1 << 5)
 125 # define VIP_CNTRL_4_TST_656      (1 << 6)
 126 # define VIP_CNTRL_4_TST_PAT      (1 << 7)
 127 #define REG_VIP_CNTRL_5           REG(0x00, 0x25)     /* write */
 128 # define VIP_CNTRL_5_CKCASE       (1 << 0)
 129 # define VIP_CNTRL_5_SP_CNT(x)    (((x) & 3) << 1)
 130 #define REG_MUX_AP                REG(0x00, 0x26)     /* read/write */
 131 # define MUX_AP_SELECT_I2S        0x64
 132 # define MUX_AP_SELECT_SPDIF      0x40
 133 #define REG_MUX_VP_VIP_OUT        REG(0x00, 0x27)     /* read/write */
 134 #define REG_MAT_CONTRL            REG(0x00, 0x80)     /* write */
 135 # define MAT_CONTRL_MAT_SC(x)     (((x) & 3) << 0)
 136 # define MAT_CONTRL_MAT_BP        (1 << 2)
 137 #define REG_VIDFORMAT             REG(0x00, 0xa0)     /* write */
 138 #define REG_REFPIX_MSB            REG(0x00, 0xa1)     /* write */
 139 #define REG_REFPIX_LSB            REG(0x00, 0xa2)     /* write */
 140 #define REG_REFLINE_MSB           REG(0x00, 0xa3)     /* write */
 141 #define REG_REFLINE_LSB           REG(0x00, 0xa4)     /* write */
 142 #define REG_NPIX_MSB              REG(0x00, 0xa5)     /* write */
 143 #define REG_NPIX_LSB              REG(0x00, 0xa6)     /* write */
 144 #define REG_NLINE_MSB             REG(0x00, 0xa7)     /* write */
 145 #define REG_NLINE_LSB             REG(0x00, 0xa8)     /* write */
 146 #define REG_VS_LINE_STRT_1_MSB    REG(0x00, 0xa9)     /* write */
 147 #define REG_VS_LINE_STRT_1_LSB    REG(0x00, 0xaa)     /* write */
 148 #define REG_VS_PIX_STRT_1_MSB     REG(0x00, 0xab)     /* write */
 149 #define REG_VS_PIX_STRT_1_LSB     REG(0x00, 0xac)     /* write */
 150 #define REG_VS_LINE_END_1_MSB     REG(0x00, 0xad)     /* write */
 151 #define REG_VS_LINE_END_1_LSB     REG(0x00, 0xae)     /* write */
 152 #define REG_VS_PIX_END_1_MSB      REG(0x00, 0xaf)     /* write */
 153 #define REG_VS_PIX_END_1_LSB      REG(0x00, 0xb0)     /* write */
 154 #define REG_VS_LINE_STRT_2_MSB    REG(0x00, 0xb1)     /* write */
 155 #define REG_VS_LINE_STRT_2_LSB    REG(0x00, 0xb2)     /* write */
 156 #define REG_VS_PIX_STRT_2_MSB     REG(0x00, 0xb3)     /* write */
 157 #define REG_VS_PIX_STRT_2_LSB     REG(0x00, 0xb4)     /* write */
 158 #define REG_VS_LINE_END_2_MSB     REG(0x00, 0xb5)     /* write */
 159 #define REG_VS_LINE_END_2_LSB     REG(0x00, 0xb6)     /* write */
 160 #define REG_VS_PIX_END_2_MSB      REG(0x00, 0xb7)     /* write */
 161 #define REG_VS_PIX_END_2_LSB      REG(0x00, 0xb8)     /* write */
 162 #define REG_HS_PIX_START_MSB      REG(0x00, 0xb9)     /* write */
 163 #define REG_HS_PIX_START_LSB      REG(0x00, 0xba)     /* write */
 164 #define REG_HS_PIX_STOP_MSB       REG(0x00, 0xbb)     /* write */
 165 #define REG_HS_PIX_STOP_LSB       REG(0x00, 0xbc)     /* write */
 166 #define REG_VWIN_START_1_MSB      REG(0x00, 0xbd)     /* write */
 167 #define REG_VWIN_START_1_LSB      REG(0x00, 0xbe)     /* write */
 168 #define REG_VWIN_END_1_MSB        REG(0x00, 0xbf)     /* write */
 169 #define REG_VWIN_END_1_LSB        REG(0x00, 0xc0)     /* write */
 170 #define REG_VWIN_START_2_MSB      REG(0x00, 0xc1)     /* write */
 171 #define REG_VWIN_START_2_LSB      REG(0x00, 0xc2)     /* write */
 172 #define REG_VWIN_END_2_MSB        REG(0x00, 0xc3)     /* write */
 173 #define REG_VWIN_END_2_LSB        REG(0x00, 0xc4)     /* write */
 174 #define REG_DE_START_MSB          REG(0x00, 0xc5)     /* write */
 175 #define REG_DE_START_LSB          REG(0x00, 0xc6)     /* write */
 176 #define REG_DE_STOP_MSB           REG(0x00, 0xc7)     /* write */
 177 #define REG_DE_STOP_LSB           REG(0x00, 0xc8)     /* write */
 178 #define REG_TBG_CNTRL_0           REG(0x00, 0xca)     /* write */
 179 # define TBG_CNTRL_0_TOP_TGL      (1 << 0)
 180 # define TBG_CNTRL_0_TOP_SEL      (1 << 1)
 181 # define TBG_CNTRL_0_DE_EXT       (1 << 2)
 182 # define TBG_CNTRL_0_TOP_EXT      (1 << 3)
 183 # define TBG_CNTRL_0_FRAME_DIS    (1 << 5)
 184 # define TBG_CNTRL_0_SYNC_MTHD    (1 << 6)
 185 # define TBG_CNTRL_0_SYNC_ONCE    (1 << 7)
 186 #define REG_TBG_CNTRL_1           REG(0x00, 0xcb)     /* write */
 187 # define TBG_CNTRL_1_H_TGL        (1 << 0)
 188 # define TBG_CNTRL_1_V_TGL        (1 << 1)
 189 # define TBG_CNTRL_1_TGL_EN       (1 << 2)
 190 # define TBG_CNTRL_1_X_EXT        (1 << 3)
 191 # define TBG_CNTRL_1_H_EXT        (1 << 4)
 192 # define TBG_CNTRL_1_V_EXT        (1 << 5)
 193 # define TBG_CNTRL_1_DWIN_DIS     (1 << 6)
 194 #define REG_ENABLE_SPACE          REG(0x00, 0xd6)     /* write */
 195 #define REG_HVF_CNTRL_0           REG(0x00, 0xe4)     /* write */
 196 # define HVF_CNTRL_0_SM           (1 << 7)
 197 # define HVF_CNTRL_0_RWB          (1 << 6)
 198 # define HVF_CNTRL_0_PREFIL(x)    (((x) & 3) << 2)
 199 # define HVF_CNTRL_0_INTPOL(x)    (((x) & 3) << 0)
 200 #define REG_HVF_CNTRL_1           REG(0x00, 0xe5)     /* write */
 201 # define HVF_CNTRL_1_FOR          (1 << 0)
 202 # define HVF_CNTRL_1_YUVBLK       (1 << 1)
 203 # define HVF_CNTRL_1_VQR(x)       (((x) & 3) << 2)
 204 # define HVF_CNTRL_1_PAD(x)       (((x) & 3) << 4)
 205 # define HVF_CNTRL_1_SEMI_PLANAR  (1 << 6)
 206 #define REG_RPT_CNTRL             REG(0x00, 0xf0)     /* write */
 207 #define REG_I2S_FORMAT            REG(0x00, 0xfc)     /* read/write */
 208 # define I2S_FORMAT(x)            (((x) & 3) << 0)
 209 #define REG_AIP_CLKSEL            REG(0x00, 0xfd)     /* write */
 210 # define AIP_CLKSEL_AIP_SPDIF     (0 << 3)
 211 # define AIP_CLKSEL_AIP_I2S       (1 << 3)
 212 # define AIP_CLKSEL_FS_ACLK       (0 << 0)
 213 # define AIP_CLKSEL_FS_MCLK       (1 << 0)
 214 # define AIP_CLKSEL_FS_FS64SPDIF  (2 << 0)
 215
 216 /* Page 02h: PLL settings */
 217 #define REG_PLL_SERIAL_1          REG(0x02, 0x00)     /* read/write */
 218 # define PLL_SERIAL_1_SRL_FDN     (1 << 0)
 219 # define PLL_SERIAL_1_SRL_IZ(x)   (((x) & 3) << 1)
 220 # define PLL_SERIAL_1_SRL_MAN_IZ  (1 << 6)
 221 #define REG_PLL_SERIAL_2          REG(0x02, 0x01)     /* read/write */
 222 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
 223 # define PLL_SERIAL_2_SRL_PR(x)   (((x) & 0xf) << 4)
 224 #define REG_PLL_SERIAL_3          REG(0x02, 0x02)     /* read/write */
 225 # define PLL_SERIAL_3_SRL_CCIR    (1 << 0)
 226 # define PLL_SERIAL_3_SRL_DE      (1 << 2)
 227 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
 228 #define REG_SERIALIZER            REG(0x02, 0x03)     /* read/write */
 229 #define REG_BUFFER_OUT            REG(0x02, 0x04)     /* read/write */
 230 #define REG_PLL_SCG1              REG(0x02, 0x05)     /* read/write */
 231 #define REG_PLL_SCG2              REG(0x02, 0x06)     /* read/write */
 232 #define REG_PLL_SCGN1             REG(0x02, 0x07)     /* read/write */
 233 #define REG_PLL_SCGN2             REG(0x02, 0x08)     /* read/write */
 234 #define REG_PLL_SCGR1             REG(0x02, 0x09)     /* read/write */
 235 #define REG_PLL_SCGR2             REG(0x02, 0x0a)     /* read/write */
 236 #define REG_AUDIO_DIV             REG(0x02, 0x0e)     /* read/write */
 237 # define AUDIO_DIV_SERCLK_1       0
 238 # define AUDIO_DIV_SERCLK_2       1
 239 # define AUDIO_DIV_SERCLK_4       2
 240 # define AUDIO_DIV_SERCLK_8       3
 241 # define AUDIO_DIV_SERCLK_16      4
 242 # define AUDIO_DIV_SERCLK_32      5
 243 #define REG_SEL_CLK               REG(0x02, 0x11)     /* read/write */
 244 # define SEL_CLK_SEL_CLK1         (1 << 0)
 245 # define SEL_CLK_SEL_VRF_CLK(x)   (((x) & 3) << 1)
 246 # define SEL_CLK_ENA_SC_CLK       (1 << 3)
 247 #define REG_ANA_GENERAL           REG(0x02, 0x12)     /* read/write */
 248
 249
 250 /* Page 09h: EDID Control */
 251 #define REG_EDID_DATA_0           REG(0x09, 0x00)     /* read */
 252 /* next 127 successive registers are the EDID block */
 253 #define REG_EDID_CTRL             REG(0x09, 0xfa)     /* read/write */
 254 #define REG_DDC_ADDR              REG(0x09, 0xfb)     /* read/write */
 255 #define REG_DDC_OFFS              REG(0x09, 0xfc)     /* read/write */
 256 #define REG_DDC_SEGM_ADDR         REG(0x09, 0xfd)     /* read/write */
 257 #define REG_DDC_SEGM              REG(0x09, 0xfe)     /* read/write */
 258
 259
 260 /* Page 10h: information frames and packets */
 261 #define REG_IF1_HB0               REG(0x10, 0x20)     /* read/write */
 262 #define REG_IF2_HB0               REG(0x10, 0x40)     /* read/write */
 263 #define REG_IF3_HB0               REG(0x10, 0x60)     /* read/write */
 264 #define REG_IF4_HB0               REG(0x10, 0x80)     /* read/write */
 265 #define REG_IF5_HB0               REG(0x10, 0xa0)     /* read/write */
 266
 267
 268 /* Page 11h: audio settings and content info packets */
 269 #define REG_AIP_CNTRL_0           REG(0x11, 0x00)     /* read/write */
 270 # define AIP_CNTRL_0_RST_FIFO     (1 << 0)
 271 # define AIP_CNTRL_0_SWAP         (1 << 1)
 272 # define AIP_CNTRL_0_LAYOUT       (1 << 2)
 273 # define AIP_CNTRL_0_ACR_MAN      (1 << 5)
 274 # define AIP_CNTRL_0_RST_CTS      (1 << 6)
 275 #define REG_CA_I2S                REG(0x11, 0x01)     /* read/write */
 276 # define CA_I2S_CA_I2S(x)         (((x) & 31) << 0)
 277 # define CA_I2S_HBR_CHSTAT        (1 << 6)
 278 #define REG_LATENCY_RD            REG(0x11, 0x04)     /* read/write */
 279 #define REG_ACR_CTS_0             REG(0x11, 0x05)     /* read/write */
 280 #define REG_ACR_CTS_1             REG(0x11, 0x06)     /* read/write */
 281 #define REG_ACR_CTS_2             REG(0x11, 0x07)     /* read/write */
 282 #define REG_ACR_N_0               REG(0x11, 0x08)     /* read/write */
 283 #define REG_ACR_N_1               REG(0x11, 0x09)     /* read/write */
 284 #define REG_ACR_N_2               REG(0x11, 0x0a)     /* read/write */
 285 #define REG_CTS_N                 REG(0x11, 0x0c)     /* read/write */
 286 # define CTS_N_K(x)               (((x) & 7) << 0)
 287 # define CTS_N_M(x)               (((x) & 3) << 4)
 288 #define REG_ENC_CNTRL             REG(0x11, 0x0d)     /* read/write */
 289 # define ENC_CNTRL_RST_ENC        (1 << 0)
 290 # define ENC_CNTRL_RST_SEL        (1 << 1)
 291 # define ENC_CNTRL_CTL_CODE(x)    (((x) & 3) << 2)
 292 #define REG_DIP_FLAGS             REG(0x11, 0x0e)     /* read/write */
 293 # define DIP_FLAGS_ACR            (1 << 0)
 294 # define DIP_FLAGS_GC             (1 << 1)
 295 #define REG_DIP_IF_FLAGS          REG(0x11, 0x0f)     /* read/write */
 296 # define DIP_IF_FLAGS_IF1         (1 << 1)
 297 # define DIP_IF_FLAGS_IF2         (1 << 2)
 298 # define DIP_IF_FLAGS_IF3         (1 << 3)
 299 # define DIP_IF_FLAGS_IF4         (1 << 4)
 300 # define DIP_IF_FLAGS_IF5         (1 << 5)
 301 #define REG_CH_STAT_B(x)          REG(0x11, 0x14 + (x)) /* read/write */
 302
 303
 304 /* Page 12h: HDCP and OTP */
 305 #define REG_TX3                   REG(0x12, 0x9a)     /* read/write */
 306 #define REG_TX4                   REG(0x12, 0x9b)     /* read/write */
 307 # define TX4_PD_RAM               (1 << 1)
 308 #define REG_TX33                  REG(0x12, 0xb8)     /* read/write */
 309 # define TX33_HDMI                (1 << 1)
 310
 311
 312 /* Page 13h: Gamut related metadata packets */
 313
 314
 315
 316 /* CEC registers: (not paged)
 317  */
 318 #define REG_CEC_INTSTATUS         0xee                /* read */
 319 # define CEC_INTSTATUS_CEC        (1 << 0)
 320 # define CEC_INTSTATUS_HDMI       (1 << 1)
 321 #define REG_CEC_FRO_IM_CLK_CTRL   0xfb                /* read/write */
 322 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
 323 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP   (1 << 6)
 324 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
 325 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV   (1 << 0)
 326 #define REG_CEC_RXSHPDINTENA      0xfc                /* read/write */
 327 #define REG_CEC_RXSHPDINT         0xfd                /* read */
 328 #define REG_CEC_RXSHPDLEV         0xfe                /* read */
 329 # define CEC_RXSHPDLEV_RXSENS     (1 << 0)
 330 # define CEC_RXSHPDLEV_HPD        (1 << 1)
 331
 332 #define REG_CEC_ENAMODS           0xff                /* read/write */
 333 # define CEC_ENAMODS_DIS_FRO      (1 << 6)
 334 # define CEC_ENAMODS_DIS_CCLK     (1 << 5)
 335 # define CEC_ENAMODS_EN_RXSENS    (1 << 2)
 336 # define CEC_ENAMODS_EN_HDMI      (1 << 1)
 337 # define CEC_ENAMODS_EN_CEC       (1 << 0)
 338
 339
 340 /* Device versions: */
 341 #define TDA9989N2                 0x0101
 342 #define TDA19989                  0x0201
 343 #define TDA19989N2                0x0202
 344 #define TDA19988                  0x0301
 345
 346 static void
 347 cec_write(struct tda998x_priv *priv, uint16_t addr, uint8_t val)
 348 {
 349         struct i2c_client *client = priv->cec;
 350         uint8_t buf[] = {addr, val};
 351         int ret;
 352
 353         ret = i2c_master_send(client, buf, sizeof(buf));
 354         if (ret < 0)
 355                 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
 356 }
 357
 358 static uint8_t
 359 cec_read(struct tda998x_priv *priv, uint8_t addr)
 360 {
 361         struct i2c_client *client = priv->cec;
 362         uint8_t val;
 363         int ret;
 364
 365         ret = i2c_master_send(client, &addr, sizeof(addr));
 366         if (ret < 0)
 367                 goto fail;
 368
 369         ret = i2c_master_recv(client, &val, sizeof(val));
 370         if (ret < 0)
 371                 goto fail;
 372
 373         return val;
 374
 375 fail:
 376         dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
 377         return 0;
 378 }
 379
 380 static int
 381 set_page(struct tda998x_priv *priv, uint16_t reg)
 382 {
 383         if (REG2PAGE(reg) != priv->current_page) {
 384                 struct i2c_client *client = priv->hdmi;
 385                 uint8_t buf[] = {
 386                                 REG_CURPAGE, REG2PAGE(reg)
 387                 };
 388                 int ret = i2c_master_send(client, buf, sizeof(buf));
 389                 if (ret < 0) {
 390                         dev_err(&client->dev, "setpage %04x err %d\n",
 391                                         reg, ret);
 392                         return ret;
 393                 }
 394
 395                 priv->current_page = REG2PAGE(reg);
 396         }
 397         return 0;
 398 }
 399
 400 static int
 401 reg_read_range(struct tda998x_priv *priv, uint16_t reg, char *buf, int cnt)
 402 {
 403         struct i2c_client *client = priv->hdmi;
 404         uint8_t addr = REG2ADDR(reg);
 405         int ret;
 406
 407         mutex_lock(&priv->mutex);
 408         ret = set_page(priv, reg);
 409         if (ret < 0)
 410                 goto out;
 411
 412         ret = i2c_master_send(client, &addr, sizeof(addr));
 413         if (ret < 0)
 414                 goto fail;
 415
 416         ret = i2c_master_recv(client, buf, cnt);
 417         if (ret < 0)
 418                 goto fail;
 419
 420         goto out;
 421
 422 fail:
 423         dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
 424 out:
 425         mutex_unlock(&priv->mutex);
 426         return ret;
 427 }
 428
 429 static void
 430 reg_write_range(struct tda998x_priv *priv, uint16_t reg, uint8_t *p, int cnt)
 431 {
 432         struct i2c_client *client = priv->hdmi;
 433         uint8_t buf[cnt+1];
 434         int ret;
 435
 436         buf[0] = REG2ADDR(reg);
 437         memcpy(&buf[1], p, cnt);
 438
 439         mutex_lock(&priv->mutex);
 440         ret = set_page(priv, reg);
 441         if (ret < 0)
 442                 goto out;
 443
 444         ret = i2c_master_send(client, buf, cnt + 1);
 445         if (ret < 0)
 446                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 447 out:
 448         mutex_unlock(&priv->mutex);
 449 }
 450
 451 static int
 452 reg_read(struct tda998x_priv *priv, uint16_t reg)
 453 {
 454         uint8_t val = 0;
 455         int ret;
 456
 457         ret = reg_read_range(priv, reg, &val, sizeof(val));
 458         if (ret < 0)
 459                 return ret;
 460         return val;
 461 }
 462
 463 static void
 464 reg_write(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
 465 {
 466         struct i2c_client *client = priv->hdmi;
 467         uint8_t buf[] = {REG2ADDR(reg), val};
 468         int ret;
 469
 470         mutex_lock(&priv->mutex);
 471         ret = set_page(priv, reg);
 472         if (ret < 0)
 473                 goto out;
 474
 475         ret = i2c_master_send(client, buf, sizeof(buf));
 476         if (ret < 0)
 477                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 478 out:
 479         mutex_unlock(&priv->mutex);
 480 }
 481
 482 static void
 483 reg_write16(struct tda998x_priv *priv, uint16_t reg, uint16_t val)
 484 {
 485         struct i2c_client *client = priv->hdmi;
 486         uint8_t buf[] = {REG2ADDR(reg), val >> 8, val};
 487         int ret;
 488
 489         mutex_lock(&priv->mutex);
 490         ret = set_page(priv, reg);
 491         if (ret < 0)
 492                 goto out;
 493
 494         ret = i2c_master_send(client, buf, sizeof(buf));
 495         if (ret < 0)
 496                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 497 out:
 498         mutex_unlock(&priv->mutex);
 499 }
 500
 501 static void
 502 reg_set(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
 503 {
 504         int old_val;
 505
 506         old_val = reg_read(priv, reg);
 507         if (old_val >= 0)
 508                 reg_write(priv, reg, old_val | val);
 509 }
 510
 511 static void
 512 reg_clear(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
 513 {
 514         int old_val;
 515
 516         old_val = reg_read(priv, reg);
 517         if (old_val >= 0)
 518                 reg_write(priv, reg, old_val & ~val);
 519 }
 520
 521 static void
 522 tda998x_reset(struct tda998x_priv *priv)
 523 {
 524         /* reset audio and i2c master: */
 525         reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
 526         msleep(50);
 527         reg_write(priv, REG_SOFTRESET, 0);
 528         msleep(50);
 529
 530         /* reset transmitter: */
 531         reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 532         reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 533
 534         /* PLL registers common configuration */
 535         reg_write(priv, REG_PLL_SERIAL_1, 0x00);
 536         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
 537         reg_write(priv, REG_PLL_SERIAL_3, 0x00);
 538         reg_write(priv, REG_SERIALIZER,   0x00);
 539         reg_write(priv, REG_BUFFER_OUT,   0x00);
 540         reg_write(priv, REG_PLL_SCG1,     0x00);
 541         reg_write(priv, REG_AUDIO_DIV,    AUDIO_DIV_SERCLK_8);
 542         reg_write(priv, REG_SEL_CLK,      SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
 543         reg_write(priv, REG_PLL_SCGN1,    0xfa);
 544         reg_write(priv, REG_PLL_SCGN2,    0x00);
 545         reg_write(priv, REG_PLL_SCGR1,    0x5b);
 546         reg_write(priv, REG_PLL_SCGR2,    0x00);
 547         reg_write(priv, REG_PLL_SCG2,     0x10);
 548
 549         /* Write the default value MUX register */
 550         reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
 551 }
 552
 553 /* handle HDMI connect/disconnect */
 554 static void tda998x_hpd(struct work_struct *work)
 555 {
 556         struct delayed_work *dwork = to_delayed_work(work);
 557         struct tda998x_priv *priv =
 558                         container_of(dwork, struct tda998x_priv, dwork);
 559
 560         if (priv->encoder && priv->encoder->dev)
 561                 drm_kms_helper_hotplug_event(priv->encoder->dev);
 562 }
 563
 564 /*
 565  * only 2 interrupts may occur: screen plug/unplug and EDID read
 566  */
 567 static irqreturn_t tda998x_irq_thread(int irq, void *data)
 568 {
 569         struct tda998x_priv *priv = data;
 570         u8 sta, cec, lvl, flag0, flag1, flag2;
 571
 572         if (!priv)
 573                 return IRQ_HANDLED;
 574         sta = cec_read(priv, REG_CEC_INTSTATUS);
 575         cec = cec_read(priv, REG_CEC_RXSHPDINT);
 576         lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
 577         flag0 = reg_read(priv, REG_INT_FLAGS_0);
 578         flag1 = reg_read(priv, REG_INT_FLAGS_1);
 579         flag2 = reg_read(priv, REG_INT_FLAGS_2);
 580         DRM_DEBUG_DRIVER(
 581                 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
 582                 sta, cec, lvl, flag0, flag1, flag2);
 583         if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
 584                 priv->wq_edid_wait = 0;
 585                 wake_up(&priv->wq_edid);
 586         } else if (cec != 0) {                  /* HPD change */
 587                 schedule_delayed_work(&priv->dwork, HZ/10);
 588         }
 589         return IRQ_HANDLED;
 590 }
 591
 592 static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes)
 593 {
 594         int sum = 0;
 595
 596         while (bytes--)
 597                 sum -= *buf++;
 598         return sum;
 599 }
 600
 601 #define HB(x) (x)
 602 #define PB(x) (HB(2) + 1 + (x))
 603
 604 static void
 605 tda998x_write_if(struct tda998x_priv *priv, uint8_t bit, uint16_t addr,
 606                  uint8_t *buf, size_t size)
 607 {
 608         buf[PB(0)] = tda998x_cksum(buf, size);
 609
 610         reg_clear(priv, REG_DIP_IF_FLAGS, bit);
 611         reg_write_range(priv, addr, buf, size);
 612         reg_set(priv, REG_DIP_IF_FLAGS, bit);
 613 }
 614
 615 static void
 616 tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p)
 617 {
 618         u8 buf[PB(HDMI_AUDIO_INFOFRAME_SIZE) + 1];
 619
 620         memset(buf, 0, sizeof(buf));
 621         buf[HB(0)] = HDMI_INFOFRAME_TYPE_AUDIO;
 622         buf[HB(1)] = 0x01;
 623         buf[HB(2)] = HDMI_AUDIO_INFOFRAME_SIZE;
 624         buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */
 625         buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */
 626         buf[PB(4)] = p->audio_frame[4];
 627         buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */
 628
 629         tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf,
 630                          sizeof(buf));
 631 }
 632
 633 static void
 634 tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
 635 {
 636         u8 buf[PB(HDMI_AVI_INFOFRAME_SIZE) + 1];
 637
 638         memset(buf, 0, sizeof(buf));
 639         buf[HB(0)] = HDMI_INFOFRAME_TYPE_AVI;
 640         buf[HB(1)] = 0x02;
 641         buf[HB(2)] = HDMI_AVI_INFOFRAME_SIZE;
 642         buf[PB(1)] = HDMI_SCAN_MODE_UNDERSCAN;
 643         buf[PB(2)] = HDMI_ACTIVE_ASPECT_PICTURE;
 644         buf[PB(3)] = HDMI_QUANTIZATION_RANGE_FULL << 2;
 645         buf[PB(4)] = drm_match_cea_mode(mode);
 646
 647         tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf,
 648                          sizeof(buf));
 649 }
 650
 651 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
 652 {
 653         if (on) {
 654                 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 655                 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 656                 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 657         } else {
 658                 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 659         }
 660 }
 661
 662 static void
 663 tda998x_configure_audio(struct tda998x_priv *priv,
 664                 struct drm_display_mode *mode, struct tda998x_encoder_params *p)
 665 {
 666         uint8_t buf[6], clksel_aip, clksel_fs, cts_n, adiv;
 667         uint32_t n;
 668
 669         /* Enable audio ports */
 670         reg_write(priv, REG_ENA_AP, p->audio_cfg);
 671         reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg);
 672
 673         /* Set audio input source */
 674         switch (p->audio_format) {
 675         case AFMT_SPDIF:
 676                 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
 677                 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
 678                 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
 679                 cts_n = CTS_N_M(3) | CTS_N_K(3);
 680                 break;
 681
 682         case AFMT_I2S:
 683                 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
 684                 clksel_aip = AIP_CLKSEL_AIP_I2S;
 685                 clksel_fs = AIP_CLKSEL_FS_ACLK;
 686                 cts_n = CTS_N_M(3) | CTS_N_K(3);
 687                 break;
 688
 689         default:
 690                 BUG();
 691                 return;
 692         }
 693
 694         reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
 695         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
 696                                         AIP_CNTRL_0_ACR_MAN);   /* auto CTS */
 697         reg_write(priv, REG_CTS_N, cts_n);
 698
 699         /*
 700          * Audio input somehow depends on HDMI line rate which is
 701          * related to pixclk. Testing showed that modes with pixclk
 702          * >100MHz need a larger divider while <40MHz need the default.
 703          * There is no detailed info in the datasheet, so we just
 704          * assume 100MHz requires larger divider.
 705          */
 706         adiv = AUDIO_DIV_SERCLK_8;
 707         if (mode->clock > 100000)
 708                 adiv++;                 /* AUDIO_DIV_SERCLK_16 */
 709
 710         /* S/PDIF asks for a larger divider */
 711         if (p->audio_format == AFMT_SPDIF)
 712                 adiv++;                 /* AUDIO_DIV_SERCLK_16 or _32 */
 713
 714         reg_write(priv, REG_AUDIO_DIV, adiv);
 715
 716         /*
 717          * This is the approximate value of N, which happens to be
 718          * the recommended values for non-coherent clocks.
 719          */
 720         n = 128 * p->audio_sample_rate / 1000;
 721
 722         /* Write the CTS and N values */
 723         buf[0] = 0x44;
 724         buf[1] = 0x42;
 725         buf[2] = 0x01;
 726         buf[3] = n;
 727         buf[4] = n >> 8;
 728         buf[5] = n >> 16;
 729         reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
 730
 731         /* Set CTS clock reference */
 732         reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
 733
 734         /* Reset CTS generator */
 735         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
 736         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
 737
 738         /* Write the channel status */
 739         buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
 740         buf[1] = 0x00;
 741         buf[2] = IEC958_AES3_CON_FS_NOTID;
 742         buf[3] = IEC958_AES4_CON_ORIGFS_NOTID |
 743                         IEC958_AES4_CON_MAX_WORDLEN_24;
 744         reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
 745
 746         tda998x_audio_mute(priv, true);
 747         msleep(20);
 748         tda998x_audio_mute(priv, false);
 749
 750         /* Write the audio information packet */
 751         tda998x_write_aif(priv, p);
 752 }
 753
 754 /* DRM encoder functions */
 755
 756 static void tda998x_encoder_set_config(struct tda998x_priv *priv,
 757                                        const struct tda998x_encoder_params *p)
 758 {
 759         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
 760                             (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
 761                             VIP_CNTRL_0_SWAP_B(p->swap_b) |
 762                             (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
 763         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
 764                             (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
 765                             VIP_CNTRL_1_SWAP_D(p->swap_d) |
 766                             (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
 767         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
 768                             (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
 769                             VIP_CNTRL_2_SWAP_F(p->swap_f) |
 770                             (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
 771
 772         priv->params = *p;
 773 }
 774
 775 static void tda998x_encoder_dpms(struct tda998x_priv *priv, int mode)
 776 {
 777         /* we only care about on or off: */
 778         if (mode != DRM_MODE_DPMS_ON)
 779                 mode = DRM_MODE_DPMS_OFF;
 780
 781         if (mode == priv->dpms)
 782                 return;
 783
 784         switch (mode) {
 785         case DRM_MODE_DPMS_ON:
 786                 /* enable video ports, audio will be enabled later */
 787                 reg_write(priv, REG_ENA_VP_0, 0xff);
 788                 reg_write(priv, REG_ENA_VP_1, 0xff);
 789                 reg_write(priv, REG_ENA_VP_2, 0xff);
 790                 /* set muxing after enabling ports: */
 791                 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
 792                 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
 793                 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
 794                 break;
 795         case DRM_MODE_DPMS_OFF:
 796                 /* disable video ports */
 797                 reg_write(priv, REG_ENA_VP_0, 0x00);
 798                 reg_write(priv, REG_ENA_VP_1, 0x00);
 799                 reg_write(priv, REG_ENA_VP_2, 0x00);
 800                 break;
 801         }
 802
 803         priv->dpms = mode;
 804 }
 805
 806 static void
 807 tda998x_encoder_save(struct drm_encoder *encoder)
 808 {
 809         DBG("");
 810 }
 811
 812 static void
 813 tda998x_encoder_restore(struct drm_encoder *encoder)
 814 {
 815         DBG("");
 816 }
 817
 818 static bool
 819 tda998x_encoder_mode_fixup(struct drm_encoder *encoder,
 820                           const struct drm_display_mode *mode,
 821                           struct drm_display_mode *adjusted_mode)
 822 {
 823         return true;
 824 }
 825
 826 static int tda998x_encoder_mode_valid(struct tda998x_priv *priv,
 827                                       struct drm_display_mode *mode)
 828 {
 829         if (mode->clock > 150000)
 830                 return MODE_CLOCK_HIGH;
 831         if (mode->htotal >= BIT(13))
 832                 return MODE_BAD_HVALUE;
 833         if (mode->vtotal >= BIT(11))
 834                 return MODE_BAD_VVALUE;
 835         return MODE_OK;
 836 }
 837
 838 static void
 839 tda998x_encoder_mode_set(struct tda998x_priv *priv,
 840                          struct drm_display_mode *mode,
 841                          struct drm_display_mode *adjusted_mode)
 842 {
 843         uint16_t ref_pix, ref_line, n_pix, n_line;
 844         uint16_t hs_pix_s, hs_pix_e;
 845         uint16_t vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
 846         uint16_t vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
 847         uint16_t vwin1_line_s, vwin1_line_e;
 848         uint16_t vwin2_line_s, vwin2_line_e;
 849         uint16_t de_pix_s, de_pix_e;
 850         uint8_t reg, div, rep;
 851
 852         /*
 853          * Internally TDA998x is using ITU-R BT.656 style sync but
 854          * we get VESA style sync. TDA998x is using a reference pixel
 855          * relative to ITU to sync to the input frame and for output
 856          * sync generation. Currently, we are using reference detection
 857          * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
 858          * which is position of rising VS with coincident rising HS.
 859          *
 860          * Now there is some issues to take care of:
 861          * - HDMI data islands require sync-before-active
 862          * - TDA998x register values must be > 0 to be enabled
 863          * - REFLINE needs an additional offset of +1
 864          * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
 865          *
 866          * So we add +1 to all horizontal and vertical register values,
 867          * plus an additional +3 for REFPIX as we are using RGB input only.
 868          */
 869         n_pix        = mode->htotal;
 870         n_line       = mode->vtotal;
 871
 872         hs_pix_e     = mode->hsync_end - mode->hdisplay;
 873         hs_pix_s     = mode->hsync_start - mode->hdisplay;
 874         de_pix_e     = mode->htotal;
 875         de_pix_s     = mode->htotal - mode->hdisplay;
 876         ref_pix      = 3 + hs_pix_s;
 877
 878         /*
 879          * Attached LCD controllers may generate broken sync. Allow
 880          * those to adjust the position of the rising VS edge by adding
 881          * HSKEW to ref_pix.
 882          */
 883         if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
 884                 ref_pix += adjusted_mode->hskew;
 885
 886         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
 887                 ref_line     = 1 + mode->vsync_start - mode->vdisplay;
 888                 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
 889                 vwin1_line_e = vwin1_line_s + mode->vdisplay;
 890                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
 891                 vs1_line_s   = mode->vsync_start - mode->vdisplay;
 892                 vs1_line_e   = vs1_line_s +
 893                                mode->vsync_end - mode->vsync_start;
 894                 vwin2_line_s = vwin2_line_e = 0;
 895                 vs2_pix_s    = vs2_pix_e  = 0;
 896                 vs2_line_s   = vs2_line_e = 0;
 897         } else {
 898                 ref_line     = 1 + (mode->vsync_start - mode->vdisplay)/2;
 899                 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
 900                 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
 901                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
 902                 vs1_line_s   = (mode->vsync_start - mode->vdisplay)/2;
 903                 vs1_line_e   = vs1_line_s +
 904                                (mode->vsync_end - mode->vsync_start)/2;
 905                 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
 906                 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
 907                 vs2_pix_s    = vs2_pix_e = hs_pix_s + mode->htotal/2;
 908                 vs2_line_s   = vs1_line_s + mode->vtotal/2 ;
 909                 vs2_line_e   = vs2_line_s +
 910                                (mode->vsync_end - mode->vsync_start)/2;
 911         }
 912
 913         div = 148500 / mode->clock;
 914         if (div != 0) {
 915                 div--;
 916                 if (div > 3)
 917                         div = 3;
 918         }
 919
 920         /* mute the audio FIFO: */
 921         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 922
 923         /* set HDMI HDCP mode off: */
 924         reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
 925         reg_clear(priv, REG_TX33, TX33_HDMI);
 926         reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
 927
 928         /* no pre-filter or interpolator: */
 929         reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
 930                         HVF_CNTRL_0_INTPOL(0));
 931         reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
 932         reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
 933                         VIP_CNTRL_4_BLC(0));
 934
 935         reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
 936         reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
 937                                           PLL_SERIAL_3_SRL_DE);
 938         reg_write(priv, REG_SERIALIZER, 0);
 939         reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
 940
 941         /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
 942         rep = 0;
 943         reg_write(priv, REG_RPT_CNTRL, 0);
 944         reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
 945                         SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
 946
 947         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
 948                         PLL_SERIAL_2_SRL_PR(rep));
 949
 950         /* set color matrix bypass flag: */
 951         reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
 952                                 MAT_CONTRL_MAT_SC(1));
 953
 954         /* set BIAS tmds value: */
 955         reg_write(priv, REG_ANA_GENERAL, 0x09);
 956
 957         /*
 958          * Sync on rising HSYNC/VSYNC
 959          */
 960         reg = VIP_CNTRL_3_SYNC_HS;
 961
 962         /*
 963          * TDA19988 requires high-active sync at input stage,
 964          * so invert low-active sync provided by master encoder here
 965          */
 966         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 967                 reg |= VIP_CNTRL_3_H_TGL;
 968         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 969                 reg |= VIP_CNTRL_3_V_TGL;
 970         reg_write(priv, REG_VIP_CNTRL_3, reg);
 971
 972         reg_write(priv, REG_VIDFORMAT, 0x00);
 973         reg_write16(priv, REG_REFPIX_MSB, ref_pix);
 974         reg_write16(priv, REG_REFLINE_MSB, ref_line);
 975         reg_write16(priv, REG_NPIX_MSB, n_pix);
 976         reg_write16(priv, REG_NLINE_MSB, n_line);
 977         reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
 978         reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
 979         reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
 980         reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
 981         reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
 982         reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
 983         reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
 984         reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
 985         reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
 986         reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
 987         reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
 988         reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
 989         reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
 990         reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
 991         reg_write16(priv, REG_DE_START_MSB, de_pix_s);
 992         reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
 993
 994         if (priv->rev == TDA19988) {
 995                 /* let incoming pixels fill the active space (if any) */
 996                 reg_write(priv, REG_ENABLE_SPACE, 0x00);
 997         }
 998
 999         /*
1000          * Always generate sync polarity relative to input sync and
1001          * revert input stage toggled sync at output stage
1002          */
1003         reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1004         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1005                 reg |= TBG_CNTRL_1_H_TGL;
1006         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1007                 reg |= TBG_CNTRL_1_V_TGL;
1008         reg_write(priv, REG_TBG_CNTRL_1, reg);
1009
1010         /* must be last register set: */
1011         reg_write(priv, REG_TBG_CNTRL_0, 0);
1012
1013         /* Only setup the info frames if the sink is HDMI */
1014         if (priv->is_hdmi_sink) {
1015                 /* We need to turn HDMI HDCP stuff on to get audio through */
1016                 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1017                 reg_write(priv, REG_TBG_CNTRL_1, reg);
1018                 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1019                 reg_set(priv, REG_TX33, TX33_HDMI);
1020
1021                 tda998x_write_avi(priv, adjusted_mode);
1022
1023                 if (priv->params.audio_cfg)
1024                         tda998x_configure_audio(priv, adjusted_mode,
1025                                                 &priv->params);
1026         }
1027 }
1028
1029 static enum drm_connector_status
1030 tda998x_encoder_detect(struct tda998x_priv *priv)
1031 {
1032         uint8_t val = cec_read(priv, REG_CEC_RXSHPDLEV);
1033
1034         return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1035                         connector_status_disconnected;
1036 }
1037
1038 static int read_edid_block(struct tda998x_priv *priv, uint8_t *buf, int blk)
1039 {
1040         uint8_t offset, segptr;
1041         int ret, i;
1042
1043         offset = (blk & 1) ? 128 : 0;
1044         segptr = blk / 2;
1045
1046         reg_write(priv, REG_DDC_ADDR, 0xa0);
1047         reg_write(priv, REG_DDC_OFFS, offset);
1048         reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1049         reg_write(priv, REG_DDC_SEGM, segptr);
1050
1051         /* enable reading EDID: */
1052         priv->wq_edid_wait = 1;
1053         reg_write(priv, REG_EDID_CTRL, 0x1);
1054
1055         /* flag must be cleared by sw: */
1056         reg_write(priv, REG_EDID_CTRL, 0x0);
1057
1058         /* wait for block read to complete: */
1059         if (priv->hdmi->irq) {
1060                 i = wait_event_timeout(priv->wq_edid,
1061                                         !priv->wq_edid_wait,
1062                                         msecs_to_jiffies(100));
1063                 if (i < 0) {
1064                         dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1065                         return i;
1066                 }
1067         } else {
1068                 for (i = 100; i > 0; i--) {
1069                         msleep(1);
1070                         ret = reg_read(priv, REG_INT_FLAGS_2);
1071                         if (ret < 0)
1072                                 return ret;
1073                         if (ret & INT_FLAGS_2_EDID_BLK_RD)
1074                                 break;
1075                 }
1076         }
1077
1078         if (i == 0) {
1079                 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1080                 return -ETIMEDOUT;
1081         }
1082
1083         ret = reg_read_range(priv, REG_EDID_DATA_0, buf, EDID_LENGTH);
1084         if (ret != EDID_LENGTH) {
1085                 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1086                         blk, ret);
1087                 return ret;
1088         }
1089
1090         return 0;
1091 }
1092
1093 static uint8_t *do_get_edid(struct tda998x_priv *priv)
1094 {
1095         int j, valid_extensions = 0;
1096         uint8_t *block, *new;
1097         bool print_bad_edid = drm_debug & DRM_UT_KMS;
1098
1099         if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1100                 return NULL;
1101
1102         if (priv->rev == TDA19988)
1103                 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1104
1105         /* base block fetch */
1106         if (read_edid_block(priv, block, 0))
1107                 goto fail;
1108
1109         if (!drm_edid_block_valid(block, 0, print_bad_edid))
1110                 goto fail;
1111
1112         /* if there's no extensions, we're done */
1113         if (block[0x7e] == 0)
1114                 goto done;
1115
1116         new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
1117         if (!new)
1118                 goto fail;
1119         block = new;
1120
1121         for (j = 1; j <= block[0x7e]; j++) {
1122                 uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH;
1123                 if (read_edid_block(priv, ext_block, j))
1124                         goto fail;
1125
1126                 if (!drm_edid_block_valid(ext_block, j, print_bad_edid))
1127                         goto fail;
1128
1129                 valid_extensions++;
1130         }
1131
1132         if (valid_extensions != block[0x7e]) {
1133                 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
1134                 block[0x7e] = valid_extensions;
1135                 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1136                 if (!new)
1137                         goto fail;
1138                 block = new;
1139         }
1140
1141 done:
1142         if (priv->rev == TDA19988)
1143                 reg_set(priv, REG_TX4, TX4_PD_RAM);
1144
1145         return block;
1146
1147 fail:
1148         if (priv->rev == TDA19988)
1149                 reg_set(priv, REG_TX4, TX4_PD_RAM);
1150         dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1151         kfree(block);
1152         return NULL;
1153 }
1154
1155 static int
1156 tda998x_encoder_get_modes(struct tda998x_priv *priv,
1157                           struct drm_connector *connector)
1158 {
1159         struct edid *edid = (struct edid *)do_get_edid(priv);
1160         int n = 0;
1161
1162         if (edid) {
1163                 drm_mode_connector_update_edid_property(connector, edid);
1164                 n = drm_add_edid_modes(connector, edid);
1165                 priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
1166                 kfree(edid);
1167         }
1168
1169         return n;
1170 }
1171
1172 static void tda998x_encoder_set_polling(struct tda998x_priv *priv,
1173                                         struct drm_connector *connector)
1174 {
1175         if (priv->hdmi->irq)
1176                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1177         else
1178                 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1179                         DRM_CONNECTOR_POLL_DISCONNECT;
1180 }
1181
1182 static int
1183 tda998x_encoder_set_property(struct drm_encoder *encoder,
1184                             struct drm_connector *connector,
1185                             struct drm_property *property,
1186                             uint64_t val)
1187 {
1188         DBG("");
1189         return 0;
1190 }
1191
1192 static void tda998x_destroy(struct tda998x_priv *priv)
1193 {
1194         /* disable all IRQs and free the IRQ handler */
1195         cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1196         reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1197         if (priv->hdmi->irq) {
1198                 free_irq(priv->hdmi->irq, priv);
1199                 cancel_delayed_work_sync(&priv->dwork);
1200         }
1201
1202         i2c_unregister_device(priv->cec);
1203 }
1204
1205 /* Slave encoder support */
1206
1207 static void
1208 tda998x_encoder_slave_set_config(struct drm_encoder *encoder, void *params)
1209 {
1210         tda998x_encoder_set_config(to_tda998x_priv(encoder), params);
1211 }
1212
1213 static void tda998x_encoder_slave_destroy(struct drm_encoder *encoder)
1214 {
1215         struct tda998x_priv *priv = to_tda998x_priv(encoder);
1216
1217         tda998x_destroy(priv);
1218         drm_i2c_encoder_destroy(encoder);
1219         kfree(priv);
1220 }
1221
1222 static void tda998x_encoder_slave_dpms(struct drm_encoder *encoder, int mode)
1223 {
1224         tda998x_encoder_dpms(to_tda998x_priv(encoder), mode);
1225 }
1226
1227 static int tda998x_encoder_slave_mode_valid(struct drm_encoder *encoder,
1228                                             struct drm_display_mode *mode)
1229 {
1230         return tda998x_encoder_mode_valid(to_tda998x_priv(encoder), mode);
1231 }
1232
1233 static void
1234 tda998x_encoder_slave_mode_set(struct drm_encoder *encoder,
1235                                struct drm_display_mode *mode,
1236                                struct drm_display_mode *adjusted_mode)
1237 {
1238         tda998x_encoder_mode_set(to_tda998x_priv(encoder), mode, adjusted_mode);
1239 }
1240
1241 static enum drm_connector_status
1242 tda998x_encoder_slave_detect(struct drm_encoder *encoder,
1243                              struct drm_connector *connector)
1244 {
1245         return tda998x_encoder_detect(to_tda998x_priv(encoder));
1246 }
1247
1248 static int tda998x_encoder_slave_get_modes(struct drm_encoder *encoder,
1249                                            struct drm_connector *connector)
1250 {
1251         return tda998x_encoder_get_modes(to_tda998x_priv(encoder), connector);
1252 }
1253
1254 static int
1255 tda998x_encoder_slave_create_resources(struct drm_encoder *encoder,
1256                                        struct drm_connector *connector)
1257 {
1258         tda998x_encoder_set_polling(to_tda998x_priv(encoder), connector);
1259         return 0;
1260 }
1261
1262 static struct drm_encoder_slave_funcs tda998x_encoder_slave_funcs = {
1263         .set_config = tda998x_encoder_slave_set_config,
1264         .destroy = tda998x_encoder_slave_destroy,
1265         .dpms = tda998x_encoder_slave_dpms,
1266         .save = tda998x_encoder_save,
1267         .restore = tda998x_encoder_restore,
1268         .mode_fixup = tda998x_encoder_mode_fixup,
1269         .mode_valid = tda998x_encoder_slave_mode_valid,
1270         .mode_set = tda998x_encoder_slave_mode_set,
1271         .detect = tda998x_encoder_slave_detect,
1272         .get_modes = tda998x_encoder_slave_get_modes,
1273         .create_resources = tda998x_encoder_slave_create_resources,
1274         .set_property = tda998x_encoder_set_property,
1275 };
1276
1277 /* I2C driver functions */
1278
1279 static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
1280 {
1281         struct device_node *np = client->dev.of_node;
1282         u32 video;
1283         int rev_lo, rev_hi, ret;
1284         unsigned short cec_addr;
1285
1286         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1287         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1288         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1289
1290         priv->current_page = 0xff;
1291         priv->hdmi = client;
1292         /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1293         cec_addr = 0x34 + (client->addr & 0x03);
1294         priv->cec = i2c_new_dummy(client->adapter, cec_addr);
1295         if (!priv->cec)
1296                 return -ENODEV;
1297
1298         priv->dpms = DRM_MODE_DPMS_OFF;
1299
1300         mutex_init(&priv->mutex);       /* protect the page access */
1301
1302         /* wake up the device: */
1303         cec_write(priv, REG_CEC_ENAMODS,
1304                         CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1305
1306         tda998x_reset(priv);
1307
1308         /* read version: */
1309         rev_lo = reg_read(priv, REG_VERSION_LSB);
1310         rev_hi = reg_read(priv, REG_VERSION_MSB);
1311         if (rev_lo < 0 || rev_hi < 0) {
1312                 ret = rev_lo < 0 ? rev_lo : rev_hi;
1313                 goto fail;
1314         }
1315
1316         priv->rev = rev_lo | rev_hi << 8;
1317
1318         /* mask off feature bits: */
1319         priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1320
1321         switch (priv->rev) {
1322         case TDA9989N2:
1323                 dev_info(&client->dev, "found TDA9989 n2");
1324                 break;
1325         case TDA19989:
1326                 dev_info(&client->dev, "found TDA19989");
1327                 break;
1328         case TDA19989N2:
1329                 dev_info(&client->dev, "found TDA19989 n2");
1330                 break;
1331         case TDA19988:
1332                 dev_info(&client->dev, "found TDA19988");
1333                 break;
1334         default:
1335                 dev_err(&client->dev, "found unsupported device: %04x\n",
1336                         priv->rev);
1337                 goto fail;
1338         }
1339
1340         /* after reset, enable DDC: */
1341         reg_write(priv, REG_DDC_DISABLE, 0x00);
1342
1343         /* set clock on DDC channel: */
1344         reg_write(priv, REG_TX3, 39);
1345
1346         /* if necessary, disable multi-master: */
1347         if (priv->rev == TDA19989)
1348                 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1349
1350         cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1351                         CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1352
1353         /* initialize the optional IRQ */
1354         if (client->irq) {
1355                 int irqf_trigger;
1356
1357                 /* init read EDID waitqueue and HDP work */
1358                 init_waitqueue_head(&priv->wq_edid);
1359                 INIT_DELAYED_WORK(&priv->dwork, tda998x_hpd);
1360
1361                 /* clear pending interrupts */
1362                 reg_read(priv, REG_INT_FLAGS_0);
1363                 reg_read(priv, REG_INT_FLAGS_1);
1364                 reg_read(priv, REG_INT_FLAGS_2);
1365
1366                 irqf_trigger =
1367                         irqd_get_trigger_type(irq_get_irq_data(client->irq));
1368                 ret = request_threaded_irq(client->irq, NULL,
1369                                            tda998x_irq_thread,
1370                                            irqf_trigger | IRQF_ONESHOT,
1371                                            "tda998x", priv);
1372                 if (ret) {
1373                         dev_err(&client->dev,
1374                                 "failed to request IRQ#%u: %d\n",
1375                                 client->irq, ret);
1376                         goto fail;
1377                 }
1378
1379                 /* enable HPD irq */
1380                 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1381         }
1382
1383         /* enable EDID read irq: */
1384         reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1385
1386         if (!np)
1387                 return 0;               /* non-DT */
1388
1389         /* get the optional video properties */
1390         ret = of_property_read_u32(np, "video-ports", &video);
1391         if (ret == 0) {
1392                 priv->vip_cntrl_0 = video >> 16;
1393                 priv->vip_cntrl_1 = video >> 8;
1394                 priv->vip_cntrl_2 = video;
1395         }
1396
1397         return 0;
1398
1399 fail:
1400         /* if encoder_init fails, the encoder slave is never registered,
1401          * so cleanup here:
1402          */
1403         if (priv->cec)
1404                 i2c_unregister_device(priv->cec);
1405         return -ENXIO;
1406 }
1407
1408 static int tda998x_encoder_init(struct i2c_client *client,
1409                                 struct drm_device *dev,
1410                                 struct drm_encoder_slave *encoder_slave)
1411 {
1412         struct tda998x_priv *priv;
1413         int ret;
1414
1415         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1416         if (!priv)
1417                 return -ENOMEM;
1418
1419         priv->encoder = &encoder_slave->base;
1420
1421         ret = tda998x_create(client, priv);
1422         if (ret) {
1423                 kfree(priv);
1424                 return ret;
1425         }
1426
1427         encoder_slave->slave_priv = priv;
1428         encoder_slave->slave_funcs = &tda998x_encoder_slave_funcs;
1429
1430         return 0;
1431 }
1432
1433 struct tda998x_priv2 {
1434         struct tda998x_priv base;
1435         struct drm_encoder encoder;
1436         struct drm_connector connector;
1437 };
1438
1439 #define conn_to_tda998x_priv2(x) \
1440         container_of(x, struct tda998x_priv2, connector);
1441
1442 #define enc_to_tda998x_priv2(x) \
1443         container_of(x, struct tda998x_priv2, encoder);
1444
1445 static void tda998x_encoder2_dpms(struct drm_encoder *encoder, int mode)
1446 {
1447         struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1448
1449         tda998x_encoder_dpms(&priv->base, mode);
1450 }
1451
1452 static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1453 {
1454         tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_OFF);
1455 }
1456
1457 static void tda998x_encoder_commit(struct drm_encoder *encoder)
1458 {
1459         tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_ON);
1460 }
1461
1462 static void tda998x_encoder2_mode_set(struct drm_encoder *encoder,
1463                                       struct drm_display_mode *mode,
1464                                       struct drm_display_mode *adjusted_mode)
1465 {
1466         struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1467
1468         tda998x_encoder_mode_set(&priv->base, mode, adjusted_mode);
1469 }
1470
1471 static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
1472         .dpms = tda998x_encoder2_dpms,
1473         .save = tda998x_encoder_save,
1474         .restore = tda998x_encoder_restore,
1475         .mode_fixup = tda998x_encoder_mode_fixup,
1476         .prepare = tda998x_encoder_prepare,
1477         .commit = tda998x_encoder_commit,
1478         .mode_set = tda998x_encoder2_mode_set,
1479 };
1480
1481 static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1482 {
1483         struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1484
1485         tda998x_destroy(&priv->base);
1486         drm_encoder_cleanup(encoder);
1487 }
1488
1489 static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1490         .destroy = tda998x_encoder_destroy,
1491 };
1492
1493 static int tda998x_connector_get_modes(struct drm_connector *connector)
1494 {
1495         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1496
1497         return tda998x_encoder_get_modes(&priv->base, connector);
1498 }
1499
1500 static int tda998x_connector_mode_valid(struct drm_connector *connector,
1501                                         struct drm_display_mode *mode)
1502 {
1503         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1504
1505         return tda998x_encoder_mode_valid(&priv->base, mode);
1506 }
1507
1508 static struct drm_encoder *
1509 tda998x_connector_best_encoder(struct drm_connector *connector)
1510 {
1511         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1512
1513         return &priv->encoder;
1514 }
1515
1516 static
1517 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1518         .get_modes = tda998x_connector_get_modes,
1519         .mode_valid = tda998x_connector_mode_valid,
1520         .best_encoder = tda998x_connector_best_encoder,
1521 };
1522
1523 static enum drm_connector_status
1524 tda998x_connector_detect(struct drm_connector *connector, bool force)
1525 {
1526         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1527
1528         return tda998x_encoder_detect(&priv->base);
1529 }
1530
1531 static void tda998x_connector_destroy(struct drm_connector *connector)
1532 {
1533         drm_connector_unregister(connector);
1534         drm_connector_cleanup(connector);
1535 }
1536
1537 static const struct drm_connector_funcs tda998x_connector_funcs = {
1538         .dpms = drm_helper_connector_dpms,
1539         .fill_modes = drm_helper_probe_single_connector_modes,
1540         .detect = tda998x_connector_detect,
1541         .destroy = tda998x_connector_destroy,
1542 };
1543
1544 static int tda998x_bind(struct device *dev, struct device *master, void *data)
1545 {
1546         struct tda998x_encoder_params *params = dev->platform_data;
1547         struct i2c_client *client = to_i2c_client(dev);
1548         struct drm_device *drm = data;
1549         struct tda998x_priv2 *priv;
1550         int ret;
1551
1552         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1553         if (!priv)
1554                 return -ENOMEM;
1555
1556         dev_set_drvdata(dev, priv);
1557
1558         priv->base.encoder = &priv->encoder;
1559         priv->connector.interlace_allowed = 1;
1560         priv->encoder.possible_crtcs = 1 << 0;
1561
1562         ret = tda998x_create(client, &priv->base);
1563         if (ret)
1564                 return ret;
1565
1566         if (!dev->of_node && params)
1567                 tda998x_encoder_set_config(&priv->base, params);
1568
1569         tda998x_encoder_set_polling(&priv->base, &priv->connector);
1570
1571         drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1572         ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
1573                                DRM_MODE_ENCODER_TMDS);
1574         if (ret)
1575                 goto err_encoder;
1576
1577         drm_connector_helper_add(&priv->connector,
1578                                  &tda998x_connector_helper_funcs);
1579         ret = drm_connector_init(drm, &priv->connector,
1580                                  &tda998x_connector_funcs,
1581                                  DRM_MODE_CONNECTOR_HDMIA);
1582         if (ret)
1583                 goto err_connector;
1584
1585         ret = drm_connector_register(&priv->connector);
1586         if (ret)
1587                 goto err_sysfs;
1588
1589         priv->connector.encoder = &priv->encoder;
1590         drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
1591
1592         return 0;
1593
1594 err_sysfs:
1595         drm_connector_cleanup(&priv->connector);
1596 err_connector:
1597         drm_encoder_cleanup(&priv->encoder);
1598 err_encoder:
1599         tda998x_destroy(&priv->base);
1600         return ret;
1601 }
1602
1603 static void tda998x_unbind(struct device *dev, struct device *master,
1604                            void *data)
1605 {
1606         struct tda998x_priv2 *priv = dev_get_drvdata(dev);
1607
1608         drm_connector_cleanup(&priv->connector);
1609         drm_encoder_cleanup(&priv->encoder);
1610         tda998x_destroy(&priv->base);
1611 }
1612
1613 static const struct component_ops tda998x_ops = {
1614         .bind = tda998x_bind,
1615         .unbind = tda998x_unbind,
1616 };
1617
1618 static int
1619 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1620 {
1621         return component_add(&client->dev, &tda998x_ops);
1622 }
1623
1624 static int tda998x_remove(struct i2c_client *client)
1625 {
1626         component_del(&client->dev, &tda998x_ops);
1627         return 0;
1628 }
1629
1630 #ifdef CONFIG_OF
1631 static const struct of_device_id tda998x_dt_ids[] = {
1632         { .compatible = "nxp,tda998x", },
1633         { }
1634 };
1635 MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1636 #endif
1637
1638 static struct i2c_device_id tda998x_ids[] = {
1639         { "tda998x", 0 },
1640         { }
1641 };
1642 MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1643
1644 static struct drm_i2c_encoder_driver tda998x_driver = {
1645         .i2c_driver = {
1646                 .probe = tda998x_probe,
1647                 .remove = tda998x_remove,
1648                 .driver = {
1649                         .name = "tda998x",
1650                         .of_match_table = of_match_ptr(tda998x_dt_ids),
1651                 },
1652                 .id_table = tda998x_ids,
1653         },
1654         .encoder_init = tda998x_encoder_init,
1655 };
1656
1657 /* Module initialization */
1658
1659 static int __init
1660 tda998x_init(void)
1661 {
1662         DBG("");
1663         return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver);
1664 }
1665
1666 static void __exit
1667 tda998x_exit(void)
1668 {
1669         DBG("");
1670         drm_i2c_encoder_unregister(&tda998x_driver);
1671 }
1672
1673 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1674 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1675 MODULE_LICENSE("GPL");
1676
1677 module_init(tda998x_init);
1678 module_exit(tda998x_exit);