drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <christian.koenig@amd.com>
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_uvd.h"
  29 #include "cikd.h"
  30
  31 #include "uvd/uvd_4_2_d.h"
  32 #include "uvd/uvd_4_2_sh_mask.h"
  33
  34 #include "oss/oss_2_0_d.h"
  35 #include "oss/oss_2_0_sh_mask.h"
  36
  37 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev);
  38 static void uvd_v4_2_init_cg(struct amdgpu_device *adev);
  39 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev);
  40 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev);
  41 static int uvd_v4_2_start(struct amdgpu_device *adev);
  42 static void uvd_v4_2_stop(struct amdgpu_device *adev);
  43
  44 /**
  45  * uvd_v4_2_ring_get_rptr - get read pointer
  46  *
  47  * @ring: amdgpu_ring pointer
  48  *
  49  * Returns the current hardware read pointer
  50  */
  51 static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring)
  52 {
  53         struct amdgpu_device *adev = ring->adev;
  54
  55         return RREG32(mmUVD_RBC_RB_RPTR);
  56 }
  57
  58 /**
  59  * uvd_v4_2_ring_get_wptr - get write pointer
  60  *
  61  * @ring: amdgpu_ring pointer
  62  *
  63  * Returns the current hardware write pointer
  64  */
  65 static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring)
  66 {
  67         struct amdgpu_device *adev = ring->adev;
  68
  69         return RREG32(mmUVD_RBC_RB_WPTR);
  70 }
  71
  72 /**
  73  * uvd_v4_2_ring_set_wptr - set write pointer
  74  *
  75  * @ring: amdgpu_ring pointer
  76  *
  77  * Commits the write pointer to the hardware
  78  */
  79 static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring)
  80 {
  81         struct amdgpu_device *adev = ring->adev;
  82
  83         WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
  84 }
  85
  86 static int uvd_v4_2_early_init(void *handle)
  87 {
  88         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  89
  90         uvd_v4_2_set_ring_funcs(adev);
  91         uvd_v4_2_set_irq_funcs(adev);
  92
  93         return 0;
  94 }
  95
  96 static int uvd_v4_2_sw_init(void *handle)
  97 {
  98         struct amdgpu_ring *ring;
  99         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 100         int r;
 101
 102         /* UVD TRAP */
 103         r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
 104         if (r)
 105                 return r;
 106
 107         r = amdgpu_uvd_sw_init(adev);
 108         if (r)
 109                 return r;
 110
 111         r = amdgpu_uvd_resume(adev);
 112         if (r)
 113                 return r;
 114
 115         ring = &adev->uvd.ring;
 116         sprintf(ring->name, "uvd");
 117         r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,
 118                              &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
 119
 120         return r;
 121 }
 122
 123 static int uvd_v4_2_sw_fini(void *handle)
 124 {
 125         int r;
 126         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 127
 128         r = amdgpu_uvd_suspend(adev);
 129         if (r)
 130                 return r;
 131
 132         r = amdgpu_uvd_sw_fini(adev);
 133         if (r)
 134                 return r;
 135
 136         return r;
 137 }
 138
 139 /**
 140  * uvd_v4_2_hw_init - start and test UVD block
 141  *
 142  * @adev: amdgpu_device pointer
 143  *
 144  * Initialize the hardware, boot up the VCPU and do some testing
 145  */
 146 static int uvd_v4_2_hw_init(void *handle)
 147 {
 148         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 149         struct amdgpu_ring *ring = &adev->uvd.ring;
 150         uint32_t tmp;
 151         int r;
 152
 153         /* raise clocks while booting up the VCPU */
 154         amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
 155
 156         r = uvd_v4_2_start(adev);
 157         if (r)
 158                 goto done;
 159
 160         ring->ready = true;
 161         r = amdgpu_ring_test_ring(ring);
 162         if (r) {
 163                 ring->ready = false;
 164                 goto done;
 165         }
 166
 167         r = amdgpu_ring_lock(ring, 10);
 168         if (r) {
 169                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 170                 goto done;
 171         }
 172
 173         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 174         amdgpu_ring_write(ring, tmp);
 175         amdgpu_ring_write(ring, 0xFFFFF);
 176
 177         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 178         amdgpu_ring_write(ring, tmp);
 179         amdgpu_ring_write(ring, 0xFFFFF);
 180
 181         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 182         amdgpu_ring_write(ring, tmp);
 183         amdgpu_ring_write(ring, 0xFFFFF);
 184
 185         /* Clear timeout status bits */
 186         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 187         amdgpu_ring_write(ring, 0x8);
 188
 189         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 190         amdgpu_ring_write(ring, 3);
 191
 192         amdgpu_ring_unlock_commit(ring);
 193
 194 done:
 195         /* lower clocks again */
 196         amdgpu_asic_set_uvd_clocks(adev, 0, 0);
 197
 198         if (!r)
 199                 DRM_INFO("UVD initialized successfully.\n");
 200
 201         return r;
 202 }
 203
 204 /**
 205  * uvd_v4_2_hw_fini - stop the hardware block
 206  *
 207  * @adev: amdgpu_device pointer
 208  *
 209  * Stop the UVD block, mark ring as not ready any more
 210  */
 211 static int uvd_v4_2_hw_fini(void *handle)
 212 {
 213         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 214         struct amdgpu_ring *ring = &adev->uvd.ring;
 215
 216         uvd_v4_2_stop(adev);
 217         ring->ready = false;
 218
 219         return 0;
 220 }
 221
 222 static int uvd_v4_2_suspend(void *handle)
 223 {
 224         int r;
 225         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 226
 227         r = amdgpu_uvd_suspend(adev);
 228         if (r)
 229                 return r;
 230
 231         r = uvd_v4_2_hw_fini(adev);
 232         if (r)
 233                 return r;
 234
 235         return r;
 236 }
 237
 238 static int uvd_v4_2_resume(void *handle)
 239 {
 240         int r;
 241         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 242
 243         r = amdgpu_uvd_resume(adev);
 244         if (r)
 245                 return r;
 246
 247         r = uvd_v4_2_hw_init(adev);
 248         if (r)
 249                 return r;
 250
 251         return r;
 252 }
 253
 254 /**
 255  * uvd_v4_2_start - start UVD block
 256  *
 257  * @adev: amdgpu_device pointer
 258  *
 259  * Setup and start the UVD block
 260  */
 261 static int uvd_v4_2_start(struct amdgpu_device *adev)
 262 {
 263         struct amdgpu_ring *ring = &adev->uvd.ring;
 264         uint32_t rb_bufsz;
 265         int i, j, r;
 266
 267         /* disable byte swapping */
 268         u32 lmi_swap_cntl = 0;
 269         u32 mp_swap_cntl = 0;
 270
 271         uvd_v4_2_mc_resume(adev);
 272
 273         /* disable clock gating */
 274         WREG32(mmUVD_CGC_GATE, 0);
 275
 276         /* disable interupt */
 277         WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
 278
 279         /* Stall UMC and register bus before resetting VCPU */
 280         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 281         mdelay(1);
 282
 283         /* put LMI, VCPU, RBC etc... into reset */
 284         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 285                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 286                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 287                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 288                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 289         mdelay(5);
 290
 291         /* take UVD block out of reset */
 292         WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 293         mdelay(5);
 294
 295         /* initialize UVD memory controller */
 296         WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
 297                              (1 << 21) | (1 << 9) | (1 << 20));
 298
 299 #ifdef __BIG_ENDIAN
 300         /* swap (8 in 32) RB and IB */
 301         lmi_swap_cntl = 0xa;
 302         mp_swap_cntl = 0;
 303 #endif
 304         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 305         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 306
 307         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 308         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 309         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 310         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 311         WREG32(mmUVD_MPC_SET_ALU, 0);
 312         WREG32(mmUVD_MPC_SET_MUX, 0x88);
 313
 314         /* take all subblocks out of reset, except VCPU */
 315         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 316         mdelay(5);
 317
 318         /* enable VCPU clock */
 319         WREG32(mmUVD_VCPU_CNTL,  1 << 9);
 320
 321         /* enable UMC */
 322         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 323
 324         /* boot up the VCPU */
 325         WREG32(mmUVD_SOFT_RESET, 0);
 326         mdelay(10);
 327
 328         for (i = 0; i < 10; ++i) {
 329                 uint32_t status;
 330                 for (j = 0; j < 100; ++j) {
 331                         status = RREG32(mmUVD_STATUS);
 332                         if (status & 2)
 333                                 break;
 334                         mdelay(10);
 335                 }
 336                 r = 0;
 337                 if (status & 2)
 338                         break;
 339
 340                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 341                 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 342                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 343                 mdelay(10);
 344                 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 345                 mdelay(10);
 346                 r = -1;
 347         }
 348
 349         if (r) {
 350                 DRM_ERROR("UVD not responding, giving up!!!\n");
 351                 return r;
 352         }
 353
 354         /* enable interupt */
 355         WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
 356
 357         /* force RBC into idle state */
 358         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 359
 360         /* Set the write pointer delay */
 361         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 362
 363         /* programm the 4GB memory segment for rptr and ring buffer */
 364         WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
 365                                    (0x7 << 16) | (0x1 << 31));
 366
 367         /* Initialize the ring buffer's read and write pointers */
 368         WREG32(mmUVD_RBC_RB_RPTR, 0x0);
 369
 370         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 371         WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
 372
 373         /* set the ring address */
 374         WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);
 375
 376         /* Set ring buffer size */
 377         rb_bufsz = order_base_2(ring->ring_size);
 378         rb_bufsz = (0x1 << 8) | rb_bufsz;
 379         WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
 380
 381         return 0;
 382 }
 383
 384 /**
 385  * uvd_v4_2_stop - stop UVD block
 386  *
 387  * @adev: amdgpu_device pointer
 388  *
 389  * stop the UVD block
 390  */
 391 static void uvd_v4_2_stop(struct amdgpu_device *adev)
 392 {
 393         /* force RBC into idle state */
 394         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 395
 396         /* Stall UMC and register bus before resetting VCPU */
 397         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 398         mdelay(1);
 399
 400         /* put VCPU into reset */
 401         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 402         mdelay(5);
 403
 404         /* disable VCPU clock */
 405         WREG32(mmUVD_VCPU_CNTL, 0x0);
 406
 407         /* Unstall UMC and register bus */
 408         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 409 }
 410
 411 /**
 412  * uvd_v4_2_ring_emit_fence - emit an fence & trap command
 413  *
 414  * @ring: amdgpu_ring pointer
 415  * @fence: fence to emit
 416  *
 417  * Write a fence and a trap command to the ring.
 418  */
 419 static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 420                                      unsigned flags)
 421 {
 422         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 423
 424         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 425         amdgpu_ring_write(ring, seq);
 426         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 427         amdgpu_ring_write(ring, addr & 0xffffffff);
 428         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 429         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 430         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 431         amdgpu_ring_write(ring, 0);
 432
 433         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 434         amdgpu_ring_write(ring, 0);
 435         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 436         amdgpu_ring_write(ring, 0);
 437         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 438         amdgpu_ring_write(ring, 2);
 439 }
 440
 441 /**
 442  * uvd_v4_2_ring_emit_semaphore - emit semaphore command
 443  *
 444  * @ring: amdgpu_ring pointer
 445  * @semaphore: semaphore to emit commands for
 446  * @emit_wait: true if we should emit a wait command
 447  *
 448  * Emit a semaphore command (either wait or signal) to the UVD ring.
 449  */
 450 static bool uvd_v4_2_ring_emit_semaphore(struct amdgpu_ring *ring,
 451                                          struct amdgpu_semaphore *semaphore,
 452                                          bool emit_wait)
 453 {
 454         uint64_t addr = semaphore->gpu_addr;
 455
 456         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0));
 457         amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
 458
 459         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0));
 460         amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
 461
 462         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0));
 463         amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));
 464
 465         return true;
 466 }
 467
 468 /**
 469  * uvd_v4_2_ring_test_ring - register write test
 470  *
 471  * @ring: amdgpu_ring pointer
 472  *
 473  * Test if we can successfully write to the context register
 474  */
 475 static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring)
 476 {
 477         struct amdgpu_device *adev = ring->adev;
 478         uint32_t tmp = 0;
 479         unsigned i;
 480         int r;
 481
 482         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
 483         r = amdgpu_ring_lock(ring, 3);
 484         if (r) {
 485                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 486                           ring->idx, r);
 487                 return r;
 488         }
 489         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 490         amdgpu_ring_write(ring, 0xDEADBEEF);
 491         amdgpu_ring_unlock_commit(ring);
 492         for (i = 0; i < adev->usec_timeout; i++) {
 493                 tmp = RREG32(mmUVD_CONTEXT_ID);
 494                 if (tmp == 0xDEADBEEF)
 495                         break;
 496                 DRM_UDELAY(1);
 497         }
 498
 499         if (i < adev->usec_timeout) {
 500                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 501                          ring->idx, i);
 502         } else {
 503                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 504                           ring->idx, tmp);
 505                 r = -EINVAL;
 506         }
 507         return r;
 508 }
 509
 510 /**
 511  * uvd_v4_2_ring_emit_ib - execute indirect buffer
 512  *
 513  * @ring: amdgpu_ring pointer
 514  * @ib: indirect buffer to execute
 515  *
 516  * Write ring commands to execute the indirect buffer
 517  */
 518 static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring,
 519                                   struct amdgpu_ib *ib)
 520 {
 521         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
 522         amdgpu_ring_write(ring, ib->gpu_addr);
 523         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
 524         amdgpu_ring_write(ring, ib->length_dw);
 525 }
 526
 527 /**
 528  * uvd_v4_2_ring_test_ib - test ib execution
 529  *
 530  * @ring: amdgpu_ring pointer
 531  *
 532  * Test if we can successfully execute an IB
 533  */
 534 static int uvd_v4_2_ring_test_ib(struct amdgpu_ring *ring)
 535 {
 536         struct amdgpu_device *adev = ring->adev;
 537         struct fence *fence = NULL;
 538         int r;
 539
 540         r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
 541         if (r) {
 542                 DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r);
 543                 return r;
 544         }
 545
 546         r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
 547         if (r) {
 548                 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);
 549                 goto error;
 550         }
 551
 552         r = amdgpu_uvd_get_destroy_msg(ring, 1, &fence);
 553         if (r) {
 554                 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
 555                 goto error;
 556         }
 557
 558         r = fence_wait(fence, false);
 559         if (r) {
 560                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 561                 goto error;
 562         }
 563         DRM_INFO("ib test on ring %d succeeded\n",  ring->idx);
 564 error:
 565         fence_put(fence);
 566         amdgpu_asic_set_uvd_clocks(adev, 0, 0);
 567         return r;
 568 }
 569
 570 /**
 571  * uvd_v4_2_mc_resume - memory controller programming
 572  *
 573  * @adev: amdgpu_device pointer
 574  *
 575  * Let the UVD memory controller know it's offsets
 576  */
 577 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
 578 {
 579         uint64_t addr;
 580         uint32_t size;
 581
 582         /* programm the VCPU memory controller bits 0-27 */
 583         addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
 584         size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3;
 585         WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
 586         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 587
 588         addr += size;
 589         size = AMDGPU_UVD_STACK_SIZE >> 3;
 590         WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
 591         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 592
 593         addr += size;
 594         size = AMDGPU_UVD_HEAP_SIZE >> 3;
 595         WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
 596         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 597
 598         /* bits 28-31 */
 599         addr = (adev->uvd.gpu_addr >> 28) & 0xF;
 600         WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
 601
 602         /* bits 32-39 */
 603         addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
 604         WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
 605
 606         uvd_v4_2_init_cg(adev);
 607 }
 608
 609 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
 610                                  bool enable)
 611 {
 612         u32 orig, data;
 613
 614         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG)) {
 615                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
 616                 data = 0xfff;
 617                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
 618
 619                 orig = data = RREG32(mmUVD_CGC_CTRL);
 620                 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 621                 if (orig != data)
 622                         WREG32(mmUVD_CGC_CTRL, data);
 623         } else {
 624                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
 625                 data &= ~0xfff;
 626                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
 627
 628                 orig = data = RREG32(mmUVD_CGC_CTRL);
 629                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 630                 if (orig != data)
 631                         WREG32(mmUVD_CGC_CTRL, data);
 632         }
 633 }
 634
 635 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
 636                              bool sw_mode)
 637 {
 638         u32 tmp, tmp2;
 639
 640         tmp = RREG32(mmUVD_CGC_CTRL);
 641         tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
 642         tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
 643                 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) |
 644                 (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT);
 645
 646         if (sw_mode) {
 647                 tmp &= ~0x7ffff800;
 648                 tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK |
 649                         UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK |
 650                         (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT);
 651         } else {
 652                 tmp |= 0x7ffff800;
 653                 tmp2 = 0;
 654         }
 655
 656         WREG32(mmUVD_CGC_CTRL, tmp);
 657         WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2);
 658 }
 659
 660 static void uvd_v4_2_init_cg(struct amdgpu_device *adev)
 661 {
 662         bool hw_mode = true;
 663
 664         if (hw_mode) {
 665                 uvd_v4_2_set_dcm(adev, false);
 666         } else {
 667                 u32 tmp = RREG32(mmUVD_CGC_CTRL);
 668                 tmp &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 669                 WREG32(mmUVD_CGC_CTRL, tmp);
 670         }
 671 }
 672
 673 static bool uvd_v4_2_is_idle(void *handle)
 674 {
 675         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 676
 677         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
 678 }
 679
 680 static int uvd_v4_2_wait_for_idle(void *handle)
 681 {
 682         unsigned i;
 683         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 684
 685         for (i = 0; i < adev->usec_timeout; i++) {
 686                 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
 687                         return 0;
 688         }
 689         return -ETIMEDOUT;
 690 }
 691
 692 static int uvd_v4_2_soft_reset(void *handle)
 693 {
 694         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 695
 696         uvd_v4_2_stop(adev);
 697
 698         WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
 699                         ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 700         mdelay(5);
 701
 702         return uvd_v4_2_start(adev);
 703 }
 704
 705 static void uvd_v4_2_print_status(void *handle)
 706 {
 707         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 708         dev_info(adev->dev, "UVD 4.2 registers\n");
 709         dev_info(adev->dev, "  UVD_SEMA_ADDR_LOW=0x%08X\n",
 710                  RREG32(mmUVD_SEMA_ADDR_LOW));
 711         dev_info(adev->dev, "  UVD_SEMA_ADDR_HIGH=0x%08X\n",
 712                  RREG32(mmUVD_SEMA_ADDR_HIGH));
 713         dev_info(adev->dev, "  UVD_SEMA_CMD=0x%08X\n",
 714                  RREG32(mmUVD_SEMA_CMD));
 715         dev_info(adev->dev, "  UVD_GPCOM_VCPU_CMD=0x%08X\n",
 716                  RREG32(mmUVD_GPCOM_VCPU_CMD));
 717         dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA0=0x%08X\n",
 718                  RREG32(mmUVD_GPCOM_VCPU_DATA0));
 719         dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA1=0x%08X\n",
 720                  RREG32(mmUVD_GPCOM_VCPU_DATA1));
 721         dev_info(adev->dev, "  UVD_ENGINE_CNTL=0x%08X\n",
 722                  RREG32(mmUVD_ENGINE_CNTL));
 723         dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
 724                  RREG32(mmUVD_UDEC_ADDR_CONFIG));
 725         dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
 726                  RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
 727         dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
 728                  RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
 729         dev_info(adev->dev, "  UVD_SEMA_CNTL=0x%08X\n",
 730                  RREG32(mmUVD_SEMA_CNTL));
 731         dev_info(adev->dev, "  UVD_LMI_EXT40_ADDR=0x%08X\n",
 732                  RREG32(mmUVD_LMI_EXT40_ADDR));
 733         dev_info(adev->dev, "  UVD_CTX_INDEX=0x%08X\n",
 734                  RREG32(mmUVD_CTX_INDEX));
 735         dev_info(adev->dev, "  UVD_CTX_DATA=0x%08X\n",
 736                  RREG32(mmUVD_CTX_DATA));
 737         dev_info(adev->dev, "  UVD_CGC_GATE=0x%08X\n",
 738                  RREG32(mmUVD_CGC_GATE));
 739         dev_info(adev->dev, "  UVD_CGC_CTRL=0x%08X\n",
 740                  RREG32(mmUVD_CGC_CTRL));
 741         dev_info(adev->dev, "  UVD_LMI_CTRL2=0x%08X\n",
 742                  RREG32(mmUVD_LMI_CTRL2));
 743         dev_info(adev->dev, "  UVD_MASTINT_EN=0x%08X\n",
 744                  RREG32(mmUVD_MASTINT_EN));
 745         dev_info(adev->dev, "  UVD_LMI_ADDR_EXT=0x%08X\n",
 746                  RREG32(mmUVD_LMI_ADDR_EXT));
 747         dev_info(adev->dev, "  UVD_LMI_CTRL=0x%08X\n",
 748                  RREG32(mmUVD_LMI_CTRL));
 749         dev_info(adev->dev, "  UVD_LMI_SWAP_CNTL=0x%08X\n",
 750                  RREG32(mmUVD_LMI_SWAP_CNTL));
 751         dev_info(adev->dev, "  UVD_MP_SWAP_CNTL=0x%08X\n",
 752                  RREG32(mmUVD_MP_SWAP_CNTL));
 753         dev_info(adev->dev, "  UVD_MPC_SET_MUXA0=0x%08X\n",
 754                  RREG32(mmUVD_MPC_SET_MUXA0));
 755         dev_info(adev->dev, "  UVD_MPC_SET_MUXA1=0x%08X\n",
 756                  RREG32(mmUVD_MPC_SET_MUXA1));
 757         dev_info(adev->dev, "  UVD_MPC_SET_MUXB0=0x%08X\n",
 758                  RREG32(mmUVD_MPC_SET_MUXB0));
 759         dev_info(adev->dev, "  UVD_MPC_SET_MUXB1=0x%08X\n",
 760                  RREG32(mmUVD_MPC_SET_MUXB1));
 761         dev_info(adev->dev, "  UVD_MPC_SET_MUX=0x%08X\n",
 762                  RREG32(mmUVD_MPC_SET_MUX));
 763         dev_info(adev->dev, "  UVD_MPC_SET_ALU=0x%08X\n",
 764                  RREG32(mmUVD_MPC_SET_ALU));
 765         dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
 766                  RREG32(mmUVD_VCPU_CACHE_OFFSET0));
 767         dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE0=0x%08X\n",
 768                  RREG32(mmUVD_VCPU_CACHE_SIZE0));
 769         dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
 770                  RREG32(mmUVD_VCPU_CACHE_OFFSET1));
 771         dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE1=0x%08X\n",
 772                  RREG32(mmUVD_VCPU_CACHE_SIZE1));
 773         dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
 774                  RREG32(mmUVD_VCPU_CACHE_OFFSET2));
 775         dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE2=0x%08X\n",
 776                  RREG32(mmUVD_VCPU_CACHE_SIZE2));
 777         dev_info(adev->dev, "  UVD_VCPU_CNTL=0x%08X\n",
 778                  RREG32(mmUVD_VCPU_CNTL));
 779         dev_info(adev->dev, "  UVD_SOFT_RESET=0x%08X\n",
 780                  RREG32(mmUVD_SOFT_RESET));
 781         dev_info(adev->dev, "  UVD_RBC_IB_BASE=0x%08X\n",
 782                  RREG32(mmUVD_RBC_IB_BASE));
 783         dev_info(adev->dev, "  UVD_RBC_IB_SIZE=0x%08X\n",
 784                  RREG32(mmUVD_RBC_IB_SIZE));
 785         dev_info(adev->dev, "  UVD_RBC_RB_BASE=0x%08X\n",
 786                  RREG32(mmUVD_RBC_RB_BASE));
 787         dev_info(adev->dev, "  UVD_RBC_RB_RPTR=0x%08X\n",
 788                  RREG32(mmUVD_RBC_RB_RPTR));
 789         dev_info(adev->dev, "  UVD_RBC_RB_WPTR=0x%08X\n",
 790                  RREG32(mmUVD_RBC_RB_WPTR));
 791         dev_info(adev->dev, "  UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
 792                  RREG32(mmUVD_RBC_RB_WPTR_CNTL));
 793         dev_info(adev->dev, "  UVD_RBC_RB_CNTL=0x%08X\n",
 794                  RREG32(mmUVD_RBC_RB_CNTL));
 795         dev_info(adev->dev, "  UVD_STATUS=0x%08X\n",
 796                  RREG32(mmUVD_STATUS));
 797         dev_info(adev->dev, "  UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
 798                  RREG32(mmUVD_SEMA_TIMEOUT_STATUS));
 799         dev_info(adev->dev, "  UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
 800                  RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));
 801         dev_info(adev->dev, "  UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
 802                  RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));
 803         dev_info(adev->dev, "  UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
 804                  RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
 805         dev_info(adev->dev, "  UVD_CONTEXT_ID=0x%08X\n",
 806                  RREG32(mmUVD_CONTEXT_ID));
 807 }
 808
 809 static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev,
 810                                         struct amdgpu_irq_src *source,
 811                                         unsigned type,
 812                                         enum amdgpu_interrupt_state state)
 813 {
 814         // TODO
 815         return 0;
 816 }
 817
 818 static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev,
 819                                       struct amdgpu_irq_src *source,
 820                                       struct amdgpu_iv_entry *entry)
 821 {
 822         DRM_DEBUG("IH: UVD TRAP\n");
 823         amdgpu_fence_process(&adev->uvd.ring);
 824         return 0;
 825 }
 826
 827 static int uvd_v4_2_set_clockgating_state(void *handle,
 828                                           enum amd_clockgating_state state)
 829 {
 830         bool gate = false;
 831         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 832
 833         if (state == AMD_CG_STATE_GATE)
 834                 gate = true;
 835
 836         uvd_v4_2_enable_mgcg(adev, gate);
 837
 838         return 0;
 839 }
 840
 841 static int uvd_v4_2_set_powergating_state(void *handle,
 842                                           enum amd_powergating_state state)
 843 {
 844         /* This doesn't actually powergate the UVD block.
 845          * That's done in the dpm code via the SMC.  This
 846          * just re-inits the block as necessary.  The actual
 847          * gating still happens in the dpm code.  We should
 848          * revisit this when there is a cleaner line between
 849          * the smc and the hw blocks
 850          */
 851          struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 852
 853         if (state == AMD_PG_STATE_GATE) {
 854                 uvd_v4_2_stop(adev);
 855                 return 0;
 856         } else {
 857                 return uvd_v4_2_start(adev);
 858         }
 859 }
 860
 861 const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
 862         .early_init = uvd_v4_2_early_init,
 863         .late_init = NULL,
 864         .sw_init = uvd_v4_2_sw_init,
 865         .sw_fini = uvd_v4_2_sw_fini,
 866         .hw_init = uvd_v4_2_hw_init,
 867         .hw_fini = uvd_v4_2_hw_fini,
 868         .suspend = uvd_v4_2_suspend,
 869         .resume = uvd_v4_2_resume,
 870         .is_idle = uvd_v4_2_is_idle,
 871         .wait_for_idle = uvd_v4_2_wait_for_idle,
 872         .soft_reset = uvd_v4_2_soft_reset,
 873         .print_status = uvd_v4_2_print_status,
 874         .set_clockgating_state = uvd_v4_2_set_clockgating_state,
 875         .set_powergating_state = uvd_v4_2_set_powergating_state,
 876 };
 877
 878 static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
 879         .get_rptr = uvd_v4_2_ring_get_rptr,
 880         .get_wptr = uvd_v4_2_ring_get_wptr,
 881         .set_wptr = uvd_v4_2_ring_set_wptr,
 882         .parse_cs = amdgpu_uvd_ring_parse_cs,
 883         .emit_ib = uvd_v4_2_ring_emit_ib,
 884         .emit_fence = uvd_v4_2_ring_emit_fence,
 885         .emit_semaphore = uvd_v4_2_ring_emit_semaphore,
 886         .test_ring = uvd_v4_2_ring_test_ring,
 887         .test_ib = uvd_v4_2_ring_test_ib,
 888         .is_lockup = amdgpu_ring_test_lockup,
 889         .insert_nop = amdgpu_ring_insert_nop,
 890 };
 891
 892 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev)
 893 {
 894         adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs;
 895 }
 896
 897 static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = {
 898         .set = uvd_v4_2_set_interrupt_state,
 899         .process = uvd_v4_2_process_interrupt,
 900 };
 901
 902 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev)
 903 {
 904         adev->uvd.irq.num_types = 1;
 905         adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs;
 906 }