drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_gfx.h"
  27 #include "vi.h"
  28 #include "vid.h"
  29 #include "amdgpu_ucode.h"
  30 #include "clearstate_vi.h"
  31
  32 #include "gmc/gmc_8_2_d.h"
  33 #include "gmc/gmc_8_2_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "bif/bif_5_0_d.h"
  39 #include "bif/bif_5_0_sh_mask.h"
  40
  41 #include "gca/gfx_8_0_d.h"
  42 #include "gca/gfx_8_0_enum.h"
  43 #include "gca/gfx_8_0_sh_mask.h"
  44 #include "gca/gfx_8_0_enum.h"
  45
  46 #include "uvd/uvd_5_0_d.h"
  47 #include "uvd/uvd_5_0_sh_mask.h"
  48
  49 #include "dce/dce_10_0_d.h"
  50 #include "dce/dce_10_0_sh_mask.h"
  51
  52 #define GFX8_NUM_GFX_RINGS     1
  53 #define GFX8_NUM_COMPUTE_RINGS 8
  54
  55 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
  56 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
  57 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
  58
  59 #define ARRAY_MODE(x)                                   ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
  60 #define PIPE_CONFIG(x)                                  ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
  61 #define TILE_SPLIT(x)                                   ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
  62 #define MICRO_TILE_MODE_NEW(x)                          ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
  63 #define SAMPLE_SPLIT(x)                                 ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
  64 #define BANK_WIDTH(x)                                   ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
  65 #define BANK_HEIGHT(x)                                  ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
  66 #define MACRO_TILE_ASPECT(x)                            ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
  67 #define NUM_BANKS(x)                                    ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
  68
  69 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
  70 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
  71 MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
  72 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
  73 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
  74 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
  75
  76 MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
  77 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
  78 MODULE_FIRMWARE("amdgpu/tonga_me.bin");
  79 MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
  80 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
  81 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
  82
  83 MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
  84 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
  85 MODULE_FIRMWARE("amdgpu/topaz_me.bin");
  86 MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
  87 MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
  88 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
  89
  90 MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
  91 MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
  92 MODULE_FIRMWARE("amdgpu/fiji_me.bin");
  93 MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
  94 MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
  95 MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
  96
  97 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  98 {
  99         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
 100         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
 101         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
 102         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
 103         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
 104         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
 105         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
 106         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
 107         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
 108         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 109         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 110         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 111         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 112         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 113         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 114         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
 115 };
 116
 117 static const u32 golden_settings_tonga_a11[] =
 118 {
 119         mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
 120         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 121         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 122         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 123         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 124         mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
 125         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 126         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 127         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 128         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 129         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 130         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
 131         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
 132         mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
 133         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
 134 };
 135
 136 static const u32 tonga_golden_common_all[] =
 137 {
 138         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 139         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
 140         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
 141         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
 142         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 143         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 144         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 145         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 146 };
 147
 148 static const u32 tonga_mgcg_cgcg_init[] =
 149 {
 150         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 151         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 152         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 153         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 154         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 155         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 156         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
 157         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 158         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 159         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 160         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 161         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 162         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 163         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 164         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 165         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 166         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 167         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 168         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 169         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 170         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 171         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 172         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 173         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 174         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 175         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 176         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 177         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 178         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 179         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 180         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 181         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 182         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 183         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 184         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 185         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 186         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 187         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 188         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 189         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 190         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 191         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 192         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 193         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 194         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 195         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 196         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 197         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 198         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 199         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 200         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 201         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 202         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 203         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 204         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 205         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 206         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 207         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 208         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 209         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 210         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 211         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 212         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 213         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 214         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 215         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 216         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 217         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 218         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 219         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 220         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 221         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 222         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 223         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 224         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 225 };
 226
 227 static const u32 fiji_golden_common_all[] =
 228 {
 229         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 230         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
 231         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
 232         mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003,
 233         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 234         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 235         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 236         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 237 };
 238
 239 static const u32 golden_settings_fiji_a10[] =
 240 {
 241         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
 242         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 243         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 244         mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x00000100,
 245         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 246         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 247         mmTCC_CTRL, 0x00100000, 0xf30fff7f,
 248         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
 249         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x7d6cf5e4,
 250         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x3928b1a0,
 251 };
 252
 253 static const u32 fiji_mgcg_cgcg_init[] =
 254 {
 255         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffc0,
 256         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 257         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 258         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 259         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 260         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 261         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
 262         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 263         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 264         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 265         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 266         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 267         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 268         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 269         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 270         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 271         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 272         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 273         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 274         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 275         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 276         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 277         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 278         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 279         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 280         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 281         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 282         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 283         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 284         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 285         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 286         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 287         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 288         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 289         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 290 };
 291
 292 static const u32 golden_settings_iceland_a11[] =
 293 {
 294         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 295         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 296         mmDB_DEBUG3, 0xc0000000, 0xc0000000,
 297         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 298         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 299         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 300         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
 301         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
 302         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 303         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 304         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 305         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 306         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
 307         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 308         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
 309 };
 310
 311 static const u32 iceland_golden_common_all[] =
 312 {
 313         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 314         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 315         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 316         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 317         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 318         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 319         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 320         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 321 };
 322
 323 static const u32 iceland_mgcg_cgcg_init[] =
 324 {
 325         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 326         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 327         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 328         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 329         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
 330         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
 331         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
 332         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 333         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 334         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 335         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 336         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 337         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 338         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 339         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 340         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 341         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 342         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 343         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 344         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 345         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 346         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 347         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
 348         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 349         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 350         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 351         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 352         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 353         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 354         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 355         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 356         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 357         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 358         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 359         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 360         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 361         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 362         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 363         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 364         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 365         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 366         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 367         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 368         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 369         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 370         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 371         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 372         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 373         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 374         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 375         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 376         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 377         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 378         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 379         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 380         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 381         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 382         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 383         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 384         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 385         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 386         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 387         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 388         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 389 };
 390
 391 static const u32 cz_golden_settings_a11[] =
 392 {
 393         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 394         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 395         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 396         mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
 397         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 398         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 399         mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
 400         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 401         mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
 402         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
 403 };
 404
 405 static const u32 cz_golden_common_all[] =
 406 {
 407         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 408         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 409         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 410         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 411         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 412         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 413         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 414         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 415 };
 416
 417 static const u32 cz_mgcg_cgcg_init[] =
 418 {
 419         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 420         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 421         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 422         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 423         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 424         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 425         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
 426         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 427         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 428         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 429         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 430         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 431         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 432         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 433         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 434         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 435         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 436         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 437         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 438         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 439         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 440         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 441         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 442         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 443         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 444         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 445         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 446         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 447         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 448         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 449         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 450         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 451         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 452         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 453         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 454         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 455         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 456         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 457         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 458         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 459         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 460         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 461         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 462         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 463         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 464         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 465         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 466         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 467         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 468         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 469         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 470         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 471         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 472         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 473         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 474         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 475         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 476         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 477         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 478         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 479         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 480         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 481         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 482         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 483         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 484         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 485         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 486         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 487         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 488         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 489         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 490         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 491         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 492         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 493         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 494 };
 495
 496 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
 497 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
 498 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
 499
 500 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
 501 {
 502         switch (adev->asic_type) {
 503         case CHIP_TOPAZ:
 504                 amdgpu_program_register_sequence(adev,
 505                                                  iceland_mgcg_cgcg_init,
 506                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
 507                 amdgpu_program_register_sequence(adev,
 508                                                  golden_settings_iceland_a11,
 509                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
 510                 amdgpu_program_register_sequence(adev,
 511                                                  iceland_golden_common_all,
 512                                                  (const u32)ARRAY_SIZE(iceland_golden_common_all));
 513                 break;
 514         case CHIP_FIJI:
 515                 amdgpu_program_register_sequence(adev,
 516                                                  fiji_mgcg_cgcg_init,
 517                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 518                 amdgpu_program_register_sequence(adev,
 519                                                  golden_settings_fiji_a10,
 520                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 521                 amdgpu_program_register_sequence(adev,
 522                                                  fiji_golden_common_all,
 523                                                  (const u32)ARRAY_SIZE(fiji_golden_common_all));
 524                 break;
 525
 526         case CHIP_TONGA:
 527                 amdgpu_program_register_sequence(adev,
 528                                                  tonga_mgcg_cgcg_init,
 529                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 530                 amdgpu_program_register_sequence(adev,
 531                                                  golden_settings_tonga_a11,
 532                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 533                 amdgpu_program_register_sequence(adev,
 534                                                  tonga_golden_common_all,
 535                                                  (const u32)ARRAY_SIZE(tonga_golden_common_all));
 536                 break;
 537         case CHIP_CARRIZO:
 538                 amdgpu_program_register_sequence(adev,
 539                                                  cz_mgcg_cgcg_init,
 540                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 541                 amdgpu_program_register_sequence(adev,
 542                                                  cz_golden_settings_a11,
 543                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 544                 amdgpu_program_register_sequence(adev,
 545                                                  cz_golden_common_all,
 546                                                  (const u32)ARRAY_SIZE(cz_golden_common_all));
 547                 break;
 548         default:
 549                 break;
 550         }
 551 }
 552
 553 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
 554 {
 555         int i;
 556
 557         adev->gfx.scratch.num_reg = 7;
 558         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
 559         for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
 560                 adev->gfx.scratch.free[i] = true;
 561                 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
 562         }
 563 }
 564
 565 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
 566 {
 567         struct amdgpu_device *adev = ring->adev;
 568         uint32_t scratch;
 569         uint32_t tmp = 0;
 570         unsigned i;
 571         int r;
 572
 573         r = amdgpu_gfx_scratch_get(adev, &scratch);
 574         if (r) {
 575                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 576                 return r;
 577         }
 578         WREG32(scratch, 0xCAFEDEAD);
 579         r = amdgpu_ring_lock(ring, 3);
 580         if (r) {
 581                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 582                           ring->idx, r);
 583                 amdgpu_gfx_scratch_free(adev, scratch);
 584                 return r;
 585         }
 586         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 587         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 588         amdgpu_ring_write(ring, 0xDEADBEEF);
 589         amdgpu_ring_unlock_commit(ring);
 590
 591         for (i = 0; i < adev->usec_timeout; i++) {
 592                 tmp = RREG32(scratch);
 593                 if (tmp == 0xDEADBEEF)
 594                         break;
 595                 DRM_UDELAY(1);
 596         }
 597         if (i < adev->usec_timeout) {
 598                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 599                          ring->idx, i);
 600         } else {
 601                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 602                           ring->idx, scratch, tmp);
 603                 r = -EINVAL;
 604         }
 605         amdgpu_gfx_scratch_free(adev, scratch);
 606         return r;
 607 }
 608
 609 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
 610 {
 611         struct amdgpu_device *adev = ring->adev;
 612         struct amdgpu_ib ib;
 613         struct fence *f = NULL;
 614         uint32_t scratch;
 615         uint32_t tmp = 0;
 616         unsigned i;
 617         int r;
 618
 619         r = amdgpu_gfx_scratch_get(adev, &scratch);
 620         if (r) {
 621                 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
 622                 return r;
 623         }
 624         WREG32(scratch, 0xCAFEDEAD);
 625         memset(&ib, 0, sizeof(ib));
 626         r = amdgpu_ib_get(ring, NULL, 256, &ib);
 627         if (r) {
 628                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 629                 goto err1;
 630         }
 631         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
 632         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
 633         ib.ptr[2] = 0xDEADBEEF;
 634         ib.length_dw = 3;
 635
 636         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
 637                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
 638                                                  &f);
 639         if (r)
 640                 goto err2;
 641
 642         r = fence_wait(f, false);
 643         if (r) {
 644                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 645                 goto err2;
 646         }
 647         for (i = 0; i < adev->usec_timeout; i++) {
 648                 tmp = RREG32(scratch);
 649                 if (tmp == 0xDEADBEEF)
 650                         break;
 651                 DRM_UDELAY(1);
 652         }
 653         if (i < adev->usec_timeout) {
 654                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 655                          ring->idx, i);
 656                 goto err2;
 657         } else {
 658                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
 659                           scratch, tmp);
 660                 r = -EINVAL;
 661         }
 662 err2:
 663         fence_put(f);
 664         amdgpu_ib_free(adev, &ib);
 665 err1:
 666         amdgpu_gfx_scratch_free(adev, scratch);
 667         return r;
 668 }
 669
 670 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
 671 {
 672         const char *chip_name;
 673         char fw_name[30];
 674         int err;
 675         struct amdgpu_firmware_info *info = NULL;
 676         const struct common_firmware_header *header = NULL;
 677         const struct gfx_firmware_header_v1_0 *cp_hdr;
 678
 679         DRM_DEBUG("\n");
 680
 681         switch (adev->asic_type) {
 682         case CHIP_TOPAZ:
 683                 chip_name = "topaz";
 684                 break;
 685         case CHIP_TONGA:
 686                 chip_name = "tonga";
 687                 break;
 688         case CHIP_CARRIZO:
 689                 chip_name = "carrizo";
 690                 break;
 691         case CHIP_FIJI:
 692                 chip_name = "fiji";
 693                 break;
 694         default:
 695                 BUG();
 696         }
 697
 698         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 699         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 700         if (err)
 701                 goto out;
 702         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 703         if (err)
 704                 goto out;
 705         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 706         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 707         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 708
 709         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 710         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 711         if (err)
 712                 goto out;
 713         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 714         if (err)
 715                 goto out;
 716         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 717         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 718         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 719
 720         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 721         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 722         if (err)
 723                 goto out;
 724         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 725         if (err)
 726                 goto out;
 727         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 728         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 729         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 730
 731         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 732         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 733         if (err)
 734                 goto out;
 735         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 736         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
 737         adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 738         adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 739
 740         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 741         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 742         if (err)
 743                 goto out;
 744         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 745         if (err)
 746                 goto out;
 747         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 748         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 749         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 750
 751         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 752         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 753         if (!err) {
 754                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 755                 if (err)
 756                         goto out;
 757                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 758                                                 adev->gfx.mec2_fw->data;
 759                 adev->gfx.mec2_fw_version = le32_to_cpu(
 760                                                 cp_hdr->header.ucode_version);
 761                 adev->gfx.mec2_feature_version = le32_to_cpu(
 762                                                 cp_hdr->ucode_feature_version);
 763         } else {
 764                 err = 0;
 765                 adev->gfx.mec2_fw = NULL;
 766         }
 767
 768         if (adev->firmware.smu_load) {
 769                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 770                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 771                 info->fw = adev->gfx.pfp_fw;
 772                 header = (const struct common_firmware_header *)info->fw->data;
 773                 adev->firmware.fw_size +=
 774                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 775
 776                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 777                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 778                 info->fw = adev->gfx.me_fw;
 779                 header = (const struct common_firmware_header *)info->fw->data;
 780                 adev->firmware.fw_size +=
 781                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 782
 783                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 784                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 785                 info->fw = adev->gfx.ce_fw;
 786                 header = (const struct common_firmware_header *)info->fw->data;
 787                 adev->firmware.fw_size +=
 788                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 789
 790                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 791                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 792                 info->fw = adev->gfx.rlc_fw;
 793                 header = (const struct common_firmware_header *)info->fw->data;
 794                 adev->firmware.fw_size +=
 795                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 796
 797                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 798                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 799                 info->fw = adev->gfx.mec_fw;
 800                 header = (const struct common_firmware_header *)info->fw->data;
 801                 adev->firmware.fw_size +=
 802                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 803
 804                 if (adev->gfx.mec2_fw) {
 805                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 806                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 807                         info->fw = adev->gfx.mec2_fw;
 808                         header = (const struct common_firmware_header *)info->fw->data;
 809                         adev->firmware.fw_size +=
 810                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 811                 }
 812
 813         }
 814
 815 out:
 816         if (err) {
 817                 dev_err(adev->dev,
 818                         "gfx8: Failed to load firmware \"%s\"\n",
 819                         fw_name);
 820                 release_firmware(adev->gfx.pfp_fw);
 821                 adev->gfx.pfp_fw = NULL;
 822                 release_firmware(adev->gfx.me_fw);
 823                 adev->gfx.me_fw = NULL;
 824                 release_firmware(adev->gfx.ce_fw);
 825                 adev->gfx.ce_fw = NULL;
 826                 release_firmware(adev->gfx.rlc_fw);
 827                 adev->gfx.rlc_fw = NULL;
 828                 release_firmware(adev->gfx.mec_fw);
 829                 adev->gfx.mec_fw = NULL;
 830                 release_firmware(adev->gfx.mec2_fw);
 831                 adev->gfx.mec2_fw = NULL;
 832         }
 833         return err;
 834 }
 835
 836 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
 837 {
 838         int r;
 839
 840         if (adev->gfx.mec.hpd_eop_obj) {
 841                 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
 842                 if (unlikely(r != 0))
 843                         dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
 844                 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
 845                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 846
 847                 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
 848                 adev->gfx.mec.hpd_eop_obj = NULL;
 849         }
 850 }
 851
 852 #define MEC_HPD_SIZE 2048
 853
 854 static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
 855 {
 856         int r;
 857         u32 *hpd;
 858
 859         /*
 860          * we assign only 1 pipe because all other pipes will
 861          * be handled by KFD
 862          */
 863         adev->gfx.mec.num_mec = 1;
 864         adev->gfx.mec.num_pipe = 1;
 865         adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
 866
 867         if (adev->gfx.mec.hpd_eop_obj == NULL) {
 868                 r = amdgpu_bo_create(adev,
 869                                      adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
 870                                      PAGE_SIZE, true,
 871                                      AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
 872                                      &adev->gfx.mec.hpd_eop_obj);
 873                 if (r) {
 874                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 875                         return r;
 876                 }
 877         }
 878
 879         r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
 880         if (unlikely(r != 0)) {
 881                 gfx_v8_0_mec_fini(adev);
 882                 return r;
 883         }
 884         r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
 885                           &adev->gfx.mec.hpd_eop_gpu_addr);
 886         if (r) {
 887                 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
 888                 gfx_v8_0_mec_fini(adev);
 889                 return r;
 890         }
 891         r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
 892         if (r) {
 893                 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
 894                 gfx_v8_0_mec_fini(adev);
 895                 return r;
 896         }
 897
 898         memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
 899
 900         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 901         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 902
 903         return 0;
 904 }
 905
 906 static int gfx_v8_0_sw_init(void *handle)
 907 {
 908         int i, r;
 909         struct amdgpu_ring *ring;
 910         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 911
 912         /* EOP Event */
 913         r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
 914         if (r)
 915                 return r;
 916
 917         /* Privileged reg */
 918         r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
 919         if (r)
 920                 return r;
 921
 922         /* Privileged inst */
 923         r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
 924         if (r)
 925                 return r;
 926
 927         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
 928
 929         gfx_v8_0_scratch_init(adev);
 930
 931         r = gfx_v8_0_init_microcode(adev);
 932         if (r) {
 933                 DRM_ERROR("Failed to load gfx firmware!\n");
 934                 return r;
 935         }
 936
 937         r = gfx_v8_0_mec_init(adev);
 938         if (r) {
 939                 DRM_ERROR("Failed to init MEC BOs!\n");
 940                 return r;
 941         }
 942
 943         /* set up the gfx ring */
 944         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 945                 ring = &adev->gfx.gfx_ring[i];
 946                 ring->ring_obj = NULL;
 947                 sprintf(ring->name, "gfx");
 948                 /* no gfx doorbells on iceland */
 949                 if (adev->asic_type != CHIP_TOPAZ) {
 950                         ring->use_doorbell = true;
 951                         ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
 952                 }
 953
 954                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
 955                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
 956                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
 957                                      AMDGPU_RING_TYPE_GFX);
 958                 if (r)
 959                         return r;
 960         }
 961
 962         /* set up the compute queues */
 963         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 964                 unsigned irq_type;
 965
 966                 /* max 32 queues per MEC */
 967                 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
 968                         DRM_ERROR("Too many (%d) compute rings!\n", i);
 969                         break;
 970                 }
 971                 ring = &adev->gfx.compute_ring[i];
 972                 ring->ring_obj = NULL;
 973                 ring->use_doorbell = true;
 974                 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
 975                 ring->me = 1; /* first MEC */
 976                 ring->pipe = i / 8;
 977                 ring->queue = i % 8;
 978                 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
 979                 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
 980                 /* type-2 packets are deprecated on MEC, use type-3 instead */
 981                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
 982                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
 983                                      &adev->gfx.eop_irq, irq_type,
 984                                      AMDGPU_RING_TYPE_COMPUTE);
 985                 if (r)
 986                         return r;
 987         }
 988
 989         /* reserve GDS, GWS and OA resource for gfx */
 990         r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
 991                         PAGE_SIZE, true,
 992                         AMDGPU_GEM_DOMAIN_GDS, 0, NULL,
 993                         NULL, &adev->gds.gds_gfx_bo);
 994         if (r)
 995                 return r;
 996
 997         r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
 998                 PAGE_SIZE, true,
 999                 AMDGPU_GEM_DOMAIN_GWS, 0, NULL,
1000                 NULL, &adev->gds.gws_gfx_bo);
1001         if (r)
1002                 return r;
1003
1004         r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
1005                         PAGE_SIZE, true,
1006                         AMDGPU_GEM_DOMAIN_OA, 0, NULL,
1007                         NULL, &adev->gds.oa_gfx_bo);
1008         if (r)
1009                 return r;
1010
1011         adev->gfx.ce_ram_size = 0x8000;
1012
1013         return 0;
1014 }
1015
1016 static int gfx_v8_0_sw_fini(void *handle)
1017 {
1018         int i;
1019         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1020
1021         amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
1022         amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
1023         amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
1024
1025         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1026                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1027         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1028                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1029
1030         gfx_v8_0_mec_fini(adev);
1031
1032         return 0;
1033 }
1034
1035 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
1036 {
1037         const u32 num_tile_mode_states = 32;
1038         const u32 num_secondary_tile_mode_states = 16;
1039         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
1040
1041         switch (adev->gfx.config.mem_row_size_in_kb) {
1042         case 1:
1043                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1044                 break;
1045         case 2:
1046         default:
1047                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1048                 break;
1049         case 4:
1050                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1051                 break;
1052         }
1053
1054         switch (adev->asic_type) {
1055         case CHIP_TOPAZ:
1056                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1057                         switch (reg_offset) {
1058                         case 0:
1059                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1060                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1061                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1062                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1063                                 break;
1064                         case 1:
1065                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1066                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1067                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1068                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1069                                 break;
1070                         case 2:
1071                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1072                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1073                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1074                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1075                                 break;
1076                         case 3:
1077                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1078                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1079                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1080                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1081                                 break;
1082                         case 4:
1083                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1084                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1085                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1086                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1087                                 break;
1088                         case 5:
1089                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1090                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1091                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1092                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1093                                 break;
1094                         case 6:
1095                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1096                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1097                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1098                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1099                                 break;
1100                         case 8:
1101                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1102                                                 PIPE_CONFIG(ADDR_SURF_P2));
1103                                 break;
1104                         case 9:
1105                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1106                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1107                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1108                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1109                                 break;
1110                         case 10:
1111                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1112                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1113                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1114                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1115                                 break;
1116                         case 11:
1117                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1118                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1119                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1120                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1121                                 break;
1122                         case 13:
1123                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1124                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1125                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1126                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1127                                 break;
1128                         case 14:
1129                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1130                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1131                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1132                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1133                                 break;
1134                         case 15:
1135                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1136                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1137                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1138                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1139                                 break;
1140                         case 16:
1141                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1142                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1143                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1144                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1145                                 break;
1146                         case 18:
1147                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1148                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1149                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1150                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1151                                 break;
1152                         case 19:
1153                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1154                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1155                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1156                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1157                                 break;
1158                         case 20:
1159                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1160                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1161                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1162                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1163                                 break;
1164                         case 21:
1165                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1166                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1167                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1168                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1169                                 break;
1170                         case 22:
1171                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1172                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1173                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1174                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1175                                 break;
1176                         case 24:
1177                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1178                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1179                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1180                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1181                                 break;
1182                         case 25:
1183                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1184                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1185                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1186                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1187                                 break;
1188                         case 26:
1189                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1190                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1191                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1192                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1193                                 break;
1194                         case 27:
1195                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1196                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1197                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1198                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1199                                 break;
1200                         case 28:
1201                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1202                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1203                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1204                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1205                                 break;
1206                         case 29:
1207                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1208                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1209                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1210                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1211                                 break;
1212                         case 7:
1213                         case 12:
1214                         case 17:
1215                         case 23:
1216                                 /* unused idx */
1217                                 continue;
1218                         default:
1219                                 gb_tile_moden = 0;
1220                                 break;
1221                         };
1222                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1223                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1224                 }
1225                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1226                         switch (reg_offset) {
1227                         case 0:
1228                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1229                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1230                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1231                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1232                                 break;
1233                         case 1:
1234                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1235                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1236                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1237                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1238                                 break;
1239                         case 2:
1240                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1241                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1242                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1243                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1244                                 break;
1245                         case 3:
1246                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1247                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1248                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1249                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1250                                 break;
1251                         case 4:
1252                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1253                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1254                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1255                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1256                                 break;
1257                         case 5:
1258                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1259                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1260                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1261                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1262                                 break;
1263                         case 6:
1264                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1265                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1266                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1267                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1268                                 break;
1269                         case 8:
1270                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1271                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1272                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1273                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1274                                 break;
1275                         case 9:
1276                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1277                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1278                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1279                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1280                                 break;
1281                         case 10:
1282                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1283                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1284                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1285                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1286                                 break;
1287                         case 11:
1288                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1289                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1290                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1291                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1292                                 break;
1293                         case 12:
1294                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1295                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1296                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1297                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1298                                 break;
1299                         case 13:
1300                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1301                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1302                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1303                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1304                                 break;
1305                         case 14:
1306                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1307                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1308                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1309                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1310                                 break;
1311                         case 7:
1312                                 /* unused idx */
1313                                 continue;
1314                         default:
1315                                 gb_tile_moden = 0;
1316                                 break;
1317                         };
1318                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1319                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1320                 }
1321         case CHIP_FIJI:
1322         case CHIP_TONGA:
1323                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1324                         switch (reg_offset) {
1325                         case 0:
1326                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1327                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1328                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1329                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1330                                 break;
1331                         case 1:
1332                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1333                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1334                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1335                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1336                                 break;
1337                         case 2:
1338                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1339                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1340                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1341                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1342                                 break;
1343                         case 3:
1344                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1345                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1346                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1347                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1348                                 break;
1349                         case 4:
1350                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1351                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1352                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1353                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1354                                 break;
1355                         case 5:
1356                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1357                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1358                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1359                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1360                                 break;
1361                         case 6:
1362                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1363                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1364                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1365                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1366                                 break;
1367                         case 7:
1368                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1369                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1370                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1371                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1372                                 break;
1373                         case 8:
1374                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1375                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
1376                                 break;
1377                         case 9:
1378                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1379                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1380                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1381                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1382                                 break;
1383                         case 10:
1384                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1385                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1386                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1387                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1388                                 break;
1389                         case 11:
1390                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1391                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1392                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1393                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1394                                 break;
1395                         case 12:
1396                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1397                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1398                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1399                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1400                                 break;
1401                         case 13:
1402                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1403                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1404                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1405                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1406                                 break;
1407                         case 14:
1408                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1409                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1410                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1411                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1412                                 break;
1413                         case 15:
1414                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1415                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1416                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1417                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1418                                 break;
1419                         case 16:
1420                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1421                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1422                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1423                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1424                                 break;
1425                         case 17:
1426                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1427                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1428                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1429                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1430                                 break;
1431                         case 18:
1432                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1433                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1434                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1435                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1436                                 break;
1437                         case 19:
1438                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1439                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1440                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1441                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1442                                 break;
1443                         case 20:
1444                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1445                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1446                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1447                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1448                                 break;
1449                         case 21:
1450                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1451                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1452                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1453                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1454                                 break;
1455                         case 22:
1456                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1457                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1458                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1459                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1460                                 break;
1461                         case 23:
1462                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1463                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1464                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1465                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1466                                 break;
1467                         case 24:
1468                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1469                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1470                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1471                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1472                                 break;
1473                         case 25:
1474                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1475                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1476                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1477                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1478                                 break;
1479                         case 26:
1480                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1481                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1482                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1483                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1484                                 break;
1485                         case 27:
1486                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1487                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1488                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1489                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1490                                 break;
1491                         case 28:
1492                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1493                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1494                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1495                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1496                                 break;
1497                         case 29:
1498                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1499                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1500                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1501                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1502                                 break;
1503                         case 30:
1504                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1505                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1506                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1507                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1508                                 break;
1509                         default:
1510                                 gb_tile_moden = 0;
1511                                 break;
1512                         };
1513                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1514                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1515                 }
1516                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1517                         switch (reg_offset) {
1518                         case 0:
1519                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1520                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1521                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1522                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1523                                 break;
1524                         case 1:
1525                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1526                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1527                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1528                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1529                                 break;
1530                         case 2:
1531                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1532                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1533                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1534                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1535                                 break;
1536                         case 3:
1537                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1538                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1539                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1540                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1541                                 break;
1542                         case 4:
1543                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1544                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1545                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1546                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1547                                 break;
1548                         case 5:
1549                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1550                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1551                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1552                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1553                                 break;
1554                         case 6:
1555                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1556                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1557                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1558                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1559                                 break;
1560                         case 8:
1561                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1562                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1563                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1564                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1565                                 break;
1566                         case 9:
1567                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1568                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1569                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1570                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1571                                 break;
1572                         case 10:
1573                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1574                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1575                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1576                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1577                                 break;
1578                         case 11:
1579                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1580                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1581                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1582                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1583                                 break;
1584                         case 12:
1585                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1586                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1587                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1588                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1589                                 break;
1590                         case 13:
1591                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1592                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1593                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1594                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1595                                 break;
1596                         case 14:
1597                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1598                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1599                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1600                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1601                                 break;
1602                         case 7:
1603                                 /* unused idx */
1604                                 continue;
1605                         default:
1606                                 gb_tile_moden = 0;
1607                                 break;
1608                         };
1609                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1610                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1611                 }
1612                 break;
1613         case CHIP_CARRIZO:
1614         default:
1615                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1616                         switch (reg_offset) {
1617                         case 0:
1618                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1619                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1620                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1621                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1622                                 break;
1623                         case 1:
1624                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1625                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1626                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1627                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1628                                 break;
1629                         case 2:
1630                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1631                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1632                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1633                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1634                                 break;
1635                         case 3:
1636                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1637                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1638                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1639                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1640                                 break;
1641                         case 4:
1642                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1643                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1644                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1645                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1646                                 break;
1647                         case 5:
1648                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1649                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1650                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1651                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1652                                 break;
1653                         case 6:
1654                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1655                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1656                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1657                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1658                                 break;
1659                         case 8:
1660                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1661                                                 PIPE_CONFIG(ADDR_SURF_P2));
1662                                 break;
1663                         case 9:
1664                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1665                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1666                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1667                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1668                                 break;
1669                         case 10:
1670                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1671                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1672                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1673                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1674                                 break;
1675                         case 11:
1676                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1677                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1678                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1679                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1680                                 break;
1681                         case 13:
1682                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1683                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1684                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1685                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1686                                 break;
1687                         case 14:
1688                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1689                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1690                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1691                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1692                                 break;
1693                         case 15:
1694                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1695                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1696                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1697                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1698                                 break;
1699                         case 16:
1700                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1701                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1702                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1703                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1704                                 break;
1705                         case 18:
1706                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1707                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1708                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1709                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1710                                 break;
1711                         case 19:
1712                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1713                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1714                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1715                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1716                                 break;
1717                         case 20:
1718                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1719                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1720                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1721                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1722                                 break;
1723                         case 21:
1724                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1725                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1726                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1727                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1728                                 break;
1729                         case 22:
1730                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1731                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1732                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1733                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1734                                 break;
1735                         case 24:
1736                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1737                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1738                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1739                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1740                                 break;
1741                         case 25:
1742                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1743                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1744                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1745                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1746                                 break;
1747                         case 26:
1748                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1749                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1750                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1751                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1752                                 break;
1753                         case 27:
1754                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1755                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1756                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1757                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1758                                 break;
1759                         case 28:
1760                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1761                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1762                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1763                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1764                                 break;
1765                         case 29:
1766                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1767                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1768                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1769                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1770                                 break;
1771                         case 7:
1772                         case 12:
1773                         case 17:
1774                         case 23:
1775                                 /* unused idx */
1776                                 continue;
1777                         default:
1778                                 gb_tile_moden = 0;
1779                                 break;
1780                         };
1781                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1782                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1783                 }
1784                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1785                         switch (reg_offset) {
1786                         case 0:
1787                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1788                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1789                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1790                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1791                                 break;
1792                         case 1:
1793                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1794                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1795                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1796                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1797                                 break;
1798                         case 2:
1799                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1800                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1801                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1802                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1803                                 break;
1804                         case 3:
1805                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1806                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1807                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1808                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1809                                 break;
1810                         case 4:
1811                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1812                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1813                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1814                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1815                                 break;
1816                         case 5:
1817                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1818                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1819                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1820                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1821                                 break;
1822                         case 6:
1823                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1824                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1825                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1826                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1827                                 break;
1828                         case 8:
1829                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1830                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1831                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1832                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1833                                 break;
1834                         case 9:
1835                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1836                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1837                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1838                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1839                                 break;
1840                         case 10:
1841                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1842                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1843                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1844                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1845                                 break;
1846                         case 11:
1847                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1848                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1849                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1850                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1851                                 break;
1852                         case 12:
1853                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1854                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1855                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1856                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1857                                 break;
1858                         case 13:
1859                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1860                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1861                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1862                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1863                                 break;
1864                         case 14:
1865                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1866                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1867                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1868                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1869                                 break;
1870                         case 7:
1871                                 /* unused idx */
1872                                 continue;
1873                         default:
1874                                 gb_tile_moden = 0;
1875                                 break;
1876                         };
1877                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1878                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1879                 }
1880         }
1881 }
1882
1883 static u32 gfx_v8_0_create_bitmask(u32 bit_width)
1884 {
1885         u32 i, mask = 0;
1886
1887         for (i = 0; i < bit_width; i++) {
1888                 mask <<= 1;
1889                 mask |= 1;
1890         }
1891         return mask;
1892 }
1893
1894 void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1895 {
1896         u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1897
1898         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1899                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1900                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1901         } else if (se_num == 0xffffffff) {
1902                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1903                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1904         } else if (sh_num == 0xffffffff) {
1905                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1906                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1907         } else {
1908                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1909                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1910         }
1911         WREG32(mmGRBM_GFX_INDEX, data);
1912 }
1913
1914 static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
1915                                     u32 max_rb_num_per_se,
1916                                     u32 sh_per_se)
1917 {
1918         u32 data, mask;
1919
1920         data = RREG32(mmCC_RB_BACKEND_DISABLE);
1921         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1922
1923         data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1924
1925         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1926
1927         mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se);
1928
1929         return data & mask;
1930 }
1931
1932 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
1933                               u32 se_num, u32 sh_per_se,
1934                               u32 max_rb_num_per_se)
1935 {
1936         int i, j;
1937         u32 data, mask;
1938         u32 disabled_rbs = 0;
1939         u32 enabled_rbs = 0;
1940
1941         mutex_lock(&adev->grbm_idx_mutex);
1942         for (i = 0; i < se_num; i++) {
1943                 for (j = 0; j < sh_per_se; j++) {
1944                         gfx_v8_0_select_se_sh(adev, i, j);
1945                         data = gfx_v8_0_get_rb_disabled(adev,
1946                                               max_rb_num_per_se, sh_per_se);
1947                         disabled_rbs |= data << ((i * sh_per_se + j) *
1948                                                  RB_BITMAP_WIDTH_PER_SH);
1949                 }
1950         }
1951         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1952         mutex_unlock(&adev->grbm_idx_mutex);
1953
1954         mask = 1;
1955         for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1956                 if (!(disabled_rbs & mask))
1957                         enabled_rbs |= mask;
1958                 mask <<= 1;
1959         }
1960
1961         adev->gfx.config.backend_enable_mask = enabled_rbs;
1962
1963         mutex_lock(&adev->grbm_idx_mutex);
1964         for (i = 0; i < se_num; i++) {
1965                 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
1966                 data = 0;
1967                 for (j = 0; j < sh_per_se; j++) {
1968                         switch (enabled_rbs & 3) {
1969                         case 0:
1970                                 if (j == 0)
1971                                         data |= (RASTER_CONFIG_RB_MAP_3 <<
1972                                                  PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1973                                 else
1974                                         data |= (RASTER_CONFIG_RB_MAP_0 <<
1975                                                  PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1976                                 break;
1977                         case 1:
1978                                 data |= (RASTER_CONFIG_RB_MAP_0 <<
1979                                          (i * sh_per_se + j) * 2);
1980                                 break;
1981                         case 2:
1982                                 data |= (RASTER_CONFIG_RB_MAP_3 <<
1983                                          (i * sh_per_se + j) * 2);
1984                                 break;
1985                         case 3:
1986                         default:
1987                                 data |= (RASTER_CONFIG_RB_MAP_2 <<
1988                                          (i * sh_per_se + j) * 2);
1989                                 break;
1990                         }
1991                         enabled_rbs >>= 2;
1992                 }
1993                 WREG32(mmPA_SC_RASTER_CONFIG, data);
1994         }
1995         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1996         mutex_unlock(&adev->grbm_idx_mutex);
1997 }
1998
1999 /**
2000  * gfx_v8_0_init_compute_vmid - gart enable
2001  *
2002  * @rdev: amdgpu_device pointer
2003  *
2004  * Initialize compute vmid sh_mem registers
2005  *
2006  */
2007 #define DEFAULT_SH_MEM_BASES    (0x6000)
2008 #define FIRST_COMPUTE_VMID      (8)
2009 #define LAST_COMPUTE_VMID       (16)
2010 static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
2011 {
2012         int i;
2013         uint32_t sh_mem_config;
2014         uint32_t sh_mem_bases;
2015
2016         /*
2017          * Configure apertures:
2018          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
2019          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
2020          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
2021          */
2022         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
2023
2024         sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
2025                         SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
2026                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
2027                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
2028                         MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
2029                         SH_MEM_CONFIG__PRIVATE_ATC_MASK;
2030
2031         mutex_lock(&adev->srbm_mutex);
2032         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
2033                 vi_srbm_select(adev, 0, 0, 0, i);
2034                 /* CP and shaders */
2035                 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
2036                 WREG32(mmSH_MEM_APE1_BASE, 1);
2037                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2038                 WREG32(mmSH_MEM_BASES, sh_mem_bases);
2039         }
2040         vi_srbm_select(adev, 0, 0, 0, 0);
2041         mutex_unlock(&adev->srbm_mutex);
2042 }
2043
2044 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
2045 {
2046         u32 gb_addr_config;
2047         u32 mc_shared_chmap, mc_arb_ramcfg;
2048         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
2049         u32 tmp;
2050         int i;
2051
2052         switch (adev->asic_type) {
2053         case CHIP_TOPAZ:
2054                 adev->gfx.config.max_shader_engines = 1;
2055                 adev->gfx.config.max_tile_pipes = 2;
2056                 adev->gfx.config.max_cu_per_sh = 6;
2057                 adev->gfx.config.max_sh_per_se = 1;
2058                 adev->gfx.config.max_backends_per_se = 2;
2059                 adev->gfx.config.max_texture_channel_caches = 2;
2060                 adev->gfx.config.max_gprs = 256;
2061                 adev->gfx.config.max_gs_threads = 32;
2062                 adev->gfx.config.max_hw_contexts = 8;
2063
2064                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2065                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2066                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2067                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2068                 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
2069                 break;
2070         case CHIP_FIJI:
2071                 adev->gfx.config.max_shader_engines = 4;
2072                 adev->gfx.config.max_tile_pipes = 16;
2073                 adev->gfx.config.max_cu_per_sh = 16;
2074                 adev->gfx.config.max_sh_per_se = 1;
2075                 adev->gfx.config.max_backends_per_se = 4;
2076                 adev->gfx.config.max_texture_channel_caches = 8;
2077                 adev->gfx.config.max_gprs = 256;
2078                 adev->gfx.config.max_gs_threads = 32;
2079                 adev->gfx.config.max_hw_contexts = 8;
2080
2081                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2082                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2083                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2084                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2085                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2086                 break;
2087         case CHIP_TONGA:
2088                 adev->gfx.config.max_shader_engines = 4;
2089                 adev->gfx.config.max_tile_pipes = 8;
2090                 adev->gfx.config.max_cu_per_sh = 8;
2091                 adev->gfx.config.max_sh_per_se = 1;
2092                 adev->gfx.config.max_backends_per_se = 2;
2093                 adev->gfx.config.max_texture_channel_caches = 8;
2094                 adev->gfx.config.max_gprs = 256;
2095                 adev->gfx.config.max_gs_threads = 32;
2096                 adev->gfx.config.max_hw_contexts = 8;
2097
2098                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2099                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2100                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2101                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2102                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2103                 break;
2104         case CHIP_CARRIZO:
2105                 adev->gfx.config.max_shader_engines = 1;
2106                 adev->gfx.config.max_tile_pipes = 2;
2107                 adev->gfx.config.max_sh_per_se = 1;
2108                 adev->gfx.config.max_backends_per_se = 2;
2109
2110                 switch (adev->pdev->revision) {
2111                 case 0xc4:
2112                 case 0x84:
2113                 case 0xc8:
2114                 case 0xcc:
2115                         /* B10 */
2116                         adev->gfx.config.max_cu_per_sh = 8;
2117                         break;
2118                 case 0xc5:
2119                 case 0x81:
2120                 case 0x85:
2121                 case 0xc9:
2122                 case 0xcd:
2123                         /* B8 */
2124                         adev->gfx.config.max_cu_per_sh = 6;
2125                         break;
2126                 case 0xc6:
2127                 case 0xca:
2128                 case 0xce:
2129                         /* B6 */
2130                         adev->gfx.config.max_cu_per_sh = 6;
2131                         break;
2132                 case 0xc7:
2133                 case 0x87:
2134                 case 0xcb:
2135                 default:
2136                         /* B4 */
2137                         adev->gfx.config.max_cu_per_sh = 4;
2138                         break;
2139                 }
2140
2141                 adev->gfx.config.max_texture_channel_caches = 2;
2142                 adev->gfx.config.max_gprs = 256;
2143                 adev->gfx.config.max_gs_threads = 32;
2144                 adev->gfx.config.max_hw_contexts = 8;
2145
2146                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2147                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2148                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2149                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2150                 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
2151                 break;
2152         default:
2153                 adev->gfx.config.max_shader_engines = 2;
2154                 adev->gfx.config.max_tile_pipes = 4;
2155                 adev->gfx.config.max_cu_per_sh = 2;
2156                 adev->gfx.config.max_sh_per_se = 1;
2157                 adev->gfx.config.max_backends_per_se = 2;
2158                 adev->gfx.config.max_texture_channel_caches = 4;
2159                 adev->gfx.config.max_gprs = 256;
2160                 adev->gfx.config.max_gs_threads = 32;
2161                 adev->gfx.config.max_hw_contexts = 8;
2162
2163                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2164                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2165                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2166                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2167                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2168                 break;
2169         }
2170
2171         tmp = RREG32(mmGRBM_CNTL);
2172         tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
2173         WREG32(mmGRBM_CNTL, tmp);
2174
2175         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
2176         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
2177         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
2178
2179         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
2180         adev->gfx.config.mem_max_burst_length_bytes = 256;
2181         if (adev->flags & AMD_IS_APU) {
2182                 /* Get memory bank mapping mode. */
2183                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
2184                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2185                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2186
2187                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
2188                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2189                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2190
2191                 /* Validate settings in case only one DIMM installed. */
2192                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
2193                         dimm00_addr_map = 0;
2194                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
2195                         dimm01_addr_map = 0;
2196                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
2197                         dimm10_addr_map = 0;
2198                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
2199                         dimm11_addr_map = 0;
2200
2201                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
2202                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
2203                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
2204                         adev->gfx.config.mem_row_size_in_kb = 2;
2205                 else
2206                         adev->gfx.config.mem_row_size_in_kb = 1;
2207         } else {
2208                 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
2209                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
2210                 if (adev->gfx.config.mem_row_size_in_kb > 4)
2211                         adev->gfx.config.mem_row_size_in_kb = 4;
2212         }
2213
2214         adev->gfx.config.shader_engine_tile_size = 32;
2215         adev->gfx.config.num_gpus = 1;
2216         adev->gfx.config.multi_gpu_tile_size = 64;
2217
2218         /* fix up row size */
2219         switch (adev->gfx.config.mem_row_size_in_kb) {
2220         case 1:
2221         default:
2222                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
2223                 break;
2224         case 2:
2225                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
2226                 break;
2227         case 4:
2228                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
2229                 break;
2230         }
2231         adev->gfx.config.gb_addr_config = gb_addr_config;
2232
2233         WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
2234         WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
2235         WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
2236         WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
2237                gb_addr_config & 0x70);
2238         WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
2239                gb_addr_config & 0x70);
2240         WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
2241         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
2242         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2243
2244         gfx_v8_0_tiling_mode_table_init(adev);
2245
2246         gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
2247                                  adev->gfx.config.max_sh_per_se,
2248                                  adev->gfx.config.max_backends_per_se);
2249
2250         /* XXX SH_MEM regs */
2251         /* where to put LDS, scratch, GPUVM in FSA64 space */
2252         mutex_lock(&adev->srbm_mutex);
2253         for (i = 0; i < 16; i++) {
2254                 vi_srbm_select(adev, 0, 0, 0, i);
2255                 /* CP and shaders */
2256                 if (i == 0) {
2257                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
2258                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
2259                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2260                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2261                         WREG32(mmSH_MEM_CONFIG, tmp);
2262                 } else {
2263                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
2264                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
2265                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2266                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2267                         WREG32(mmSH_MEM_CONFIG, tmp);
2268                 }
2269
2270                 WREG32(mmSH_MEM_APE1_BASE, 1);
2271                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2272                 WREG32(mmSH_MEM_BASES, 0);
2273         }
2274         vi_srbm_select(adev, 0, 0, 0, 0);
2275         mutex_unlock(&adev->srbm_mutex);
2276
2277         gfx_v8_0_init_compute_vmid(adev);
2278
2279         mutex_lock(&adev->grbm_idx_mutex);
2280         /*
2281          * making sure that the following register writes will be broadcasted
2282          * to all the shaders
2283          */
2284         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2285
2286         WREG32(mmPA_SC_FIFO_SIZE,
2287                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
2288                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2289                    (adev->gfx.config.sc_prim_fifo_size_backend <<
2290                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2291                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
2292                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2293                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
2294                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
2295         mutex_unlock(&adev->grbm_idx_mutex);
2296
2297 }
2298
2299 static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2300 {
2301         u32 i, j, k;
2302         u32 mask;
2303
2304         mutex_lock(&adev->grbm_idx_mutex);
2305         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2306                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2307                         gfx_v8_0_select_se_sh(adev, i, j);
2308                         for (k = 0; k < adev->usec_timeout; k++) {
2309                                 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2310                                         break;
2311                                 udelay(1);
2312                         }
2313                 }
2314         }
2315         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2316         mutex_unlock(&adev->grbm_idx_mutex);
2317
2318         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2319                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2320                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2321                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2322         for (k = 0; k < adev->usec_timeout; k++) {
2323                 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2324                         break;
2325                 udelay(1);
2326         }
2327 }
2328
2329 static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2330                                                bool enable)
2331 {
2332         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2333
2334         if (enable) {
2335                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1);
2336                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1);
2337                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1);
2338                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1);
2339         } else {
2340                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0);
2341                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0);
2342                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0);
2343                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0);
2344         }
2345         WREG32(mmCP_INT_CNTL_RING0, tmp);
2346 }
2347
2348 void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
2349 {
2350         u32 tmp = RREG32(mmRLC_CNTL);
2351
2352         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2353         WREG32(mmRLC_CNTL, tmp);
2354
2355         gfx_v8_0_enable_gui_idle_interrupt(adev, false);
2356
2357         gfx_v8_0_wait_for_rlc_serdes(adev);
2358 }
2359
2360 static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
2361 {
2362         u32 tmp = RREG32(mmGRBM_SOFT_RESET);
2363
2364         tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2365         WREG32(mmGRBM_SOFT_RESET, tmp);
2366         udelay(50);
2367         tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2368         WREG32(mmGRBM_SOFT_RESET, tmp);
2369         udelay(50);
2370 }
2371
2372 static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
2373 {
2374         u32 tmp = RREG32(mmRLC_CNTL);
2375
2376         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
2377         WREG32(mmRLC_CNTL, tmp);
2378
2379         /* carrizo do enable cp interrupt after cp inited */
2380         if (adev->asic_type != CHIP_CARRIZO)
2381                 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
2382
2383         udelay(50);
2384 }
2385
2386 static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
2387 {
2388         const struct rlc_firmware_header_v2_0 *hdr;
2389         const __le32 *fw_data;
2390         unsigned i, fw_size;
2391
2392         if (!adev->gfx.rlc_fw)
2393                 return -EINVAL;
2394
2395         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2396         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2397
2398         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2399                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2400         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2401
2402         WREG32(mmRLC_GPM_UCODE_ADDR, 0);
2403         for (i = 0; i < fw_size; i++)
2404                 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2405         WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2406
2407         return 0;
2408 }
2409
2410 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
2411 {
2412         int r;
2413
2414         gfx_v8_0_rlc_stop(adev);
2415
2416         /* disable CG */
2417         WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
2418
2419         /* disable PG */
2420         WREG32(mmRLC_PG_CNTL, 0);
2421
2422         gfx_v8_0_rlc_reset(adev);
2423
2424         if (!adev->firmware.smu_load) {
2425                 /* legacy rlc firmware loading */
2426                 r = gfx_v8_0_rlc_load_microcode(adev);
2427                 if (r)
2428                         return r;
2429         } else {
2430                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
2431                                                 AMDGPU_UCODE_ID_RLC_G);
2432                 if (r)
2433                         return -EINVAL;
2434         }
2435
2436         gfx_v8_0_rlc_start(adev);
2437
2438         return 0;
2439 }
2440
2441 static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2442 {
2443         int i;
2444         u32 tmp = RREG32(mmCP_ME_CNTL);
2445
2446         if (enable) {
2447                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
2448                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
2449                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
2450         } else {
2451                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
2452                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
2453                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
2454                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2455                         adev->gfx.gfx_ring[i].ready = false;
2456         }
2457         WREG32(mmCP_ME_CNTL, tmp);
2458         udelay(50);
2459 }
2460
2461 static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2462 {
2463         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2464         const struct gfx_firmware_header_v1_0 *ce_hdr;
2465         const struct gfx_firmware_header_v1_0 *me_hdr;
2466         const __le32 *fw_data;
2467         unsigned i, fw_size;
2468
2469         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2470                 return -EINVAL;
2471
2472         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2473                 adev->gfx.pfp_fw->data;
2474         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2475                 adev->gfx.ce_fw->data;
2476         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2477                 adev->gfx.me_fw->data;
2478
2479         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2480         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2481         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2482
2483         gfx_v8_0_cp_gfx_enable(adev, false);
2484
2485         /* PFP */
2486         fw_data = (const __le32 *)
2487                 (adev->gfx.pfp_fw->data +
2488                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2489         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2490         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2491         for (i = 0; i < fw_size; i++)
2492                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2493         WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2494
2495         /* CE */
2496         fw_data = (const __le32 *)
2497                 (adev->gfx.ce_fw->data +
2498                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2499         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2500         WREG32(mmCP_CE_UCODE_ADDR, 0);
2501         for (i = 0; i < fw_size; i++)
2502                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2503         WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2504
2505         /* ME */
2506         fw_data = (const __le32 *)
2507                 (adev->gfx.me_fw->data +
2508                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2509         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2510         WREG32(mmCP_ME_RAM_WADDR, 0);
2511         for (i = 0; i < fw_size; i++)
2512                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2513         WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2514
2515         return 0;
2516 }
2517
2518 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
2519 {
2520         u32 count = 0;
2521         const struct cs_section_def *sect = NULL;
2522         const struct cs_extent_def *ext = NULL;
2523
2524         /* begin clear state */
2525         count += 2;
2526         /* context control state */
2527         count += 3;
2528
2529         for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2530                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2531                         if (sect->id == SECT_CONTEXT)
2532                                 count += 2 + ext->reg_count;
2533                         else
2534                                 return 0;
2535                 }
2536         }
2537         /* pa_sc_raster_config/pa_sc_raster_config1 */
2538         count += 4;
2539         /* end clear state */
2540         count += 2;
2541         /* clear state */
2542         count += 2;
2543
2544         return count;
2545 }
2546
2547 static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
2548 {
2549         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2550         const struct cs_section_def *sect = NULL;
2551         const struct cs_extent_def *ext = NULL;
2552         int r, i;
2553
2554         /* init the CP */
2555         WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2556         WREG32(mmCP_ENDIAN_SWAP, 0);
2557         WREG32(mmCP_DEVICE_ID, 1);
2558
2559         gfx_v8_0_cp_gfx_enable(adev, true);
2560
2561         r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4);
2562         if (r) {
2563                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2564                 return r;
2565         }
2566
2567         /* clear state buffer */
2568         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2569         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2570
2571         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2572         amdgpu_ring_write(ring, 0x80000000);
2573         amdgpu_ring_write(ring, 0x80000000);
2574
2575         for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2576                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2577                         if (sect->id == SECT_CONTEXT) {
2578                                 amdgpu_ring_write(ring,
2579                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2580                                                ext->reg_count));
2581                                 amdgpu_ring_write(ring,
2582                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2583                                 for (i = 0; i < ext->reg_count; i++)
2584                                         amdgpu_ring_write(ring, ext->extent[i]);
2585                         }
2586                 }
2587         }
2588
2589         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2590         amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2591         switch (adev->asic_type) {
2592         case CHIP_TONGA:
2593         case CHIP_FIJI:
2594                 amdgpu_ring_write(ring, 0x16000012);
2595                 amdgpu_ring_write(ring, 0x0000002A);
2596                 break;
2597         case CHIP_TOPAZ:
2598         case CHIP_CARRIZO:
2599                 amdgpu_ring_write(ring, 0x00000002);
2600                 amdgpu_ring_write(ring, 0x00000000);
2601                 break;
2602         default:
2603                 BUG();
2604         }
2605
2606         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2607         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2608
2609         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2610         amdgpu_ring_write(ring, 0);
2611
2612         /* init the CE partitions */
2613         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2614         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2615         amdgpu_ring_write(ring, 0x8000);
2616         amdgpu_ring_write(ring, 0x8000);
2617
2618         amdgpu_ring_unlock_commit(ring);
2619
2620         return 0;
2621 }
2622
2623 static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
2624 {
2625         struct amdgpu_ring *ring;
2626         u32 tmp;
2627         u32 rb_bufsz;
2628         u64 rb_addr, rptr_addr;
2629         int r;
2630
2631         /* Set the write pointer delay */
2632         WREG32(mmCP_RB_WPTR_DELAY, 0);
2633
2634         /* set the RB to use vmid 0 */
2635         WREG32(mmCP_RB_VMID, 0);
2636
2637         /* Set ring buffer size */
2638         ring = &adev->gfx.gfx_ring[0];
2639         rb_bufsz = order_base_2(ring->ring_size / 8);
2640         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2641         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2642         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
2643         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
2644 #ifdef __BIG_ENDIAN
2645         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2646 #endif
2647         WREG32(mmCP_RB0_CNTL, tmp);
2648
2649         /* Initialize the ring buffer's read and write pointers */
2650         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2651         ring->wptr = 0;
2652         WREG32(mmCP_RB0_WPTR, ring->wptr);
2653
2654         /* set the wb address wether it's enabled or not */
2655         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2656         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2657         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2658
2659         mdelay(1);
2660         WREG32(mmCP_RB0_CNTL, tmp);
2661
2662         rb_addr = ring->gpu_addr >> 8;
2663         WREG32(mmCP_RB0_BASE, rb_addr);
2664         WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2665
2666         /* no gfx doorbells on iceland */
2667         if (adev->asic_type != CHIP_TOPAZ) {
2668                 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
2669                 if (ring->use_doorbell) {
2670                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2671                                             DOORBELL_OFFSET, ring->doorbell_index);
2672                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2673                                             DOORBELL_EN, 1);
2674                 } else {
2675                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2676                                             DOORBELL_EN, 0);
2677                 }
2678                 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
2679
2680                 if (adev->asic_type == CHIP_TONGA) {
2681                         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2682                                             DOORBELL_RANGE_LOWER,
2683                                             AMDGPU_DOORBELL_GFX_RING0);
2684                         WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2685
2686                         WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
2687                                CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2688                 }
2689
2690         }
2691
2692         /* start the ring */
2693         gfx_v8_0_cp_gfx_start(adev);
2694         ring->ready = true;
2695         r = amdgpu_ring_test_ring(ring);
2696         if (r) {
2697                 ring->ready = false;
2698                 return r;
2699         }
2700
2701         return 0;
2702 }
2703
2704 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2705 {
2706         int i;
2707
2708         if (enable) {
2709                 WREG32(mmCP_MEC_CNTL, 0);
2710         } else {
2711                 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2712                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2713                         adev->gfx.compute_ring[i].ready = false;
2714         }
2715         udelay(50);
2716 }
2717
2718 static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
2719 {
2720         gfx_v8_0_cp_compute_enable(adev, true);
2721
2722         return 0;
2723 }
2724
2725 static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2726 {
2727         const struct gfx_firmware_header_v1_0 *mec_hdr;
2728         const __le32 *fw_data;
2729         unsigned i, fw_size;
2730
2731         if (!adev->gfx.mec_fw)
2732                 return -EINVAL;
2733
2734         gfx_v8_0_cp_compute_enable(adev, false);
2735
2736         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2737         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2738
2739         fw_data = (const __le32 *)
2740                 (adev->gfx.mec_fw->data +
2741                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2742         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2743
2744         /* MEC1 */
2745         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2746         for (i = 0; i < fw_size; i++)
2747                 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
2748         WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2749
2750         /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2751         if (adev->gfx.mec2_fw) {
2752                 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2753
2754                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2755                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2756
2757                 fw_data = (const __le32 *)
2758                         (adev->gfx.mec2_fw->data +
2759                          le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2760                 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2761
2762                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2763                 for (i = 0; i < fw_size; i++)
2764                         WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
2765                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
2766         }
2767
2768         return 0;
2769 }
2770
2771 struct vi_mqd {
2772         uint32_t header;  /* ordinal0 */
2773         uint32_t compute_dispatch_initiator;  /* ordinal1 */
2774         uint32_t compute_dim_x;  /* ordinal2 */
2775         uint32_t compute_dim_y;  /* ordinal3 */
2776         uint32_t compute_dim_z;  /* ordinal4 */
2777         uint32_t compute_start_x;  /* ordinal5 */
2778         uint32_t compute_start_y;  /* ordinal6 */
2779         uint32_t compute_start_z;  /* ordinal7 */
2780         uint32_t compute_num_thread_x;  /* ordinal8 */
2781         uint32_t compute_num_thread_y;  /* ordinal9 */
2782         uint32_t compute_num_thread_z;  /* ordinal10 */
2783         uint32_t compute_pipelinestat_enable;  /* ordinal11 */
2784         uint32_t compute_perfcount_enable;  /* ordinal12 */
2785         uint32_t compute_pgm_lo;  /* ordinal13 */
2786         uint32_t compute_pgm_hi;  /* ordinal14 */
2787         uint32_t compute_tba_lo;  /* ordinal15 */
2788         uint32_t compute_tba_hi;  /* ordinal16 */
2789         uint32_t compute_tma_lo;  /* ordinal17 */
2790         uint32_t compute_tma_hi;  /* ordinal18 */
2791         uint32_t compute_pgm_rsrc1;  /* ordinal19 */
2792         uint32_t compute_pgm_rsrc2;  /* ordinal20 */
2793         uint32_t compute_vmid;  /* ordinal21 */
2794         uint32_t compute_resource_limits;  /* ordinal22 */
2795         uint32_t compute_static_thread_mgmt_se0;  /* ordinal23 */
2796         uint32_t compute_static_thread_mgmt_se1;  /* ordinal24 */
2797         uint32_t compute_tmpring_size;  /* ordinal25 */
2798         uint32_t compute_static_thread_mgmt_se2;  /* ordinal26 */
2799         uint32_t compute_static_thread_mgmt_se3;  /* ordinal27 */
2800         uint32_t compute_restart_x;  /* ordinal28 */
2801         uint32_t compute_restart_y;  /* ordinal29 */
2802         uint32_t compute_restart_z;  /* ordinal30 */
2803         uint32_t compute_thread_trace_enable;  /* ordinal31 */
2804         uint32_t compute_misc_reserved;  /* ordinal32 */
2805         uint32_t compute_dispatch_id;  /* ordinal33 */
2806         uint32_t compute_threadgroup_id;  /* ordinal34 */
2807         uint32_t compute_relaunch;  /* ordinal35 */
2808         uint32_t compute_wave_restore_addr_lo;  /* ordinal36 */
2809         uint32_t compute_wave_restore_addr_hi;  /* ordinal37 */
2810         uint32_t compute_wave_restore_control;  /* ordinal38 */
2811         uint32_t reserved9;  /* ordinal39 */
2812         uint32_t reserved10;  /* ordinal40 */
2813         uint32_t reserved11;  /* ordinal41 */
2814         uint32_t reserved12;  /* ordinal42 */
2815         uint32_t reserved13;  /* ordinal43 */
2816         uint32_t reserved14;  /* ordinal44 */
2817         uint32_t reserved15;  /* ordinal45 */
2818         uint32_t reserved16;  /* ordinal46 */
2819         uint32_t reserved17;  /* ordinal47 */
2820         uint32_t reserved18;  /* ordinal48 */
2821         uint32_t reserved19;  /* ordinal49 */
2822         uint32_t reserved20;  /* ordinal50 */
2823         uint32_t reserved21;  /* ordinal51 */
2824         uint32_t reserved22;  /* ordinal52 */
2825         uint32_t reserved23;  /* ordinal53 */
2826         uint32_t reserved24;  /* ordinal54 */
2827         uint32_t reserved25;  /* ordinal55 */
2828         uint32_t reserved26;  /* ordinal56 */
2829         uint32_t reserved27;  /* ordinal57 */
2830         uint32_t reserved28;  /* ordinal58 */
2831         uint32_t reserved29;  /* ordinal59 */
2832         uint32_t reserved30;  /* ordinal60 */
2833         uint32_t reserved31;  /* ordinal61 */
2834         uint32_t reserved32;  /* ordinal62 */
2835         uint32_t reserved33;  /* ordinal63 */
2836         uint32_t reserved34;  /* ordinal64 */
2837         uint32_t compute_user_data_0;  /* ordinal65 */
2838         uint32_t compute_user_data_1;  /* ordinal66 */
2839         uint32_t compute_user_data_2;  /* ordinal67 */
2840         uint32_t compute_user_data_3;  /* ordinal68 */
2841         uint32_t compute_user_data_4;  /* ordinal69 */
2842         uint32_t compute_user_data_5;  /* ordinal70 */
2843         uint32_t compute_user_data_6;  /* ordinal71 */
2844         uint32_t compute_user_data_7;  /* ordinal72 */
2845         uint32_t compute_user_data_8;  /* ordinal73 */
2846         uint32_t compute_user_data_9;  /* ordinal74 */
2847         uint32_t compute_user_data_10;  /* ordinal75 */
2848         uint32_t compute_user_data_11;  /* ordinal76 */
2849         uint32_t compute_user_data_12;  /* ordinal77 */
2850         uint32_t compute_user_data_13;  /* ordinal78 */
2851         uint32_t compute_user_data_14;  /* ordinal79 */
2852         uint32_t compute_user_data_15;  /* ordinal80 */
2853         uint32_t cp_compute_csinvoc_count_lo;  /* ordinal81 */
2854         uint32_t cp_compute_csinvoc_count_hi;  /* ordinal82 */
2855         uint32_t reserved35;  /* ordinal83 */
2856         uint32_t reserved36;  /* ordinal84 */
2857         uint32_t reserved37;  /* ordinal85 */
2858         uint32_t cp_mqd_query_time_lo;  /* ordinal86 */
2859         uint32_t cp_mqd_query_time_hi;  /* ordinal87 */
2860         uint32_t cp_mqd_connect_start_time_lo;  /* ordinal88 */
2861         uint32_t cp_mqd_connect_start_time_hi;  /* ordinal89 */
2862         uint32_t cp_mqd_connect_end_time_lo;  /* ordinal90 */
2863         uint32_t cp_mqd_connect_end_time_hi;  /* ordinal91 */
2864         uint32_t cp_mqd_connect_end_wf_count;  /* ordinal92 */
2865         uint32_t cp_mqd_connect_end_pq_rptr;  /* ordinal93 */
2866         uint32_t cp_mqd_connect_end_pq_wptr;  /* ordinal94 */
2867         uint32_t cp_mqd_connect_end_ib_rptr;  /* ordinal95 */
2868         uint32_t reserved38;  /* ordinal96 */
2869         uint32_t reserved39;  /* ordinal97 */
2870         uint32_t cp_mqd_save_start_time_lo;  /* ordinal98 */
2871         uint32_t cp_mqd_save_start_time_hi;  /* ordinal99 */
2872         uint32_t cp_mqd_save_end_time_lo;  /* ordinal100 */
2873         uint32_t cp_mqd_save_end_time_hi;  /* ordinal101 */
2874         uint32_t cp_mqd_restore_start_time_lo;  /* ordinal102 */
2875         uint32_t cp_mqd_restore_start_time_hi;  /* ordinal103 */
2876         uint32_t cp_mqd_restore_end_time_lo;  /* ordinal104 */
2877         uint32_t cp_mqd_restore_end_time_hi;  /* ordinal105 */
2878         uint32_t reserved40;  /* ordinal106 */
2879         uint32_t reserved41;  /* ordinal107 */
2880         uint32_t gds_cs_ctxsw_cnt0;  /* ordinal108 */
2881         uint32_t gds_cs_ctxsw_cnt1;  /* ordinal109 */
2882         uint32_t gds_cs_ctxsw_cnt2;  /* ordinal110 */
2883         uint32_t gds_cs_ctxsw_cnt3;  /* ordinal111 */
2884         uint32_t reserved42;  /* ordinal112 */
2885         uint32_t reserved43;  /* ordinal113 */
2886         uint32_t cp_pq_exe_status_lo;  /* ordinal114 */
2887         uint32_t cp_pq_exe_status_hi;  /* ordinal115 */
2888         uint32_t cp_packet_id_lo;  /* ordinal116 */
2889         uint32_t cp_packet_id_hi;  /* ordinal117 */
2890         uint32_t cp_packet_exe_status_lo;  /* ordinal118 */
2891         uint32_t cp_packet_exe_status_hi;  /* ordinal119 */
2892         uint32_t gds_save_base_addr_lo;  /* ordinal120 */
2893         uint32_t gds_save_base_addr_hi;  /* ordinal121 */
2894         uint32_t gds_save_mask_lo;  /* ordinal122 */
2895         uint32_t gds_save_mask_hi;  /* ordinal123 */
2896         uint32_t ctx_save_base_addr_lo;  /* ordinal124 */
2897         uint32_t ctx_save_base_addr_hi;  /* ordinal125 */
2898         uint32_t reserved44;  /* ordinal126 */
2899         uint32_t reserved45;  /* ordinal127 */
2900         uint32_t cp_mqd_base_addr_lo;  /* ordinal128 */
2901         uint32_t cp_mqd_base_addr_hi;  /* ordinal129 */
2902         uint32_t cp_hqd_active;  /* ordinal130 */
2903         uint32_t cp_hqd_vmid;  /* ordinal131 */
2904         uint32_t cp_hqd_persistent_state;  /* ordinal132 */
2905         uint32_t cp_hqd_pipe_priority;  /* ordinal133 */
2906         uint32_t cp_hqd_queue_priority;  /* ordinal134 */
2907         uint32_t cp_hqd_quantum;  /* ordinal135 */
2908         uint32_t cp_hqd_pq_base_lo;  /* ordinal136 */
2909         uint32_t cp_hqd_pq_base_hi;  /* ordinal137 */
2910         uint32_t cp_hqd_pq_rptr;  /* ordinal138 */
2911         uint32_t cp_hqd_pq_rptr_report_addr_lo;  /* ordinal139 */
2912         uint32_t cp_hqd_pq_rptr_report_addr_hi;  /* ordinal140 */
2913         uint32_t cp_hqd_pq_wptr_poll_addr;  /* ordinal141 */
2914         uint32_t cp_hqd_pq_wptr_poll_addr_hi;  /* ordinal142 */
2915         uint32_t cp_hqd_pq_doorbell_control;  /* ordinal143 */
2916         uint32_t cp_hqd_pq_wptr;  /* ordinal144 */
2917         uint32_t cp_hqd_pq_control;  /* ordinal145 */
2918         uint32_t cp_hqd_ib_base_addr_lo;  /* ordinal146 */
2919         uint32_t cp_hqd_ib_base_addr_hi;  /* ordinal147 */
2920         uint32_t cp_hqd_ib_rptr;  /* ordinal148 */
2921         uint32_t cp_hqd_ib_control;  /* ordinal149 */
2922         uint32_t cp_hqd_iq_timer;  /* ordinal150 */
2923         uint32_t cp_hqd_iq_rptr;  /* ordinal151 */
2924         uint32_t cp_hqd_dequeue_request;  /* ordinal152 */
2925         uint32_t cp_hqd_dma_offload;  /* ordinal153 */
2926         uint32_t cp_hqd_sema_cmd;  /* ordinal154 */
2927         uint32_t cp_hqd_msg_type;  /* ordinal155 */
2928         uint32_t cp_hqd_atomic0_preop_lo;  /* ordinal156 */
2929         uint32_t cp_hqd_atomic0_preop_hi;  /* ordinal157 */
2930         uint32_t cp_hqd_atomic1_preop_lo;  /* ordinal158 */
2931         uint32_t cp_hqd_atomic1_preop_hi;  /* ordinal159 */
2932         uint32_t cp_hqd_hq_status0;  /* ordinal160 */
2933         uint32_t cp_hqd_hq_control0;  /* ordinal161 */
2934         uint32_t cp_mqd_control;  /* ordinal162 */
2935         uint32_t cp_hqd_hq_status1;  /* ordinal163 */
2936         uint32_t cp_hqd_hq_control1;  /* ordinal164 */
2937         uint32_t cp_hqd_eop_base_addr_lo;  /* ordinal165 */
2938         uint32_t cp_hqd_eop_base_addr_hi;  /* ordinal166 */
2939         uint32_t cp_hqd_eop_control;  /* ordinal167 */
2940         uint32_t cp_hqd_eop_rptr;  /* ordinal168 */
2941         uint32_t cp_hqd_eop_wptr;  /* ordinal169 */
2942         uint32_t cp_hqd_eop_done_events;  /* ordinal170 */
2943         uint32_t cp_hqd_ctx_save_base_addr_lo;  /* ordinal171 */
2944         uint32_t cp_hqd_ctx_save_base_addr_hi;  /* ordinal172 */
2945         uint32_t cp_hqd_ctx_save_control;  /* ordinal173 */
2946         uint32_t cp_hqd_cntl_stack_offset;  /* ordinal174 */
2947         uint32_t cp_hqd_cntl_stack_size;  /* ordinal175 */
2948         uint32_t cp_hqd_wg_state_offset;  /* ordinal176 */
2949         uint32_t cp_hqd_ctx_save_size;  /* ordinal177 */
2950         uint32_t cp_hqd_gds_resource_state;  /* ordinal178 */
2951         uint32_t cp_hqd_error;  /* ordinal179 */
2952         uint32_t cp_hqd_eop_wptr_mem;  /* ordinal180 */
2953         uint32_t cp_hqd_eop_dones;  /* ordinal181 */
2954         uint32_t reserved46;  /* ordinal182 */
2955         uint32_t reserved47;  /* ordinal183 */
2956         uint32_t reserved48;  /* ordinal184 */
2957         uint32_t reserved49;  /* ordinal185 */
2958         uint32_t reserved50;  /* ordinal186 */
2959         uint32_t reserved51;  /* ordinal187 */
2960         uint32_t reserved52;  /* ordinal188 */
2961         uint32_t reserved53;  /* ordinal189 */
2962         uint32_t reserved54;  /* ordinal190 */
2963         uint32_t reserved55;  /* ordinal191 */
2964         uint32_t iqtimer_pkt_header;  /* ordinal192 */
2965         uint32_t iqtimer_pkt_dw0;  /* ordinal193 */
2966         uint32_t iqtimer_pkt_dw1;  /* ordinal194 */
2967         uint32_t iqtimer_pkt_dw2;  /* ordinal195 */
2968         uint32_t iqtimer_pkt_dw3;  /* ordinal196 */
2969         uint32_t iqtimer_pkt_dw4;  /* ordinal197 */
2970         uint32_t iqtimer_pkt_dw5;  /* ordinal198 */
2971         uint32_t iqtimer_pkt_dw6;  /* ordinal199 */
2972         uint32_t iqtimer_pkt_dw7;  /* ordinal200 */
2973         uint32_t iqtimer_pkt_dw8;  /* ordinal201 */
2974         uint32_t iqtimer_pkt_dw9;  /* ordinal202 */
2975         uint32_t iqtimer_pkt_dw10;  /* ordinal203 */
2976         uint32_t iqtimer_pkt_dw11;  /* ordinal204 */
2977         uint32_t iqtimer_pkt_dw12;  /* ordinal205 */
2978         uint32_t iqtimer_pkt_dw13;  /* ordinal206 */
2979         uint32_t iqtimer_pkt_dw14;  /* ordinal207 */
2980         uint32_t iqtimer_pkt_dw15;  /* ordinal208 */
2981         uint32_t iqtimer_pkt_dw16;  /* ordinal209 */
2982         uint32_t iqtimer_pkt_dw17;  /* ordinal210 */
2983         uint32_t iqtimer_pkt_dw18;  /* ordinal211 */
2984         uint32_t iqtimer_pkt_dw19;  /* ordinal212 */
2985         uint32_t iqtimer_pkt_dw20;  /* ordinal213 */
2986         uint32_t iqtimer_pkt_dw21;  /* ordinal214 */
2987         uint32_t iqtimer_pkt_dw22;  /* ordinal215 */
2988         uint32_t iqtimer_pkt_dw23;  /* ordinal216 */
2989         uint32_t iqtimer_pkt_dw24;  /* ordinal217 */
2990         uint32_t iqtimer_pkt_dw25;  /* ordinal218 */
2991         uint32_t iqtimer_pkt_dw26;  /* ordinal219 */
2992         uint32_t iqtimer_pkt_dw27;  /* ordinal220 */
2993         uint32_t iqtimer_pkt_dw28;  /* ordinal221 */
2994         uint32_t iqtimer_pkt_dw29;  /* ordinal222 */
2995         uint32_t iqtimer_pkt_dw30;  /* ordinal223 */
2996         uint32_t iqtimer_pkt_dw31;  /* ordinal224 */
2997         uint32_t reserved56;  /* ordinal225 */
2998         uint32_t reserved57;  /* ordinal226 */
2999         uint32_t reserved58;  /* ordinal227 */
3000         uint32_t set_resources_header;  /* ordinal228 */
3001         uint32_t set_resources_dw1;  /* ordinal229 */
3002         uint32_t set_resources_dw2;  /* ordinal230 */
3003         uint32_t set_resources_dw3;  /* ordinal231 */
3004         uint32_t set_resources_dw4;  /* ordinal232 */
3005         uint32_t set_resources_dw5;  /* ordinal233 */
3006         uint32_t set_resources_dw6;  /* ordinal234 */
3007         uint32_t set_resources_dw7;  /* ordinal235 */
3008         uint32_t reserved59;  /* ordinal236 */
3009         uint32_t reserved60;  /* ordinal237 */
3010         uint32_t reserved61;  /* ordinal238 */
3011         uint32_t reserved62;  /* ordinal239 */
3012         uint32_t reserved63;  /* ordinal240 */
3013         uint32_t reserved64;  /* ordinal241 */
3014         uint32_t reserved65;  /* ordinal242 */
3015         uint32_t reserved66;  /* ordinal243 */
3016         uint32_t reserved67;  /* ordinal244 */
3017         uint32_t reserved68;  /* ordinal245 */
3018         uint32_t reserved69;  /* ordinal246 */
3019         uint32_t reserved70;  /* ordinal247 */
3020         uint32_t reserved71;  /* ordinal248 */
3021         uint32_t reserved72;  /* ordinal249 */
3022         uint32_t reserved73;  /* ordinal250 */
3023         uint32_t reserved74;  /* ordinal251 */
3024         uint32_t reserved75;  /* ordinal252 */
3025         uint32_t reserved76;  /* ordinal253 */
3026         uint32_t reserved77;  /* ordinal254 */
3027         uint32_t reserved78;  /* ordinal255 */
3028
3029         uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
3030 };
3031
3032 static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
3033 {
3034         int i, r;
3035
3036         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3037                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3038
3039                 if (ring->mqd_obj) {
3040                         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3041                         if (unlikely(r != 0))
3042                                 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
3043
3044                         amdgpu_bo_unpin(ring->mqd_obj);
3045                         amdgpu_bo_unreserve(ring->mqd_obj);
3046
3047                         amdgpu_bo_unref(&ring->mqd_obj);
3048                         ring->mqd_obj = NULL;
3049                 }
3050         }
3051 }
3052
3053 static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
3054 {
3055         int r, i, j;
3056         u32 tmp;
3057         bool use_doorbell = true;
3058         u64 hqd_gpu_addr;
3059         u64 mqd_gpu_addr;
3060         u64 eop_gpu_addr;
3061         u64 wb_gpu_addr;
3062         u32 *buf;
3063         struct vi_mqd *mqd;
3064
3065         /* init the pipes */
3066         mutex_lock(&adev->srbm_mutex);
3067         for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
3068                 int me = (i < 4) ? 1 : 2;
3069                 int pipe = (i < 4) ? i : (i - 4);
3070
3071                 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
3072                 eop_gpu_addr >>= 8;
3073
3074                 vi_srbm_select(adev, me, pipe, 0, 0);
3075
3076                 /* write the EOP addr */
3077                 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
3078                 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
3079
3080                 /* set the VMID assigned */
3081                 WREG32(mmCP_HQD_VMID, 0);
3082
3083                 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3084                 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
3085                 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3086                                     (order_base_2(MEC_HPD_SIZE / 4) - 1));
3087                 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
3088         }
3089         vi_srbm_select(adev, 0, 0, 0, 0);
3090         mutex_unlock(&adev->srbm_mutex);
3091
3092         /* init the queues.  Just two for now. */
3093         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3094                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3095
3096                 if (ring->mqd_obj == NULL) {
3097                         r = amdgpu_bo_create(adev,
3098                                              sizeof(struct vi_mqd),
3099                                              PAGE_SIZE, true,
3100                                              AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3101                                              NULL, &ring->mqd_obj);
3102                         if (r) {
3103                                 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3104                                 return r;
3105                         }
3106                 }
3107
3108                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3109                 if (unlikely(r != 0)) {
3110                         gfx_v8_0_cp_compute_fini(adev);
3111                         return r;
3112                 }
3113                 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3114                                   &mqd_gpu_addr);
3115                 if (r) {
3116                         dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3117                         gfx_v8_0_cp_compute_fini(adev);
3118                         return r;
3119                 }
3120                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3121                 if (r) {
3122                         dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3123                         gfx_v8_0_cp_compute_fini(adev);
3124                         return r;
3125                 }
3126
3127                 /* init the mqd struct */
3128                 memset(buf, 0, sizeof(struct vi_mqd));
3129
3130                 mqd = (struct vi_mqd *)buf;
3131                 mqd->header = 0xC0310800;
3132                 mqd->compute_pipelinestat_enable = 0x00000001;
3133                 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3134                 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3135                 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3136                 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3137                 mqd->compute_misc_reserved = 0x00000003;
3138
3139                 mutex_lock(&adev->srbm_mutex);
3140                 vi_srbm_select(adev, ring->me,
3141                                ring->pipe,
3142                                ring->queue, 0);
3143
3144                 /* disable wptr polling */
3145                 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3146                 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3147                 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3148
3149                 mqd->cp_hqd_eop_base_addr_lo =
3150                         RREG32(mmCP_HQD_EOP_BASE_ADDR);
3151                 mqd->cp_hqd_eop_base_addr_hi =
3152                         RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
3153
3154                 /* enable doorbell? */
3155                 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3156                 if (use_doorbell) {
3157                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3158                 } else {
3159                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3160                 }
3161                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
3162                 mqd->cp_hqd_pq_doorbell_control = tmp;
3163
3164                 /* disable the queue if it's active */
3165                 mqd->cp_hqd_dequeue_request = 0;
3166                 mqd->cp_hqd_pq_rptr = 0;
3167                 mqd->cp_hqd_pq_wptr= 0;
3168                 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3169                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3170                         for (j = 0; j < adev->usec_timeout; j++) {
3171                                 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3172                                         break;
3173                                 udelay(1);
3174                         }
3175                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
3176                         WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
3177                         WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3178                 }
3179
3180                 /* set the pointer to the MQD */
3181                 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3182                 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3183                 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
3184                 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3185
3186                 /* set MQD vmid to 0 */
3187                 tmp = RREG32(mmCP_MQD_CONTROL);
3188                 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3189                 WREG32(mmCP_MQD_CONTROL, tmp);
3190                 mqd->cp_mqd_control = tmp;
3191
3192                 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3193                 hqd_gpu_addr = ring->gpu_addr >> 8;
3194                 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3195                 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3196                 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
3197                 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
3198
3199                 /* set up the HQD, this is similar to CP_RB0_CNTL */
3200                 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
3201                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3202                                     (order_base_2(ring->ring_size / 4) - 1));
3203                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3204                                ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3205 #ifdef __BIG_ENDIAN
3206                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3207 #endif
3208                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3209                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3210                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3211                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3212                 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
3213                 mqd->cp_hqd_pq_control = tmp;
3214
3215                 /* set the wb address wether it's enabled or not */
3216                 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3217                 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3218                 mqd->cp_hqd_pq_rptr_report_addr_hi =
3219                         upper_32_bits(wb_gpu_addr) & 0xffff;
3220                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3221                        mqd->cp_hqd_pq_rptr_report_addr_lo);
3222                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3223                        mqd->cp_hqd_pq_rptr_report_addr_hi);
3224
3225                 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3226                 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3227                 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3228                 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3229                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
3230                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3231                        mqd->cp_hqd_pq_wptr_poll_addr_hi);
3232
3233                 /* enable the doorbell if requested */
3234                 if (use_doorbell) {
3235                         if ((adev->asic_type == CHIP_CARRIZO) ||
3236                             (adev->asic_type == CHIP_FIJI)) {
3237                                 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
3238                                        AMDGPU_DOORBELL_KIQ << 2);
3239                                 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
3240                                        AMDGPU_DOORBELL_MEC_RING7 << 2);
3241                         }
3242                         tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3243                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3244                                             DOORBELL_OFFSET, ring->doorbell_index);
3245                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3246                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3247                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3248                         mqd->cp_hqd_pq_doorbell_control = tmp;
3249
3250                 } else {
3251                         mqd->cp_hqd_pq_doorbell_control = 0;
3252                 }
3253                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3254                        mqd->cp_hqd_pq_doorbell_control);
3255
3256                 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3257                 ring->wptr = 0;
3258                 mqd->cp_hqd_pq_wptr = ring->wptr;
3259                 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3260                 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3261
3262                 /* set the vmid for the queue */
3263                 mqd->cp_hqd_vmid = 0;
3264                 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3265
3266                 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
3267                 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3268                 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
3269                 mqd->cp_hqd_persistent_state = tmp;
3270
3271                 /* activate the queue */
3272                 mqd->cp_hqd_active = 1;
3273                 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
3274
3275                 vi_srbm_select(adev, 0, 0, 0, 0);
3276                 mutex_unlock(&adev->srbm_mutex);
3277
3278                 amdgpu_bo_kunmap(ring->mqd_obj);
3279                 amdgpu_bo_unreserve(ring->mqd_obj);
3280         }
3281
3282         if (use_doorbell) {
3283                 tmp = RREG32(mmCP_PQ_STATUS);
3284                 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3285                 WREG32(mmCP_PQ_STATUS, tmp);
3286         }
3287
3288         r = gfx_v8_0_cp_compute_start(adev);
3289         if (r)
3290                 return r;
3291
3292         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3293                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3294
3295                 ring->ready = true;
3296                 r = amdgpu_ring_test_ring(ring);
3297                 if (r)
3298                         ring->ready = false;
3299         }
3300
3301         return 0;
3302 }
3303
3304 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
3305 {
3306         int r;
3307
3308         if (adev->asic_type != CHIP_CARRIZO)
3309                 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3310
3311         if (!adev->firmware.smu_load) {
3312                 /* legacy firmware loading */
3313                 r = gfx_v8_0_cp_gfx_load_microcode(adev);
3314                 if (r)
3315                         return r;
3316
3317                 r = gfx_v8_0_cp_compute_load_microcode(adev);
3318                 if (r)
3319                         return r;
3320         } else {
3321                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3322                                                 AMDGPU_UCODE_ID_CP_CE);
3323                 if (r)
3324                         return -EINVAL;
3325
3326                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3327                                                 AMDGPU_UCODE_ID_CP_PFP);
3328                 if (r)
3329                         return -EINVAL;
3330
3331                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3332                                                 AMDGPU_UCODE_ID_CP_ME);
3333                 if (r)
3334                         return -EINVAL;
3335
3336                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3337                                                 AMDGPU_UCODE_ID_CP_MEC1);
3338                 if (r)
3339                         return -EINVAL;
3340         }
3341
3342         r = gfx_v8_0_cp_gfx_resume(adev);
3343         if (r)
3344                 return r;
3345
3346         r = gfx_v8_0_cp_compute_resume(adev);
3347         if (r)
3348                 return r;
3349
3350         gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3351
3352         return 0;
3353 }
3354
3355 static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
3356 {
3357         gfx_v8_0_cp_gfx_enable(adev, enable);
3358         gfx_v8_0_cp_compute_enable(adev, enable);
3359 }
3360
3361 static int gfx_v8_0_hw_init(void *handle)
3362 {
3363         int r;
3364         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3365
3366         gfx_v8_0_init_golden_registers(adev);
3367
3368         gfx_v8_0_gpu_init(adev);
3369
3370         r = gfx_v8_0_rlc_resume(adev);
3371         if (r)
3372                 return r;
3373
3374         r = gfx_v8_0_cp_resume(adev);
3375         if (r)
3376                 return r;
3377
3378         return r;
3379 }
3380
3381 static int gfx_v8_0_hw_fini(void *handle)
3382 {
3383         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3384
3385         gfx_v8_0_cp_enable(adev, false);
3386         gfx_v8_0_rlc_stop(adev);
3387         gfx_v8_0_cp_compute_fini(adev);
3388
3389         return 0;
3390 }
3391
3392 static int gfx_v8_0_suspend(void *handle)
3393 {
3394         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3395
3396         return gfx_v8_0_hw_fini(adev);
3397 }
3398
3399 static int gfx_v8_0_resume(void *handle)
3400 {
3401         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3402
3403         return gfx_v8_0_hw_init(adev);
3404 }
3405
3406 static bool gfx_v8_0_is_idle(void *handle)
3407 {
3408         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3409
3410         if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
3411                 return false;
3412         else
3413                 return true;
3414 }
3415
3416 static int gfx_v8_0_wait_for_idle(void *handle)
3417 {
3418         unsigned i;
3419         u32 tmp;
3420         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3421
3422         for (i = 0; i < adev->usec_timeout; i++) {
3423                 /* read MC_STATUS */
3424                 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
3425
3426                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3427                         return 0;
3428                 udelay(1);
3429         }
3430         return -ETIMEDOUT;
3431 }
3432
3433 static void gfx_v8_0_print_status(void *handle)
3434 {
3435         int i;
3436         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3437
3438         dev_info(adev->dev, "GFX 8.x registers\n");
3439         dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
3440                  RREG32(mmGRBM_STATUS));
3441         dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
3442                  RREG32(mmGRBM_STATUS2));
3443         dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
3444                  RREG32(mmGRBM_STATUS_SE0));
3445         dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
3446                  RREG32(mmGRBM_STATUS_SE1));
3447         dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
3448                  RREG32(mmGRBM_STATUS_SE2));
3449         dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
3450                  RREG32(mmGRBM_STATUS_SE3));
3451         dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
3452         dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
3453                  RREG32(mmCP_STALLED_STAT1));
3454         dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
3455                  RREG32(mmCP_STALLED_STAT2));
3456         dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
3457                  RREG32(mmCP_STALLED_STAT3));
3458         dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
3459                  RREG32(mmCP_CPF_BUSY_STAT));
3460         dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
3461                  RREG32(mmCP_CPF_STALLED_STAT1));
3462         dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
3463         dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
3464         dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
3465                  RREG32(mmCP_CPC_STALLED_STAT1));
3466         dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
3467
3468         for (i = 0; i < 32; i++) {
3469                 dev_info(adev->dev, "  GB_TILE_MODE%d=0x%08X\n",
3470                          i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
3471         }
3472         for (i = 0; i < 16; i++) {
3473                 dev_info(adev->dev, "  GB_MACROTILE_MODE%d=0x%08X\n",
3474                          i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
3475         }
3476         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3477                 dev_info(adev->dev, "  se: %d\n", i);
3478                 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
3479                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG=0x%08X\n",
3480                          RREG32(mmPA_SC_RASTER_CONFIG));
3481                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG_1=0x%08X\n",
3482                          RREG32(mmPA_SC_RASTER_CONFIG_1));
3483         }
3484         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3485
3486         dev_info(adev->dev, "  GB_ADDR_CONFIG=0x%08X\n",
3487                  RREG32(mmGB_ADDR_CONFIG));
3488         dev_info(adev->dev, "  HDP_ADDR_CONFIG=0x%08X\n",
3489                  RREG32(mmHDP_ADDR_CONFIG));
3490         dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
3491                  RREG32(mmDMIF_ADDR_CALC));
3492         dev_info(adev->dev, "  SDMA0_TILING_CONFIG=0x%08X\n",
3493                  RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
3494         dev_info(adev->dev, "  SDMA1_TILING_CONFIG=0x%08X\n",
3495                  RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
3496         dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
3497                  RREG32(mmUVD_UDEC_ADDR_CONFIG));
3498         dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
3499                  RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
3500         dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
3501                  RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
3502
3503         dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",
3504                  RREG32(mmCP_MEQ_THRESHOLDS));
3505         dev_info(adev->dev, "  SX_DEBUG_1=0x%08X\n",
3506                  RREG32(mmSX_DEBUG_1));
3507         dev_info(adev->dev, "  TA_CNTL_AUX=0x%08X\n",
3508                  RREG32(mmTA_CNTL_AUX));
3509         dev_info(adev->dev, "  SPI_CONFIG_CNTL=0x%08X\n",
3510                  RREG32(mmSPI_CONFIG_CNTL));
3511         dev_info(adev->dev, "  SQ_CONFIG=0x%08X\n",
3512                  RREG32(mmSQ_CONFIG));
3513         dev_info(adev->dev, "  DB_DEBUG=0x%08X\n",
3514                  RREG32(mmDB_DEBUG));
3515         dev_info(adev->dev, "  DB_DEBUG2=0x%08X\n",
3516                  RREG32(mmDB_DEBUG2));
3517         dev_info(adev->dev, "  DB_DEBUG3=0x%08X\n",
3518                  RREG32(mmDB_DEBUG3));
3519         dev_info(adev->dev, "  CB_HW_CONTROL=0x%08X\n",
3520                  RREG32(mmCB_HW_CONTROL));
3521         dev_info(adev->dev, "  SPI_CONFIG_CNTL_1=0x%08X\n",
3522                  RREG32(mmSPI_CONFIG_CNTL_1));
3523         dev_info(adev->dev, "  PA_SC_FIFO_SIZE=0x%08X\n",
3524                  RREG32(mmPA_SC_FIFO_SIZE));
3525         dev_info(adev->dev, "  VGT_NUM_INSTANCES=0x%08X\n",
3526                  RREG32(mmVGT_NUM_INSTANCES));
3527         dev_info(adev->dev, "  CP_PERFMON_CNTL=0x%08X\n",
3528                  RREG32(mmCP_PERFMON_CNTL));
3529         dev_info(adev->dev, "  PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
3530                  RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
3531         dev_info(adev->dev, "  VGT_CACHE_INVALIDATION=0x%08X\n",
3532                  RREG32(mmVGT_CACHE_INVALIDATION));
3533         dev_info(adev->dev, "  VGT_GS_VERTEX_REUSE=0x%08X\n",
3534                  RREG32(mmVGT_GS_VERTEX_REUSE));
3535         dev_info(adev->dev, "  PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
3536                  RREG32(mmPA_SC_LINE_STIPPLE_STATE));
3537         dev_info(adev->dev, "  PA_CL_ENHANCE=0x%08X\n",
3538                  RREG32(mmPA_CL_ENHANCE));
3539         dev_info(adev->dev, "  PA_SC_ENHANCE=0x%08X\n",
3540                  RREG32(mmPA_SC_ENHANCE));
3541
3542         dev_info(adev->dev, "  CP_ME_CNTL=0x%08X\n",
3543                  RREG32(mmCP_ME_CNTL));
3544         dev_info(adev->dev, "  CP_MAX_CONTEXT=0x%08X\n",
3545                  RREG32(mmCP_MAX_CONTEXT));
3546         dev_info(adev->dev, "  CP_ENDIAN_SWAP=0x%08X\n",
3547                  RREG32(mmCP_ENDIAN_SWAP));
3548         dev_info(adev->dev, "  CP_DEVICE_ID=0x%08X\n",
3549                  RREG32(mmCP_DEVICE_ID));
3550
3551         dev_info(adev->dev, "  CP_SEM_WAIT_TIMER=0x%08X\n",
3552                  RREG32(mmCP_SEM_WAIT_TIMER));
3553
3554         dev_info(adev->dev, "  CP_RB_WPTR_DELAY=0x%08X\n",
3555                  RREG32(mmCP_RB_WPTR_DELAY));
3556         dev_info(adev->dev, "  CP_RB_VMID=0x%08X\n",
3557                  RREG32(mmCP_RB_VMID));
3558         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
3559                  RREG32(mmCP_RB0_CNTL));
3560         dev_info(adev->dev, "  CP_RB0_WPTR=0x%08X\n",
3561                  RREG32(mmCP_RB0_WPTR));
3562         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR=0x%08X\n",
3563                  RREG32(mmCP_RB0_RPTR_ADDR));
3564         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR_HI=0x%08X\n",
3565                  RREG32(mmCP_RB0_RPTR_ADDR_HI));
3566         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
3567                  RREG32(mmCP_RB0_CNTL));
3568         dev_info(adev->dev, "  CP_RB0_BASE=0x%08X\n",
3569                  RREG32(mmCP_RB0_BASE));
3570         dev_info(adev->dev, "  CP_RB0_BASE_HI=0x%08X\n",
3571                  RREG32(mmCP_RB0_BASE_HI));
3572         dev_info(adev->dev, "  CP_MEC_CNTL=0x%08X\n",
3573                  RREG32(mmCP_MEC_CNTL));
3574         dev_info(adev->dev, "  CP_CPF_DEBUG=0x%08X\n",
3575                  RREG32(mmCP_CPF_DEBUG));
3576
3577         dev_info(adev->dev, "  SCRATCH_ADDR=0x%08X\n",
3578                  RREG32(mmSCRATCH_ADDR));
3579         dev_info(adev->dev, "  SCRATCH_UMSK=0x%08X\n",
3580                  RREG32(mmSCRATCH_UMSK));
3581
3582         dev_info(adev->dev, "  CP_INT_CNTL_RING0=0x%08X\n",
3583                  RREG32(mmCP_INT_CNTL_RING0));
3584         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
3585                  RREG32(mmRLC_LB_CNTL));
3586         dev_info(adev->dev, "  RLC_CNTL=0x%08X\n",
3587                  RREG32(mmRLC_CNTL));
3588         dev_info(adev->dev, "  RLC_CGCG_CGLS_CTRL=0x%08X\n",
3589                  RREG32(mmRLC_CGCG_CGLS_CTRL));
3590         dev_info(adev->dev, "  RLC_LB_CNTR_INIT=0x%08X\n",
3591                  RREG32(mmRLC_LB_CNTR_INIT));
3592         dev_info(adev->dev, "  RLC_LB_CNTR_MAX=0x%08X\n",
3593                  RREG32(mmRLC_LB_CNTR_MAX));
3594         dev_info(adev->dev, "  RLC_LB_INIT_CU_MASK=0x%08X\n",
3595                  RREG32(mmRLC_LB_INIT_CU_MASK));
3596         dev_info(adev->dev, "  RLC_LB_PARAMS=0x%08X\n",
3597                  RREG32(mmRLC_LB_PARAMS));
3598         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
3599                  RREG32(mmRLC_LB_CNTL));
3600         dev_info(adev->dev, "  RLC_MC_CNTL=0x%08X\n",
3601                  RREG32(mmRLC_MC_CNTL));
3602         dev_info(adev->dev, "  RLC_UCODE_CNTL=0x%08X\n",
3603                  RREG32(mmRLC_UCODE_CNTL));
3604
3605         mutex_lock(&adev->srbm_mutex);
3606         for (i = 0; i < 16; i++) {
3607                 vi_srbm_select(adev, 0, 0, 0, i);
3608                 dev_info(adev->dev, "  VM %d:\n", i);
3609                 dev_info(adev->dev, "  SH_MEM_CONFIG=0x%08X\n",
3610                          RREG32(mmSH_MEM_CONFIG));
3611                 dev_info(adev->dev, "  SH_MEM_APE1_BASE=0x%08X\n",
3612                          RREG32(mmSH_MEM_APE1_BASE));
3613                 dev_info(adev->dev, "  SH_MEM_APE1_LIMIT=0x%08X\n",
3614                          RREG32(mmSH_MEM_APE1_LIMIT));
3615                 dev_info(adev->dev, "  SH_MEM_BASES=0x%08X\n",
3616                          RREG32(mmSH_MEM_BASES));
3617         }
3618         vi_srbm_select(adev, 0, 0, 0, 0);
3619         mutex_unlock(&adev->srbm_mutex);
3620 }
3621
3622 static int gfx_v8_0_soft_reset(void *handle)
3623 {
3624         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3625         u32 tmp;
3626         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3627
3628         /* GRBM_STATUS */
3629         tmp = RREG32(mmGRBM_STATUS);
3630         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3631                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3632                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3633                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3634                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3635                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3636                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3637                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3638                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3639                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3640         }
3641
3642         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3643                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3644                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3645                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3646                                                 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3647         }
3648
3649         /* GRBM_STATUS2 */
3650         tmp = RREG32(mmGRBM_STATUS2);
3651         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3652                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3653                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3654
3655         /* SRBM_STATUS */
3656         tmp = RREG32(mmSRBM_STATUS);
3657         if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
3658                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3659                                                 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3660
3661         if (grbm_soft_reset || srbm_soft_reset) {
3662                 gfx_v8_0_print_status((void *)adev);
3663                 /* stop the rlc */
3664                 gfx_v8_0_rlc_stop(adev);
3665
3666                 /* Disable GFX parsing/prefetching */
3667                 gfx_v8_0_cp_gfx_enable(adev, false);
3668
3669                 /* Disable MEC parsing/prefetching */
3670                 /* XXX todo */
3671
3672                 if (grbm_soft_reset) {
3673                         tmp = RREG32(mmGRBM_SOFT_RESET);
3674                         tmp |= grbm_soft_reset;
3675                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3676                         WREG32(mmGRBM_SOFT_RESET, tmp);
3677                         tmp = RREG32(mmGRBM_SOFT_RESET);
3678
3679                         udelay(50);
3680
3681                         tmp &= ~grbm_soft_reset;
3682                         WREG32(mmGRBM_SOFT_RESET, tmp);
3683                         tmp = RREG32(mmGRBM_SOFT_RESET);
3684                 }
3685
3686                 if (srbm_soft_reset) {
3687                         tmp = RREG32(mmSRBM_SOFT_RESET);
3688                         tmp |= srbm_soft_reset;
3689                         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3690                         WREG32(mmSRBM_SOFT_RESET, tmp);
3691                         tmp = RREG32(mmSRBM_SOFT_RESET);
3692
3693                         udelay(50);
3694
3695                         tmp &= ~srbm_soft_reset;
3696                         WREG32(mmSRBM_SOFT_RESET, tmp);
3697                         tmp = RREG32(mmSRBM_SOFT_RESET);
3698                 }
3699                 /* Wait a little for things to settle down */
3700                 udelay(50);
3701                 gfx_v8_0_print_status((void *)adev);
3702         }
3703         return 0;
3704 }
3705
3706 /**
3707  * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
3708  *
3709  * @adev: amdgpu_device pointer
3710  *
3711  * Fetches a GPU clock counter snapshot.
3712  * Returns the 64 bit clock counter snapshot.
3713  */
3714 uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3715 {
3716         uint64_t clock;
3717
3718         mutex_lock(&adev->gfx.gpu_clock_mutex);
3719         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3720         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3721                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3722         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3723         return clock;
3724 }
3725
3726 static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3727                                           uint32_t vmid,
3728                                           uint32_t gds_base, uint32_t gds_size,
3729                                           uint32_t gws_base, uint32_t gws_size,
3730                                           uint32_t oa_base, uint32_t oa_size)
3731 {
3732         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3733         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3734
3735         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3736         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3737
3738         oa_base = oa_base >> AMDGPU_OA_SHIFT;
3739         oa_size = oa_size >> AMDGPU_OA_SHIFT;
3740
3741         /* GDS Base */
3742         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3743         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3744                                 WRITE_DATA_DST_SEL(0)));
3745         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
3746         amdgpu_ring_write(ring, 0);
3747         amdgpu_ring_write(ring, gds_base);
3748
3749         /* GDS Size */
3750         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3751         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3752                                 WRITE_DATA_DST_SEL(0)));
3753         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
3754         amdgpu_ring_write(ring, 0);
3755         amdgpu_ring_write(ring, gds_size);
3756
3757         /* GWS */
3758         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3759         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3760                                 WRITE_DATA_DST_SEL(0)));
3761         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
3762         amdgpu_ring_write(ring, 0);
3763         amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3764
3765         /* OA */
3766         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3767         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3768                                 WRITE_DATA_DST_SEL(0)));
3769         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
3770         amdgpu_ring_write(ring, 0);
3771         amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
3772 }
3773
3774 static int gfx_v8_0_early_init(void *handle)
3775 {
3776         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3777
3778         adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
3779         adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
3780         gfx_v8_0_set_ring_funcs(adev);
3781         gfx_v8_0_set_irq_funcs(adev);
3782         gfx_v8_0_set_gds_init(adev);
3783
3784         return 0;
3785 }
3786
3787 static int gfx_v8_0_set_powergating_state(void *handle,
3788                                           enum amd_powergating_state state)
3789 {
3790         return 0;
3791 }
3792
3793 static int gfx_v8_0_set_clockgating_state(void *handle,
3794                                           enum amd_clockgating_state state)
3795 {
3796         return 0;
3797 }
3798
3799 static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3800 {
3801         u32 rptr;
3802
3803         rptr = ring->adev->wb.wb[ring->rptr_offs];
3804
3805         return rptr;
3806 }
3807
3808 static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3809 {
3810         struct amdgpu_device *adev = ring->adev;
3811         u32 wptr;
3812
3813         if (ring->use_doorbell)
3814                 /* XXX check if swapping is necessary on BE */
3815                 wptr = ring->adev->wb.wb[ring->wptr_offs];
3816         else
3817                 wptr = RREG32(mmCP_RB0_WPTR);
3818
3819         return wptr;
3820 }
3821
3822 static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3823 {
3824         struct amdgpu_device *adev = ring->adev;
3825
3826         if (ring->use_doorbell) {
3827                 /* XXX check if swapping is necessary on BE */
3828                 adev->wb.wb[ring->wptr_offs] = ring->wptr;
3829                 WDOORBELL32(ring->doorbell_index, ring->wptr);
3830         } else {
3831                 WREG32(mmCP_RB0_WPTR, ring->wptr);
3832                 (void)RREG32(mmCP_RB0_WPTR);
3833         }
3834 }
3835
3836 static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3837 {
3838         u32 ref_and_mask, reg_mem_engine;
3839
3840         if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
3841                 switch (ring->me) {
3842                 case 1:
3843                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
3844                         break;
3845                 case 2:
3846                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
3847                         break;
3848                 default:
3849                         return;
3850                 }
3851                 reg_mem_engine = 0;
3852         } else {
3853                 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
3854                 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
3855         }
3856
3857         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3858         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3859                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
3860                                  reg_mem_engine));
3861         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
3862         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
3863         amdgpu_ring_write(ring, ref_and_mask);
3864         amdgpu_ring_write(ring, ref_and_mask);
3865         amdgpu_ring_write(ring, 0x20); /* poll interval */
3866 }
3867
3868 static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3869                                   struct amdgpu_ib *ib)
3870 {
3871         bool need_ctx_switch = ring->current_ctx != ib->ctx;
3872         u32 header, control = 0;
3873         u32 next_rptr = ring->wptr + 5;
3874
3875         /* drop the CE preamble IB for the same context */
3876         if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
3877                 return;
3878
3879         if (need_ctx_switch)
3880                 next_rptr += 2;
3881
3882         next_rptr += 4;
3883         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3884         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3885         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3886         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3887         amdgpu_ring_write(ring, next_rptr);
3888
3889         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
3890         if (need_ctx_switch) {
3891                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3892                 amdgpu_ring_write(ring, 0);
3893         }
3894
3895         if (ib->flags & AMDGPU_IB_FLAG_CE)
3896                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3897         else
3898                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3899
3900         control |= ib->length_dw |
3901                 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3902
3903         amdgpu_ring_write(ring, header);
3904         amdgpu_ring_write(ring,
3905 #ifdef __BIG_ENDIAN
3906                           (2 << 0) |
3907 #endif
3908                           (ib->gpu_addr & 0xFFFFFFFC));
3909         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3910         amdgpu_ring_write(ring, control);
3911 }
3912
3913 static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3914                                   struct amdgpu_ib *ib)
3915 {
3916         u32 header, control = 0;
3917         u32 next_rptr = ring->wptr + 5;
3918
3919         control |= INDIRECT_BUFFER_VALID;
3920
3921         next_rptr += 4;
3922         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3923         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3924         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3925         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3926         amdgpu_ring_write(ring, next_rptr);
3927
3928         header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3929
3930         control |= ib->length_dw |
3931                            (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3932
3933         amdgpu_ring_write(ring, header);
3934         amdgpu_ring_write(ring,
3935 #ifdef __BIG_ENDIAN
3936                                           (2 << 0) |
3937 #endif
3938                                           (ib->gpu_addr & 0xFFFFFFFC));
3939         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3940         amdgpu_ring_write(ring, control);
3941 }
3942
3943 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
3944                                          u64 seq, unsigned flags)
3945 {
3946         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3947         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3948
3949         /* EVENT_WRITE_EOP - flush caches, send int */
3950         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3951         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3952                                  EOP_TC_ACTION_EN |
3953                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3954                                  EVENT_INDEX(5)));
3955         amdgpu_ring_write(ring, addr & 0xfffffffc);
3956         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
3957                           DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3958         amdgpu_ring_write(ring, lower_32_bits(seq));
3959         amdgpu_ring_write(ring, upper_32_bits(seq));
3960
3961 }
3962
3963 /**
3964  * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring
3965  *
3966  * @ring: amdgpu ring buffer object
3967  * @semaphore: amdgpu semaphore object
3968  * @emit_wait: Is this a sempahore wait?
3969  *
3970  * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
3971  * from running ahead of semaphore waits.
3972  */
3973 static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
3974                                          struct amdgpu_semaphore *semaphore,
3975                                          bool emit_wait)
3976 {
3977         uint64_t addr = semaphore->gpu_addr;
3978         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3979
3980         if (ring->adev->asic_type == CHIP_TOPAZ ||
3981             ring->adev->asic_type == CHIP_TONGA ||
3982             ring->adev->asic_type == CHIP_FIJI)
3983                 /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */
3984                 return false;
3985         else {
3986                 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
3987                 amdgpu_ring_write(ring, lower_32_bits(addr));
3988                 amdgpu_ring_write(ring, upper_32_bits(addr));
3989                 amdgpu_ring_write(ring, sel);
3990         }
3991
3992         if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
3993                 /* Prevent the PFP from running ahead of the semaphore wait */
3994                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3995                 amdgpu_ring_write(ring, 0x0);
3996         }
3997
3998         return true;
3999 }
4000
4001 static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4002                                         unsigned vm_id, uint64_t pd_addr)
4003 {
4004         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
4005         uint32_t seq = ring->fence_drv.sync_seq[ring->idx];
4006         uint64_t addr = ring->fence_drv.gpu_addr;
4007
4008         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4009         amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
4010                  WAIT_REG_MEM_FUNCTION(3))); /* equal */
4011         amdgpu_ring_write(ring, addr & 0xfffffffc);
4012         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
4013         amdgpu_ring_write(ring, seq);
4014         amdgpu_ring_write(ring, 0xffffffff);
4015         amdgpu_ring_write(ring, 4); /* poll interval */
4016
4017         if (usepfp) {
4018                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
4019                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4020                 amdgpu_ring_write(ring, 0);
4021                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4022                 amdgpu_ring_write(ring, 0);
4023         }
4024
4025         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4026         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
4027                                  WRITE_DATA_DST_SEL(0)) |
4028                                  WR_CONFIRM);
4029         if (vm_id < 8) {
4030                 amdgpu_ring_write(ring,
4031                                   (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
4032         } else {
4033                 amdgpu_ring_write(ring,
4034                                   (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
4035         }
4036         amdgpu_ring_write(ring, 0);
4037         amdgpu_ring_write(ring, pd_addr >> 12);
4038
4039         /* bits 0-15 are the VM contexts0-15 */
4040         /* invalidate the cache */
4041         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4042         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4043                                  WRITE_DATA_DST_SEL(0)));
4044         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4045         amdgpu_ring_write(ring, 0);
4046         amdgpu_ring_write(ring, 1 << vm_id);
4047
4048         /* wait for the invalidate to complete */
4049         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4050         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
4051                                  WAIT_REG_MEM_FUNCTION(0) |  /* always */
4052                                  WAIT_REG_MEM_ENGINE(0))); /* me */
4053         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4054         amdgpu_ring_write(ring, 0);
4055         amdgpu_ring_write(ring, 0); /* ref */
4056         amdgpu_ring_write(ring, 0); /* mask */
4057         amdgpu_ring_write(ring, 0x20); /* poll interval */
4058
4059         /* compute doesn't have PFP */
4060         if (usepfp) {
4061                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4062                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4063                 amdgpu_ring_write(ring, 0x0);
4064                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4065                 amdgpu_ring_write(ring, 0);
4066                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4067                 amdgpu_ring_write(ring, 0);
4068         }
4069 }
4070
4071 static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring)
4072 {
4073         if (gfx_v8_0_is_idle(ring->adev)) {
4074                 amdgpu_ring_lockup_update(ring);
4075                 return false;
4076         }
4077         return amdgpu_ring_test_lockup(ring);
4078 }
4079
4080 static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4081 {
4082         return ring->adev->wb.wb[ring->rptr_offs];
4083 }
4084
4085 static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4086 {
4087         return ring->adev->wb.wb[ring->wptr_offs];
4088 }
4089
4090 static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4091 {
4092         struct amdgpu_device *adev = ring->adev;
4093
4094         /* XXX check if swapping is necessary on BE */
4095         adev->wb.wb[ring->wptr_offs] = ring->wptr;
4096         WDOORBELL32(ring->doorbell_index, ring->wptr);
4097 }
4098
4099 static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
4100                                              u64 addr, u64 seq,
4101                                              unsigned flags)
4102 {
4103         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4104         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4105
4106         /* RELEASE_MEM - flush caches, send int */
4107         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
4108         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
4109                                  EOP_TC_ACTION_EN |
4110                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4111                                  EVENT_INDEX(5)));
4112         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4113         amdgpu_ring_write(ring, addr & 0xfffffffc);
4114         amdgpu_ring_write(ring, upper_32_bits(addr));
4115         amdgpu_ring_write(ring, lower_32_bits(seq));
4116         amdgpu_ring_write(ring, upper_32_bits(seq));
4117 }
4118
4119 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4120                                                  enum amdgpu_interrupt_state state)
4121 {
4122         u32 cp_int_cntl;
4123
4124         switch (state) {
4125         case AMDGPU_IRQ_STATE_DISABLE:
4126                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4127                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4128                                             TIME_STAMP_INT_ENABLE, 0);
4129                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4130                 break;
4131         case AMDGPU_IRQ_STATE_ENABLE:
4132                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4133                 cp_int_cntl =
4134                         REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4135                                       TIME_STAMP_INT_ENABLE, 1);
4136                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4137                 break;
4138         default:
4139                 break;
4140         }
4141 }
4142
4143 static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4144                                                      int me, int pipe,
4145                                                      enum amdgpu_interrupt_state state)
4146 {
4147         u32 mec_int_cntl, mec_int_cntl_reg;
4148
4149         /*
4150          * amdgpu controls only pipe 0 of MEC1. That's why this function only
4151          * handles the setting of interrupts for this specific pipe. All other
4152          * pipes' interrupts are set by amdkfd.
4153          */
4154
4155         if (me == 1) {
4156                 switch (pipe) {
4157                 case 0:
4158                         mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4159                         break;
4160                 default:
4161                         DRM_DEBUG("invalid pipe %d\n", pipe);
4162                         return;
4163                 }
4164         } else {
4165                 DRM_DEBUG("invalid me %d\n", me);
4166                 return;
4167         }
4168
4169         switch (state) {
4170         case AMDGPU_IRQ_STATE_DISABLE:
4171                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4172                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4173                                              TIME_STAMP_INT_ENABLE, 0);
4174                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4175                 break;
4176         case AMDGPU_IRQ_STATE_ENABLE:
4177                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4178                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4179                                              TIME_STAMP_INT_ENABLE, 1);
4180                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4181                 break;
4182         default:
4183                 break;
4184         }
4185 }
4186
4187 static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4188                                              struct amdgpu_irq_src *source,
4189                                              unsigned type,
4190                                              enum amdgpu_interrupt_state state)
4191 {
4192         u32 cp_int_cntl;
4193
4194         switch (state) {
4195         case AMDGPU_IRQ_STATE_DISABLE:
4196                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4197                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4198                                             PRIV_REG_INT_ENABLE, 0);
4199                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4200                 break;
4201         case AMDGPU_IRQ_STATE_ENABLE:
4202                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4203                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4204                                             PRIV_REG_INT_ENABLE, 0);
4205                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4206                 break;
4207         default:
4208                 break;
4209         }
4210
4211         return 0;
4212 }
4213
4214 static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4215                                               struct amdgpu_irq_src *source,
4216                                               unsigned type,
4217                                               enum amdgpu_interrupt_state state)
4218 {
4219         u32 cp_int_cntl;
4220
4221         switch (state) {
4222         case AMDGPU_IRQ_STATE_DISABLE:
4223                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4224                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4225                                             PRIV_INSTR_INT_ENABLE, 0);
4226                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4227                 break;
4228         case AMDGPU_IRQ_STATE_ENABLE:
4229                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4230                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4231                                             PRIV_INSTR_INT_ENABLE, 1);
4232                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4233                 break;
4234         default:
4235                 break;
4236         }
4237
4238         return 0;
4239 }
4240
4241 static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4242                                             struct amdgpu_irq_src *src,
4243                                             unsigned type,
4244                                             enum amdgpu_interrupt_state state)
4245 {
4246         switch (type) {
4247         case AMDGPU_CP_IRQ_GFX_EOP:
4248                 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
4249                 break;
4250         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4251                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4252                 break;
4253         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4254                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4255                 break;
4256         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4257                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4258                 break;
4259         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4260                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4261                 break;
4262         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4263                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4264                 break;
4265         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4266                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4267                 break;
4268         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4269                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4270                 break;
4271         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4272                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4273                 break;
4274         default:
4275                 break;
4276         }
4277         return 0;
4278 }
4279
4280 static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
4281                             struct amdgpu_irq_src *source,
4282                             struct amdgpu_iv_entry *entry)
4283 {
4284         int i;
4285         u8 me_id, pipe_id, queue_id;
4286         struct amdgpu_ring *ring;
4287
4288         DRM_DEBUG("IH: CP EOP\n");
4289         me_id = (entry->ring_id & 0x0c) >> 2;
4290         pipe_id = (entry->ring_id & 0x03) >> 0;
4291         queue_id = (entry->ring_id & 0x70) >> 4;
4292
4293         switch (me_id) {
4294         case 0:
4295                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4296                 break;
4297         case 1:
4298         case 2:
4299                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4300                         ring = &adev->gfx.compute_ring[i];
4301                         /* Per-queue interrupt is supported for MEC starting from VI.
4302                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4303                           */
4304                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4305                                 amdgpu_fence_process(ring);
4306                 }
4307                 break;
4308         }
4309         return 0;
4310 }
4311
4312 static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
4313                                  struct amdgpu_irq_src *source,
4314                                  struct amdgpu_iv_entry *entry)
4315 {
4316         DRM_ERROR("Illegal register access in command stream\n");
4317         schedule_work(&adev->reset_work);
4318         return 0;
4319 }
4320
4321 static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
4322                                   struct amdgpu_irq_src *source,
4323                                   struct amdgpu_iv_entry *entry)
4324 {
4325         DRM_ERROR("Illegal instruction in command stream\n");
4326         schedule_work(&adev->reset_work);
4327         return 0;
4328 }
4329
4330 const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
4331         .early_init = gfx_v8_0_early_init,
4332         .late_init = NULL,
4333         .sw_init = gfx_v8_0_sw_init,
4334         .sw_fini = gfx_v8_0_sw_fini,
4335         .hw_init = gfx_v8_0_hw_init,
4336         .hw_fini = gfx_v8_0_hw_fini,
4337         .suspend = gfx_v8_0_suspend,
4338         .resume = gfx_v8_0_resume,
4339         .is_idle = gfx_v8_0_is_idle,
4340         .wait_for_idle = gfx_v8_0_wait_for_idle,
4341         .soft_reset = gfx_v8_0_soft_reset,
4342         .print_status = gfx_v8_0_print_status,
4343         .set_clockgating_state = gfx_v8_0_set_clockgating_state,
4344         .set_powergating_state = gfx_v8_0_set_powergating_state,
4345 };
4346
4347 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
4348         .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
4349         .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
4350         .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
4351         .parse_cs = NULL,
4352         .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
4353         .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
4354         .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4355         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4356         .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4357         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4358         .test_ring = gfx_v8_0_ring_test_ring,
4359         .test_ib = gfx_v8_0_ring_test_ib,
4360         .is_lockup = gfx_v8_0_ring_is_lockup,
4361         .insert_nop = amdgpu_ring_insert_nop,
4362 };
4363
4364 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
4365         .get_rptr = gfx_v8_0_ring_get_rptr_compute,
4366         .get_wptr = gfx_v8_0_ring_get_wptr_compute,
4367         .set_wptr = gfx_v8_0_ring_set_wptr_compute,
4368         .parse_cs = NULL,
4369         .emit_ib = gfx_v8_0_ring_emit_ib_compute,
4370         .emit_fence = gfx_v8_0_ring_emit_fence_compute,
4371         .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4372         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4373         .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4374         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4375         .test_ring = gfx_v8_0_ring_test_ring,
4376         .test_ib = gfx_v8_0_ring_test_ib,
4377         .is_lockup = gfx_v8_0_ring_is_lockup,
4378         .insert_nop = amdgpu_ring_insert_nop,
4379 };
4380
4381 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
4382 {
4383         int i;
4384
4385         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4386                 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
4387
4388         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4389                 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
4390 }
4391
4392 static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
4393         .set = gfx_v8_0_set_eop_interrupt_state,
4394         .process = gfx_v8_0_eop_irq,
4395 };
4396
4397 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
4398         .set = gfx_v8_0_set_priv_reg_fault_state,
4399         .process = gfx_v8_0_priv_reg_irq,
4400 };
4401
4402 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
4403         .set = gfx_v8_0_set_priv_inst_fault_state,
4404         .process = gfx_v8_0_priv_inst_irq,
4405 };
4406
4407 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
4408 {
4409         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4410         adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
4411
4412         adev->gfx.priv_reg_irq.num_types = 1;
4413         adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
4414
4415         adev->gfx.priv_inst_irq.num_types = 1;
4416         adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
4417 }
4418
4419 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
4420 {
4421         /* init asci gds info */
4422         adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
4423         adev->gds.gws.total_size = 64;
4424         adev->gds.oa.total_size = 16;
4425
4426         if (adev->gds.mem.total_size == 64 * 1024) {
4427                 adev->gds.mem.gfx_partition_size = 4096;
4428                 adev->gds.mem.cs_partition_size = 4096;
4429
4430                 adev->gds.gws.gfx_partition_size = 4;
4431                 adev->gds.gws.cs_partition_size = 4;
4432
4433                 adev->gds.oa.gfx_partition_size = 4;
4434                 adev->gds.oa.cs_partition_size = 1;
4435         } else {
4436                 adev->gds.mem.gfx_partition_size = 1024;
4437                 adev->gds.mem.cs_partition_size = 1024;
4438
4439                 adev->gds.gws.gfx_partition_size = 16;
4440                 adev->gds.gws.cs_partition_size = 16;
4441
4442                 adev->gds.oa.gfx_partition_size = 4;
4443                 adev->gds.oa.cs_partition_size = 4;
4444         }
4445 }
4446
4447 static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev,
4448                 u32 se, u32 sh)
4449 {
4450         u32 mask = 0, tmp, tmp1;
4451         int i;
4452
4453         gfx_v8_0_select_se_sh(adev, se, sh);
4454         tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4455         tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4456         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4457
4458         tmp &= 0xffff0000;
4459
4460         tmp |= tmp1;
4461         tmp >>= 16;
4462
4463         for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
4464                 mask <<= 1;
4465                 mask |= 1;
4466         }
4467
4468         return (~tmp) & mask;
4469 }
4470
4471 int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
4472                                                  struct amdgpu_cu_info *cu_info)
4473 {
4474         int i, j, k, counter, active_cu_number = 0;
4475         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4476
4477         if (!adev || !cu_info)
4478                 return -EINVAL;
4479
4480         mutex_lock(&adev->grbm_idx_mutex);
4481         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4482                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4483                         mask = 1;
4484                         ao_bitmap = 0;
4485                         counter = 0;
4486                         bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j);
4487                         cu_info->bitmap[i][j] = bitmap;
4488
4489                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4490                                 if (bitmap & mask) {
4491                                         if (counter < 2)
4492                                                 ao_bitmap |= mask;
4493                                         counter ++;
4494                                 }
4495                                 mask <<= 1;
4496                         }
4497                         active_cu_number += counter;
4498                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4499                 }
4500         }
4501
4502         cu_info->number = active_cu_number;
4503         cu_info->ao_cu_mask = ao_cu_mask;
4504         mutex_unlock(&adev->grbm_idx_mutex);
4505         return 0;
4506 }