drivers/dma/tegra20-apb-dma.c

   1 /*
   2  * DMA driver for Nvidia's Tegra20 APB DMA controller.
   3  *
   4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/bitops.h>
  20 #include <linux/clk.h>
  21 #include <linux/delay.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/err.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/mm.h>
  29 #include <linux/module.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/pm.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/slab.h>
  36 #include <linux/clk/tegra.h>
  37
  38 #include "dmaengine.h"
  39
  40 #define TEGRA_APBDMA_GENERAL                    0x0
  41 #define TEGRA_APBDMA_GENERAL_ENABLE             BIT(31)
  42
  43 #define TEGRA_APBDMA_CONTROL                    0x010
  44 #define TEGRA_APBDMA_IRQ_MASK                   0x01c
  45 #define TEGRA_APBDMA_IRQ_MASK_SET               0x020
  46
  47 /* CSR register */
  48 #define TEGRA_APBDMA_CHAN_CSR                   0x00
  49 #define TEGRA_APBDMA_CSR_ENB                    BIT(31)
  50 #define TEGRA_APBDMA_CSR_IE_EOC                 BIT(30)
  51 #define TEGRA_APBDMA_CSR_HOLD                   BIT(29)
  52 #define TEGRA_APBDMA_CSR_DIR                    BIT(28)
  53 #define TEGRA_APBDMA_CSR_ONCE                   BIT(27)
  54 #define TEGRA_APBDMA_CSR_FLOW                   BIT(21)
  55 #define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT          16
  56 #define TEGRA_APBDMA_CSR_WCOUNT_MASK            0xFFFC
  57
  58 /* STATUS register */
  59 #define TEGRA_APBDMA_CHAN_STATUS                0x004
  60 #define TEGRA_APBDMA_STATUS_BUSY                BIT(31)
  61 #define TEGRA_APBDMA_STATUS_ISE_EOC             BIT(30)
  62 #define TEGRA_APBDMA_STATUS_HALT                BIT(29)
  63 #define TEGRA_APBDMA_STATUS_PING_PONG           BIT(28)
  64 #define TEGRA_APBDMA_STATUS_COUNT_SHIFT         2
  65 #define TEGRA_APBDMA_STATUS_COUNT_MASK          0xFFFC
  66
  67 #define TEGRA_APBDMA_CHAN_CSRE                  0x00C
  68 #define TEGRA_APBDMA_CHAN_CSRE_PAUSE            (1 << 31)
  69
  70 /* AHB memory address */
  71 #define TEGRA_APBDMA_CHAN_AHBPTR                0x010
  72
  73 /* AHB sequence register */
  74 #define TEGRA_APBDMA_CHAN_AHBSEQ                0x14
  75 #define TEGRA_APBDMA_AHBSEQ_INTR_ENB            BIT(31)
  76 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8         (0 << 28)
  77 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16        (1 << 28)
  78 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32        (2 << 28)
  79 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64        (3 << 28)
  80 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128       (4 << 28)
  81 #define TEGRA_APBDMA_AHBSEQ_DATA_SWAP           BIT(27)
  82 #define TEGRA_APBDMA_AHBSEQ_BURST_1             (4 << 24)
  83 #define TEGRA_APBDMA_AHBSEQ_BURST_4             (5 << 24)
  84 #define TEGRA_APBDMA_AHBSEQ_BURST_8             (6 << 24)
  85 #define TEGRA_APBDMA_AHBSEQ_DBL_BUF             BIT(19)
  86 #define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT          16
  87 #define TEGRA_APBDMA_AHBSEQ_WRAP_NONE           0
  88
  89 /* APB address */
  90 #define TEGRA_APBDMA_CHAN_APBPTR                0x018
  91
  92 /* APB sequence register */
  93 #define TEGRA_APBDMA_CHAN_APBSEQ                0x01c
  94 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8         (0 << 28)
  95 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16        (1 << 28)
  96 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32        (2 << 28)
  97 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64        (3 << 28)
  98 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128       (4 << 28)
  99 #define TEGRA_APBDMA_APBSEQ_DATA_SWAP           BIT(27)
 100 #define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1         (1 << 16)
 101
 102 /*
 103  * If any burst is in flight and DMA paused then this is the time to complete
 104  * on-flight burst and update DMA status register.
 105  */
 106 #define TEGRA_APBDMA_BURST_COMPLETE_TIME        20
 107
 108 /* Channel base address offset from APBDMA base address */
 109 #define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET    0x1000
 110
 111 /* DMA channel register space size */
 112 #define TEGRA_APBDMA_CHANNEL_REGISTER_SIZE      0x20
 113
 114 struct tegra_dma;
 115
 116 /*
 117  * tegra_dma_chip_data Tegra chip specific DMA data
 118  * @nr_channels: Number of channels available in the controller.
 119  * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
 120  * @support_channel_pause: Support channel wise pause of dma.
 121  */
 122 struct tegra_dma_chip_data {
 123         int nr_channels;
 124         int max_dma_count;
 125         bool support_channel_pause;
 126 };
 127
 128 /* DMA channel registers */
 129 struct tegra_dma_channel_regs {
 130         unsigned long   csr;
 131         unsigned long   ahb_ptr;
 132         unsigned long   apb_ptr;
 133         unsigned long   ahb_seq;
 134         unsigned long   apb_seq;
 135 };
 136
 137 /*
 138  * tegra_dma_sg_req: Dma request details to configure hardware. This
 139  * contains the details for one transfer to configure DMA hw.
 140  * The client's request for data transfer can be broken into multiple
 141  * sub-transfer as per requester details and hw support.
 142  * This sub transfer get added in the list of transfer and point to Tegra
 143  * DMA descriptor which manages the transfer details.
 144  */
 145 struct tegra_dma_sg_req {
 146         struct tegra_dma_channel_regs   ch_regs;
 147         int                             req_len;
 148         bool                            configured;
 149         bool                            last_sg;
 150         bool                            half_done;
 151         struct list_head                node;
 152         struct tegra_dma_desc           *dma_desc;
 153 };
 154
 155 /*
 156  * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
 157  * This descriptor keep track of transfer status, callbacks and request
 158  * counts etc.
 159  */
 160 struct tegra_dma_desc {
 161         struct dma_async_tx_descriptor  txd;
 162         int                             bytes_requested;
 163         int                             bytes_transferred;
 164         enum dma_status                 dma_status;
 165         struct list_head                node;
 166         struct list_head                tx_list;
 167         struct list_head                cb_node;
 168         int                             cb_count;
 169 };
 170
 171 struct tegra_dma_channel;
 172
 173 typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
 174                                 bool to_terminate);
 175
 176 /* tegra_dma_channel: Channel specific information */
 177 struct tegra_dma_channel {
 178         struct dma_chan         dma_chan;
 179         char                    name[30];
 180         bool                    config_init;
 181         int                     id;
 182         int                     irq;
 183         unsigned long           chan_base_offset;
 184         spinlock_t              lock;
 185         bool                    busy;
 186         struct tegra_dma        *tdma;
 187         bool                    cyclic;
 188
 189         /* Different lists for managing the requests */
 190         struct list_head        free_sg_req;
 191         struct list_head        pending_sg_req;
 192         struct list_head        free_dma_desc;
 193         struct list_head        cb_desc;
 194
 195         /* ISR handler and tasklet for bottom half of isr handling */
 196         dma_isr_handler         isr_handler;
 197         struct tasklet_struct   tasklet;
 198         dma_async_tx_callback   callback;
 199         void                    *callback_param;
 200
 201         /* Channel-slave specific configuration */
 202         struct dma_slave_config dma_sconfig;
 203         struct tegra_dma_channel_regs   channel_reg;
 204 };
 205
 206 /* tegra_dma: Tegra DMA specific information */
 207 struct tegra_dma {
 208         struct dma_device               dma_dev;
 209         struct device                   *dev;
 210         struct clk                      *dma_clk;
 211         spinlock_t                      global_lock;
 212         void __iomem                    *base_addr;
 213         const struct tegra_dma_chip_data *chip_data;
 214
 215         /* Some register need to be cache before suspend */
 216         u32                             reg_gen;
 217
 218         /* Last member of the structure */
 219         struct tegra_dma_channel channels[0];
 220 };
 221
 222 static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
 223 {
 224         writel(val, tdma->base_addr + reg);
 225 }
 226
 227 static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
 228 {
 229         return readl(tdma->base_addr + reg);
 230 }
 231
 232 static inline void tdc_write(struct tegra_dma_channel *tdc,
 233                 u32 reg, u32 val)
 234 {
 235         writel(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
 236 }
 237
 238 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
 239 {
 240         return readl(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
 241 }
 242
 243 static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
 244 {
 245         return container_of(dc, struct tegra_dma_channel, dma_chan);
 246 }
 247
 248 static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
 249                 struct dma_async_tx_descriptor *td)
 250 {
 251         return container_of(td, struct tegra_dma_desc, txd);
 252 }
 253
 254 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
 255 {
 256         return &tdc->dma_chan.dev->device;
 257 }
 258
 259 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx);
 260 static int tegra_dma_runtime_suspend(struct device *dev);
 261 static int tegra_dma_runtime_resume(struct device *dev);
 262
 263 /* Get DMA desc from free list, if not there then allocate it.  */
 264 static struct tegra_dma_desc *tegra_dma_desc_get(
 265                 struct tegra_dma_channel *tdc)
 266 {
 267         struct tegra_dma_desc *dma_desc;
 268         unsigned long flags;
 269
 270         spin_lock_irqsave(&tdc->lock, flags);
 271
 272         /* Do not allocate if desc are waiting for ack */
 273         list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
 274                 if (async_tx_test_ack(&dma_desc->txd)) {
 275                         list_del(&dma_desc->node);
 276                         spin_unlock_irqrestore(&tdc->lock, flags);
 277                         dma_desc->txd.flags = 0;
 278                         return dma_desc;
 279                 }
 280         }
 281
 282         spin_unlock_irqrestore(&tdc->lock, flags);
 283
 284         /* Allocate DMA desc */
 285         dma_desc = kzalloc(sizeof(*dma_desc), GFP_ATOMIC);
 286         if (!dma_desc) {
 287                 dev_err(tdc2dev(tdc), "dma_desc alloc failed\n");
 288                 return NULL;
 289         }
 290
 291         dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
 292         dma_desc->txd.tx_submit = tegra_dma_tx_submit;
 293         dma_desc->txd.flags = 0;
 294         return dma_desc;
 295 }
 296
 297 static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
 298                 struct tegra_dma_desc *dma_desc)
 299 {
 300         unsigned long flags;
 301
 302         spin_lock_irqsave(&tdc->lock, flags);
 303         if (!list_empty(&dma_desc->tx_list))
 304                 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
 305         list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
 306         spin_unlock_irqrestore(&tdc->lock, flags);
 307 }
 308
 309 static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
 310                 struct tegra_dma_channel *tdc)
 311 {
 312         struct tegra_dma_sg_req *sg_req = NULL;
 313         unsigned long flags;
 314
 315         spin_lock_irqsave(&tdc->lock, flags);
 316         if (!list_empty(&tdc->free_sg_req)) {
 317                 sg_req = list_first_entry(&tdc->free_sg_req,
 318                                         typeof(*sg_req), node);
 319                 list_del(&sg_req->node);
 320                 spin_unlock_irqrestore(&tdc->lock, flags);
 321                 return sg_req;
 322         }
 323         spin_unlock_irqrestore(&tdc->lock, flags);
 324
 325         sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_ATOMIC);
 326         if (!sg_req)
 327                 dev_err(tdc2dev(tdc), "sg_req alloc failed\n");
 328         return sg_req;
 329 }
 330
 331 static int tegra_dma_slave_config(struct dma_chan *dc,
 332                 struct dma_slave_config *sconfig)
 333 {
 334         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 335
 336         if (!list_empty(&tdc->pending_sg_req)) {
 337                 dev_err(tdc2dev(tdc), "Configuration not allowed\n");
 338                 return -EBUSY;
 339         }
 340
 341         memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
 342         tdc->config_init = true;
 343         return 0;
 344 }
 345
 346 static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
 347         bool wait_for_burst_complete)
 348 {
 349         struct tegra_dma *tdma = tdc->tdma;
 350
 351         spin_lock(&tdma->global_lock);
 352         tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
 353         if (wait_for_burst_complete)
 354                 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
 355 }
 356
 357 static void tegra_dma_global_resume(struct tegra_dma_channel *tdc)
 358 {
 359         struct tegra_dma *tdma = tdc->tdma;
 360
 361         tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
 362         spin_unlock(&tdma->global_lock);
 363 }
 364
 365 static void tegra_dma_pause(struct tegra_dma_channel *tdc,
 366         bool wait_for_burst_complete)
 367 {
 368         struct tegra_dma *tdma = tdc->tdma;
 369
 370         if (tdma->chip_data->support_channel_pause) {
 371                 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE,
 372                                 TEGRA_APBDMA_CHAN_CSRE_PAUSE);
 373                 if (wait_for_burst_complete)
 374                         udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
 375         } else {
 376                 tegra_dma_global_pause(tdc, wait_for_burst_complete);
 377         }
 378 }
 379
 380 static void tegra_dma_resume(struct tegra_dma_channel *tdc)
 381 {
 382         struct tegra_dma *tdma = tdc->tdma;
 383
 384         if (tdma->chip_data->support_channel_pause) {
 385                 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0);
 386         } else {
 387                 tegra_dma_global_resume(tdc);
 388         }
 389 }
 390
 391 static void tegra_dma_stop(struct tegra_dma_channel *tdc)
 392 {
 393         u32 csr;
 394         u32 status;
 395
 396         /* Disable interrupts */
 397         csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
 398         csr &= ~TEGRA_APBDMA_CSR_IE_EOC;
 399         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
 400
 401         /* Disable DMA */
 402         csr &= ~TEGRA_APBDMA_CSR_ENB;
 403         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
 404
 405         /* Clear interrupt status if it is there */
 406         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 407         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 408                 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
 409                 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
 410         }
 411         tdc->busy = false;
 412 }
 413
 414 static void tegra_dma_start(struct tegra_dma_channel *tdc,
 415                 struct tegra_dma_sg_req *sg_req)
 416 {
 417         struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
 418
 419         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);
 420         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);
 421         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr);
 422         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq);
 423         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr);
 424
 425         /* Start DMA */
 426         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
 427                                 ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
 428 }
 429
 430 static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
 431                 struct tegra_dma_sg_req *nsg_req)
 432 {
 433         unsigned long status;
 434
 435         /*
 436          * The DMA controller reloads the new configuration for next transfer
 437          * after last burst of current transfer completes.
 438          * If there is no IEC status then this makes sure that last burst
 439          * has not be completed. There may be case that last burst is on
 440          * flight and so it can complete but because DMA is paused, it
 441          * will not generates interrupt as well as not reload the new
 442          * configuration.
 443          * If there is already IEC status then interrupt handler need to
 444          * load new configuration.
 445          */
 446         tegra_dma_pause(tdc, false);
 447         status  = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 448
 449         /*
 450          * If interrupt is pending then do nothing as the ISR will handle
 451          * the programing for new request.
 452          */
 453         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 454                 dev_err(tdc2dev(tdc),
 455                         "Skipping new configuration as interrupt is pending\n");
 456                 tegra_dma_resume(tdc);
 457                 return;
 458         }
 459
 460         /* Safe to program new configuration */
 461         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
 462         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
 463         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
 464                                 nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
 465         nsg_req->configured = true;
 466
 467         tegra_dma_resume(tdc);
 468 }
 469
 470 static void tdc_start_head_req(struct tegra_dma_channel *tdc)
 471 {
 472         struct tegra_dma_sg_req *sg_req;
 473
 474         if (list_empty(&tdc->pending_sg_req))
 475                 return;
 476
 477         sg_req = list_first_entry(&tdc->pending_sg_req,
 478                                         typeof(*sg_req), node);
 479         tegra_dma_start(tdc, sg_req);
 480         sg_req->configured = true;
 481         tdc->busy = true;
 482 }
 483
 484 static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
 485 {
 486         struct tegra_dma_sg_req *hsgreq;
 487         struct tegra_dma_sg_req *hnsgreq;
 488
 489         if (list_empty(&tdc->pending_sg_req))
 490                 return;
 491
 492         hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
 493         if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
 494                 hnsgreq = list_first_entry(&hsgreq->node,
 495                                         typeof(*hnsgreq), node);
 496                 tegra_dma_configure_for_next(tdc, hnsgreq);
 497         }
 498 }
 499
 500 static inline int get_current_xferred_count(struct tegra_dma_channel *tdc,
 501         struct tegra_dma_sg_req *sg_req, unsigned long status)
 502 {
 503         return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
 504 }
 505
 506 static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
 507 {
 508         struct tegra_dma_sg_req *sgreq;
 509         struct tegra_dma_desc *dma_desc;
 510
 511         while (!list_empty(&tdc->pending_sg_req)) {
 512                 sgreq = list_first_entry(&tdc->pending_sg_req,
 513                                                 typeof(*sgreq), node);
 514                 list_move_tail(&sgreq->node, &tdc->free_sg_req);
 515                 if (sgreq->last_sg) {
 516                         dma_desc = sgreq->dma_desc;
 517                         dma_desc->dma_status = DMA_ERROR;
 518                         list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
 519
 520                         /* Add in cb list if it is not there. */
 521                         if (!dma_desc->cb_count)
 522                                 list_add_tail(&dma_desc->cb_node,
 523                                                         &tdc->cb_desc);
 524                         dma_desc->cb_count++;
 525                 }
 526         }
 527         tdc->isr_handler = NULL;
 528 }
 529
 530 static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
 531                 struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
 532 {
 533         struct tegra_dma_sg_req *hsgreq = NULL;
 534
 535         if (list_empty(&tdc->pending_sg_req)) {
 536                 dev_err(tdc2dev(tdc), "Dma is running without req\n");
 537                 tegra_dma_stop(tdc);
 538                 return false;
 539         }
 540
 541         /*
 542          * Check that head req on list should be in flight.
 543          * If it is not in flight then abort transfer as
 544          * looping of transfer can not continue.
 545          */
 546         hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
 547         if (!hsgreq->configured) {
 548                 tegra_dma_stop(tdc);
 549                 dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
 550                 tegra_dma_abort_all(tdc);
 551                 return false;
 552         }
 553
 554         /* Configure next request */
 555         if (!to_terminate)
 556                 tdc_configure_next_head_desc(tdc);
 557         return true;
 558 }
 559
 560 static void handle_once_dma_done(struct tegra_dma_channel *tdc,
 561         bool to_terminate)
 562 {
 563         struct tegra_dma_sg_req *sgreq;
 564         struct tegra_dma_desc *dma_desc;
 565
 566         tdc->busy = false;
 567         sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
 568         dma_desc = sgreq->dma_desc;
 569         dma_desc->bytes_transferred += sgreq->req_len;
 570
 571         list_del(&sgreq->node);
 572         if (sgreq->last_sg) {
 573                 dma_desc->dma_status = DMA_COMPLETE;
 574                 dma_cookie_complete(&dma_desc->txd);
 575                 if (!dma_desc->cb_count)
 576                         list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
 577                 dma_desc->cb_count++;
 578                 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
 579         }
 580         list_add_tail(&sgreq->node, &tdc->free_sg_req);
 581
 582         /* Do not start DMA if it is going to be terminate */
 583         if (to_terminate || list_empty(&tdc->pending_sg_req))
 584                 return;
 585
 586         tdc_start_head_req(tdc);
 587         return;
 588 }
 589
 590 static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
 591                 bool to_terminate)
 592 {
 593         struct tegra_dma_sg_req *sgreq;
 594         struct tegra_dma_desc *dma_desc;
 595         bool st;
 596
 597         sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
 598         dma_desc = sgreq->dma_desc;
 599         dma_desc->bytes_transferred += sgreq->req_len;
 600
 601         /* Callback need to be call */
 602         if (!dma_desc->cb_count)
 603                 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
 604         dma_desc->cb_count++;
 605
 606         /* If not last req then put at end of pending list */
 607         if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
 608                 list_move_tail(&sgreq->node, &tdc->pending_sg_req);
 609                 sgreq->configured = false;
 610                 st = handle_continuous_head_request(tdc, sgreq, to_terminate);
 611                 if (!st)
 612                         dma_desc->dma_status = DMA_ERROR;
 613         }
 614         return;
 615 }
 616
 617 static void tegra_dma_tasklet(unsigned long data)
 618 {
 619         struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
 620         dma_async_tx_callback callback = NULL;
 621         void *callback_param = NULL;
 622         struct tegra_dma_desc *dma_desc;
 623         unsigned long flags;
 624         int cb_count;
 625
 626         spin_lock_irqsave(&tdc->lock, flags);
 627         while (!list_empty(&tdc->cb_desc)) {
 628                 dma_desc  = list_first_entry(&tdc->cb_desc,
 629                                         typeof(*dma_desc), cb_node);
 630                 list_del(&dma_desc->cb_node);
 631                 callback = dma_desc->txd.callback;
 632                 callback_param = dma_desc->txd.callback_param;
 633                 cb_count = dma_desc->cb_count;
 634                 dma_desc->cb_count = 0;
 635                 spin_unlock_irqrestore(&tdc->lock, flags);
 636                 while (cb_count-- && callback)
 637                         callback(callback_param);
 638                 spin_lock_irqsave(&tdc->lock, flags);
 639         }
 640         spin_unlock_irqrestore(&tdc->lock, flags);
 641 }
 642
 643 static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
 644 {
 645         struct tegra_dma_channel *tdc = dev_id;
 646         unsigned long status;
 647         unsigned long flags;
 648
 649         spin_lock_irqsave(&tdc->lock, flags);
 650
 651         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 652         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 653                 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
 654                 tdc->isr_handler(tdc, false);
 655                 tasklet_schedule(&tdc->tasklet);
 656                 spin_unlock_irqrestore(&tdc->lock, flags);
 657                 return IRQ_HANDLED;
 658         }
 659
 660         spin_unlock_irqrestore(&tdc->lock, flags);
 661         dev_info(tdc2dev(tdc),
 662                 "Interrupt already served status 0x%08lx\n", status);
 663         return IRQ_NONE;
 664 }
 665
 666 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
 667 {
 668         struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
 669         struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
 670         unsigned long flags;
 671         dma_cookie_t cookie;
 672
 673         spin_lock_irqsave(&tdc->lock, flags);
 674         dma_desc->dma_status = DMA_IN_PROGRESS;
 675         cookie = dma_cookie_assign(&dma_desc->txd);
 676         list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
 677         spin_unlock_irqrestore(&tdc->lock, flags);
 678         return cookie;
 679 }
 680
 681 static void tegra_dma_issue_pending(struct dma_chan *dc)
 682 {
 683         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 684         unsigned long flags;
 685
 686         spin_lock_irqsave(&tdc->lock, flags);
 687         if (list_empty(&tdc->pending_sg_req)) {
 688                 dev_err(tdc2dev(tdc), "No DMA request\n");
 689                 goto end;
 690         }
 691         if (!tdc->busy) {
 692                 tdc_start_head_req(tdc);
 693
 694                 /* Continuous single mode: Configure next req */
 695                 if (tdc->cyclic) {
 696                         /*
 697                          * Wait for 1 burst time for configure DMA for
 698                          * next transfer.
 699                          */
 700                         udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
 701                         tdc_configure_next_head_desc(tdc);
 702                 }
 703         }
 704 end:
 705         spin_unlock_irqrestore(&tdc->lock, flags);
 706         return;
 707 }
 708
 709 static void tegra_dma_terminate_all(struct dma_chan *dc)
 710 {
 711         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 712         struct tegra_dma_sg_req *sgreq;
 713         struct tegra_dma_desc *dma_desc;
 714         unsigned long flags;
 715         unsigned long status;
 716         bool was_busy;
 717
 718         spin_lock_irqsave(&tdc->lock, flags);
 719         if (list_empty(&tdc->pending_sg_req)) {
 720                 spin_unlock_irqrestore(&tdc->lock, flags);
 721                 return;
 722         }
 723
 724         if (!tdc->busy)
 725                 goto skip_dma_stop;
 726
 727         /* Pause DMA before checking the queue status */
 728         tegra_dma_pause(tdc, true);
 729
 730         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 731         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 732                 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
 733                 tdc->isr_handler(tdc, true);
 734                 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 735         }
 736
 737         was_busy = tdc->busy;
 738         tegra_dma_stop(tdc);
 739
 740         if (!list_empty(&tdc->pending_sg_req) && was_busy) {
 741                 sgreq = list_first_entry(&tdc->pending_sg_req,
 742                                         typeof(*sgreq), node);
 743                 sgreq->dma_desc->bytes_transferred +=
 744                                 get_current_xferred_count(tdc, sgreq, status);
 745         }
 746         tegra_dma_resume(tdc);
 747
 748 skip_dma_stop:
 749         tegra_dma_abort_all(tdc);
 750
 751         while (!list_empty(&tdc->cb_desc)) {
 752                 dma_desc  = list_first_entry(&tdc->cb_desc,
 753                                         typeof(*dma_desc), cb_node);
 754                 list_del(&dma_desc->cb_node);
 755                 dma_desc->cb_count = 0;
 756         }
 757         spin_unlock_irqrestore(&tdc->lock, flags);
 758 }
 759
 760 static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
 761         dma_cookie_t cookie, struct dma_tx_state *txstate)
 762 {
 763         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 764         struct tegra_dma_desc *dma_desc;
 765         struct tegra_dma_sg_req *sg_req;
 766         enum dma_status ret;
 767         unsigned long flags;
 768         unsigned int residual;
 769
 770         ret = dma_cookie_status(dc, cookie, txstate);
 771         if (ret == DMA_COMPLETE)
 772                 return ret;
 773
 774         spin_lock_irqsave(&tdc->lock, flags);
 775
 776         /* Check on wait_ack desc status */
 777         list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
 778                 if (dma_desc->txd.cookie == cookie) {
 779                         residual =  dma_desc->bytes_requested -
 780                                         (dma_desc->bytes_transferred %
 781                                                 dma_desc->bytes_requested);
 782                         dma_set_residue(txstate, residual);
 783                         ret = dma_desc->dma_status;
 784                         spin_unlock_irqrestore(&tdc->lock, flags);
 785                         return ret;
 786                 }
 787         }
 788
 789         /* Check in pending list */
 790         list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
 791                 dma_desc = sg_req->dma_desc;
 792                 if (dma_desc->txd.cookie == cookie) {
 793                         residual =  dma_desc->bytes_requested -
 794                                         (dma_desc->bytes_transferred %
 795                                                 dma_desc->bytes_requested);
 796                         dma_set_residue(txstate, residual);
 797                         ret = dma_desc->dma_status;
 798                         spin_unlock_irqrestore(&tdc->lock, flags);
 799                         return ret;
 800                 }
 801         }
 802
 803         dev_dbg(tdc2dev(tdc), "cookie %d does not found\n", cookie);
 804         spin_unlock_irqrestore(&tdc->lock, flags);
 805         return ret;
 806 }
 807
 808 static int tegra_dma_device_control(struct dma_chan *dc, enum dma_ctrl_cmd cmd,
 809                         unsigned long arg)
 810 {
 811         switch (cmd) {
 812         case DMA_SLAVE_CONFIG:
 813                 return tegra_dma_slave_config(dc,
 814                                 (struct dma_slave_config *)arg);
 815
 816         case DMA_TERMINATE_ALL:
 817                 tegra_dma_terminate_all(dc);
 818                 return 0;
 819
 820         default:
 821                 break;
 822         }
 823
 824         return -ENXIO;
 825 }
 826
 827 static inline int get_bus_width(struct tegra_dma_channel *tdc,
 828                 enum dma_slave_buswidth slave_bw)
 829 {
 830         switch (slave_bw) {
 831         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 832                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8;
 833         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 834                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16;
 835         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 836                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
 837         case DMA_SLAVE_BUSWIDTH_8_BYTES:
 838                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
 839         default:
 840                 dev_warn(tdc2dev(tdc),
 841                         "slave bw is not supported, using 32bits\n");
 842                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
 843         }
 844 }
 845
 846 static inline int get_burst_size(struct tegra_dma_channel *tdc,
 847         u32 burst_size, enum dma_slave_buswidth slave_bw, int len)
 848 {
 849         int burst_byte;
 850         int burst_ahb_width;
 851
 852         /*
 853          * burst_size from client is in terms of the bus_width.
 854          * convert them into AHB memory width which is 4 byte.
 855          */
 856         burst_byte = burst_size * slave_bw;
 857         burst_ahb_width = burst_byte / 4;
 858
 859         /* If burst size is 0 then calculate the burst size based on length */
 860         if (!burst_ahb_width) {
 861                 if (len & 0xF)
 862                         return TEGRA_APBDMA_AHBSEQ_BURST_1;
 863                 else if ((len >> 4) & 0x1)
 864                         return TEGRA_APBDMA_AHBSEQ_BURST_4;
 865                 else
 866                         return TEGRA_APBDMA_AHBSEQ_BURST_8;
 867         }
 868         if (burst_ahb_width < 4)
 869                 return TEGRA_APBDMA_AHBSEQ_BURST_1;
 870         else if (burst_ahb_width < 8)
 871                 return TEGRA_APBDMA_AHBSEQ_BURST_4;
 872         else
 873                 return TEGRA_APBDMA_AHBSEQ_BURST_8;
 874 }
 875
 876 static int get_transfer_param(struct tegra_dma_channel *tdc,
 877         enum dma_transfer_direction direction, unsigned long *apb_addr,
 878         unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size,
 879         enum dma_slave_buswidth *slave_bw)
 880 {
 881
 882         switch (direction) {
 883         case DMA_MEM_TO_DEV:
 884                 *apb_addr = tdc->dma_sconfig.dst_addr;
 885                 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
 886                 *burst_size = tdc->dma_sconfig.dst_maxburst;
 887                 *slave_bw = tdc->dma_sconfig.dst_addr_width;
 888                 *csr = TEGRA_APBDMA_CSR_DIR;
 889                 return 0;
 890
 891         case DMA_DEV_TO_MEM:
 892                 *apb_addr = tdc->dma_sconfig.src_addr;
 893                 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
 894                 *burst_size = tdc->dma_sconfig.src_maxburst;
 895                 *slave_bw = tdc->dma_sconfig.src_addr_width;
 896                 *csr = 0;
 897                 return 0;
 898
 899         default:
 900                 dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
 901                 return -EINVAL;
 902         }
 903         return -EINVAL;
 904 }
 905
 906 static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
 907         struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
 908         enum dma_transfer_direction direction, unsigned long flags,
 909         void *context)
 910 {
 911         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 912         struct tegra_dma_desc *dma_desc;
 913         unsigned int        i;
 914         struct scatterlist      *sg;
 915         unsigned long csr, ahb_seq, apb_ptr, apb_seq;
 916         struct list_head req_list;
 917         struct tegra_dma_sg_req  *sg_req = NULL;
 918         u32 burst_size;
 919         enum dma_slave_buswidth slave_bw;
 920         int ret;
 921
 922         if (!tdc->config_init) {
 923                 dev_err(tdc2dev(tdc), "dma channel is not configured\n");
 924                 return NULL;
 925         }
 926         if (sg_len < 1) {
 927                 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
 928                 return NULL;
 929         }
 930
 931         ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
 932                                 &burst_size, &slave_bw);
 933         if (ret < 0)
 934                 return NULL;
 935
 936         INIT_LIST_HEAD(&req_list);
 937
 938         ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
 939         ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
 940                                         TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
 941         ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
 942
 943         csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
 944         csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
 945         if (flags & DMA_PREP_INTERRUPT)
 946                 csr |= TEGRA_APBDMA_CSR_IE_EOC;
 947
 948         apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
 949
 950         dma_desc = tegra_dma_desc_get(tdc);
 951         if (!dma_desc) {
 952                 dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
 953                 return NULL;
 954         }
 955         INIT_LIST_HEAD(&dma_desc->tx_list);
 956         INIT_LIST_HEAD(&dma_desc->cb_node);
 957         dma_desc->cb_count = 0;
 958         dma_desc->bytes_requested = 0;
 959         dma_desc->bytes_transferred = 0;
 960         dma_desc->dma_status = DMA_IN_PROGRESS;
 961
 962         /* Make transfer requests */
 963         for_each_sg(sgl, sg, sg_len, i) {
 964                 u32 len, mem;
 965
 966                 mem = sg_dma_address(sg);
 967                 len = sg_dma_len(sg);
 968
 969                 if ((len & 3) || (mem & 3) ||
 970                                 (len > tdc->tdma->chip_data->max_dma_count)) {
 971                         dev_err(tdc2dev(tdc),
 972                                 "Dma length/memory address is not supported\n");
 973                         tegra_dma_desc_put(tdc, dma_desc);
 974                         return NULL;
 975                 }
 976
 977                 sg_req = tegra_dma_sg_req_get(tdc);
 978                 if (!sg_req) {
 979                         dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
 980                         tegra_dma_desc_put(tdc, dma_desc);
 981                         return NULL;
 982                 }
 983
 984                 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
 985                 dma_desc->bytes_requested += len;
 986
 987                 sg_req->ch_regs.apb_ptr = apb_ptr;
 988                 sg_req->ch_regs.ahb_ptr = mem;
 989                 sg_req->ch_regs.csr = csr | ((len - 4) & 0xFFFC);
 990                 sg_req->ch_regs.apb_seq = apb_seq;
 991                 sg_req->ch_regs.ahb_seq = ahb_seq;
 992                 sg_req->configured = false;
 993                 sg_req->last_sg = false;
 994                 sg_req->dma_desc = dma_desc;
 995                 sg_req->req_len = len;
 996
 997                 list_add_tail(&sg_req->node, &dma_desc->tx_list);
 998         }
 999         sg_req->last_sg = true;
1000         if (flags & DMA_CTRL_ACK)
1001                 dma_desc->txd.flags = DMA_CTRL_ACK;
1002
1003         /*
1004          * Make sure that mode should not be conflicting with currently
1005          * configured mode.
1006          */
1007         if (!tdc->isr_handler) {
1008                 tdc->isr_handler = handle_once_dma_done;
1009                 tdc->cyclic = false;
1010         } else {
1011                 if (tdc->cyclic) {
1012                         dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
1013                         tegra_dma_desc_put(tdc, dma_desc);
1014                         return NULL;
1015                 }
1016         }
1017
1018         return &dma_desc->txd;
1019 }
1020
1021 static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
1022         struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
1023         size_t period_len, enum dma_transfer_direction direction,
1024         unsigned long flags, void *context)
1025 {
1026         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1027         struct tegra_dma_desc *dma_desc = NULL;
1028         struct tegra_dma_sg_req  *sg_req = NULL;
1029         unsigned long csr, ahb_seq, apb_ptr, apb_seq;
1030         int len;
1031         size_t remain_len;
1032         dma_addr_t mem = buf_addr;
1033         u32 burst_size;
1034         enum dma_slave_buswidth slave_bw;
1035         int ret;
1036
1037         if (!buf_len || !period_len) {
1038                 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
1039                 return NULL;
1040         }
1041
1042         if (!tdc->config_init) {
1043                 dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
1044                 return NULL;
1045         }
1046
1047         /*
1048          * We allow to take more number of requests till DMA is
1049          * not started. The driver will loop over all requests.
1050          * Once DMA is started then new requests can be queued only after
1051          * terminating the DMA.
1052          */
1053         if (tdc->busy) {
1054                 dev_err(tdc2dev(tdc), "Request not allowed when dma running\n");
1055                 return NULL;
1056         }
1057
1058         /*
1059          * We only support cycle transfer when buf_len is multiple of
1060          * period_len.
1061          */
1062         if (buf_len % period_len) {
1063                 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
1064                 return NULL;
1065         }
1066
1067         len = period_len;
1068         if ((len & 3) || (buf_addr & 3) ||
1069                         (len > tdc->tdma->chip_data->max_dma_count)) {
1070                 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
1071                 return NULL;
1072         }
1073
1074         ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
1075                                 &burst_size, &slave_bw);
1076         if (ret < 0)
1077                 return NULL;
1078
1079
1080         ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
1081         ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
1082                                         TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
1083         ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
1084
1085         csr |= TEGRA_APBDMA_CSR_FLOW;
1086         if (flags & DMA_PREP_INTERRUPT)
1087                 csr |= TEGRA_APBDMA_CSR_IE_EOC;
1088         csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
1089
1090         apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
1091
1092         dma_desc = tegra_dma_desc_get(tdc);
1093         if (!dma_desc) {
1094                 dev_err(tdc2dev(tdc), "not enough descriptors available\n");
1095                 return NULL;
1096         }
1097
1098         INIT_LIST_HEAD(&dma_desc->tx_list);
1099         INIT_LIST_HEAD(&dma_desc->cb_node);
1100         dma_desc->cb_count = 0;
1101
1102         dma_desc->bytes_transferred = 0;
1103         dma_desc->bytes_requested = buf_len;
1104         remain_len = buf_len;
1105
1106         /* Split transfer equal to period size */
1107         while (remain_len) {
1108                 sg_req = tegra_dma_sg_req_get(tdc);
1109                 if (!sg_req) {
1110                         dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
1111                         tegra_dma_desc_put(tdc, dma_desc);
1112                         return NULL;
1113                 }
1114
1115                 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1116                 sg_req->ch_regs.apb_ptr = apb_ptr;
1117                 sg_req->ch_regs.ahb_ptr = mem;
1118                 sg_req->ch_regs.csr = csr | ((len - 4) & 0xFFFC);
1119                 sg_req->ch_regs.apb_seq = apb_seq;
1120                 sg_req->ch_regs.ahb_seq = ahb_seq;
1121                 sg_req->configured = false;
1122                 sg_req->half_done = false;
1123                 sg_req->last_sg = false;
1124                 sg_req->dma_desc = dma_desc;
1125                 sg_req->req_len = len;
1126
1127                 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1128                 remain_len -= len;
1129                 mem += len;
1130         }
1131         sg_req->last_sg = true;
1132         if (flags & DMA_CTRL_ACK)
1133                 dma_desc->txd.flags = DMA_CTRL_ACK;
1134
1135         /*
1136          * Make sure that mode should not be conflicting with currently
1137          * configured mode.
1138          */
1139         if (!tdc->isr_handler) {
1140                 tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
1141                 tdc->cyclic = true;
1142         } else {
1143                 if (!tdc->cyclic) {
1144                         dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
1145                         tegra_dma_desc_put(tdc, dma_desc);
1146                         return NULL;
1147                 }
1148         }
1149
1150         return &dma_desc->txd;
1151 }
1152
1153 static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
1154 {
1155         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1156         struct tegra_dma *tdma = tdc->tdma;
1157         int ret;
1158
1159         dma_cookie_init(&tdc->dma_chan);
1160         tdc->config_init = false;
1161         ret = clk_prepare_enable(tdma->dma_clk);
1162         if (ret < 0)
1163                 dev_err(tdc2dev(tdc), "clk_prepare_enable failed: %d\n", ret);
1164         return ret;
1165 }
1166
1167 static void tegra_dma_free_chan_resources(struct dma_chan *dc)
1168 {
1169         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1170         struct tegra_dma *tdma = tdc->tdma;
1171
1172         struct tegra_dma_desc *dma_desc;
1173         struct tegra_dma_sg_req *sg_req;
1174         struct list_head dma_desc_list;
1175         struct list_head sg_req_list;
1176         unsigned long flags;
1177
1178         INIT_LIST_HEAD(&dma_desc_list);
1179         INIT_LIST_HEAD(&sg_req_list);
1180
1181         dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
1182
1183         if (tdc->busy)
1184                 tegra_dma_terminate_all(dc);
1185
1186         spin_lock_irqsave(&tdc->lock, flags);
1187         list_splice_init(&tdc->pending_sg_req, &sg_req_list);
1188         list_splice_init(&tdc->free_sg_req, &sg_req_list);
1189         list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
1190         INIT_LIST_HEAD(&tdc->cb_desc);
1191         tdc->config_init = false;
1192         tdc->isr_handler = NULL;
1193         spin_unlock_irqrestore(&tdc->lock, flags);
1194
1195         while (!list_empty(&dma_desc_list)) {
1196                 dma_desc = list_first_entry(&dma_desc_list,
1197                                         typeof(*dma_desc), node);
1198                 list_del(&dma_desc->node);
1199                 kfree(dma_desc);
1200         }
1201
1202         while (!list_empty(&sg_req_list)) {
1203                 sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
1204                 list_del(&sg_req->node);
1205                 kfree(sg_req);
1206         }
1207         clk_disable_unprepare(tdma->dma_clk);
1208 }
1209
1210 /* Tegra20 specific DMA controller information */
1211 static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
1212         .nr_channels            = 16,
1213         .max_dma_count          = 1024UL * 64,
1214         .support_channel_pause  = false,
1215 };
1216
1217 /* Tegra30 specific DMA controller information */
1218 static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
1219         .nr_channels            = 32,
1220         .max_dma_count          = 1024UL * 64,
1221         .support_channel_pause  = false,
1222 };
1223
1224 /* Tegra114 specific DMA controller information */
1225 static const struct tegra_dma_chip_data tegra114_dma_chip_data = {
1226         .nr_channels            = 32,
1227         .max_dma_count          = 1024UL * 64,
1228         .support_channel_pause  = true,
1229 };
1230
1231
1232 static const struct of_device_id tegra_dma_of_match[] = {
1233         {
1234                 .compatible = "nvidia,tegra114-apbdma",
1235                 .data = &tegra114_dma_chip_data,
1236         }, {
1237                 .compatible = "nvidia,tegra30-apbdma",
1238                 .data = &tegra30_dma_chip_data,
1239         }, {
1240                 .compatible = "nvidia,tegra20-apbdma",
1241                 .data = &tegra20_dma_chip_data,
1242         }, {
1243         },
1244 };
1245 MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
1246
1247 static int tegra_dma_probe(struct platform_device *pdev)
1248 {
1249         struct resource *res;
1250         struct tegra_dma *tdma;
1251         int ret;
1252         int i;
1253         const struct tegra_dma_chip_data *cdata = NULL;
1254         const struct of_device_id *match;
1255
1256         match = of_match_device(tegra_dma_of_match, &pdev->dev);
1257         if (!match) {
1258                 dev_err(&pdev->dev, "Error: No device match found\n");
1259                 return -ENODEV;
1260         }
1261         cdata = match->data;
1262
1263         tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
1264                         sizeof(struct tegra_dma_channel), GFP_KERNEL);
1265         if (!tdma) {
1266                 dev_err(&pdev->dev, "Error: memory allocation failed\n");
1267                 return -ENOMEM;
1268         }
1269
1270         tdma->dev = &pdev->dev;
1271         tdma->chip_data = cdata;
1272         platform_set_drvdata(pdev, tdma);
1273
1274         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1275         tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
1276         if (IS_ERR(tdma->base_addr))
1277                 return PTR_ERR(tdma->base_addr);
1278
1279         tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);
1280         if (IS_ERR(tdma->dma_clk)) {
1281                 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1282                 return PTR_ERR(tdma->dma_clk);
1283         }
1284
1285         spin_lock_init(&tdma->global_lock);
1286
1287         pm_runtime_enable(&pdev->dev);
1288         if (!pm_runtime_enabled(&pdev->dev)) {
1289                 ret = tegra_dma_runtime_resume(&pdev->dev);
1290                 if (ret) {
1291                         dev_err(&pdev->dev, "dma_runtime_resume failed %d\n",
1292                                 ret);
1293                         goto err_pm_disable;
1294                 }
1295         }
1296
1297         /* Enable clock before accessing registers */
1298         ret = clk_prepare_enable(tdma->dma_clk);
1299         if (ret < 0) {
1300                 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1301                 goto err_pm_disable;
1302         }
1303
1304         /* Reset DMA controller */
1305         tegra_periph_reset_assert(tdma->dma_clk);
1306         udelay(2);
1307         tegra_periph_reset_deassert(tdma->dma_clk);
1308
1309         /* Enable global DMA registers */
1310         tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
1311         tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1312         tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1313
1314         clk_disable_unprepare(tdma->dma_clk);
1315
1316         INIT_LIST_HEAD(&tdma->dma_dev.channels);
1317         for (i = 0; i < cdata->nr_channels; i++) {
1318                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1319
1320                 tdc->chan_base_offset = TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET +
1321                                         i * TEGRA_APBDMA_CHANNEL_REGISTER_SIZE;
1322
1323                 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1324                 if (!res) {
1325                         ret = -EINVAL;
1326                         dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1327                         goto err_irq;
1328                 }
1329                 tdc->irq = res->start;
1330                 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i);
1331                 ret = devm_request_irq(&pdev->dev, tdc->irq,
1332                                 tegra_dma_isr, 0, tdc->name, tdc);
1333                 if (ret) {
1334                         dev_err(&pdev->dev,
1335                                 "request_irq failed with err %d channel %d\n",
1336                                 ret, i);
1337                         goto err_irq;
1338                 }
1339
1340                 tdc->dma_chan.device = &tdma->dma_dev;
1341                 dma_cookie_init(&tdc->dma_chan);
1342                 list_add_tail(&tdc->dma_chan.device_node,
1343                                 &tdma->dma_dev.channels);
1344                 tdc->tdma = tdma;
1345                 tdc->id = i;
1346
1347                 tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
1348                                 (unsigned long)tdc);
1349                 spin_lock_init(&tdc->lock);
1350
1351                 INIT_LIST_HEAD(&tdc->pending_sg_req);
1352                 INIT_LIST_HEAD(&tdc->free_sg_req);
1353                 INIT_LIST_HEAD(&tdc->free_dma_desc);
1354                 INIT_LIST_HEAD(&tdc->cb_desc);
1355         }
1356
1357         dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
1358         dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
1359         dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
1360
1361         tdma->dma_dev.dev = &pdev->dev;
1362         tdma->dma_dev.device_alloc_chan_resources =
1363                                         tegra_dma_alloc_chan_resources;
1364         tdma->dma_dev.device_free_chan_resources =
1365                                         tegra_dma_free_chan_resources;
1366         tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
1367         tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
1368         tdma->dma_dev.device_control = tegra_dma_device_control;
1369         tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
1370         tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
1371
1372         ret = dma_async_device_register(&tdma->dma_dev);
1373         if (ret < 0) {
1374                 dev_err(&pdev->dev,
1375                         "Tegra20 APB DMA driver registration failed %d\n", ret);
1376                 goto err_irq;
1377         }
1378
1379         dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
1380                         cdata->nr_channels);
1381         return 0;
1382
1383 err_irq:
1384         while (--i >= 0) {
1385                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1386                 tasklet_kill(&tdc->tasklet);
1387         }
1388
1389 err_pm_disable:
1390         pm_runtime_disable(&pdev->dev);
1391         if (!pm_runtime_status_suspended(&pdev->dev))
1392                 tegra_dma_runtime_suspend(&pdev->dev);
1393         return ret;
1394 }
1395
1396 static int tegra_dma_remove(struct platform_device *pdev)
1397 {
1398         struct tegra_dma *tdma = platform_get_drvdata(pdev);
1399         int i;
1400         struct tegra_dma_channel *tdc;
1401
1402         dma_async_device_unregister(&tdma->dma_dev);
1403
1404         for (i = 0; i < tdma->chip_data->nr_channels; ++i) {
1405                 tdc = &tdma->channels[i];
1406                 tasklet_kill(&tdc->tasklet);
1407         }
1408
1409         pm_runtime_disable(&pdev->dev);
1410         if (!pm_runtime_status_suspended(&pdev->dev))
1411                 tegra_dma_runtime_suspend(&pdev->dev);
1412
1413         return 0;
1414 }
1415
1416 static int tegra_dma_runtime_suspend(struct device *dev)
1417 {
1418         struct platform_device *pdev = to_platform_device(dev);
1419         struct tegra_dma *tdma = platform_get_drvdata(pdev);
1420
1421         clk_disable_unprepare(tdma->dma_clk);
1422         return 0;
1423 }
1424
1425 static int tegra_dma_runtime_resume(struct device *dev)
1426 {
1427         struct platform_device *pdev = to_platform_device(dev);
1428         struct tegra_dma *tdma = platform_get_drvdata(pdev);
1429         int ret;
1430
1431         ret = clk_prepare_enable(tdma->dma_clk);
1432         if (ret < 0) {
1433                 dev_err(dev, "clk_enable failed: %d\n", ret);
1434                 return ret;
1435         }
1436         return 0;
1437 }
1438
1439 #ifdef CONFIG_PM_SLEEP
1440 static int tegra_dma_pm_suspend(struct device *dev)
1441 {
1442         struct tegra_dma *tdma = dev_get_drvdata(dev);
1443         int i;
1444         int ret;
1445
1446         /* Enable clock before accessing register */
1447         ret = tegra_dma_runtime_resume(dev);
1448         if (ret < 0)
1449                 return ret;
1450
1451         tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);
1452         for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1453                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1454                 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1455
1456                 ch_reg->csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
1457                 ch_reg->ahb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
1458                 ch_reg->apb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBPTR);
1459                 ch_reg->ahb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBSEQ);
1460                 ch_reg->apb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBSEQ);
1461         }
1462
1463         /* Disable clock */
1464         tegra_dma_runtime_suspend(dev);
1465         return 0;
1466 }
1467
1468 static int tegra_dma_pm_resume(struct device *dev)
1469 {
1470         struct tegra_dma *tdma = dev_get_drvdata(dev);
1471         int i;
1472         int ret;
1473
1474         /* Enable clock before accessing register */
1475         ret = tegra_dma_runtime_resume(dev);
1476         if (ret < 0)
1477                 return ret;
1478
1479         tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen);
1480         tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1481         tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1482
1483         for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1484                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1485                 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1486
1487                 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq);
1488                 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr);
1489                 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq);
1490                 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr);
1491                 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
1492                         (ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB));
1493         }
1494
1495         /* Disable clock */
1496         tegra_dma_runtime_suspend(dev);
1497         return 0;
1498 }
1499 #endif
1500
1501 static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
1502 #ifdef CONFIG_PM_RUNTIME
1503         .runtime_suspend = tegra_dma_runtime_suspend,
1504         .runtime_resume = tegra_dma_runtime_resume,
1505 #endif
1506         SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
1507 };
1508
1509 static struct platform_driver tegra_dmac_driver = {
1510         .driver = {
1511                 .name   = "tegra-apbdma",
1512                 .owner = THIS_MODULE,
1513                 .pm     = &tegra_dma_dev_pm_ops,
1514                 .of_match_table = tegra_dma_of_match,
1515         },
1516         .probe          = tegra_dma_probe,
1517         .remove         = tegra_dma_remove,
1518 };
1519
1520 module_platform_driver(tegra_dmac_driver);
1521
1522 MODULE_ALIAS("platform:tegra20-apbdma");
1523 MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
1524 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1525 MODULE_LICENSE("GPL v2");