drivers/dma/sh/shdmac.c

   1 /*
   2  * Renesas SuperH DMA Engine support
   3  *
   4  * base is drivers/dma/flsdma.c
   5  *
   6  * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
   8  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
   9  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * - DMA of SuperH does not have Hardware DMA chain mode.
  17  * - MAX DMA size is 16MB.
  18  *
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/slab.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/dmaengine.h>
  28 #include <linux/delay.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/notifier.h>
  33 #include <linux/kdebug.h>
  34 #include <linux/spinlock.h>
  35 #include <linux/rculist.h>
  36
  37 #include "../dmaengine.h"
  38 #include "shdma.h"
  39
  40 /* DMA register */
  41 #define SAR     0x00
  42 #define DAR     0x04
  43 #define TCR     0x08
  44 #define CHCR    0x0C
  45 #define DMAOR   0x40
  46
  47 #define TEND    0x18 /* USB-DMAC */
  48
  49 #define SH_DMAE_DRV_NAME "sh-dma-engine"
  50
  51 /* Default MEMCPY transfer size = 2^2 = 4 bytes */
  52 #define LOG2_DEFAULT_XFER_SIZE  2
  53 #define SH_DMA_SLAVE_NUMBER 256
  54 #define SH_DMA_TCR_MAX (16 * 1024 * 1024 - 1)
  55
  56 /*
  57  * Used for write-side mutual exclusion for the global device list,
  58  * read-side synchronization by way of RCU, and per-controller data.
  59  */
  60 static DEFINE_SPINLOCK(sh_dmae_lock);
  61 static LIST_HEAD(sh_dmae_devices);
  62
  63 /*
  64  * Different DMAC implementations provide different ways to clear DMA channels:
  65  * (1) none - no CHCLR registers are available
  66  * (2) one CHCLR register per channel - 0 has to be written to it to clear
  67  *     channel buffers
  68  * (3) one CHCLR per several channels - 1 has to be written to the bit,
  69  *     corresponding to the specific channel to reset it
  70  */
  71 static void channel_clear(struct sh_dmae_chan *sh_dc)
  72 {
  73         struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
  74         const struct sh_dmae_channel *chan_pdata = shdev->pdata->channel +
  75                 sh_dc->shdma_chan.id;
  76         u32 val = shdev->pdata->chclr_bitwise ? 1 << chan_pdata->chclr_bit : 0;
  77
  78         __raw_writel(val, shdev->chan_reg + chan_pdata->chclr_offset);
  79 }
  80
  81 static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
  82 {
  83         __raw_writel(data, sh_dc->base + reg);
  84 }
  85
  86 static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
  87 {
  88         return __raw_readl(sh_dc->base + reg);
  89 }
  90
  91 static u16 dmaor_read(struct sh_dmae_device *shdev)
  92 {
  93         void __iomem *addr = shdev->chan_reg + DMAOR;
  94
  95         if (shdev->pdata->dmaor_is_32bit)
  96                 return __raw_readl(addr);
  97         else
  98                 return __raw_readw(addr);
  99 }
 100
 101 static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
 102 {
 103         void __iomem *addr = shdev->chan_reg + DMAOR;
 104
 105         if (shdev->pdata->dmaor_is_32bit)
 106                 __raw_writel(data, addr);
 107         else
 108                 __raw_writew(data, addr);
 109 }
 110
 111 static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data)
 112 {
 113         struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
 114
 115         __raw_writel(data, sh_dc->base + shdev->chcr_offset);
 116 }
 117
 118 static u32 chcr_read(struct sh_dmae_chan *sh_dc)
 119 {
 120         struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
 121
 122         return __raw_readl(sh_dc->base + shdev->chcr_offset);
 123 }
 124
 125 /*
 126  * Reset DMA controller
 127  *
 128  * SH7780 has two DMAOR register
 129  */
 130 static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
 131 {
 132         unsigned short dmaor;
 133         unsigned long flags;
 134
 135         spin_lock_irqsave(&sh_dmae_lock, flags);
 136
 137         dmaor = dmaor_read(shdev);
 138         dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
 139
 140         spin_unlock_irqrestore(&sh_dmae_lock, flags);
 141 }
 142
 143 static int sh_dmae_rst(struct sh_dmae_device *shdev)
 144 {
 145         unsigned short dmaor;
 146         unsigned long flags;
 147
 148         spin_lock_irqsave(&sh_dmae_lock, flags);
 149
 150         dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME);
 151
 152         if (shdev->pdata->chclr_present) {
 153                 int i;
 154                 for (i = 0; i < shdev->pdata->channel_num; i++) {
 155                         struct sh_dmae_chan *sh_chan = shdev->chan[i];
 156                         if (sh_chan)
 157                                 channel_clear(sh_chan);
 158                 }
 159         }
 160
 161         dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init);
 162
 163         dmaor = dmaor_read(shdev);
 164
 165         spin_unlock_irqrestore(&sh_dmae_lock, flags);
 166
 167         if (dmaor & (DMAOR_AE | DMAOR_NMIF)) {
 168                 dev_warn(shdev->shdma_dev.dma_dev.dev, "Can't initialize DMAOR.\n");
 169                 return -EIO;
 170         }
 171         if (shdev->pdata->dmaor_init & ~dmaor)
 172                 dev_warn(shdev->shdma_dev.dma_dev.dev,
 173                          "DMAOR=0x%x hasn't latched the initial value 0x%x.\n",
 174                          dmaor, shdev->pdata->dmaor_init);
 175         return 0;
 176 }
 177
 178 static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
 179 {
 180         u32 chcr = chcr_read(sh_chan);
 181
 182         if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
 183                 return true; /* working */
 184
 185         return false; /* waiting */
 186 }
 187
 188 static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
 189 {
 190         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 191         const struct sh_dmae_pdata *pdata = shdev->pdata;
 192         int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
 193                 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
 194
 195         if (cnt >= pdata->ts_shift_num)
 196                 cnt = 0;
 197
 198         return pdata->ts_shift[cnt];
 199 }
 200
 201 static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
 202 {
 203         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 204         const struct sh_dmae_pdata *pdata = shdev->pdata;
 205         int i;
 206
 207         for (i = 0; i < pdata->ts_shift_num; i++)
 208                 if (pdata->ts_shift[i] == l2size)
 209                         break;
 210
 211         if (i == pdata->ts_shift_num)
 212                 i = 0;
 213
 214         return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
 215                 ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
 216 }
 217
 218 static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
 219 {
 220         sh_dmae_writel(sh_chan, hw->sar, SAR);
 221         sh_dmae_writel(sh_chan, hw->dar, DAR);
 222         sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
 223 }
 224
 225 static void dmae_start(struct sh_dmae_chan *sh_chan)
 226 {
 227         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 228         u32 chcr = chcr_read(sh_chan);
 229
 230         if (shdev->pdata->needs_tend_set)
 231                 sh_dmae_writel(sh_chan, 0xFFFFFFFF, TEND);
 232
 233         chcr |= CHCR_DE | shdev->chcr_ie_bit;
 234         chcr_write(sh_chan, chcr & ~CHCR_TE);
 235 }
 236
 237 static void dmae_init(struct sh_dmae_chan *sh_chan)
 238 {
 239         /*
 240          * Default configuration for dual address memory-memory transfer.
 241          * 0x400 represents auto-request.
 242          */
 243         u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
 244                                                    LOG2_DEFAULT_XFER_SIZE);
 245         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
 246         chcr_write(sh_chan, chcr);
 247 }
 248
 249 static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
 250 {
 251         /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */
 252         if (dmae_is_busy(sh_chan))
 253                 return -EBUSY;
 254
 255         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
 256         chcr_write(sh_chan, val);
 257
 258         return 0;
 259 }
 260
 261 static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
 262 {
 263         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 264         const struct sh_dmae_pdata *pdata = shdev->pdata;
 265         const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->shdma_chan.id];
 266         void __iomem *addr = shdev->dmars;
 267         unsigned int shift = chan_pdata->dmars_bit;
 268
 269         if (dmae_is_busy(sh_chan))
 270                 return -EBUSY;
 271
 272         if (pdata->no_dmars)
 273                 return 0;
 274
 275         /* in the case of a missing DMARS resource use first memory window */
 276         if (!addr)
 277                 addr = shdev->chan_reg;
 278         addr += chan_pdata->dmars;
 279
 280         __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
 281                      addr);
 282
 283         return 0;
 284 }
 285
 286 static void sh_dmae_start_xfer(struct shdma_chan *schan,
 287                                struct shdma_desc *sdesc)
 288 {
 289         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 290                                                     shdma_chan);
 291         struct sh_dmae_desc *sh_desc = container_of(sdesc,
 292                                         struct sh_dmae_desc, shdma_desc);
 293         dev_dbg(sh_chan->shdma_chan.dev, "Queue #%d to %d: %u@%x -> %x\n",
 294                 sdesc->async_tx.cookie, sh_chan->shdma_chan.id,
 295                 sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar);
 296         /* Get the ld start address from ld_queue */
 297         dmae_set_reg(sh_chan, &sh_desc->hw);
 298         dmae_start(sh_chan);
 299 }
 300
 301 static bool sh_dmae_channel_busy(struct shdma_chan *schan)
 302 {
 303         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 304                                                     shdma_chan);
 305         return dmae_is_busy(sh_chan);
 306 }
 307
 308 static void sh_dmae_setup_xfer(struct shdma_chan *schan,
 309                                int slave_id)
 310 {
 311         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 312                                                     shdma_chan);
 313
 314         if (slave_id >= 0) {
 315                 const struct sh_dmae_slave_config *cfg =
 316                         sh_chan->config;
 317
 318                 dmae_set_dmars(sh_chan, cfg->mid_rid);
 319                 dmae_set_chcr(sh_chan, cfg->chcr);
 320         } else {
 321                 dmae_init(sh_chan);
 322         }
 323 }
 324
 325 /*
 326  * Find a slave channel configuration from the contoller list by either a slave
 327  * ID in the non-DT case, or by a MID/RID value in the DT case
 328  */
 329 static const struct sh_dmae_slave_config *dmae_find_slave(
 330         struct sh_dmae_chan *sh_chan, int match)
 331 {
 332         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 333         const struct sh_dmae_pdata *pdata = shdev->pdata;
 334         const struct sh_dmae_slave_config *cfg;
 335         int i;
 336
 337         if (!sh_chan->shdma_chan.dev->of_node) {
 338                 if (match >= SH_DMA_SLAVE_NUMBER)
 339                         return NULL;
 340
 341                 for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
 342                         if (cfg->slave_id == match)
 343                                 return cfg;
 344         } else {
 345                 for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
 346                         if (cfg->mid_rid == match) {
 347                                 sh_chan->shdma_chan.slave_id = i;
 348                                 return cfg;
 349                         }
 350         }
 351
 352         return NULL;
 353 }
 354
 355 static int sh_dmae_set_slave(struct shdma_chan *schan,
 356                              int slave_id, dma_addr_t slave_addr, bool try)
 357 {
 358         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 359                                                     shdma_chan);
 360         const struct sh_dmae_slave_config *cfg = dmae_find_slave(sh_chan, slave_id);
 361         if (!cfg)
 362                 return -ENXIO;
 363
 364         if (!try) {
 365                 sh_chan->config = cfg;
 366                 sh_chan->slave_addr = slave_addr ? : cfg->addr;
 367         }
 368
 369         return 0;
 370 }
 371
 372 static void dmae_halt(struct sh_dmae_chan *sh_chan)
 373 {
 374         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 375         u32 chcr = chcr_read(sh_chan);
 376
 377         chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit);
 378         chcr_write(sh_chan, chcr);
 379 }
 380
 381 static int sh_dmae_desc_setup(struct shdma_chan *schan,
 382                               struct shdma_desc *sdesc,
 383                               dma_addr_t src, dma_addr_t dst, size_t *len)
 384 {
 385         struct sh_dmae_desc *sh_desc = container_of(sdesc,
 386                                         struct sh_dmae_desc, shdma_desc);
 387
 388         if (*len > schan->max_xfer_len)
 389                 *len = schan->max_xfer_len;
 390
 391         sh_desc->hw.sar = src;
 392         sh_desc->hw.dar = dst;
 393         sh_desc->hw.tcr = *len;
 394
 395         return 0;
 396 }
 397
 398 static void sh_dmae_halt(struct shdma_chan *schan)
 399 {
 400         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 401                                                     shdma_chan);
 402         dmae_halt(sh_chan);
 403 }
 404
 405 static bool sh_dmae_chan_irq(struct shdma_chan *schan, int irq)
 406 {
 407         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 408                                                     shdma_chan);
 409
 410         if (!(chcr_read(sh_chan) & CHCR_TE))
 411                 return false;
 412
 413         /* DMA stop */
 414         dmae_halt(sh_chan);
 415
 416         return true;
 417 }
 418
 419 static size_t sh_dmae_get_partial(struct shdma_chan *schan,
 420                                   struct shdma_desc *sdesc)
 421 {
 422         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 423                                                     shdma_chan);
 424         struct sh_dmae_desc *sh_desc = container_of(sdesc,
 425                                         struct sh_dmae_desc, shdma_desc);
 426         return sh_desc->hw.tcr -
 427                 (sh_dmae_readl(sh_chan, TCR) << sh_chan->xmit_shift);
 428 }
 429
 430 /* Called from error IRQ or NMI */
 431 static bool sh_dmae_reset(struct sh_dmae_device *shdev)
 432 {
 433         bool ret;
 434
 435         /* halt the dma controller */
 436         sh_dmae_ctl_stop(shdev);
 437
 438         /* We cannot detect, which channel caused the error, have to reset all */
 439         ret = shdma_reset(&shdev->shdma_dev);
 440
 441         sh_dmae_rst(shdev);
 442
 443         return ret;
 444 }
 445
 446 static irqreturn_t sh_dmae_err(int irq, void *data)
 447 {
 448         struct sh_dmae_device *shdev = data;
 449
 450         if (!(dmaor_read(shdev) & DMAOR_AE))
 451                 return IRQ_NONE;
 452
 453         sh_dmae_reset(shdev);
 454         return IRQ_HANDLED;
 455 }
 456
 457 static bool sh_dmae_desc_completed(struct shdma_chan *schan,
 458                                    struct shdma_desc *sdesc)
 459 {
 460         struct sh_dmae_chan *sh_chan = container_of(schan,
 461                                         struct sh_dmae_chan, shdma_chan);
 462         struct sh_dmae_desc *sh_desc = container_of(sdesc,
 463                                         struct sh_dmae_desc, shdma_desc);
 464         u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
 465         u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
 466
 467         return  (sdesc->direction == DMA_DEV_TO_MEM &&
 468                  (sh_desc->hw.dar + sh_desc->hw.tcr) == dar_buf) ||
 469                 (sdesc->direction != DMA_DEV_TO_MEM &&
 470                  (sh_desc->hw.sar + sh_desc->hw.tcr) == sar_buf);
 471 }
 472
 473 static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev)
 474 {
 475         /* Fast path out if NMIF is not asserted for this controller */
 476         if ((dmaor_read(shdev) & DMAOR_NMIF) == 0)
 477                 return false;
 478
 479         return sh_dmae_reset(shdev);
 480 }
 481
 482 static int sh_dmae_nmi_handler(struct notifier_block *self,
 483                                unsigned long cmd, void *data)
 484 {
 485         struct sh_dmae_device *shdev;
 486         int ret = NOTIFY_DONE;
 487         bool triggered;
 488
 489         /*
 490          * Only concern ourselves with NMI events.
 491          *
 492          * Normally we would check the die chain value, but as this needs
 493          * to be architecture independent, check for NMI context instead.
 494          */
 495         if (!in_nmi())
 496                 return NOTIFY_DONE;
 497
 498         rcu_read_lock();
 499         list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) {
 500                 /*
 501                  * Only stop if one of the controllers has NMIF asserted,
 502                  * we do not want to interfere with regular address error
 503                  * handling or NMI events that don't concern the DMACs.
 504                  */
 505                 triggered = sh_dmae_nmi_notify(shdev);
 506                 if (triggered == true)
 507                         ret = NOTIFY_OK;
 508         }
 509         rcu_read_unlock();
 510
 511         return ret;
 512 }
 513
 514 static struct notifier_block sh_dmae_nmi_notifier __read_mostly = {
 515         .notifier_call  = sh_dmae_nmi_handler,
 516
 517         /* Run before NMI debug handler and KGDB */
 518         .priority       = 1,
 519 };
 520
 521 static int sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
 522                                         int irq, unsigned long flags)
 523 {
 524         const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
 525         struct shdma_dev *sdev = &shdev->shdma_dev;
 526         struct platform_device *pdev = to_platform_device(sdev->dma_dev.dev);
 527         struct sh_dmae_chan *sh_chan;
 528         struct shdma_chan *schan;
 529         int err;
 530
 531         sh_chan = devm_kzalloc(sdev->dma_dev.dev, sizeof(struct sh_dmae_chan),
 532                                GFP_KERNEL);
 533         if (!sh_chan) {
 534                 dev_err(sdev->dma_dev.dev,
 535                         "No free memory for allocating dma channels!\n");
 536                 return -ENOMEM;
 537         }
 538
 539         schan = &sh_chan->shdma_chan;
 540         schan->max_xfer_len = SH_DMA_TCR_MAX + 1;
 541
 542         shdma_chan_probe(sdev, schan, id);
 543
 544         sh_chan->base = shdev->chan_reg + chan_pdata->offset;
 545
 546         /* set up channel irq */
 547         if (pdev->id >= 0)
 548                 snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
 549                          "sh-dmae%d.%d", pdev->id, id);
 550         else
 551                 snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
 552                          "sh-dma%d", id);
 553
 554         err = shdma_request_irq(schan, irq, flags, sh_chan->dev_id);
 555         if (err) {
 556                 dev_err(sdev->dma_dev.dev,
 557                         "DMA channel %d request_irq error %d\n",
 558                         id, err);
 559                 goto err_no_irq;
 560         }
 561
 562         shdev->chan[id] = sh_chan;
 563         return 0;
 564
 565 err_no_irq:
 566         /* remove from dmaengine device node */
 567         shdma_chan_remove(schan);
 568         return err;
 569 }
 570
 571 static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
 572 {
 573         struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev;
 574         struct shdma_chan *schan;
 575         int i;
 576
 577         shdma_for_each_chan(schan, &shdev->shdma_dev, i) {
 578                 BUG_ON(!schan);
 579
 580                 shdma_chan_remove(schan);
 581         }
 582         dma_dev->chancnt = 0;
 583 }
 584
 585 static void sh_dmae_shutdown(struct platform_device *pdev)
 586 {
 587         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
 588         sh_dmae_ctl_stop(shdev);
 589 }
 590
 591 static int sh_dmae_runtime_suspend(struct device *dev)
 592 {
 593         return 0;
 594 }
 595
 596 static int sh_dmae_runtime_resume(struct device *dev)
 597 {
 598         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
 599
 600         return sh_dmae_rst(shdev);
 601 }
 602
 603 #ifdef CONFIG_PM
 604 static int sh_dmae_suspend(struct device *dev)
 605 {
 606         return 0;
 607 }
 608
 609 static int sh_dmae_resume(struct device *dev)
 610 {
 611         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
 612         int i, ret;
 613
 614         ret = sh_dmae_rst(shdev);
 615         if (ret < 0)
 616                 dev_err(dev, "Failed to reset!\n");
 617
 618         for (i = 0; i < shdev->pdata->channel_num; i++) {
 619                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
 620
 621                 if (!sh_chan->shdma_chan.desc_num)
 622                         continue;
 623
 624                 if (sh_chan->shdma_chan.slave_id >= 0) {
 625                         const struct sh_dmae_slave_config *cfg = sh_chan->config;
 626                         dmae_set_dmars(sh_chan, cfg->mid_rid);
 627                         dmae_set_chcr(sh_chan, cfg->chcr);
 628                 } else {
 629                         dmae_init(sh_chan);
 630                 }
 631         }
 632
 633         return 0;
 634 }
 635 #else
 636 #define sh_dmae_suspend NULL
 637 #define sh_dmae_resume NULL
 638 #endif
 639
 640 const struct dev_pm_ops sh_dmae_pm = {
 641         .suspend                = sh_dmae_suspend,
 642         .resume                 = sh_dmae_resume,
 643         .runtime_suspend        = sh_dmae_runtime_suspend,
 644         .runtime_resume         = sh_dmae_runtime_resume,
 645 };
 646
 647 static dma_addr_t sh_dmae_slave_addr(struct shdma_chan *schan)
 648 {
 649         struct sh_dmae_chan *sh_chan = container_of(schan,
 650                                         struct sh_dmae_chan, shdma_chan);
 651
 652         /*
 653          * Implicit BUG_ON(!sh_chan->config)
 654          * This is an exclusive slave DMA operation, may only be called after a
 655          * successful slave configuration.
 656          */
 657         return sh_chan->slave_addr;
 658 }
 659
 660 static struct shdma_desc *sh_dmae_embedded_desc(void *buf, int i)
 661 {
 662         return &((struct sh_dmae_desc *)buf)[i].shdma_desc;
 663 }
 664
 665 static const struct shdma_ops sh_dmae_shdma_ops = {
 666         .desc_completed = sh_dmae_desc_completed,
 667         .halt_channel = sh_dmae_halt,
 668         .channel_busy = sh_dmae_channel_busy,
 669         .slave_addr = sh_dmae_slave_addr,
 670         .desc_setup = sh_dmae_desc_setup,
 671         .set_slave = sh_dmae_set_slave,
 672         .setup_xfer = sh_dmae_setup_xfer,
 673         .start_xfer = sh_dmae_start_xfer,
 674         .embedded_desc = sh_dmae_embedded_desc,
 675         .chan_irq = sh_dmae_chan_irq,
 676         .get_partial = sh_dmae_get_partial,
 677 };
 678
 679 static const struct of_device_id sh_dmae_of_match[] = {
 680         {.compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid,},
 681         {}
 682 };
 683 MODULE_DEVICE_TABLE(of, sh_dmae_of_match);
 684
 685 static int sh_dmae_probe(struct platform_device *pdev)
 686 {
 687         const struct sh_dmae_pdata *pdata;
 688         unsigned long irqflags = 0,
 689                 chan_flag[SH_DMAE_MAX_CHANNELS] = {};
 690         int errirq, chan_irq[SH_DMAE_MAX_CHANNELS];
 691         int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
 692         struct sh_dmae_device *shdev;
 693         struct dma_device *dma_dev;
 694         struct resource *chan, *dmars, *errirq_res, *chanirq_res;
 695
 696         if (pdev->dev.of_node)
 697                 pdata = of_match_device(sh_dmae_of_match, &pdev->dev)->data;
 698         else
 699                 pdata = dev_get_platdata(&pdev->dev);
 700
 701         /* get platform data */
 702         if (!pdata || !pdata->channel_num)
 703                 return -ENODEV;
 704
 705         chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 706         /* DMARS area is optional */
 707         dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 708         /*
 709          * IRQ resources:
 710          * 1. there always must be at least one IRQ IO-resource. On SH4 it is
 711          *    the error IRQ, in which case it is the only IRQ in this resource:
 712          *    start == end. If it is the only IRQ resource, all channels also
 713          *    use the same IRQ.
 714          * 2. DMA channel IRQ resources can be specified one per resource or in
 715          *    ranges (start != end)
 716          * 3. iff all events (channels and, optionally, error) on this
 717          *    controller use the same IRQ, only one IRQ resource can be
 718          *    specified, otherwise there must be one IRQ per channel, even if
 719          *    some of them are equal
 720          * 4. if all IRQs on this controller are equal or if some specific IRQs
 721          *    specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
 722          *    requested with the IRQF_SHARED flag
 723          */
 724         errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 725         if (!chan || !errirq_res)
 726                 return -ENODEV;
 727
 728         shdev = devm_kzalloc(&pdev->dev, sizeof(struct sh_dmae_device),
 729                              GFP_KERNEL);
 730         if (!shdev) {
 731                 dev_err(&pdev->dev, "Not enough memory\n");
 732                 return -ENOMEM;
 733         }
 734
 735         dma_dev = &shdev->shdma_dev.dma_dev;
 736
 737         shdev->chan_reg = devm_ioremap_resource(&pdev->dev, chan);
 738         if (IS_ERR(shdev->chan_reg))
 739                 return PTR_ERR(shdev->chan_reg);
 740         if (dmars) {
 741                 shdev->dmars = devm_ioremap_resource(&pdev->dev, dmars);
 742                 if (IS_ERR(shdev->dmars))
 743                         return PTR_ERR(shdev->dmars);
 744         }
 745
 746         if (!pdata->slave_only)
 747                 dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
 748         if (pdata->slave && pdata->slave_num)
 749                 dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
 750
 751         /* Default transfer size of 32 bytes requires 32-byte alignment */
 752         dma_dev->copy_align = LOG2_DEFAULT_XFER_SIZE;
 753
 754         shdev->shdma_dev.ops = &sh_dmae_shdma_ops;
 755         shdev->shdma_dev.desc_size = sizeof(struct sh_dmae_desc);
 756         err = shdma_init(&pdev->dev, &shdev->shdma_dev,
 757                               pdata->channel_num);
 758         if (err < 0)
 759                 goto eshdma;
 760
 761         /* platform data */
 762         shdev->pdata = pdata;
 763
 764         if (pdata->chcr_offset)
 765                 shdev->chcr_offset = pdata->chcr_offset;
 766         else
 767                 shdev->chcr_offset = CHCR;
 768
 769         if (pdata->chcr_ie_bit)
 770                 shdev->chcr_ie_bit = pdata->chcr_ie_bit;
 771         else
 772                 shdev->chcr_ie_bit = CHCR_IE;
 773
 774         platform_set_drvdata(pdev, shdev);
 775
 776         pm_runtime_enable(&pdev->dev);
 777         err = pm_runtime_get_sync(&pdev->dev);
 778         if (err < 0)
 779                 dev_err(&pdev->dev, "%s(): GET = %d\n", __func__, err);
 780
 781         spin_lock_irq(&sh_dmae_lock);
 782         list_add_tail_rcu(&shdev->node, &sh_dmae_devices);
 783         spin_unlock_irq(&sh_dmae_lock);
 784
 785         /* reset dma controller - only needed as a test */
 786         err = sh_dmae_rst(shdev);
 787         if (err)
 788                 goto rst_err;
 789
 790 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 791         chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
 792
 793         if (!chanirq_res)
 794                 chanirq_res = errirq_res;
 795         else
 796                 irqres++;
 797
 798         if (chanirq_res == errirq_res ||
 799             (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
 800                 irqflags = IRQF_SHARED;
 801
 802         errirq = errirq_res->start;
 803
 804         err = devm_request_irq(&pdev->dev, errirq, sh_dmae_err, irqflags,
 805                                "DMAC Address Error", shdev);
 806         if (err) {
 807                 dev_err(&pdev->dev,
 808                         "DMA failed requesting irq #%d, error %d\n",
 809                         errirq, err);
 810                 goto eirq_err;
 811         }
 812
 813 #else
 814         chanirq_res = errirq_res;
 815 #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
 816
 817         if (chanirq_res->start == chanirq_res->end &&
 818             !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
 819                 /* Special case - all multiplexed */
 820                 for (; irq_cnt < pdata->channel_num; irq_cnt++) {
 821                         if (irq_cnt < SH_DMAE_MAX_CHANNELS) {
 822                                 chan_irq[irq_cnt] = chanirq_res->start;
 823                                 chan_flag[irq_cnt] = IRQF_SHARED;
 824                         } else {
 825                                 irq_cap = 1;
 826                                 break;
 827                         }
 828                 }
 829         } else {
 830                 do {
 831                         for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
 832                                 if (irq_cnt >= SH_DMAE_MAX_CHANNELS) {
 833                                         irq_cap = 1;
 834                                         break;
 835                                 }
 836
 837                                 if ((errirq_res->flags & IORESOURCE_BITS) ==
 838                                     IORESOURCE_IRQ_SHAREABLE)
 839                                         chan_flag[irq_cnt] = IRQF_SHARED;
 840                                 else
 841                                         chan_flag[irq_cnt] = 0;
 842                                 dev_dbg(&pdev->dev,
 843                                         "Found IRQ %d for channel %d\n",
 844                                         i, irq_cnt);
 845                                 chan_irq[irq_cnt++] = i;
 846                         }
 847
 848                         if (irq_cnt >= SH_DMAE_MAX_CHANNELS)
 849                                 break;
 850
 851                         chanirq_res = platform_get_resource(pdev,
 852                                                 IORESOURCE_IRQ, ++irqres);
 853                 } while (irq_cnt < pdata->channel_num && chanirq_res);
 854         }
 855
 856         /* Create DMA Channel */
 857         for (i = 0; i < irq_cnt; i++) {
 858                 err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
 859                 if (err)
 860                         goto chan_probe_err;
 861         }
 862
 863         if (irq_cap)
 864                 dev_notice(&pdev->dev, "Attempting to register %d DMA "
 865                            "channels when a maximum of %d are supported.\n",
 866                            pdata->channel_num, SH_DMAE_MAX_CHANNELS);
 867
 868         pm_runtime_put(&pdev->dev);
 869
 870         err = dma_async_device_register(&shdev->shdma_dev.dma_dev);
 871         if (err < 0)
 872                 goto edmadevreg;
 873
 874         return err;
 875
 876 edmadevreg:
 877         pm_runtime_get(&pdev->dev);
 878
 879 chan_probe_err:
 880         sh_dmae_chan_remove(shdev);
 881
 882 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 883 eirq_err:
 884 #endif
 885 rst_err:
 886         spin_lock_irq(&sh_dmae_lock);
 887         list_del_rcu(&shdev->node);
 888         spin_unlock_irq(&sh_dmae_lock);
 889
 890         pm_runtime_put(&pdev->dev);
 891         pm_runtime_disable(&pdev->dev);
 892
 893         shdma_cleanup(&shdev->shdma_dev);
 894 eshdma:
 895         synchronize_rcu();
 896
 897         return err;
 898 }
 899
 900 static int sh_dmae_remove(struct platform_device *pdev)
 901 {
 902         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
 903         struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev;
 904
 905         dma_async_device_unregister(dma_dev);
 906
 907         spin_lock_irq(&sh_dmae_lock);
 908         list_del_rcu(&shdev->node);
 909         spin_unlock_irq(&sh_dmae_lock);
 910
 911         pm_runtime_disable(&pdev->dev);
 912
 913         sh_dmae_chan_remove(shdev);
 914         shdma_cleanup(&shdev->shdma_dev);
 915
 916         synchronize_rcu();
 917
 918         return 0;
 919 }
 920
 921 static struct platform_driver sh_dmae_driver = {
 922         .driver         = {
 923                 .owner  = THIS_MODULE,
 924                 .pm     = &sh_dmae_pm,
 925                 .name   = SH_DMAE_DRV_NAME,
 926                 .of_match_table = sh_dmae_of_match,
 927         },
 928         .remove         = sh_dmae_remove,
 929         .shutdown       = sh_dmae_shutdown,
 930 };
 931
 932 static int __init sh_dmae_init(void)
 933 {
 934         /* Wire up NMI handling */
 935         int err = register_die_notifier(&sh_dmae_nmi_notifier);
 936         if (err)
 937                 return err;
 938
 939         return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
 940 }
 941 module_init(sh_dmae_init);
 942
 943 static void __exit sh_dmae_exit(void)
 944 {
 945         platform_driver_unregister(&sh_dmae_driver);
 946
 947         unregister_die_notifier(&sh_dmae_nmi_notifier);
 948 }
 949 module_exit(sh_dmae_exit);
 950
 951 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
 952 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
 953 MODULE_LICENSE("GPL");
 954 MODULE_ALIAS("platform:" SH_DMAE_DRV_NAME);