drivers/dma/ipu/ipu_idmac.c

   1 /*
   2  * Copyright (C) 2008
   3  * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
   4  *
   5  * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/dma-mapping.h>
  13 #include <linux/init.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/err.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/delay.h>
  18 #include <linux/list.h>
  19 #include <linux/clk.h>
  20 #include <linux/vmalloc.h>
  21 #include <linux/string.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/module.h>
  25 #include <linux/dma/ipu-dma.h>
  26
  27 #include "../dmaengine.h"
  28 #include "ipu_intern.h"
  29
  30 #define FS_VF_IN_VALID  0x00000002
  31 #define FS_ENC_IN_VALID 0x00000001
  32
  33 static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
  34                                bool wait_for_stop);
  35
  36 /*
  37  * There can be only one, we could allocate it dynamically, but then we'd have
  38  * to add an extra parameter to some functions, and use something as ugly as
  39  *      struct ipu *ipu = to_ipu(to_idmac(ichan->dma_chan.device));
  40  * in the ISR
  41  */
  42 static struct ipu ipu_data;
  43
  44 #define to_ipu(id) container_of(id, struct ipu, idmac)
  45
  46 static u32 __idmac_read_icreg(struct ipu *ipu, unsigned long reg)
  47 {
  48         return __raw_readl(ipu->reg_ic + reg);
  49 }
  50
  51 #define idmac_read_icreg(ipu, reg) __idmac_read_icreg(ipu, reg - IC_CONF)
  52
  53 static void __idmac_write_icreg(struct ipu *ipu, u32 value, unsigned long reg)
  54 {
  55         __raw_writel(value, ipu->reg_ic + reg);
  56 }
  57
  58 #define idmac_write_icreg(ipu, v, reg) __idmac_write_icreg(ipu, v, reg - IC_CONF)
  59
  60 static u32 idmac_read_ipureg(struct ipu *ipu, unsigned long reg)
  61 {
  62         return __raw_readl(ipu->reg_ipu + reg);
  63 }
  64
  65 static void idmac_write_ipureg(struct ipu *ipu, u32 value, unsigned long reg)
  66 {
  67         __raw_writel(value, ipu->reg_ipu + reg);
  68 }
  69
  70 /*****************************************************************************
  71  * IPU / IC common functions
  72  */
  73 static void dump_idmac_reg(struct ipu *ipu)
  74 {
  75         dev_dbg(ipu->dev, "IDMAC_CONF 0x%x, IC_CONF 0x%x, IDMAC_CHA_EN 0x%x, "
  76                 "IDMAC_CHA_PRI 0x%x, IDMAC_CHA_BUSY 0x%x\n",
  77                 idmac_read_icreg(ipu, IDMAC_CONF),
  78                 idmac_read_icreg(ipu, IC_CONF),
  79                 idmac_read_icreg(ipu, IDMAC_CHA_EN),
  80                 idmac_read_icreg(ipu, IDMAC_CHA_PRI),
  81                 idmac_read_icreg(ipu, IDMAC_CHA_BUSY));
  82         dev_dbg(ipu->dev, "BUF0_RDY 0x%x, BUF1_RDY 0x%x, CUR_BUF 0x%x, "
  83                 "DB_MODE 0x%x, TASKS_STAT 0x%x\n",
  84                 idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
  85                 idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
  86                 idmac_read_ipureg(ipu, IPU_CHA_CUR_BUF),
  87                 idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL),
  88                 idmac_read_ipureg(ipu, IPU_TASKS_STAT));
  89 }
  90
  91 static uint32_t bytes_per_pixel(enum pixel_fmt fmt)
  92 {
  93         switch (fmt) {
  94         case IPU_PIX_FMT_GENERIC:       /* generic data */
  95         case IPU_PIX_FMT_RGB332:
  96         case IPU_PIX_FMT_YUV420P:
  97         case IPU_PIX_FMT_YUV422P:
  98         default:
  99                 return 1;
 100         case IPU_PIX_FMT_RGB565:
 101         case IPU_PIX_FMT_YUYV:
 102         case IPU_PIX_FMT_UYVY:
 103                 return 2;
 104         case IPU_PIX_FMT_BGR24:
 105         case IPU_PIX_FMT_RGB24:
 106                 return 3;
 107         case IPU_PIX_FMT_GENERIC_32:    /* generic data */
 108         case IPU_PIX_FMT_BGR32:
 109         case IPU_PIX_FMT_RGB32:
 110         case IPU_PIX_FMT_ABGR32:
 111                 return 4;
 112         }
 113 }
 114
 115 /* Enable direct write to memory by the Camera Sensor Interface */
 116 static void ipu_ic_enable_task(struct ipu *ipu, enum ipu_channel channel)
 117 {
 118         uint32_t ic_conf, mask;
 119
 120         switch (channel) {
 121         case IDMAC_IC_0:
 122                 mask = IC_CONF_PRPENC_EN;
 123                 break;
 124         case IDMAC_IC_7:
 125                 mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
 126                 break;
 127         default:
 128                 return;
 129         }
 130         ic_conf = idmac_read_icreg(ipu, IC_CONF) | mask;
 131         idmac_write_icreg(ipu, ic_conf, IC_CONF);
 132 }
 133
 134 /* Called under spin_lock_irqsave(&ipu_data.lock) */
 135 static void ipu_ic_disable_task(struct ipu *ipu, enum ipu_channel channel)
 136 {
 137         uint32_t ic_conf, mask;
 138
 139         switch (channel) {
 140         case IDMAC_IC_0:
 141                 mask = IC_CONF_PRPENC_EN;
 142                 break;
 143         case IDMAC_IC_7:
 144                 mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
 145                 break;
 146         default:
 147                 return;
 148         }
 149         ic_conf = idmac_read_icreg(ipu, IC_CONF) & ~mask;
 150         idmac_write_icreg(ipu, ic_conf, IC_CONF);
 151 }
 152
 153 static uint32_t ipu_channel_status(struct ipu *ipu, enum ipu_channel channel)
 154 {
 155         uint32_t stat = TASK_STAT_IDLE;
 156         uint32_t task_stat_reg = idmac_read_ipureg(ipu, IPU_TASKS_STAT);
 157
 158         switch (channel) {
 159         case IDMAC_IC_7:
 160                 stat = (task_stat_reg & TSTAT_CSI2MEM_MASK) >>
 161                         TSTAT_CSI2MEM_OFFSET;
 162                 break;
 163         case IDMAC_IC_0:
 164         case IDMAC_SDC_0:
 165         case IDMAC_SDC_1:
 166         default:
 167                 break;
 168         }
 169         return stat;
 170 }
 171
 172 struct chan_param_mem_planar {
 173         /* Word 0 */
 174         u32     xv:10;
 175         u32     yv:10;
 176         u32     xb:12;
 177
 178         u32     yb:12;
 179         u32     res1:2;
 180         u32     nsb:1;
 181         u32     lnpb:6;
 182         u32     ubo_l:11;
 183
 184         u32     ubo_h:15;
 185         u32     vbo_l:17;
 186
 187         u32     vbo_h:9;
 188         u32     res2:3;
 189         u32     fw:12;
 190         u32     fh_l:8;
 191
 192         u32     fh_h:4;
 193         u32     res3:28;
 194
 195         /* Word 1 */
 196         u32     eba0;
 197
 198         u32     eba1;
 199
 200         u32     bpp:3;
 201         u32     sl:14;
 202         u32     pfs:3;
 203         u32     bam:3;
 204         u32     res4:2;
 205         u32     npb:6;
 206         u32     res5:1;
 207
 208         u32     sat:2;
 209         u32     res6:30;
 210 } __attribute__ ((packed));
 211
 212 struct chan_param_mem_interleaved {
 213         /* Word 0 */
 214         u32     xv:10;
 215         u32     yv:10;
 216         u32     xb:12;
 217
 218         u32     yb:12;
 219         u32     sce:1;
 220         u32     res1:1;
 221         u32     nsb:1;
 222         u32     lnpb:6;
 223         u32     sx:10;
 224         u32     sy_l:1;
 225
 226         u32     sy_h:9;
 227         u32     ns:10;
 228         u32     sm:10;
 229         u32     sdx_l:3;
 230
 231         u32     sdx_h:2;
 232         u32     sdy:5;
 233         u32     sdrx:1;
 234         u32     sdry:1;
 235         u32     sdr1:1;
 236         u32     res2:2;
 237         u32     fw:12;
 238         u32     fh_l:8;
 239
 240         u32     fh_h:4;
 241         u32     res3:28;
 242
 243         /* Word 1 */
 244         u32     eba0;
 245
 246         u32     eba1;
 247
 248         u32     bpp:3;
 249         u32     sl:14;
 250         u32     pfs:3;
 251         u32     bam:3;
 252         u32     res4:2;
 253         u32     npb:6;
 254         u32     res5:1;
 255
 256         u32     sat:2;
 257         u32     scc:1;
 258         u32     ofs0:5;
 259         u32     ofs1:5;
 260         u32     ofs2:5;
 261         u32     ofs3:5;
 262         u32     wid0:3;
 263         u32     wid1:3;
 264         u32     wid2:3;
 265
 266         u32     wid3:3;
 267         u32     dec_sel:1;
 268         u32     res6:28;
 269 } __attribute__ ((packed));
 270
 271 union chan_param_mem {
 272         struct chan_param_mem_planar            pp;
 273         struct chan_param_mem_interleaved       ip;
 274 };
 275
 276 static void ipu_ch_param_set_plane_offset(union chan_param_mem *params,
 277                                           u32 u_offset, u32 v_offset)
 278 {
 279         params->pp.ubo_l = u_offset & 0x7ff;
 280         params->pp.ubo_h = u_offset >> 11;
 281         params->pp.vbo_l = v_offset & 0x1ffff;
 282         params->pp.vbo_h = v_offset >> 17;
 283 }
 284
 285 static void ipu_ch_param_set_size(union chan_param_mem *params,
 286                                   uint32_t pixel_fmt, uint16_t width,
 287                                   uint16_t height, uint16_t stride)
 288 {
 289         u32 u_offset;
 290         u32 v_offset;
 291
 292         params->pp.fw           = width - 1;
 293         params->pp.fh_l         = height - 1;
 294         params->pp.fh_h         = (height - 1) >> 8;
 295         params->pp.sl           = stride - 1;
 296
 297         switch (pixel_fmt) {
 298         case IPU_PIX_FMT_GENERIC:
 299                 /*Represents 8-bit Generic data */
 300                 params->pp.bpp  = 3;
 301                 params->pp.pfs  = 7;
 302                 params->pp.npb  = 31;
 303                 params->pp.sat  = 2;            /* SAT = use 32-bit access */
 304                 break;
 305         case IPU_PIX_FMT_GENERIC_32:
 306                 /*Represents 32-bit Generic data */
 307                 params->pp.bpp  = 0;
 308                 params->pp.pfs  = 7;
 309                 params->pp.npb  = 7;
 310                 params->pp.sat  = 2;            /* SAT = use 32-bit access */
 311                 break;
 312         case IPU_PIX_FMT_RGB565:
 313                 params->ip.bpp  = 2;
 314                 params->ip.pfs  = 4;
 315                 params->ip.npb  = 15;
 316                 params->ip.sat  = 2;            /* SAT = 32-bit access */
 317                 params->ip.ofs0 = 0;            /* Red bit offset */
 318                 params->ip.ofs1 = 5;            /* Green bit offset */
 319                 params->ip.ofs2 = 11;           /* Blue bit offset */
 320                 params->ip.ofs3 = 16;           /* Alpha bit offset */
 321                 params->ip.wid0 = 4;            /* Red bit width - 1 */
 322                 params->ip.wid1 = 5;            /* Green bit width - 1 */
 323                 params->ip.wid2 = 4;            /* Blue bit width - 1 */
 324                 break;
 325         case IPU_PIX_FMT_BGR24:
 326                 params->ip.bpp  = 1;            /* 24 BPP & RGB PFS */
 327                 params->ip.pfs  = 4;
 328                 params->ip.npb  = 7;
 329                 params->ip.sat  = 2;            /* SAT = 32-bit access */
 330                 params->ip.ofs0 = 0;            /* Red bit offset */
 331                 params->ip.ofs1 = 8;            /* Green bit offset */
 332                 params->ip.ofs2 = 16;           /* Blue bit offset */
 333                 params->ip.ofs3 = 24;           /* Alpha bit offset */
 334                 params->ip.wid0 = 7;            /* Red bit width - 1 */
 335                 params->ip.wid1 = 7;            /* Green bit width - 1 */
 336                 params->ip.wid2 = 7;            /* Blue bit width - 1 */
 337                 break;
 338         case IPU_PIX_FMT_RGB24:
 339                 params->ip.bpp  = 1;            /* 24 BPP & RGB PFS */
 340                 params->ip.pfs  = 4;
 341                 params->ip.npb  = 7;
 342                 params->ip.sat  = 2;            /* SAT = 32-bit access */
 343                 params->ip.ofs0 = 16;           /* Red bit offset */
 344                 params->ip.ofs1 = 8;            /* Green bit offset */
 345                 params->ip.ofs2 = 0;            /* Blue bit offset */
 346                 params->ip.ofs3 = 24;           /* Alpha bit offset */
 347                 params->ip.wid0 = 7;            /* Red bit width - 1 */
 348                 params->ip.wid1 = 7;            /* Green bit width - 1 */
 349                 params->ip.wid2 = 7;            /* Blue bit width - 1 */
 350                 break;
 351         case IPU_PIX_FMT_BGRA32:
 352         case IPU_PIX_FMT_BGR32:
 353         case IPU_PIX_FMT_ABGR32:
 354                 params->ip.bpp  = 0;
 355                 params->ip.pfs  = 4;
 356                 params->ip.npb  = 7;
 357                 params->ip.sat  = 2;            /* SAT = 32-bit access */
 358                 params->ip.ofs0 = 8;            /* Red bit offset */
 359                 params->ip.ofs1 = 16;           /* Green bit offset */
 360                 params->ip.ofs2 = 24;           /* Blue bit offset */
 361                 params->ip.ofs3 = 0;            /* Alpha bit offset */
 362                 params->ip.wid0 = 7;            /* Red bit width - 1 */
 363                 params->ip.wid1 = 7;            /* Green bit width - 1 */
 364                 params->ip.wid2 = 7;            /* Blue bit width - 1 */
 365                 params->ip.wid3 = 7;            /* Alpha bit width - 1 */
 366                 break;
 367         case IPU_PIX_FMT_RGBA32:
 368         case IPU_PIX_FMT_RGB32:
 369                 params->ip.bpp  = 0;
 370                 params->ip.pfs  = 4;
 371                 params->ip.npb  = 7;
 372                 params->ip.sat  = 2;            /* SAT = 32-bit access */
 373                 params->ip.ofs0 = 24;           /* Red bit offset */
 374                 params->ip.ofs1 = 16;           /* Green bit offset */
 375                 params->ip.ofs2 = 8;            /* Blue bit offset */
 376                 params->ip.ofs3 = 0;            /* Alpha bit offset */
 377                 params->ip.wid0 = 7;            /* Red bit width - 1 */
 378                 params->ip.wid1 = 7;            /* Green bit width - 1 */
 379                 params->ip.wid2 = 7;            /* Blue bit width - 1 */
 380                 params->ip.wid3 = 7;            /* Alpha bit width - 1 */
 381                 break;
 382         case IPU_PIX_FMT_UYVY:
 383                 params->ip.bpp  = 2;
 384                 params->ip.pfs  = 6;
 385                 params->ip.npb  = 7;
 386                 params->ip.sat  = 2;            /* SAT = 32-bit access */
 387                 break;
 388         case IPU_PIX_FMT_YUV420P2:
 389         case IPU_PIX_FMT_YUV420P:
 390                 params->ip.bpp  = 3;
 391                 params->ip.pfs  = 3;
 392                 params->ip.npb  = 7;
 393                 params->ip.sat  = 2;            /* SAT = 32-bit access */
 394                 u_offset = stride * height;
 395                 v_offset = u_offset + u_offset / 4;
 396                 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
 397                 break;
 398         case IPU_PIX_FMT_YVU422P:
 399                 params->ip.bpp  = 3;
 400                 params->ip.pfs  = 2;
 401                 params->ip.npb  = 7;
 402                 params->ip.sat  = 2;            /* SAT = 32-bit access */
 403                 v_offset = stride * height;
 404                 u_offset = v_offset + v_offset / 2;
 405                 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
 406                 break;
 407         case IPU_PIX_FMT_YUV422P:
 408                 params->ip.bpp  = 3;
 409                 params->ip.pfs  = 2;
 410                 params->ip.npb  = 7;
 411                 params->ip.sat  = 2;            /* SAT = 32-bit access */
 412                 u_offset = stride * height;
 413                 v_offset = u_offset + u_offset / 2;
 414                 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
 415                 break;
 416         default:
 417                 dev_err(ipu_data.dev,
 418                         "mx3 ipu: unimplemented pixel format %d\n", pixel_fmt);
 419                 break;
 420         }
 421
 422         params->pp.nsb = 1;
 423 }
 424
 425 static void ipu_ch_param_set_buffer(union chan_param_mem *params,
 426                                     dma_addr_t buf0, dma_addr_t buf1)
 427 {
 428         params->pp.eba0 = buf0;
 429         params->pp.eba1 = buf1;
 430 }
 431
 432 static void ipu_ch_param_set_rotation(union chan_param_mem *params,
 433                                       enum ipu_rotate_mode rotate)
 434 {
 435         params->pp.bam = rotate;
 436 }
 437
 438 static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
 439                                 uint32_t num_words)
 440 {
 441         for (; num_words > 0; num_words--) {
 442                 dev_dbg(ipu_data.dev,
 443                         "write param mem - addr = 0x%08X, data = 0x%08X\n",
 444                         addr, *data);
 445                 idmac_write_ipureg(&ipu_data, addr, IPU_IMA_ADDR);
 446                 idmac_write_ipureg(&ipu_data, *data++, IPU_IMA_DATA);
 447                 addr++;
 448                 if ((addr & 0x7) == 5) {
 449                         addr &= ~0x7;   /* set to word 0 */
 450                         addr += 8;      /* increment to next row */
 451                 }
 452         }
 453 }
 454
 455 static int calc_resize_coeffs(uint32_t in_size, uint32_t out_size,
 456                               uint32_t *resize_coeff,
 457                               uint32_t *downsize_coeff)
 458 {
 459         uint32_t temp_size;
 460         uint32_t temp_downsize;
 461
 462         *resize_coeff   = 1 << 13;
 463         *downsize_coeff = 1 << 13;
 464
 465         /* Cannot downsize more than 8:1 */
 466         if (out_size << 3 < in_size)
 467                 return -EINVAL;
 468
 469         /* compute downsizing coefficient */
 470         temp_downsize = 0;
 471         temp_size = in_size;
 472         while (temp_size >= out_size * 2 && temp_downsize < 2) {
 473                 temp_size >>= 1;
 474                 temp_downsize++;
 475         }
 476         *downsize_coeff = temp_downsize;
 477
 478         /*
 479          * compute resizing coefficient using the following formula:
 480          * resize_coeff = M*(SI -1)/(SO - 1)
 481          * where M = 2^13, SI - input size, SO - output size
 482          */
 483         *resize_coeff = (8192L * (temp_size - 1)) / (out_size - 1);
 484         if (*resize_coeff >= 16384L) {
 485                 dev_err(ipu_data.dev, "Warning! Overflow on resize coeff.\n");
 486                 *resize_coeff = 0x3FFF;
 487         }
 488
 489         dev_dbg(ipu_data.dev, "resizing from %u -> %u pixels, "
 490                 "downsize=%u, resize=%u.%lu (reg=%u)\n", in_size, out_size,
 491                 *downsize_coeff, *resize_coeff >= 8192L ? 1 : 0,
 492                 ((*resize_coeff & 0x1FFF) * 10000L) / 8192L, *resize_coeff);
 493
 494         return 0;
 495 }
 496
 497 static enum ipu_color_space format_to_colorspace(enum pixel_fmt fmt)
 498 {
 499         switch (fmt) {
 500         case IPU_PIX_FMT_RGB565:
 501         case IPU_PIX_FMT_BGR24:
 502         case IPU_PIX_FMT_RGB24:
 503         case IPU_PIX_FMT_BGR32:
 504         case IPU_PIX_FMT_RGB32:
 505                 return IPU_COLORSPACE_RGB;
 506         default:
 507                 return IPU_COLORSPACE_YCBCR;
 508         }
 509 }
 510
 511 static int ipu_ic_init_prpenc(struct ipu *ipu,
 512                               union ipu_channel_param *params, bool src_is_csi)
 513 {
 514         uint32_t reg, ic_conf;
 515         uint32_t downsize_coeff, resize_coeff;
 516         enum ipu_color_space in_fmt, out_fmt;
 517
 518         /* Setup vertical resizing */
 519         calc_resize_coeffs(params->video.in_height,
 520                             params->video.out_height,
 521                             &resize_coeff, &downsize_coeff);
 522         reg = (downsize_coeff << 30) | (resize_coeff << 16);
 523
 524         /* Setup horizontal resizing */
 525         calc_resize_coeffs(params->video.in_width,
 526                             params->video.out_width,
 527                             &resize_coeff, &downsize_coeff);
 528         reg |= (downsize_coeff << 14) | resize_coeff;
 529
 530         /* Setup color space conversion */
 531         in_fmt = format_to_colorspace(params->video.in_pixel_fmt);
 532         out_fmt = format_to_colorspace(params->video.out_pixel_fmt);
 533
 534         /*
 535          * Colourspace conversion unsupported yet - see _init_csc() in
 536          * Freescale sources
 537          */
 538         if (in_fmt != out_fmt) {
 539                 dev_err(ipu->dev, "Colourspace conversion unsupported!\n");
 540                 return -EOPNOTSUPP;
 541         }
 542
 543         idmac_write_icreg(ipu, reg, IC_PRP_ENC_RSC);
 544
 545         ic_conf = idmac_read_icreg(ipu, IC_CONF);
 546
 547         if (src_is_csi)
 548                 ic_conf &= ~IC_CONF_RWS_EN;
 549         else
 550                 ic_conf |= IC_CONF_RWS_EN;
 551
 552         idmac_write_icreg(ipu, ic_conf, IC_CONF);
 553
 554         return 0;
 555 }
 556
 557 static uint32_t dma_param_addr(uint32_t dma_ch)
 558 {
 559         /* Channel Parameter Memory */
 560         return 0x10000 | (dma_ch << 4);
 561 }
 562
 563 static void ipu_channel_set_priority(struct ipu *ipu, enum ipu_channel channel,
 564                                      bool prio)
 565 {
 566         u32 reg = idmac_read_icreg(ipu, IDMAC_CHA_PRI);
 567
 568         if (prio)
 569                 reg |= 1UL << channel;
 570         else
 571                 reg &= ~(1UL << channel);
 572
 573         idmac_write_icreg(ipu, reg, IDMAC_CHA_PRI);
 574
 575         dump_idmac_reg(ipu);
 576 }
 577
 578 static uint32_t ipu_channel_conf_mask(enum ipu_channel channel)
 579 {
 580         uint32_t mask;
 581
 582         switch (channel) {
 583         case IDMAC_IC_0:
 584         case IDMAC_IC_7:
 585                 mask = IPU_CONF_CSI_EN | IPU_CONF_IC_EN;
 586                 break;
 587         case IDMAC_SDC_0:
 588         case IDMAC_SDC_1:
 589                 mask = IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
 590                 break;
 591         default:
 592                 mask = 0;
 593                 break;
 594         }
 595
 596         return mask;
 597 }
 598
 599 /**
 600  * ipu_enable_channel() - enable an IPU channel.
 601  * @idmac:      IPU DMAC context.
 602  * @ichan:      IDMAC channel.
 603  * @return:     0 on success or negative error code on failure.
 604  */
 605 static int ipu_enable_channel(struct idmac *idmac, struct idmac_channel *ichan)
 606 {
 607         struct ipu *ipu = to_ipu(idmac);
 608         enum ipu_channel channel = ichan->dma_chan.chan_id;
 609         uint32_t reg;
 610         unsigned long flags;
 611
 612         spin_lock_irqsave(&ipu->lock, flags);
 613
 614         /* Reset to buffer 0 */
 615         idmac_write_ipureg(ipu, 1UL << channel, IPU_CHA_CUR_BUF);
 616         ichan->active_buffer = 0;
 617         ichan->status = IPU_CHANNEL_ENABLED;
 618
 619         switch (channel) {
 620         case IDMAC_SDC_0:
 621         case IDMAC_SDC_1:
 622         case IDMAC_IC_7:
 623                 ipu_channel_set_priority(ipu, channel, true);
 624         default:
 625                 break;
 626         }
 627
 628         reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
 629
 630         idmac_write_icreg(ipu, reg | (1UL << channel), IDMAC_CHA_EN);
 631
 632         ipu_ic_enable_task(ipu, channel);
 633
 634         spin_unlock_irqrestore(&ipu->lock, flags);
 635         return 0;
 636 }
 637
 638 /**
 639  * ipu_init_channel_buffer() - initialize a buffer for logical IPU channel.
 640  * @ichan:      IDMAC channel.
 641  * @pixel_fmt:  pixel format of buffer. Pixel format is a FOURCC ASCII code.
 642  * @width:      width of buffer in pixels.
 643  * @height:     height of buffer in pixels.
 644  * @stride:     stride length of buffer in pixels.
 645  * @rot_mode:   rotation mode of buffer. A rotation setting other than
 646  *              IPU_ROTATE_VERT_FLIP should only be used for input buffers of
 647  *              rotation channels.
 648  * @phyaddr_0:  buffer 0 physical address.
 649  * @phyaddr_1:  buffer 1 physical address. Setting this to a value other than
 650  *              NULL enables double buffering mode.
 651  * @return:     0 on success or negative error code on failure.
 652  */
 653 static int ipu_init_channel_buffer(struct idmac_channel *ichan,
 654                                    enum pixel_fmt pixel_fmt,
 655                                    uint16_t width, uint16_t height,
 656                                    uint32_t stride,
 657                                    enum ipu_rotate_mode rot_mode,
 658                                    dma_addr_t phyaddr_0, dma_addr_t phyaddr_1)
 659 {
 660         enum ipu_channel channel = ichan->dma_chan.chan_id;
 661         struct idmac *idmac = to_idmac(ichan->dma_chan.device);
 662         struct ipu *ipu = to_ipu(idmac);
 663         union chan_param_mem params = {};
 664         unsigned long flags;
 665         uint32_t reg;
 666         uint32_t stride_bytes;
 667
 668         stride_bytes = stride * bytes_per_pixel(pixel_fmt);
 669
 670         if (stride_bytes % 4) {
 671                 dev_err(ipu->dev,
 672                         "Stride length must be 32-bit aligned, stride = %d, bytes = %d\n",
 673                         stride, stride_bytes);
 674                 return -EINVAL;
 675         }
 676
 677         /* IC channel's stride must be a multiple of 8 pixels */
 678         if ((channel <= IDMAC_IC_13) && (stride % 8)) {
 679                 dev_err(ipu->dev, "Stride must be 8 pixel multiple\n");
 680                 return -EINVAL;
 681         }
 682
 683         /* Build parameter memory data for DMA channel */
 684         ipu_ch_param_set_size(&params, pixel_fmt, width, height, stride_bytes);
 685         ipu_ch_param_set_buffer(&params, phyaddr_0, phyaddr_1);
 686         ipu_ch_param_set_rotation(&params, rot_mode);
 687
 688         spin_lock_irqsave(&ipu->lock, flags);
 689
 690         ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)&params, 10);
 691
 692         reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
 693
 694         if (phyaddr_1)
 695                 reg |= 1UL << channel;
 696         else
 697                 reg &= ~(1UL << channel);
 698
 699         idmac_write_ipureg(ipu, reg, IPU_CHA_DB_MODE_SEL);
 700
 701         ichan->status = IPU_CHANNEL_READY;
 702
 703         spin_unlock_irqrestore(&ipu->lock, flags);
 704
 705         return 0;
 706 }
 707
 708 /**
 709  * ipu_select_buffer() - mark a channel's buffer as ready.
 710  * @channel:    channel ID.
 711  * @buffer_n:   buffer number to mark ready.
 712  */
 713 static void ipu_select_buffer(enum ipu_channel channel, int buffer_n)
 714 {
 715         /* No locking - this is a write-one-to-set register, cleared by IPU */
 716         if (buffer_n == 0)
 717                 /* Mark buffer 0 as ready. */
 718                 idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF0_RDY);
 719         else
 720                 /* Mark buffer 1 as ready. */
 721                 idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF1_RDY);
 722 }
 723
 724 /**
 725  * ipu_update_channel_buffer() - update physical address of a channel buffer.
 726  * @ichan:      IDMAC channel.
 727  * @buffer_n:   buffer number to update.
 728  *              0 or 1 are the only valid values.
 729  * @phyaddr:    buffer physical address.
 730  */
 731 /* Called under spin_lock(_irqsave)(&ichan->lock) */
 732 static void ipu_update_channel_buffer(struct idmac_channel *ichan,
 733                                       int buffer_n, dma_addr_t phyaddr)
 734 {
 735         enum ipu_channel channel = ichan->dma_chan.chan_id;
 736         uint32_t reg;
 737         unsigned long flags;
 738
 739         spin_lock_irqsave(&ipu_data.lock, flags);
 740
 741         if (buffer_n == 0) {
 742                 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
 743                 if (reg & (1UL << channel)) {
 744                         ipu_ic_disable_task(&ipu_data, channel);
 745                         ichan->status = IPU_CHANNEL_READY;
 746                 }
 747
 748                 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
 749                 idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
 750                                    0x0008UL, IPU_IMA_ADDR);
 751                 idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
 752         } else {
 753                 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
 754                 if (reg & (1UL << channel)) {
 755                         ipu_ic_disable_task(&ipu_data, channel);
 756                         ichan->status = IPU_CHANNEL_READY;
 757                 }
 758
 759                 /* Check if double-buffering is already enabled */
 760                 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_DB_MODE_SEL);
 761
 762                 if (!(reg & (1UL << channel)))
 763                         idmac_write_ipureg(&ipu_data, reg | (1UL << channel),
 764                                            IPU_CHA_DB_MODE_SEL);
 765
 766                 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 1) */
 767                 idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
 768                                    0x0009UL, IPU_IMA_ADDR);
 769                 idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
 770         }
 771
 772         spin_unlock_irqrestore(&ipu_data.lock, flags);
 773 }
 774
 775 /* Called under spin_lock_irqsave(&ichan->lock) */
 776 static int ipu_submit_buffer(struct idmac_channel *ichan,
 777         struct idmac_tx_desc *desc, struct scatterlist *sg, int buf_idx)
 778 {
 779         unsigned int chan_id = ichan->dma_chan.chan_id;
 780         struct device *dev = &ichan->dma_chan.dev->device;
 781
 782         if (async_tx_test_ack(&desc->txd))
 783                 return -EINTR;
 784
 785         /*
 786          * On first invocation this shouldn't be necessary, the call to
 787          * ipu_init_channel_buffer() above will set addresses for us, so we
 788          * could make it conditional on status >= IPU_CHANNEL_ENABLED, but
 789          * doing it again shouldn't hurt either.
 790          */
 791         ipu_update_channel_buffer(ichan, buf_idx, sg_dma_address(sg));
 792
 793         ipu_select_buffer(chan_id, buf_idx);
 794         dev_dbg(dev, "Updated sg %p on channel 0x%x buffer %d\n",
 795                 sg, chan_id, buf_idx);
 796
 797         return 0;
 798 }
 799
 800 /* Called under spin_lock_irqsave(&ichan->lock) */
 801 static int ipu_submit_channel_buffers(struct idmac_channel *ichan,
 802                                       struct idmac_tx_desc *desc)
 803 {
 804         struct scatterlist *sg;
 805         int i, ret = 0;
 806
 807         for (i = 0, sg = desc->sg; i < 2 && sg; i++) {
 808                 if (!ichan->sg[i]) {
 809                         ichan->sg[i] = sg;
 810
 811                         ret = ipu_submit_buffer(ichan, desc, sg, i);
 812                         if (ret < 0)
 813                                 return ret;
 814
 815                         sg = sg_next(sg);
 816                 }
 817         }
 818
 819         return ret;
 820 }
 821
 822 static dma_cookie_t idmac_tx_submit(struct dma_async_tx_descriptor *tx)
 823 {
 824         struct idmac_tx_desc *desc = to_tx_desc(tx);
 825         struct idmac_channel *ichan = to_idmac_chan(tx->chan);
 826         struct idmac *idmac = to_idmac(tx->chan->device);
 827         struct ipu *ipu = to_ipu(idmac);
 828         struct device *dev = &ichan->dma_chan.dev->device;
 829         dma_cookie_t cookie;
 830         unsigned long flags;
 831         int ret;
 832
 833         /* Sanity check */
 834         if (!list_empty(&desc->list)) {
 835                 /* The descriptor doesn't belong to client */
 836                 dev_err(dev, "Descriptor %p not prepared!\n", tx);
 837                 return -EBUSY;
 838         }
 839
 840         mutex_lock(&ichan->chan_mutex);
 841
 842         async_tx_clear_ack(tx);
 843
 844         if (ichan->status < IPU_CHANNEL_READY) {
 845                 struct idmac_video_param *video = &ichan->params.video;
 846                 /*
 847                  * Initial buffer assignment - the first two sg-entries from
 848                  * the descriptor will end up in the IDMAC buffers
 849                  */
 850                 dma_addr_t dma_1 = sg_is_last(desc->sg) ? 0 :
 851                         sg_dma_address(&desc->sg[1]);
 852
 853                 WARN_ON(ichan->sg[0] || ichan->sg[1]);
 854
 855                 cookie = ipu_init_channel_buffer(ichan,
 856                                                  video->out_pixel_fmt,
 857                                                  video->out_width,
 858                                                  video->out_height,
 859                                                  video->out_stride,
 860                                                  IPU_ROTATE_NONE,
 861                                                  sg_dma_address(&desc->sg[0]),
 862                                                  dma_1);
 863                 if (cookie < 0)
 864                         goto out;
 865         }
 866
 867         dev_dbg(dev, "Submitting sg %p\n", &desc->sg[0]);
 868
 869         cookie = dma_cookie_assign(tx);
 870
 871         /* ipu->lock can be taken under ichan->lock, but not v.v. */
 872         spin_lock_irqsave(&ichan->lock, flags);
 873
 874         list_add_tail(&desc->list, &ichan->queue);
 875         /* submit_buffers() atomically verifies and fills empty sg slots */
 876         ret = ipu_submit_channel_buffers(ichan, desc);
 877
 878         spin_unlock_irqrestore(&ichan->lock, flags);
 879
 880         if (ret < 0) {
 881                 cookie = ret;
 882                 goto dequeue;
 883         }
 884
 885         if (ichan->status < IPU_CHANNEL_ENABLED) {
 886                 ret = ipu_enable_channel(idmac, ichan);
 887                 if (ret < 0) {
 888                         cookie = ret;
 889                         goto dequeue;
 890                 }
 891         }
 892
 893         dump_idmac_reg(ipu);
 894
 895 dequeue:
 896         if (cookie < 0) {
 897                 spin_lock_irqsave(&ichan->lock, flags);
 898                 list_del_init(&desc->list);
 899                 spin_unlock_irqrestore(&ichan->lock, flags);
 900                 tx->cookie = cookie;
 901                 ichan->dma_chan.cookie = cookie;
 902         }
 903
 904 out:
 905         mutex_unlock(&ichan->chan_mutex);
 906
 907         return cookie;
 908 }
 909
 910 /* Called with ichan->chan_mutex held */
 911 static int idmac_desc_alloc(struct idmac_channel *ichan, int n)
 912 {
 913         struct idmac_tx_desc *desc = vmalloc(n * sizeof(struct idmac_tx_desc));
 914         struct idmac *idmac = to_idmac(ichan->dma_chan.device);
 915
 916         if (!desc)
 917                 return -ENOMEM;
 918
 919         /* No interrupts, just disable the tasklet for a moment */
 920         tasklet_disable(&to_ipu(idmac)->tasklet);
 921
 922         ichan->n_tx_desc = n;
 923         ichan->desc = desc;
 924         INIT_LIST_HEAD(&ichan->queue);
 925         INIT_LIST_HEAD(&ichan->free_list);
 926
 927         while (n--) {
 928                 struct dma_async_tx_descriptor *txd = &desc->txd;
 929
 930                 memset(txd, 0, sizeof(*txd));
 931                 dma_async_tx_descriptor_init(txd, &ichan->dma_chan);
 932                 txd->tx_submit          = idmac_tx_submit;
 933
 934                 list_add(&desc->list, &ichan->free_list);
 935
 936                 desc++;
 937         }
 938
 939         tasklet_enable(&to_ipu(idmac)->tasklet);
 940
 941         return 0;
 942 }
 943
 944 /**
 945  * ipu_init_channel() - initialize an IPU channel.
 946  * @idmac:      IPU DMAC context.
 947  * @ichan:      pointer to the channel object.
 948  * @return      0 on success or negative error code on failure.
 949  */
 950 static int ipu_init_channel(struct idmac *idmac, struct idmac_channel *ichan)
 951 {
 952         union ipu_channel_param *params = &ichan->params;
 953         uint32_t ipu_conf;
 954         enum ipu_channel channel = ichan->dma_chan.chan_id;
 955         unsigned long flags;
 956         uint32_t reg;
 957         struct ipu *ipu = to_ipu(idmac);
 958         int ret = 0, n_desc = 0;
 959
 960         dev_dbg(ipu->dev, "init channel = %d\n", channel);
 961
 962         if (channel != IDMAC_SDC_0 && channel != IDMAC_SDC_1 &&
 963             channel != IDMAC_IC_7)
 964                 return -EINVAL;
 965
 966         spin_lock_irqsave(&ipu->lock, flags);
 967
 968         switch (channel) {
 969         case IDMAC_IC_7:
 970                 n_desc = 16;
 971                 reg = idmac_read_icreg(ipu, IC_CONF);
 972                 idmac_write_icreg(ipu, reg & ~IC_CONF_CSI_MEM_WR_EN, IC_CONF);
 973                 break;
 974         case IDMAC_IC_0:
 975                 n_desc = 16;
 976                 reg = idmac_read_ipureg(ipu, IPU_FS_PROC_FLOW);
 977                 idmac_write_ipureg(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW);
 978                 ret = ipu_ic_init_prpenc(ipu, params, true);
 979                 break;
 980         case IDMAC_SDC_0:
 981         case IDMAC_SDC_1:
 982                 n_desc = 4;
 983         default:
 984                 break;
 985         }
 986
 987         ipu->channel_init_mask |= 1L << channel;
 988
 989         /* Enable IPU sub module */
 990         ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) |
 991                 ipu_channel_conf_mask(channel);
 992         idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
 993
 994         spin_unlock_irqrestore(&ipu->lock, flags);
 995
 996         if (n_desc && !ichan->desc)
 997                 ret = idmac_desc_alloc(ichan, n_desc);
 998
 999         dump_idmac_reg(ipu);
1000
1001         return ret;
1002 }
1003
1004 /**
1005  * ipu_uninit_channel() - uninitialize an IPU channel.
1006  * @idmac:      IPU DMAC context.
1007  * @ichan:      pointer to the channel object.
1008  */
1009 static void ipu_uninit_channel(struct idmac *idmac, struct idmac_channel *ichan)
1010 {
1011         enum ipu_channel channel = ichan->dma_chan.chan_id;
1012         unsigned long flags;
1013         uint32_t reg;
1014         unsigned long chan_mask = 1UL << channel;
1015         uint32_t ipu_conf;
1016         struct ipu *ipu = to_ipu(idmac);
1017
1018         spin_lock_irqsave(&ipu->lock, flags);
1019
1020         if (!(ipu->channel_init_mask & chan_mask)) {
1021                 dev_err(ipu->dev, "Channel already uninitialized %d\n",
1022                         channel);
1023                 spin_unlock_irqrestore(&ipu->lock, flags);
1024                 return;
1025         }
1026
1027         /* Reset the double buffer */
1028         reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
1029         idmac_write_ipureg(ipu, reg & ~chan_mask, IPU_CHA_DB_MODE_SEL);
1030
1031         ichan->sec_chan_en = false;
1032
1033         switch (channel) {
1034         case IDMAC_IC_7:
1035                 reg = idmac_read_icreg(ipu, IC_CONF);
1036                 idmac_write_icreg(ipu, reg & ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN),
1037                              IC_CONF);
1038                 break;
1039         case IDMAC_IC_0:
1040                 reg = idmac_read_icreg(ipu, IC_CONF);
1041                 idmac_write_icreg(ipu, reg & ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1),
1042                                   IC_CONF);
1043                 break;
1044         case IDMAC_SDC_0:
1045         case IDMAC_SDC_1:
1046         default:
1047                 break;
1048         }
1049
1050         ipu->channel_init_mask &= ~(1L << channel);
1051
1052         ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) &
1053                 ~ipu_channel_conf_mask(channel);
1054         idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
1055
1056         spin_unlock_irqrestore(&ipu->lock, flags);
1057
1058         ichan->n_tx_desc = 0;
1059         vfree(ichan->desc);
1060         ichan->desc = NULL;
1061 }
1062
1063 /**
1064  * ipu_disable_channel() - disable an IPU channel.
1065  * @idmac:              IPU DMAC context.
1066  * @ichan:              channel object pointer.
1067  * @wait_for_stop:      flag to set whether to wait for channel end of frame or
1068  *                      return immediately.
1069  * @return:             0 on success or negative error code on failure.
1070  */
1071 static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
1072                                bool wait_for_stop)
1073 {
1074         enum ipu_channel channel = ichan->dma_chan.chan_id;
1075         struct ipu *ipu = to_ipu(idmac);
1076         uint32_t reg;
1077         unsigned long flags;
1078         unsigned long chan_mask = 1UL << channel;
1079         unsigned int timeout;
1080
1081         if (wait_for_stop && channel != IDMAC_SDC_1 && channel != IDMAC_SDC_0) {
1082                 timeout = 40;
1083                 /* This waiting always fails. Related to spurious irq problem */
1084                 while ((idmac_read_icreg(ipu, IDMAC_CHA_BUSY) & chan_mask) ||
1085                        (ipu_channel_status(ipu, channel) == TASK_STAT_ACTIVE)) {
1086                         timeout--;
1087                         msleep(10);
1088
1089                         if (!timeout) {
1090                                 dev_dbg(ipu->dev,
1091                                         "Warning: timeout waiting for channel %u to "
1092                                         "stop: buf0_rdy = 0x%08X, buf1_rdy = 0x%08X, "
1093                                         "busy = 0x%08X, tstat = 0x%08X\n", channel,
1094                                         idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
1095                                         idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
1096                                         idmac_read_icreg(ipu, IDMAC_CHA_BUSY),
1097                                         idmac_read_ipureg(ipu, IPU_TASKS_STAT));
1098                                 break;
1099                         }
1100                 }
1101                 dev_dbg(ipu->dev, "timeout = %d * 10ms\n", 40 - timeout);
1102         }
1103         /* SDC BG and FG must be disabled before DMA is disabled */
1104         if (wait_for_stop && (channel == IDMAC_SDC_0 ||
1105                               channel == IDMAC_SDC_1)) {
1106                 for (timeout = 5;
1107                      timeout && !ipu_irq_status(ichan->eof_irq); timeout--)
1108                         msleep(5);
1109         }
1110
1111         spin_lock_irqsave(&ipu->lock, flags);
1112
1113         /* Disable IC task */
1114         ipu_ic_disable_task(ipu, channel);
1115
1116         /* Disable DMA channel(s) */
1117         reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
1118         idmac_write_icreg(ipu, reg & ~chan_mask, IDMAC_CHA_EN);
1119
1120         spin_unlock_irqrestore(&ipu->lock, flags);
1121
1122         return 0;
1123 }
1124
1125 static struct scatterlist *idmac_sg_next(struct idmac_channel *ichan,
1126         struct idmac_tx_desc **desc, struct scatterlist *sg)
1127 {
1128         struct scatterlist *sgnew = sg ? sg_next(sg) : NULL;
1129
1130         if (sgnew)
1131                 /* next sg-element in this list */
1132                 return sgnew;
1133
1134         if ((*desc)->list.next == &ichan->queue)
1135                 /* No more descriptors on the queue */
1136                 return NULL;
1137
1138         /* Fetch next descriptor */
1139         *desc = list_entry((*desc)->list.next, struct idmac_tx_desc, list);
1140         return (*desc)->sg;
1141 }
1142
1143 /*
1144  * We have several possibilities here:
1145  * current BUF          next BUF
1146  *
1147  * not last sg          next not last sg
1148  * not last sg          next last sg
1149  * last sg              first sg from next descriptor
1150  * last sg              NULL
1151  *
1152  * Besides, the descriptor queue might be empty or not. We process all these
1153  * cases carefully.
1154  */
1155 static irqreturn_t idmac_interrupt(int irq, void *dev_id)
1156 {
1157         struct idmac_channel *ichan = dev_id;
1158         struct device *dev = &ichan->dma_chan.dev->device;
1159         unsigned int chan_id = ichan->dma_chan.chan_id;
1160         struct scatterlist **sg, *sgnext, *sgnew = NULL;
1161         /* Next transfer descriptor */
1162         struct idmac_tx_desc *desc, *descnew;
1163         dma_async_tx_callback callback;
1164         void *callback_param;
1165         bool done = false;
1166         u32 ready0, ready1, curbuf, err;
1167         unsigned long flags;
1168
1169         /* IDMAC has cleared the respective BUFx_RDY bit, we manage the buffer */
1170
1171         dev_dbg(dev, "IDMAC irq %d, buf %d\n", irq, ichan->active_buffer);
1172
1173         spin_lock_irqsave(&ipu_data.lock, flags);
1174
1175         ready0  = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
1176         ready1  = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
1177         curbuf  = idmac_read_ipureg(&ipu_data, IPU_CHA_CUR_BUF);
1178         err     = idmac_read_ipureg(&ipu_data, IPU_INT_STAT_4);
1179
1180         if (err & (1 << chan_id)) {
1181                 idmac_write_ipureg(&ipu_data, 1 << chan_id, IPU_INT_STAT_4);
1182                 spin_unlock_irqrestore(&ipu_data.lock, flags);
1183                 /*
1184                  * Doing this
1185                  * ichan->sg[0] = ichan->sg[1] = NULL;
1186                  * you can force channel re-enable on the next tx_submit(), but
1187                  * this is dirty - think about descriptors with multiple
1188                  * sg elements.
1189                  */
1190                 dev_warn(dev, "NFB4EOF on channel %d, ready %x, %x, cur %x\n",
1191                          chan_id, ready0, ready1, curbuf);
1192                 return IRQ_HANDLED;
1193         }
1194         spin_unlock_irqrestore(&ipu_data.lock, flags);
1195
1196         /* Other interrupts do not interfere with this channel */
1197         spin_lock(&ichan->lock);
1198         if (unlikely((ichan->active_buffer && (ready1 >> chan_id) & 1) ||
1199                      (!ichan->active_buffer && (ready0 >> chan_id) & 1)
1200                      )) {
1201                 spin_unlock(&ichan->lock);
1202                 dev_dbg(dev,
1203                         "IRQ with active buffer still ready on channel %x, "
1204                         "active %d, ready %x, %x!\n", chan_id,
1205                         ichan->active_buffer, ready0, ready1);
1206                 return IRQ_NONE;
1207         }
1208
1209         if (unlikely(list_empty(&ichan->queue))) {
1210                 ichan->sg[ichan->active_buffer] = NULL;
1211                 spin_unlock(&ichan->lock);
1212                 dev_err(dev,
1213                         "IRQ without queued buffers on channel %x, active %d, "
1214                         "ready %x, %x!\n", chan_id,
1215                         ichan->active_buffer, ready0, ready1);
1216                 return IRQ_NONE;
1217         }
1218
1219         /*
1220          * active_buffer is a software flag, it shows which buffer we are
1221          * currently expecting back from the hardware, IDMAC should be
1222          * processing the other buffer already
1223          */
1224         sg = &ichan->sg[ichan->active_buffer];
1225         sgnext = ichan->sg[!ichan->active_buffer];
1226
1227         if (!*sg) {
1228                 spin_unlock(&ichan->lock);
1229                 return IRQ_HANDLED;
1230         }
1231
1232         desc = list_entry(ichan->queue.next, struct idmac_tx_desc, list);
1233         descnew = desc;
1234
1235         dev_dbg(dev, "IDMAC irq %d, dma %#llx, next dma %#llx, current %d, curbuf %#x\n",
1236                 irq, (u64)sg_dma_address(*sg),
1237                 sgnext ? (u64)sg_dma_address(sgnext) : 0,
1238                 ichan->active_buffer, curbuf);
1239
1240         /* Find the descriptor of sgnext */
1241         sgnew = idmac_sg_next(ichan, &descnew, *sg);
1242         if (sgnext != sgnew)
1243                 dev_err(dev, "Submitted buffer %p, next buffer %p\n", sgnext, sgnew);
1244
1245         /*
1246          * if sgnext == NULL sg must be the last element in a scatterlist and
1247          * queue must be empty
1248          */
1249         if (unlikely(!sgnext)) {
1250                 if (!WARN_ON(sg_next(*sg)))
1251                         dev_dbg(dev, "Underrun on channel %x\n", chan_id);
1252                 ichan->sg[!ichan->active_buffer] = sgnew;
1253
1254                 if (unlikely(sgnew)) {
1255                         ipu_submit_buffer(ichan, descnew, sgnew, !ichan->active_buffer);
1256                 } else {
1257                         spin_lock_irqsave(&ipu_data.lock, flags);
1258                         ipu_ic_disable_task(&ipu_data, chan_id);
1259                         spin_unlock_irqrestore(&ipu_data.lock, flags);
1260                         ichan->status = IPU_CHANNEL_READY;
1261                         /* Continue to check for complete descriptor */
1262                 }
1263         }
1264
1265         /* Calculate and submit the next sg element */
1266         sgnew = idmac_sg_next(ichan, &descnew, sgnew);
1267
1268         if (unlikely(!sg_next(*sg)) || !sgnext) {
1269                 /*
1270                  * Last element in scatterlist done, remove from the queue,
1271                  * _init for debugging
1272                  */
1273                 list_del_init(&desc->list);
1274                 done = true;
1275         }
1276
1277         *sg = sgnew;
1278
1279         if (likely(sgnew) &&
1280             ipu_submit_buffer(ichan, descnew, sgnew, ichan->active_buffer) < 0) {
1281                 callback = descnew->txd.callback;
1282                 callback_param = descnew->txd.callback_param;
1283                 list_del_init(&descnew->list);
1284                 spin_unlock(&ichan->lock);
1285                 if (callback)
1286                         callback(callback_param);
1287                 spin_lock(&ichan->lock);
1288         }
1289
1290         /* Flip the active buffer - even if update above failed */
1291         ichan->active_buffer = !ichan->active_buffer;
1292         if (done)
1293                 dma_cookie_complete(&desc->txd);
1294
1295         callback = desc->txd.callback;
1296         callback_param = desc->txd.callback_param;
1297
1298         spin_unlock(&ichan->lock);
1299
1300         if (done && (desc->txd.flags & DMA_PREP_INTERRUPT) && callback)
1301                 callback(callback_param);
1302
1303         return IRQ_HANDLED;
1304 }
1305
1306 static void ipu_gc_tasklet(unsigned long arg)
1307 {
1308         struct ipu *ipu = (struct ipu *)arg;
1309         int i;
1310
1311         for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1312                 struct idmac_channel *ichan = ipu->channel + i;
1313                 struct idmac_tx_desc *desc;
1314                 unsigned long flags;
1315                 struct scatterlist *sg;
1316                 int j, k;
1317
1318                 for (j = 0; j < ichan->n_tx_desc; j++) {
1319                         desc = ichan->desc + j;
1320                         spin_lock_irqsave(&ichan->lock, flags);
1321                         if (async_tx_test_ack(&desc->txd)) {
1322                                 list_move(&desc->list, &ichan->free_list);
1323                                 for_each_sg(desc->sg, sg, desc->sg_len, k) {
1324                                         if (ichan->sg[0] == sg)
1325                                                 ichan->sg[0] = NULL;
1326                                         else if (ichan->sg[1] == sg)
1327                                                 ichan->sg[1] = NULL;
1328                                 }
1329                                 async_tx_clear_ack(&desc->txd);
1330                         }
1331                         spin_unlock_irqrestore(&ichan->lock, flags);
1332                 }
1333         }
1334 }
1335
1336 /* Allocate and initialise a transfer descriptor. */
1337 static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan,
1338                 struct scatterlist *sgl, unsigned int sg_len,
1339                 enum dma_transfer_direction direction, unsigned long tx_flags,
1340                 void *context)
1341 {
1342         struct idmac_channel *ichan = to_idmac_chan(chan);
1343         struct idmac_tx_desc *desc = NULL;
1344         struct dma_async_tx_descriptor *txd = NULL;
1345         unsigned long flags;
1346
1347         /* We only can handle these three channels so far */
1348         if (chan->chan_id != IDMAC_SDC_0 && chan->chan_id != IDMAC_SDC_1 &&
1349             chan->chan_id != IDMAC_IC_7)
1350                 return NULL;
1351
1352         if (!is_slave_direction(direction)) {
1353                 dev_err(chan->device->dev, "Invalid DMA direction %d!\n", direction);
1354                 return NULL;
1355         }
1356
1357         mutex_lock(&ichan->chan_mutex);
1358
1359         spin_lock_irqsave(&ichan->lock, flags);
1360         if (!list_empty(&ichan->free_list)) {
1361                 desc = list_entry(ichan->free_list.next,
1362                                   struct idmac_tx_desc, list);
1363
1364                 list_del_init(&desc->list);
1365
1366                 desc->sg_len    = sg_len;
1367                 desc->sg        = sgl;
1368                 txd             = &desc->txd;
1369                 txd->flags      = tx_flags;
1370         }
1371         spin_unlock_irqrestore(&ichan->lock, flags);
1372
1373         mutex_unlock(&ichan->chan_mutex);
1374
1375         tasklet_schedule(&to_ipu(to_idmac(chan->device))->tasklet);
1376
1377         return txd;
1378 }
1379
1380 /* Re-select the current buffer and re-activate the channel */
1381 static void idmac_issue_pending(struct dma_chan *chan)
1382 {
1383         struct idmac_channel *ichan = to_idmac_chan(chan);
1384         struct idmac *idmac = to_idmac(chan->device);
1385         struct ipu *ipu = to_ipu(idmac);
1386         unsigned long flags;
1387
1388         /* This is not always needed, but doesn't hurt either */
1389         spin_lock_irqsave(&ipu->lock, flags);
1390         ipu_select_buffer(chan->chan_id, ichan->active_buffer);
1391         spin_unlock_irqrestore(&ipu->lock, flags);
1392
1393         /*
1394          * Might need to perform some parts of initialisation from
1395          * ipu_enable_channel(), but not all, we do not want to reset to buffer
1396          * 0, don't need to set priority again either, but re-enabling the task
1397          * and the channel might be a good idea.
1398          */
1399 }
1400
1401 static int __idmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1402                            unsigned long arg)
1403 {
1404         struct idmac_channel *ichan = to_idmac_chan(chan);
1405         struct idmac *idmac = to_idmac(chan->device);
1406         struct ipu *ipu = to_ipu(idmac);
1407         struct list_head *list, *tmp;
1408         unsigned long flags;
1409         int i;
1410
1411         switch (cmd) {
1412         case DMA_PAUSE:
1413                 spin_lock_irqsave(&ipu->lock, flags);
1414                 ipu_ic_disable_task(ipu, chan->chan_id);
1415
1416                 /* Return all descriptors into "prepared" state */
1417                 list_for_each_safe(list, tmp, &ichan->queue)
1418                         list_del_init(list);
1419
1420                 ichan->sg[0] = NULL;
1421                 ichan->sg[1] = NULL;
1422
1423                 spin_unlock_irqrestore(&ipu->lock, flags);
1424
1425                 ichan->status = IPU_CHANNEL_INITIALIZED;
1426                 break;
1427         case DMA_TERMINATE_ALL:
1428                 ipu_disable_channel(idmac, ichan,
1429                                     ichan->status >= IPU_CHANNEL_ENABLED);
1430
1431                 tasklet_disable(&ipu->tasklet);
1432
1433                 /* ichan->queue is modified in ISR, have to spinlock */
1434                 spin_lock_irqsave(&ichan->lock, flags);
1435                 list_splice_init(&ichan->queue, &ichan->free_list);
1436
1437                 if (ichan->desc)
1438                         for (i = 0; i < ichan->n_tx_desc; i++) {
1439                                 struct idmac_tx_desc *desc = ichan->desc + i;
1440                                 if (list_empty(&desc->list))
1441                                         /* Descriptor was prepared, but not submitted */
1442                                         list_add(&desc->list, &ichan->free_list);
1443
1444                                 async_tx_clear_ack(&desc->txd);
1445                         }
1446
1447                 ichan->sg[0] = NULL;
1448                 ichan->sg[1] = NULL;
1449                 spin_unlock_irqrestore(&ichan->lock, flags);
1450
1451                 tasklet_enable(&ipu->tasklet);
1452
1453                 ichan->status = IPU_CHANNEL_INITIALIZED;
1454                 break;
1455         default:
1456                 return -ENOSYS;
1457         }
1458
1459         return 0;
1460 }
1461
1462 static int idmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1463                          unsigned long arg)
1464 {
1465         struct idmac_channel *ichan = to_idmac_chan(chan);
1466         int ret;
1467
1468         mutex_lock(&ichan->chan_mutex);
1469
1470         ret = __idmac_control(chan, cmd, arg);
1471
1472         mutex_unlock(&ichan->chan_mutex);
1473
1474         return ret;
1475 }
1476
1477 #ifdef DEBUG
1478 static irqreturn_t ic_sof_irq(int irq, void *dev_id)
1479 {
1480         struct idmac_channel *ichan = dev_id;
1481         printk(KERN_DEBUG "Got SOF IRQ %d on Channel %d\n",
1482                irq, ichan->dma_chan.chan_id);
1483         disable_irq_nosync(irq);
1484         return IRQ_HANDLED;
1485 }
1486
1487 static irqreturn_t ic_eof_irq(int irq, void *dev_id)
1488 {
1489         struct idmac_channel *ichan = dev_id;
1490         printk(KERN_DEBUG "Got EOF IRQ %d on Channel %d\n",
1491                irq, ichan->dma_chan.chan_id);
1492         disable_irq_nosync(irq);
1493         return IRQ_HANDLED;
1494 }
1495
1496 static int ic_sof = -EINVAL, ic_eof = -EINVAL;
1497 #endif
1498
1499 static int idmac_alloc_chan_resources(struct dma_chan *chan)
1500 {
1501         struct idmac_channel *ichan = to_idmac_chan(chan);
1502         struct idmac *idmac = to_idmac(chan->device);
1503         int ret;
1504
1505         /* dmaengine.c now guarantees to only offer free channels */
1506         BUG_ON(chan->client_count > 1);
1507         WARN_ON(ichan->status != IPU_CHANNEL_FREE);
1508
1509         dma_cookie_init(chan);
1510
1511         ret = ipu_irq_map(chan->chan_id);
1512         if (ret < 0)
1513                 goto eimap;
1514
1515         ichan->eof_irq = ret;
1516
1517         /*
1518          * Important to first disable the channel, because maybe someone
1519          * used it before us, e.g., the bootloader
1520          */
1521         ipu_disable_channel(idmac, ichan, true);
1522
1523         ret = ipu_init_channel(idmac, ichan);
1524         if (ret < 0)
1525                 goto eichan;
1526
1527         ret = request_irq(ichan->eof_irq, idmac_interrupt, 0,
1528                           ichan->eof_name, ichan);
1529         if (ret < 0)
1530                 goto erirq;
1531
1532 #ifdef DEBUG
1533         if (chan->chan_id == IDMAC_IC_7) {
1534                 ic_sof = ipu_irq_map(69);
1535                 if (ic_sof > 0)
1536                         request_irq(ic_sof, ic_sof_irq, 0, "IC SOF", ichan);
1537                 ic_eof = ipu_irq_map(70);
1538                 if (ic_eof > 0)
1539                         request_irq(ic_eof, ic_eof_irq, 0, "IC EOF", ichan);
1540         }
1541 #endif
1542
1543         ichan->status = IPU_CHANNEL_INITIALIZED;
1544
1545         dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n",
1546                 chan->chan_id, ichan->eof_irq);
1547
1548         return ret;
1549
1550 erirq:
1551         ipu_uninit_channel(idmac, ichan);
1552 eichan:
1553         ipu_irq_unmap(chan->chan_id);
1554 eimap:
1555         return ret;
1556 }
1557
1558 static void idmac_free_chan_resources(struct dma_chan *chan)
1559 {
1560         struct idmac_channel *ichan = to_idmac_chan(chan);
1561         struct idmac *idmac = to_idmac(chan->device);
1562
1563         mutex_lock(&ichan->chan_mutex);
1564
1565         __idmac_control(chan, DMA_TERMINATE_ALL, 0);
1566
1567         if (ichan->status > IPU_CHANNEL_FREE) {
1568 #ifdef DEBUG
1569                 if (chan->chan_id == IDMAC_IC_7) {
1570                         if (ic_sof > 0) {
1571                                 free_irq(ic_sof, ichan);
1572                                 ipu_irq_unmap(69);
1573                                 ic_sof = -EINVAL;
1574                         }
1575                         if (ic_eof > 0) {
1576                                 free_irq(ic_eof, ichan);
1577                                 ipu_irq_unmap(70);
1578                                 ic_eof = -EINVAL;
1579                         }
1580                 }
1581 #endif
1582                 free_irq(ichan->eof_irq, ichan);
1583                 ipu_irq_unmap(chan->chan_id);
1584         }
1585
1586         ichan->status = IPU_CHANNEL_FREE;
1587
1588         ipu_uninit_channel(idmac, ichan);
1589
1590         mutex_unlock(&ichan->chan_mutex);
1591
1592         tasklet_schedule(&to_ipu(idmac)->tasklet);
1593 }
1594
1595 static enum dma_status idmac_tx_status(struct dma_chan *chan,
1596                        dma_cookie_t cookie, struct dma_tx_state *txstate)
1597 {
1598         return dma_cookie_status(chan, cookie, txstate);
1599 }
1600
1601 static int __init ipu_idmac_init(struct ipu *ipu)
1602 {
1603         struct idmac *idmac = &ipu->idmac;
1604         struct dma_device *dma = &idmac->dma;
1605         int i;
1606
1607         dma_cap_set(DMA_SLAVE, dma->cap_mask);
1608         dma_cap_set(DMA_PRIVATE, dma->cap_mask);
1609
1610         /* Compulsory common fields */
1611         dma->dev                                = ipu->dev;
1612         dma->device_alloc_chan_resources        = idmac_alloc_chan_resources;
1613         dma->device_free_chan_resources         = idmac_free_chan_resources;
1614         dma->device_tx_status                   = idmac_tx_status;
1615         dma->device_issue_pending               = idmac_issue_pending;
1616
1617         /* Compulsory for DMA_SLAVE fields */
1618         dma->device_prep_slave_sg               = idmac_prep_slave_sg;
1619         dma->device_control                     = idmac_control;
1620
1621         INIT_LIST_HEAD(&dma->channels);
1622         for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1623                 struct idmac_channel *ichan = ipu->channel + i;
1624                 struct dma_chan *dma_chan = &ichan->dma_chan;
1625
1626                 spin_lock_init(&ichan->lock);
1627                 mutex_init(&ichan->chan_mutex);
1628
1629                 ichan->status           = IPU_CHANNEL_FREE;
1630                 ichan->sec_chan_en      = false;
1631                 snprintf(ichan->eof_name, sizeof(ichan->eof_name), "IDMAC EOF %d", i);
1632
1633                 dma_chan->device        = &idmac->dma;
1634                 dma_cookie_init(dma_chan);
1635                 dma_chan->chan_id       = i;
1636                 list_add_tail(&dma_chan->device_node, &dma->channels);
1637         }
1638
1639         idmac_write_icreg(ipu, 0x00000070, IDMAC_CONF);
1640
1641         return dma_async_device_register(&idmac->dma);
1642 }
1643
1644 static void ipu_idmac_exit(struct ipu *ipu)
1645 {
1646         int i;
1647         struct idmac *idmac = &ipu->idmac;
1648
1649         for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1650                 struct idmac_channel *ichan = ipu->channel + i;
1651
1652                 idmac_control(&ichan->dma_chan, DMA_TERMINATE_ALL, 0);
1653         }
1654
1655         dma_async_device_unregister(&idmac->dma);
1656 }
1657
1658 /*****************************************************************************
1659  * IPU common probe / remove
1660  */
1661
1662 static int __init ipu_probe(struct platform_device *pdev)
1663 {
1664         struct resource *mem_ipu, *mem_ic;
1665         int ret;
1666
1667         spin_lock_init(&ipu_data.lock);
1668
1669         mem_ipu = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1670         mem_ic  = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1671         if (!mem_ipu || !mem_ic)
1672                 return -EINVAL;
1673
1674         ipu_data.dev = &pdev->dev;
1675
1676         platform_set_drvdata(pdev, &ipu_data);
1677
1678         ret = platform_get_irq(pdev, 0);
1679         if (ret < 0)
1680                 goto err_noirq;
1681
1682         ipu_data.irq_fn = ret;
1683         ret = platform_get_irq(pdev, 1);
1684         if (ret < 0)
1685                 goto err_noirq;
1686
1687         ipu_data.irq_err = ret;
1688
1689         dev_dbg(&pdev->dev, "fn irq %u, err irq %u\n",
1690                 ipu_data.irq_fn, ipu_data.irq_err);
1691
1692         /* Remap IPU common registers */
1693         ipu_data.reg_ipu = ioremap(mem_ipu->start, resource_size(mem_ipu));
1694         if (!ipu_data.reg_ipu) {
1695                 ret = -ENOMEM;
1696                 goto err_ioremap_ipu;
1697         }
1698
1699         /* Remap Image Converter and Image DMA Controller registers */
1700         ipu_data.reg_ic = ioremap(mem_ic->start, resource_size(mem_ic));
1701         if (!ipu_data.reg_ic) {
1702                 ret = -ENOMEM;
1703                 goto err_ioremap_ic;
1704         }
1705
1706         /* Get IPU clock */
1707         ipu_data.ipu_clk = clk_get(&pdev->dev, NULL);
1708         if (IS_ERR(ipu_data.ipu_clk)) {
1709                 ret = PTR_ERR(ipu_data.ipu_clk);
1710                 goto err_clk_get;
1711         }
1712
1713         /* Make sure IPU HSP clock is running */
1714         clk_prepare_enable(ipu_data.ipu_clk);
1715
1716         /* Disable all interrupts */
1717         idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_1);
1718         idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_2);
1719         idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_3);
1720         idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_4);
1721         idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_5);
1722
1723         dev_dbg(&pdev->dev, "%s @ 0x%08lx, fn irq %u, err irq %u\n", pdev->name,
1724                 (unsigned long)mem_ipu->start, ipu_data.irq_fn, ipu_data.irq_err);
1725
1726         ret = ipu_irq_attach_irq(&ipu_data, pdev);
1727         if (ret < 0)
1728                 goto err_attach_irq;
1729
1730         /* Initialize DMA engine */
1731         ret = ipu_idmac_init(&ipu_data);
1732         if (ret < 0)
1733                 goto err_idmac_init;
1734
1735         tasklet_init(&ipu_data.tasklet, ipu_gc_tasklet, (unsigned long)&ipu_data);
1736
1737         ipu_data.dev = &pdev->dev;
1738
1739         dev_dbg(ipu_data.dev, "IPU initialized\n");
1740
1741         return 0;
1742
1743 err_idmac_init:
1744 err_attach_irq:
1745         ipu_irq_detach_irq(&ipu_data, pdev);
1746         clk_disable_unprepare(ipu_data.ipu_clk);
1747         clk_put(ipu_data.ipu_clk);
1748 err_clk_get:
1749         iounmap(ipu_data.reg_ic);
1750 err_ioremap_ic:
1751         iounmap(ipu_data.reg_ipu);
1752 err_ioremap_ipu:
1753 err_noirq:
1754         dev_err(&pdev->dev, "Failed to probe IPU: %d\n", ret);
1755         return ret;
1756 }
1757
1758 static int ipu_remove(struct platform_device *pdev)
1759 {
1760         struct ipu *ipu = platform_get_drvdata(pdev);
1761
1762         ipu_idmac_exit(ipu);
1763         ipu_irq_detach_irq(ipu, pdev);
1764         clk_disable_unprepare(ipu->ipu_clk);
1765         clk_put(ipu->ipu_clk);
1766         iounmap(ipu->reg_ic);
1767         iounmap(ipu->reg_ipu);
1768         tasklet_kill(&ipu->tasklet);
1769
1770         return 0;
1771 }
1772
1773 /*
1774  * We need two MEM resources - with IPU-common and Image Converter registers,
1775  * including PF_CONF and IDMAC_* registers, and two IRQs - function and error
1776  */
1777 static struct platform_driver ipu_platform_driver = {
1778         .driver = {
1779                 .name   = "ipu-core",
1780                 .owner  = THIS_MODULE,
1781         },
1782         .remove         = ipu_remove,
1783 };
1784
1785 static int __init ipu_init(void)
1786 {
1787         return platform_driver_probe(&ipu_platform_driver, ipu_probe);
1788 }
1789 subsys_initcall(ipu_init);
1790
1791 MODULE_DESCRIPTION("IPU core driver");
1792 MODULE_LICENSE("GPL v2");
1793 MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
1794 MODULE_ALIAS("platform:ipu-core");