drivers/dma/dw/core.c

   1 /*
   2  * Core driver for the Synopsys DesignWare DMA Controller
   3  *
   4  * Copyright (C) 2007-2008 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  * Copyright (C) 2013 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/bitops.h>
  14 #include <linux/delay.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/dmapool.h>
  18 #include <linux/err.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/mm.h>
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/pm_runtime.h>
  26
  27 #include "../dmaengine.h"
  28 #include "internal.h"
  29
  30 /*
  31  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
  32  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
  33  * of which use ARM any more).  See the "Databook" from Synopsys for
  34  * information beyond what licensees probably provide.
  35  *
  36  * The driver has been tested with the Atmel AT32AP7000, which does not
  37  * support descriptor writeback.
  38  */
  39
  40 #define DWC_DEFAULT_CTLLO(_chan) ({                             \
  41                 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
  42                 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
  43                 bool _is_slave = is_slave_direction(_dwc->direction);   \
  44                 u8 _smsize = _is_slave ? _sconfig->src_maxburst :       \
  45                         DW_DMA_MSIZE_16;                        \
  46                 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst :       \
  47                         DW_DMA_MSIZE_16;                        \
  48                                                                 \
  49                 (DWC_CTLL_DST_MSIZE(_dmsize)                    \
  50                  | DWC_CTLL_SRC_MSIZE(_smsize)                  \
  51                  | DWC_CTLL_LLP_D_EN                            \
  52                  | DWC_CTLL_LLP_S_EN                            \
  53                  | DWC_CTLL_DMS(_dwc->dst_master)               \
  54                  | DWC_CTLL_SMS(_dwc->src_master));             \
  55         })
  56
  57 /*
  58  * Number of descriptors to allocate for each channel. This should be
  59  * made configurable somehow; preferably, the clients (at least the
  60  * ones using slave transfers) should be able to give us a hint.
  61  */
  62 #define NR_DESCS_PER_CHANNEL    64
  63
  64 /* The set of bus widths supported by the DMA controller */
  65 #define DW_DMA_BUSWIDTHS                          \
  66         BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED)       | \
  67         BIT(DMA_SLAVE_BUSWIDTH_1_BYTE)          | \
  68         BIT(DMA_SLAVE_BUSWIDTH_2_BYTES)         | \
  69         BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
  70
  71 /*----------------------------------------------------------------------*/
  72
  73 static struct device *chan2dev(struct dma_chan *chan)
  74 {
  75         return &chan->dev->device;
  76 }
  77
  78 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
  79 {
  80         return to_dw_desc(dwc->active_list.next);
  81 }
  82
  83 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
  84 {
  85         struct dw_desc *desc, *_desc;
  86         struct dw_desc *ret = NULL;
  87         unsigned int i = 0;
  88         unsigned long flags;
  89
  90         spin_lock_irqsave(&dwc->lock, flags);
  91         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
  92                 i++;
  93                 if (async_tx_test_ack(&desc->txd)) {
  94                         list_del(&desc->desc_node);
  95                         ret = desc;
  96                         break;
  97                 }
  98                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
  99         }
 100         spin_unlock_irqrestore(&dwc->lock, flags);
 101
 102         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
 103
 104         return ret;
 105 }
 106
 107 /*
 108  * Move a descriptor, including any children, to the free list.
 109  * `desc' must not be on any lists.
 110  */
 111 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 112 {
 113         unsigned long flags;
 114
 115         if (desc) {
 116                 struct dw_desc *child;
 117
 118                 spin_lock_irqsave(&dwc->lock, flags);
 119                 list_for_each_entry(child, &desc->tx_list, desc_node)
 120                         dev_vdbg(chan2dev(&dwc->chan),
 121                                         "moving child desc %p to freelist\n",
 122                                         child);
 123                 list_splice_init(&desc->tx_list, &dwc->free_list);
 124                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
 125                 list_add(&desc->desc_node, &dwc->free_list);
 126                 spin_unlock_irqrestore(&dwc->lock, flags);
 127         }
 128 }
 129
 130 static void dwc_initialize(struct dw_dma_chan *dwc)
 131 {
 132         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 133         struct dw_dma_slave *dws = dwc->chan.private;
 134         u32 cfghi = DWC_CFGH_FIFO_MODE;
 135         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
 136
 137         if (dwc->initialized == true)
 138                 return;
 139
 140         if (dws) {
 141                 /*
 142                  * We need controller-specific data to set up slave
 143                  * transfers.
 144                  */
 145                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 146
 147                 cfghi |= DWC_CFGH_DST_PER(dws->dst_id);
 148                 cfghi |= DWC_CFGH_SRC_PER(dws->src_id);
 149         } else {
 150                 cfghi |= DWC_CFGH_DST_PER(dwc->dst_id);
 151                 cfghi |= DWC_CFGH_SRC_PER(dwc->src_id);
 152         }
 153
 154         channel_writel(dwc, CFG_LO, cfglo);
 155         channel_writel(dwc, CFG_HI, cfghi);
 156
 157         /* Enable interrupts */
 158         channel_set_bit(dw, MASK.XFER, dwc->mask);
 159         channel_set_bit(dw, MASK.ERROR, dwc->mask);
 160
 161         dwc->initialized = true;
 162 }
 163
 164 /*----------------------------------------------------------------------*/
 165
 166 static inline unsigned int dwc_fast_fls(unsigned long long v)
 167 {
 168         /*
 169          * We can be a lot more clever here, but this should take care
 170          * of the most common optimization.
 171          */
 172         if (!(v & 7))
 173                 return 3;
 174         else if (!(v & 3))
 175                 return 2;
 176         else if (!(v & 1))
 177                 return 1;
 178         return 0;
 179 }
 180
 181 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
 182 {
 183         dev_err(chan2dev(&dwc->chan),
 184                 "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 185                 channel_readl(dwc, SAR),
 186                 channel_readl(dwc, DAR),
 187                 channel_readl(dwc, LLP),
 188                 channel_readl(dwc, CTL_HI),
 189                 channel_readl(dwc, CTL_LO));
 190 }
 191
 192 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
 193 {
 194         channel_clear_bit(dw, CH_EN, dwc->mask);
 195         while (dma_readl(dw, CH_EN) & dwc->mask)
 196                 cpu_relax();
 197 }
 198
 199 /*----------------------------------------------------------------------*/
 200
 201 /* Perform single block transfer */
 202 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
 203                                        struct dw_desc *desc)
 204 {
 205         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 206         u32             ctllo;
 207
 208         /*
 209          * Software emulation of LLP mode relies on interrupts to continue
 210          * multi block transfer.
 211          */
 212         ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
 213
 214         channel_writel(dwc, SAR, desc->lli.sar);
 215         channel_writel(dwc, DAR, desc->lli.dar);
 216         channel_writel(dwc, CTL_LO, ctllo);
 217         channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
 218         channel_set_bit(dw, CH_EN, dwc->mask);
 219
 220         /* Move pointer to next descriptor */
 221         dwc->tx_node_active = dwc->tx_node_active->next;
 222 }
 223
 224 /* Called with dwc->lock held and bh disabled */
 225 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 226 {
 227         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 228         unsigned long   was_soft_llp;
 229
 230         /* ASSERT:  channel is idle */
 231         if (dma_readl(dw, CH_EN) & dwc->mask) {
 232                 dev_err(chan2dev(&dwc->chan),
 233                         "%s: BUG: Attempted to start non-idle channel\n",
 234                         __func__);
 235                 dwc_dump_chan_regs(dwc);
 236
 237                 /* The tasklet will hopefully advance the queue... */
 238                 return;
 239         }
 240
 241         if (dwc->nollp) {
 242                 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
 243                                                 &dwc->flags);
 244                 if (was_soft_llp) {
 245                         dev_err(chan2dev(&dwc->chan),
 246                                 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
 247                         return;
 248                 }
 249
 250                 dwc_initialize(dwc);
 251
 252                 dwc->residue = first->total_len;
 253                 dwc->tx_node_active = &first->tx_list;
 254
 255                 /* Submit first block */
 256                 dwc_do_single_block(dwc, first);
 257
 258                 return;
 259         }
 260
 261         dwc_initialize(dwc);
 262
 263         channel_writel(dwc, LLP, first->txd.phys);
 264         channel_writel(dwc, CTL_LO,
 265                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 266         channel_writel(dwc, CTL_HI, 0);
 267         channel_set_bit(dw, CH_EN, dwc->mask);
 268 }
 269
 270 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
 271 {
 272         struct dw_desc *desc;
 273
 274         if (list_empty(&dwc->queue))
 275                 return;
 276
 277         list_move(dwc->queue.next, &dwc->active_list);
 278         desc = dwc_first_active(dwc);
 279         dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie);
 280         dwc_dostart(dwc, desc);
 281 }
 282
 283 /*----------------------------------------------------------------------*/
 284
 285 static void
 286 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 287                 bool callback_required)
 288 {
 289         dma_async_tx_callback           callback = NULL;
 290         void                            *param = NULL;
 291         struct dma_async_tx_descriptor  *txd = &desc->txd;
 292         struct dw_desc                  *child;
 293         unsigned long                   flags;
 294
 295         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 296
 297         spin_lock_irqsave(&dwc->lock, flags);
 298         dma_cookie_complete(txd);
 299         if (callback_required) {
 300                 callback = txd->callback;
 301                 param = txd->callback_param;
 302         }
 303
 304         /* async_tx_ack */
 305         list_for_each_entry(child, &desc->tx_list, desc_node)
 306                 async_tx_ack(&child->txd);
 307         async_tx_ack(&desc->txd);
 308
 309         list_splice_init(&desc->tx_list, &dwc->free_list);
 310         list_move(&desc->desc_node, &dwc->free_list);
 311
 312         dma_descriptor_unmap(txd);
 313         spin_unlock_irqrestore(&dwc->lock, flags);
 314
 315         if (callback)
 316                 callback(param);
 317 }
 318
 319 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
 320 {
 321         struct dw_desc *desc, *_desc;
 322         LIST_HEAD(list);
 323         unsigned long flags;
 324
 325         spin_lock_irqsave(&dwc->lock, flags);
 326         if (dma_readl(dw, CH_EN) & dwc->mask) {
 327                 dev_err(chan2dev(&dwc->chan),
 328                         "BUG: XFER bit set, but channel not idle!\n");
 329
 330                 /* Try to continue after resetting the channel... */
 331                 dwc_chan_disable(dw, dwc);
 332         }
 333
 334         /*
 335          * Submit queued descriptors ASAP, i.e. before we go through
 336          * the completed ones.
 337          */
 338         list_splice_init(&dwc->active_list, &list);
 339         dwc_dostart_first_queued(dwc);
 340
 341         spin_unlock_irqrestore(&dwc->lock, flags);
 342
 343         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 344                 dwc_descriptor_complete(dwc, desc, true);
 345 }
 346
 347 /* Returns how many bytes were already received from source */
 348 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
 349 {
 350         u32 ctlhi = channel_readl(dwc, CTL_HI);
 351         u32 ctllo = channel_readl(dwc, CTL_LO);
 352
 353         return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
 354 }
 355
 356 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 357 {
 358         dma_addr_t llp;
 359         struct dw_desc *desc, *_desc;
 360         struct dw_desc *child;
 361         u32 status_xfer;
 362         unsigned long flags;
 363
 364         spin_lock_irqsave(&dwc->lock, flags);
 365         llp = channel_readl(dwc, LLP);
 366         status_xfer = dma_readl(dw, RAW.XFER);
 367
 368         if (status_xfer & dwc->mask) {
 369                 /* Everything we've submitted is done */
 370                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 371
 372                 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 373                         struct list_head *head, *active = dwc->tx_node_active;
 374
 375                         /*
 376                          * We are inside first active descriptor.
 377                          * Otherwise something is really wrong.
 378                          */
 379                         desc = dwc_first_active(dwc);
 380
 381                         head = &desc->tx_list;
 382                         if (active != head) {
 383                                 /* Update desc to reflect last sent one */
 384                                 if (active != head->next)
 385                                         desc = to_dw_desc(active->prev);
 386
 387                                 dwc->residue -= desc->len;
 388
 389                                 child = to_dw_desc(active);
 390
 391                                 /* Submit next block */
 392                                 dwc_do_single_block(dwc, child);
 393
 394                                 spin_unlock_irqrestore(&dwc->lock, flags);
 395                                 return;
 396                         }
 397
 398                         /* We are done here */
 399                         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
 400                 }
 401
 402                 dwc->residue = 0;
 403
 404                 spin_unlock_irqrestore(&dwc->lock, flags);
 405
 406                 dwc_complete_all(dw, dwc);
 407                 return;
 408         }
 409
 410         if (list_empty(&dwc->active_list)) {
 411                 dwc->residue = 0;
 412                 spin_unlock_irqrestore(&dwc->lock, flags);
 413                 return;
 414         }
 415
 416         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 417                 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
 418                 spin_unlock_irqrestore(&dwc->lock, flags);
 419                 return;
 420         }
 421
 422         dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
 423
 424         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 425                 /* Initial residue value */
 426                 dwc->residue = desc->total_len;
 427
 428                 /* Check first descriptors addr */
 429                 if (desc->txd.phys == llp) {
 430                         spin_unlock_irqrestore(&dwc->lock, flags);
 431                         return;
 432                 }
 433
 434                 /* Check first descriptors llp */
 435                 if (desc->lli.llp == llp) {
 436                         /* This one is currently in progress */
 437                         dwc->residue -= dwc_get_sent(dwc);
 438                         spin_unlock_irqrestore(&dwc->lock, flags);
 439                         return;
 440                 }
 441
 442                 dwc->residue -= desc->len;
 443                 list_for_each_entry(child, &desc->tx_list, desc_node) {
 444                         if (child->lli.llp == llp) {
 445                                 /* Currently in progress */
 446                                 dwc->residue -= dwc_get_sent(dwc);
 447                                 spin_unlock_irqrestore(&dwc->lock, flags);
 448                                 return;
 449                         }
 450                         dwc->residue -= child->len;
 451                 }
 452
 453                 /*
 454                  * No descriptors so far seem to be in progress, i.e.
 455                  * this one must be done.
 456                  */
 457                 spin_unlock_irqrestore(&dwc->lock, flags);
 458                 dwc_descriptor_complete(dwc, desc, true);
 459                 spin_lock_irqsave(&dwc->lock, flags);
 460         }
 461
 462         dev_err(chan2dev(&dwc->chan),
 463                 "BUG: All descriptors done, but channel not idle!\n");
 464
 465         /* Try to continue after resetting the channel... */
 466         dwc_chan_disable(dw, dwc);
 467
 468         dwc_dostart_first_queued(dwc);
 469         spin_unlock_irqrestore(&dwc->lock, flags);
 470 }
 471
 472 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
 473 {
 474         dev_crit(chan2dev(&dwc->chan), "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
 475                  lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
 476 }
 477
 478 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
 479 {
 480         struct dw_desc *bad_desc;
 481         struct dw_desc *child;
 482         unsigned long flags;
 483
 484         dwc_scan_descriptors(dw, dwc);
 485
 486         spin_lock_irqsave(&dwc->lock, flags);
 487
 488         /*
 489          * The descriptor currently at the head of the active list is
 490          * borked. Since we don't have any way to report errors, we'll
 491          * just have to scream loudly and try to carry on.
 492          */
 493         bad_desc = dwc_first_active(dwc);
 494         list_del_init(&bad_desc->desc_node);
 495         list_move(dwc->queue.next, dwc->active_list.prev);
 496
 497         /* Clear the error flag and try to restart the controller */
 498         dma_writel(dw, CLEAR.ERROR, dwc->mask);
 499         if (!list_empty(&dwc->active_list))
 500                 dwc_dostart(dwc, dwc_first_active(dwc));
 501
 502         /*
 503          * WARN may seem harsh, but since this only happens
 504          * when someone submits a bad physical address in a
 505          * descriptor, we should consider ourselves lucky that the
 506          * controller flagged an error instead of scribbling over
 507          * random memory locations.
 508          */
 509         dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
 510                                        "  cookie: %d\n", bad_desc->txd.cookie);
 511         dwc_dump_lli(dwc, &bad_desc->lli);
 512         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 513                 dwc_dump_lli(dwc, &child->lli);
 514
 515         spin_unlock_irqrestore(&dwc->lock, flags);
 516
 517         /* Pretend the descriptor completed successfully */
 518         dwc_descriptor_complete(dwc, bad_desc, true);
 519 }
 520
 521 /* --------------------- Cyclic DMA API extensions -------------------- */
 522
 523 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
 524 {
 525         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 526         return channel_readl(dwc, SAR);
 527 }
 528 EXPORT_SYMBOL(dw_dma_get_src_addr);
 529
 530 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
 531 {
 532         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 533         return channel_readl(dwc, DAR);
 534 }
 535 EXPORT_SYMBOL(dw_dma_get_dst_addr);
 536
 537 /* Called with dwc->lock held and all DMAC interrupts disabled */
 538 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 539                 u32 status_err, u32 status_xfer)
 540 {
 541         unsigned long flags;
 542
 543         if (dwc->mask) {
 544                 void (*callback)(void *param);
 545                 void *callback_param;
 546
 547                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
 548                                 channel_readl(dwc, LLP));
 549
 550                 callback = dwc->cdesc->period_callback;
 551                 callback_param = dwc->cdesc->period_callback_param;
 552
 553                 if (callback)
 554                         callback(callback_param);
 555         }
 556
 557         /*
 558          * Error and transfer complete are highly unlikely, and will most
 559          * likely be due to a configuration error by the user.
 560          */
 561         if (unlikely(status_err & dwc->mask) ||
 562                         unlikely(status_xfer & dwc->mask)) {
 563                 int i;
 564
 565                 dev_err(chan2dev(&dwc->chan),
 566                         "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
 567                         status_xfer ? "xfer" : "error");
 568
 569                 spin_lock_irqsave(&dwc->lock, flags);
 570
 571                 dwc_dump_chan_regs(dwc);
 572
 573                 dwc_chan_disable(dw, dwc);
 574
 575                 /* Make sure DMA does not restart by loading a new list */
 576                 channel_writel(dwc, LLP, 0);
 577                 channel_writel(dwc, CTL_LO, 0);
 578                 channel_writel(dwc, CTL_HI, 0);
 579
 580                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
 581                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 582
 583                 for (i = 0; i < dwc->cdesc->periods; i++)
 584                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
 585
 586                 spin_unlock_irqrestore(&dwc->lock, flags);
 587         }
 588 }
 589
 590 /* ------------------------------------------------------------------------- */
 591
 592 static void dw_dma_tasklet(unsigned long data)
 593 {
 594         struct dw_dma *dw = (struct dw_dma *)data;
 595         struct dw_dma_chan *dwc;
 596         u32 status_xfer;
 597         u32 status_err;
 598         int i;
 599
 600         status_xfer = dma_readl(dw, RAW.XFER);
 601         status_err = dma_readl(dw, RAW.ERROR);
 602
 603         dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
 604
 605         for (i = 0; i < dw->dma.chancnt; i++) {
 606                 dwc = &dw->chan[i];
 607                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
 608                         dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
 609                 else if (status_err & (1 << i))
 610                         dwc_handle_error(dw, dwc);
 611                 else if (status_xfer & (1 << i))
 612                         dwc_scan_descriptors(dw, dwc);
 613         }
 614
 615         /*
 616          * Re-enable interrupts.
 617          */
 618         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
 619         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 620 }
 621
 622 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 623 {
 624         struct dw_dma *dw = dev_id;
 625         u32 status = dma_readl(dw, STATUS_INT);
 626
 627         dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
 628
 629         /* Check if we have any interrupt from the DMAC */
 630         if (!status || !dw->in_use)
 631                 return IRQ_NONE;
 632
 633         /*
 634          * Just disable the interrupts. We'll turn them back on in the
 635          * softirq handler.
 636          */
 637         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
 638         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 639
 640         status = dma_readl(dw, STATUS_INT);
 641         if (status) {
 642                 dev_err(dw->dma.dev,
 643                         "BUG: Unexpected interrupts pending: 0x%x\n",
 644                         status);
 645
 646                 /* Try to recover */
 647                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
 648                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
 649                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
 650                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
 651         }
 652
 653         tasklet_schedule(&dw->tasklet);
 654
 655         return IRQ_HANDLED;
 656 }
 657
 658 /*----------------------------------------------------------------------*/
 659
 660 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 661 {
 662         struct dw_desc          *desc = txd_to_dw_desc(tx);
 663         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
 664         dma_cookie_t            cookie;
 665         unsigned long           flags;
 666
 667         spin_lock_irqsave(&dwc->lock, flags);
 668         cookie = dma_cookie_assign(tx);
 669
 670         /*
 671          * REVISIT: We should attempt to chain as many descriptors as
 672          * possible, perhaps even appending to those already submitted
 673          * for DMA. But this is hard to do in a race-free manner.
 674          */
 675
 676         dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie);
 677         list_add_tail(&desc->desc_node, &dwc->queue);
 678
 679         spin_unlock_irqrestore(&dwc->lock, flags);
 680
 681         return cookie;
 682 }
 683
 684 static struct dma_async_tx_descriptor *
 685 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 686                 size_t len, unsigned long flags)
 687 {
 688         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 689         struct dw_dma           *dw = to_dw_dma(chan->device);
 690         struct dw_desc          *desc;
 691         struct dw_desc          *first;
 692         struct dw_desc          *prev;
 693         size_t                  xfer_count;
 694         size_t                  offset;
 695         unsigned int            src_width;
 696         unsigned int            dst_width;
 697         unsigned int            data_width;
 698         u32                     ctllo;
 699
 700         dev_vdbg(chan2dev(chan),
 701                         "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
 702                         &dest, &src, len, flags);
 703
 704         if (unlikely(!len)) {
 705                 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
 706                 return NULL;
 707         }
 708
 709         dwc->direction = DMA_MEM_TO_MEM;
 710
 711         data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
 712                            dw->data_width[dwc->dst_master]);
 713
 714         src_width = dst_width = min_t(unsigned int, data_width,
 715                                       dwc_fast_fls(src | dest | len));
 716
 717         ctllo = DWC_DEFAULT_CTLLO(chan)
 718                         | DWC_CTLL_DST_WIDTH(dst_width)
 719                         | DWC_CTLL_SRC_WIDTH(src_width)
 720                         | DWC_CTLL_DST_INC
 721                         | DWC_CTLL_SRC_INC
 722                         | DWC_CTLL_FC_M2M;
 723         prev = first = NULL;
 724
 725         for (offset = 0; offset < len; offset += xfer_count << src_width) {
 726                 xfer_count = min_t(size_t, (len - offset) >> src_width,
 727                                            dwc->block_size);
 728
 729                 desc = dwc_desc_get(dwc);
 730                 if (!desc)
 731                         goto err_desc_get;
 732
 733                 desc->lli.sar = src + offset;
 734                 desc->lli.dar = dest + offset;
 735                 desc->lli.ctllo = ctllo;
 736                 desc->lli.ctlhi = xfer_count;
 737                 desc->len = xfer_count << src_width;
 738
 739                 if (!first) {
 740                         first = desc;
 741                 } else {
 742                         prev->lli.llp = desc->txd.phys;
 743                         list_add_tail(&desc->desc_node,
 744                                         &first->tx_list);
 745                 }
 746                 prev = desc;
 747         }
 748
 749         if (flags & DMA_PREP_INTERRUPT)
 750                 /* Trigger interrupt after last block */
 751                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 752
 753         prev->lli.llp = 0;
 754         first->txd.flags = flags;
 755         first->total_len = len;
 756
 757         return &first->txd;
 758
 759 err_desc_get:
 760         dwc_desc_put(dwc, first);
 761         return NULL;
 762 }
 763
 764 static struct dma_async_tx_descriptor *
 765 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 766                 unsigned int sg_len, enum dma_transfer_direction direction,
 767                 unsigned long flags, void *context)
 768 {
 769         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 770         struct dw_dma           *dw = to_dw_dma(chan->device);
 771         struct dma_slave_config *sconfig = &dwc->dma_sconfig;
 772         struct dw_desc          *prev;
 773         struct dw_desc          *first;
 774         u32                     ctllo;
 775         dma_addr_t              reg;
 776         unsigned int            reg_width;
 777         unsigned int            mem_width;
 778         unsigned int            data_width;
 779         unsigned int            i;
 780         struct scatterlist      *sg;
 781         size_t                  total_len = 0;
 782
 783         dev_vdbg(chan2dev(chan), "%s\n", __func__);
 784
 785         if (unlikely(!is_slave_direction(direction) || !sg_len))
 786                 return NULL;
 787
 788         dwc->direction = direction;
 789
 790         prev = first = NULL;
 791
 792         switch (direction) {
 793         case DMA_MEM_TO_DEV:
 794                 reg_width = __fls(sconfig->dst_addr_width);
 795                 reg = sconfig->dst_addr;
 796                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 797                                 | DWC_CTLL_DST_WIDTH(reg_width)
 798                                 | DWC_CTLL_DST_FIX
 799                                 | DWC_CTLL_SRC_INC);
 800
 801                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
 802                         DWC_CTLL_FC(DW_DMA_FC_D_M2P);
 803
 804                 data_width = dw->data_width[dwc->src_master];
 805
 806                 for_each_sg(sgl, sg, sg_len, i) {
 807                         struct dw_desc  *desc;
 808                         u32             len, dlen, mem;
 809
 810                         mem = sg_dma_address(sg);
 811                         len = sg_dma_len(sg);
 812
 813                         mem_width = min_t(unsigned int,
 814                                           data_width, dwc_fast_fls(mem | len));
 815
 816 slave_sg_todev_fill_desc:
 817                         desc = dwc_desc_get(dwc);
 818                         if (!desc)
 819                                 goto err_desc_get;
 820
 821                         desc->lli.sar = mem;
 822                         desc->lli.dar = reg;
 823                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
 824                         if ((len >> mem_width) > dwc->block_size) {
 825                                 dlen = dwc->block_size << mem_width;
 826                                 mem += dlen;
 827                                 len -= dlen;
 828                         } else {
 829                                 dlen = len;
 830                                 len = 0;
 831                         }
 832
 833                         desc->lli.ctlhi = dlen >> mem_width;
 834                         desc->len = dlen;
 835
 836                         if (!first) {
 837                                 first = desc;
 838                         } else {
 839                                 prev->lli.llp = desc->txd.phys;
 840                                 list_add_tail(&desc->desc_node,
 841                                                 &first->tx_list);
 842                         }
 843                         prev = desc;
 844                         total_len += dlen;
 845
 846                         if (len)
 847                                 goto slave_sg_todev_fill_desc;
 848                 }
 849                 break;
 850         case DMA_DEV_TO_MEM:
 851                 reg_width = __fls(sconfig->src_addr_width);
 852                 reg = sconfig->src_addr;
 853                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 854                                 | DWC_CTLL_SRC_WIDTH(reg_width)
 855                                 | DWC_CTLL_DST_INC
 856                                 | DWC_CTLL_SRC_FIX);
 857
 858                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
 859                         DWC_CTLL_FC(DW_DMA_FC_D_P2M);
 860
 861                 data_width = dw->data_width[dwc->dst_master];
 862
 863                 for_each_sg(sgl, sg, sg_len, i) {
 864                         struct dw_desc  *desc;
 865                         u32             len, dlen, mem;
 866
 867                         mem = sg_dma_address(sg);
 868                         len = sg_dma_len(sg);
 869
 870                         mem_width = min_t(unsigned int,
 871                                           data_width, dwc_fast_fls(mem | len));
 872
 873 slave_sg_fromdev_fill_desc:
 874                         desc = dwc_desc_get(dwc);
 875                         if (!desc)
 876                                 goto err_desc_get;
 877
 878                         desc->lli.sar = reg;
 879                         desc->lli.dar = mem;
 880                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
 881                         if ((len >> reg_width) > dwc->block_size) {
 882                                 dlen = dwc->block_size << reg_width;
 883                                 mem += dlen;
 884                                 len -= dlen;
 885                         } else {
 886                                 dlen = len;
 887                                 len = 0;
 888                         }
 889                         desc->lli.ctlhi = dlen >> reg_width;
 890                         desc->len = dlen;
 891
 892                         if (!first) {
 893                                 first = desc;
 894                         } else {
 895                                 prev->lli.llp = desc->txd.phys;
 896                                 list_add_tail(&desc->desc_node,
 897                                                 &first->tx_list);
 898                         }
 899                         prev = desc;
 900                         total_len += dlen;
 901
 902                         if (len)
 903                                 goto slave_sg_fromdev_fill_desc;
 904                 }
 905                 break;
 906         default:
 907                 return NULL;
 908         }
 909
 910         if (flags & DMA_PREP_INTERRUPT)
 911                 /* Trigger interrupt after last block */
 912                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 913
 914         prev->lli.llp = 0;
 915         first->total_len = total_len;
 916
 917         return &first->txd;
 918
 919 err_desc_get:
 920         dev_err(chan2dev(chan),
 921                 "not enough descriptors available. Direction %d\n", direction);
 922         dwc_desc_put(dwc, first);
 923         return NULL;
 924 }
 925
 926 bool dw_dma_filter(struct dma_chan *chan, void *param)
 927 {
 928         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 929         struct dw_dma_slave *dws = param;
 930
 931         if (!dws || dws->dma_dev != chan->device->dev)
 932                 return false;
 933
 934         /* We have to copy data since dws can be temporary storage */
 935
 936         dwc->src_id = dws->src_id;
 937         dwc->dst_id = dws->dst_id;
 938
 939         dwc->src_master = dws->src_master;
 940         dwc->dst_master = dws->dst_master;
 941
 942         return true;
 943 }
 944 EXPORT_SYMBOL_GPL(dw_dma_filter);
 945
 946 /*
 947  * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
 948  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 949  *
 950  * NOTE: burst size 2 is not supported by controller.
 951  *
 952  * This can be done by finding least significant bit set: n & (n - 1)
 953  */
 954 static inline void convert_burst(u32 *maxburst)
 955 {
 956         if (*maxburst > 1)
 957                 *maxburst = fls(*maxburst) - 2;
 958         else
 959                 *maxburst = 0;
 960 }
 961
 962 static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
 963 {
 964         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 965
 966         /* Check if chan will be configured for slave transfers */
 967         if (!is_slave_direction(sconfig->direction))
 968                 return -EINVAL;
 969
 970         memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
 971         dwc->direction = sconfig->direction;
 972
 973         convert_burst(&dwc->dma_sconfig.src_maxburst);
 974         convert_burst(&dwc->dma_sconfig.dst_maxburst);
 975
 976         return 0;
 977 }
 978
 979 static int dwc_pause(struct dma_chan *chan)
 980 {
 981         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 982         unsigned long           flags;
 983         unsigned int            count = 20;     /* timeout iterations */
 984         u32                     cfglo;
 985
 986         spin_lock_irqsave(&dwc->lock, flags);
 987
 988         cfglo = channel_readl(dwc, CFG_LO);
 989         channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
 990         while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
 991                 udelay(2);
 992
 993         dwc->paused = true;
 994
 995         spin_unlock_irqrestore(&dwc->lock, flags);
 996
 997         return 0;
 998 }
 999
1000 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
1001 {
1002         u32 cfglo = channel_readl(dwc, CFG_LO);
1003
1004         channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1005
1006         dwc->paused = false;
1007 }
1008
1009 static int dwc_resume(struct dma_chan *chan)
1010 {
1011         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1012         unsigned long           flags;
1013
1014         if (!dwc->paused)
1015                 return 0;
1016
1017         spin_lock_irqsave(&dwc->lock, flags);
1018
1019         dwc_chan_resume(dwc);
1020
1021         spin_unlock_irqrestore(&dwc->lock, flags);
1022
1023         return 0;
1024 }
1025
1026 static int dwc_terminate_all(struct dma_chan *chan)
1027 {
1028         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1029         struct dw_dma           *dw = to_dw_dma(chan->device);
1030         struct dw_desc          *desc, *_desc;
1031         unsigned long           flags;
1032         LIST_HEAD(list);
1033
1034         spin_lock_irqsave(&dwc->lock, flags);
1035
1036         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1037
1038         dwc_chan_disable(dw, dwc);
1039
1040         dwc_chan_resume(dwc);
1041
1042         /* active_list entries will end up before queued entries */
1043         list_splice_init(&dwc->queue, &list);
1044         list_splice_init(&dwc->active_list, &list);
1045
1046         spin_unlock_irqrestore(&dwc->lock, flags);
1047
1048         /* Flush all pending and queued descriptors */
1049         list_for_each_entry_safe(desc, _desc, &list, desc_node)
1050                 dwc_descriptor_complete(dwc, desc, false);
1051
1052         return 0;
1053 }
1054
1055 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1056 {
1057         unsigned long flags;
1058         u32 residue;
1059
1060         spin_lock_irqsave(&dwc->lock, flags);
1061
1062         residue = dwc->residue;
1063         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1064                 residue -= dwc_get_sent(dwc);
1065
1066         spin_unlock_irqrestore(&dwc->lock, flags);
1067         return residue;
1068 }
1069
1070 static enum dma_status
1071 dwc_tx_status(struct dma_chan *chan,
1072               dma_cookie_t cookie,
1073               struct dma_tx_state *txstate)
1074 {
1075         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1076         enum dma_status         ret;
1077
1078         ret = dma_cookie_status(chan, cookie, txstate);
1079         if (ret == DMA_COMPLETE)
1080                 return ret;
1081
1082         dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1083
1084         ret = dma_cookie_status(chan, cookie, txstate);
1085         if (ret != DMA_COMPLETE)
1086                 dma_set_residue(txstate, dwc_get_residue(dwc));
1087
1088         if (dwc->paused && ret == DMA_IN_PROGRESS)
1089                 return DMA_PAUSED;
1090
1091         return ret;
1092 }
1093
1094 static void dwc_issue_pending(struct dma_chan *chan)
1095 {
1096         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1097         unsigned long           flags;
1098
1099         spin_lock_irqsave(&dwc->lock, flags);
1100         if (list_empty(&dwc->active_list))
1101                 dwc_dostart_first_queued(dwc);
1102         spin_unlock_irqrestore(&dwc->lock, flags);
1103 }
1104
1105 /*----------------------------------------------------------------------*/
1106
1107 static void dw_dma_off(struct dw_dma *dw)
1108 {
1109         int i;
1110
1111         dma_writel(dw, CFG, 0);
1112
1113         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1114         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1115         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1116         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1117
1118         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1119                 cpu_relax();
1120
1121         for (i = 0; i < dw->dma.chancnt; i++)
1122                 dw->chan[i].initialized = false;
1123 }
1124
1125 static void dw_dma_on(struct dw_dma *dw)
1126 {
1127         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1128 }
1129
1130 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1131 {
1132         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1133         struct dw_dma           *dw = to_dw_dma(chan->device);
1134         struct dw_desc          *desc;
1135         int                     i;
1136         unsigned long           flags;
1137
1138         dev_vdbg(chan2dev(chan), "%s\n", __func__);
1139
1140         /* ASSERT:  channel is idle */
1141         if (dma_readl(dw, CH_EN) & dwc->mask) {
1142                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1143                 return -EIO;
1144         }
1145
1146         dma_cookie_init(chan);
1147
1148         /*
1149          * NOTE: some controllers may have additional features that we
1150          * need to initialize here, like "scatter-gather" (which
1151          * doesn't mean what you think it means), and status writeback.
1152          */
1153
1154         /* Enable controller here if needed */
1155         if (!dw->in_use)
1156                 dw_dma_on(dw);
1157         dw->in_use |= dwc->mask;
1158
1159         spin_lock_irqsave(&dwc->lock, flags);
1160         i = dwc->descs_allocated;
1161         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1162                 dma_addr_t phys;
1163
1164                 spin_unlock_irqrestore(&dwc->lock, flags);
1165
1166                 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1167                 if (!desc)
1168                         goto err_desc_alloc;
1169
1170                 memset(desc, 0, sizeof(struct dw_desc));
1171
1172                 INIT_LIST_HEAD(&desc->tx_list);
1173                 dma_async_tx_descriptor_init(&desc->txd, chan);
1174                 desc->txd.tx_submit = dwc_tx_submit;
1175                 desc->txd.flags = DMA_CTRL_ACK;
1176                 desc->txd.phys = phys;
1177
1178                 dwc_desc_put(dwc, desc);
1179
1180                 spin_lock_irqsave(&dwc->lock, flags);
1181                 i = ++dwc->descs_allocated;
1182         }
1183
1184         spin_unlock_irqrestore(&dwc->lock, flags);
1185
1186         dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1187
1188         return i;
1189
1190 err_desc_alloc:
1191         dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1192
1193         return i;
1194 }
1195
1196 static void dwc_free_chan_resources(struct dma_chan *chan)
1197 {
1198         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1199         struct dw_dma           *dw = to_dw_dma(chan->device);
1200         struct dw_desc          *desc, *_desc;
1201         unsigned long           flags;
1202         LIST_HEAD(list);
1203
1204         dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1205                         dwc->descs_allocated);
1206
1207         /* ASSERT:  channel is idle */
1208         BUG_ON(!list_empty(&dwc->active_list));
1209         BUG_ON(!list_empty(&dwc->queue));
1210         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1211
1212         spin_lock_irqsave(&dwc->lock, flags);
1213         list_splice_init(&dwc->free_list, &list);
1214         dwc->descs_allocated = 0;
1215         dwc->initialized = false;
1216
1217         /* Disable interrupts */
1218         channel_clear_bit(dw, MASK.XFER, dwc->mask);
1219         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1220
1221         spin_unlock_irqrestore(&dwc->lock, flags);
1222
1223         /* Disable controller in case it was a last user */
1224         dw->in_use &= ~dwc->mask;
1225         if (!dw->in_use)
1226                 dw_dma_off(dw);
1227
1228         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1229                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1230                 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1231         }
1232
1233         dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1234 }
1235
1236 /* --------------------- Cyclic DMA API extensions -------------------- */
1237
1238 /**
1239  * dw_dma_cyclic_start - start the cyclic DMA transfer
1240  * @chan: the DMA channel to start
1241  *
1242  * Must be called with soft interrupts disabled. Returns zero on success or
1243  * -errno on failure.
1244  */
1245 int dw_dma_cyclic_start(struct dma_chan *chan)
1246 {
1247         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1248         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1249         unsigned long           flags;
1250
1251         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1252                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1253                 return -ENODEV;
1254         }
1255
1256         spin_lock_irqsave(&dwc->lock, flags);
1257
1258         /* Assert channel is idle */
1259         if (dma_readl(dw, CH_EN) & dwc->mask) {
1260                 dev_err(chan2dev(&dwc->chan),
1261                         "%s: BUG: Attempted to start non-idle channel\n",
1262                         __func__);
1263                 dwc_dump_chan_regs(dwc);
1264                 spin_unlock_irqrestore(&dwc->lock, flags);
1265                 return -EBUSY;
1266         }
1267
1268         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1269         dma_writel(dw, CLEAR.XFER, dwc->mask);
1270
1271         /* Setup DMAC channel registers */
1272         channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1273         channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1274         channel_writel(dwc, CTL_HI, 0);
1275
1276         channel_set_bit(dw, CH_EN, dwc->mask);
1277
1278         spin_unlock_irqrestore(&dwc->lock, flags);
1279
1280         return 0;
1281 }
1282 EXPORT_SYMBOL(dw_dma_cyclic_start);
1283
1284 /**
1285  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1286  * @chan: the DMA channel to stop
1287  *
1288  * Must be called with soft interrupts disabled.
1289  */
1290 void dw_dma_cyclic_stop(struct dma_chan *chan)
1291 {
1292         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1293         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1294         unsigned long           flags;
1295
1296         spin_lock_irqsave(&dwc->lock, flags);
1297
1298         dwc_chan_disable(dw, dwc);
1299
1300         spin_unlock_irqrestore(&dwc->lock, flags);
1301 }
1302 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1303
1304 /**
1305  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1306  * @chan: the DMA channel to prepare
1307  * @buf_addr: physical DMA address where the buffer starts
1308  * @buf_len: total number of bytes for the entire buffer
1309  * @period_len: number of bytes for each period
1310  * @direction: transfer direction, to or from device
1311  *
1312  * Must be called before trying to start the transfer. Returns a valid struct
1313  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1314  */
1315 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1316                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1317                 enum dma_transfer_direction direction)
1318 {
1319         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1320         struct dma_slave_config         *sconfig = &dwc->dma_sconfig;
1321         struct dw_cyclic_desc           *cdesc;
1322         struct dw_cyclic_desc           *retval = NULL;
1323         struct dw_desc                  *desc;
1324         struct dw_desc                  *last = NULL;
1325         unsigned long                   was_cyclic;
1326         unsigned int                    reg_width;
1327         unsigned int                    periods;
1328         unsigned int                    i;
1329         unsigned long                   flags;
1330
1331         spin_lock_irqsave(&dwc->lock, flags);
1332         if (dwc->nollp) {
1333                 spin_unlock_irqrestore(&dwc->lock, flags);
1334                 dev_dbg(chan2dev(&dwc->chan),
1335                                 "channel doesn't support LLP transfers\n");
1336                 return ERR_PTR(-EINVAL);
1337         }
1338
1339         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1340                 spin_unlock_irqrestore(&dwc->lock, flags);
1341                 dev_dbg(chan2dev(&dwc->chan),
1342                                 "queue and/or active list are not empty\n");
1343                 return ERR_PTR(-EBUSY);
1344         }
1345
1346         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1347         spin_unlock_irqrestore(&dwc->lock, flags);
1348         if (was_cyclic) {
1349                 dev_dbg(chan2dev(&dwc->chan),
1350                                 "channel already prepared for cyclic DMA\n");
1351                 return ERR_PTR(-EBUSY);
1352         }
1353
1354         retval = ERR_PTR(-EINVAL);
1355
1356         if (unlikely(!is_slave_direction(direction)))
1357                 goto out_err;
1358
1359         dwc->direction = direction;
1360
1361         if (direction == DMA_MEM_TO_DEV)
1362                 reg_width = __ffs(sconfig->dst_addr_width);
1363         else
1364                 reg_width = __ffs(sconfig->src_addr_width);
1365
1366         periods = buf_len / period_len;
1367
1368         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1369         if (period_len > (dwc->block_size << reg_width))
1370                 goto out_err;
1371         if (unlikely(period_len & ((1 << reg_width) - 1)))
1372                 goto out_err;
1373         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1374                 goto out_err;
1375
1376         retval = ERR_PTR(-ENOMEM);
1377
1378         if (periods > NR_DESCS_PER_CHANNEL)
1379                 goto out_err;
1380
1381         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1382         if (!cdesc)
1383                 goto out_err;
1384
1385         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1386         if (!cdesc->desc)
1387                 goto out_err_alloc;
1388
1389         for (i = 0; i < periods; i++) {
1390                 desc = dwc_desc_get(dwc);
1391                 if (!desc)
1392                         goto out_err_desc_get;
1393
1394                 switch (direction) {
1395                 case DMA_MEM_TO_DEV:
1396                         desc->lli.dar = sconfig->dst_addr;
1397                         desc->lli.sar = buf_addr + (period_len * i);
1398                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1399                                         | DWC_CTLL_DST_WIDTH(reg_width)
1400                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1401                                         | DWC_CTLL_DST_FIX
1402                                         | DWC_CTLL_SRC_INC
1403                                         | DWC_CTLL_INT_EN);
1404
1405                         desc->lli.ctllo |= sconfig->device_fc ?
1406                                 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1407                                 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1408
1409                         break;
1410                 case DMA_DEV_TO_MEM:
1411                         desc->lli.dar = buf_addr + (period_len * i);
1412                         desc->lli.sar = sconfig->src_addr;
1413                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1414                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1415                                         | DWC_CTLL_DST_WIDTH(reg_width)
1416                                         | DWC_CTLL_DST_INC
1417                                         | DWC_CTLL_SRC_FIX
1418                                         | DWC_CTLL_INT_EN);
1419
1420                         desc->lli.ctllo |= sconfig->device_fc ?
1421                                 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1422                                 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1423
1424                         break;
1425                 default:
1426                         break;
1427                 }
1428
1429                 desc->lli.ctlhi = (period_len >> reg_width);
1430                 cdesc->desc[i] = desc;
1431
1432                 if (last)
1433                         last->lli.llp = desc->txd.phys;
1434
1435                 last = desc;
1436         }
1437
1438         /* Let's make a cyclic list */
1439         last->lli.llp = cdesc->desc[0]->txd.phys;
1440
1441         dev_dbg(chan2dev(&dwc->chan),
1442                         "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1443                         &buf_addr, buf_len, period_len, periods);
1444
1445         cdesc->periods = periods;
1446         dwc->cdesc = cdesc;
1447
1448         return cdesc;
1449
1450 out_err_desc_get:
1451         while (i--)
1452                 dwc_desc_put(dwc, cdesc->desc[i]);
1453 out_err_alloc:
1454         kfree(cdesc);
1455 out_err:
1456         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1457         return (struct dw_cyclic_desc *)retval;
1458 }
1459 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1460
1461 /**
1462  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1463  * @chan: the DMA channel to free
1464  */
1465 void dw_dma_cyclic_free(struct dma_chan *chan)
1466 {
1467         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1468         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1469         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1470         int                     i;
1471         unsigned long           flags;
1472
1473         dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1474
1475         if (!cdesc)
1476                 return;
1477
1478         spin_lock_irqsave(&dwc->lock, flags);
1479
1480         dwc_chan_disable(dw, dwc);
1481
1482         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1483         dma_writel(dw, CLEAR.XFER, dwc->mask);
1484
1485         spin_unlock_irqrestore(&dwc->lock, flags);
1486
1487         for (i = 0; i < cdesc->periods; i++)
1488                 dwc_desc_put(dwc, cdesc->desc[i]);
1489
1490         kfree(cdesc->desc);
1491         kfree(cdesc);
1492
1493         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1494 }
1495 EXPORT_SYMBOL(dw_dma_cyclic_free);
1496
1497 /*----------------------------------------------------------------------*/
1498
1499 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1500 {
1501         struct dw_dma           *dw;
1502         bool                    autocfg;
1503         unsigned int            dw_params;
1504         unsigned int            nr_channels;
1505         unsigned int            max_blk_size = 0;
1506         int                     err;
1507         int                     i;
1508
1509         dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
1510         if (!dw)
1511                 return -ENOMEM;
1512
1513         dw->regs = chip->regs;
1514         chip->dw = dw;
1515
1516         pm_runtime_get_sync(chip->dev);
1517
1518         dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1519         autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1520
1521         dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1522
1523         if (!pdata && autocfg) {
1524                 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
1525                 if (!pdata) {
1526                         err = -ENOMEM;
1527                         goto err_pdata;
1528                 }
1529
1530                 /* Fill platform data with the default values */
1531                 pdata->is_private = true;
1532                 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1533                 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1534         } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1535                 err = -EINVAL;
1536                 goto err_pdata;
1537         }
1538
1539         if (autocfg)
1540                 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1541         else
1542                 nr_channels = pdata->nr_channels;
1543
1544         dw->chan = devm_kcalloc(chip->dev, nr_channels, sizeof(*dw->chan),
1545                                 GFP_KERNEL);
1546         if (!dw->chan) {
1547                 err = -ENOMEM;
1548                 goto err_pdata;
1549         }
1550
1551         /* Get hardware configuration parameters */
1552         if (autocfg) {
1553                 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1554
1555                 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1556                 for (i = 0; i < dw->nr_masters; i++) {
1557                         dw->data_width[i] =
1558                                 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1559                 }
1560         } else {
1561                 dw->nr_masters = pdata->nr_masters;
1562                 for (i = 0; i < dw->nr_masters; i++)
1563                         dw->data_width[i] = pdata->data_width[i];
1564         }
1565
1566         /* Calculate all channel mask before DMA setup */
1567         dw->all_chan_mask = (1 << nr_channels) - 1;
1568
1569         /* Force dma off, just in case */
1570         dw_dma_off(dw);
1571
1572         /* Disable BLOCK interrupts as well */
1573         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1574
1575         /* Create a pool of consistent memory blocks for hardware descriptors */
1576         dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1577                                          sizeof(struct dw_desc), 4, 0);
1578         if (!dw->desc_pool) {
1579                 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1580                 err = -ENOMEM;
1581                 goto err_pdata;
1582         }
1583
1584         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1585
1586         err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1587                           "dw_dmac", dw);
1588         if (err)
1589                 goto err_pdata;
1590
1591         INIT_LIST_HEAD(&dw->dma.channels);
1592         for (i = 0; i < nr_channels; i++) {
1593                 struct dw_dma_chan      *dwc = &dw->chan[i];
1594                 int                     r = nr_channels - i - 1;
1595
1596                 dwc->chan.device = &dw->dma;
1597                 dma_cookie_init(&dwc->chan);
1598                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1599                         list_add_tail(&dwc->chan.device_node,
1600                                         &dw->dma.channels);
1601                 else
1602                         list_add(&dwc->chan.device_node, &dw->dma.channels);
1603
1604                 /* 7 is highest priority & 0 is lowest. */
1605                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1606                         dwc->priority = r;
1607                 else
1608                         dwc->priority = i;
1609
1610                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1611                 spin_lock_init(&dwc->lock);
1612                 dwc->mask = 1 << i;
1613
1614                 INIT_LIST_HEAD(&dwc->active_list);
1615                 INIT_LIST_HEAD(&dwc->queue);
1616                 INIT_LIST_HEAD(&dwc->free_list);
1617
1618                 channel_clear_bit(dw, CH_EN, dwc->mask);
1619
1620                 dwc->direction = DMA_TRANS_NONE;
1621
1622                 /* Hardware configuration */
1623                 if (autocfg) {
1624                         unsigned int dwc_params;
1625                         void __iomem *addr = chip->regs + r * sizeof(u32);
1626
1627                         dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
1628
1629                         dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1630                                            dwc_params);
1631
1632                         /*
1633                          * Decode maximum block size for given channel. The
1634                          * stored 4 bit value represents blocks from 0x00 for 3
1635                          * up to 0x0a for 4095.
1636                          */
1637                         dwc->block_size =
1638                                 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1639                         dwc->nollp =
1640                                 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1641                 } else {
1642                         dwc->block_size = pdata->block_size;
1643
1644                         /* Check if channel supports multi block transfer */
1645                         channel_writel(dwc, LLP, 0xfffffffc);
1646                         dwc->nollp =
1647                                 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1648                         channel_writel(dwc, LLP, 0);
1649                 }
1650         }
1651
1652         /* Clear all interrupts on all channels. */
1653         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1654         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1655         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1656         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1657         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1658
1659         dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1660         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1661         if (pdata->is_private)
1662                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1663         dw->dma.dev = chip->dev;
1664         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1665         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1666
1667         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1668         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1669
1670         dw->dma.device_config = dwc_config;
1671         dw->dma.device_pause = dwc_pause;
1672         dw->dma.device_resume = dwc_resume;
1673         dw->dma.device_terminate_all = dwc_terminate_all;
1674
1675         dw->dma.device_tx_status = dwc_tx_status;
1676         dw->dma.device_issue_pending = dwc_issue_pending;
1677
1678         /* DMA capabilities */
1679         dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
1680         dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
1681         dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
1682                              BIT(DMA_MEM_TO_MEM);
1683         dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1684
1685         err = dma_async_device_register(&dw->dma);
1686         if (err)
1687                 goto err_dma_register;
1688
1689         dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1690                  nr_channels);
1691
1692         pm_runtime_put_sync_suspend(chip->dev);
1693
1694         return 0;
1695
1696 err_dma_register:
1697         free_irq(chip->irq, dw);
1698 err_pdata:
1699         pm_runtime_put_sync_suspend(chip->dev);
1700         return err;
1701 }
1702 EXPORT_SYMBOL_GPL(dw_dma_probe);
1703
1704 int dw_dma_remove(struct dw_dma_chip *chip)
1705 {
1706         struct dw_dma           *dw = chip->dw;
1707         struct dw_dma_chan      *dwc, *_dwc;
1708
1709         pm_runtime_get_sync(chip->dev);
1710
1711         dw_dma_off(dw);
1712         dma_async_device_unregister(&dw->dma);
1713
1714         free_irq(chip->irq, dw);
1715         tasklet_kill(&dw->tasklet);
1716
1717         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1718                         chan.device_node) {
1719                 list_del(&dwc->chan.device_node);
1720                 channel_clear_bit(dw, CH_EN, dwc->mask);
1721         }
1722
1723         pm_runtime_put_sync_suspend(chip->dev);
1724         return 0;
1725 }
1726 EXPORT_SYMBOL_GPL(dw_dma_remove);
1727
1728 int dw_dma_disable(struct dw_dma_chip *chip)
1729 {
1730         struct dw_dma *dw = chip->dw;
1731
1732         dw_dma_off(dw);
1733         return 0;
1734 }
1735 EXPORT_SYMBOL_GPL(dw_dma_disable);
1736
1737 int dw_dma_enable(struct dw_dma_chip *chip)
1738 {
1739         struct dw_dma *dw = chip->dw;
1740
1741         dw_dma_on(dw);
1742         return 0;
1743 }
1744 EXPORT_SYMBOL_GPL(dw_dma_enable);
1745
1746 MODULE_LICENSE("GPL v2");
1747 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1748 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1749 MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");