drivers/dma/dw/core.c

   1 /*
   2  * Core driver for the Synopsys DesignWare DMA Controller
   3  *
   4  * Copyright (C) 2007-2008 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  * Copyright (C) 2013 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/bitops.h>
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/mm.h>
  24 #include <linux/module.h>
  25 #include <linux/slab.h>
  26
  27 #include "../dmaengine.h"
  28 #include "internal.h"
  29
  30 /*
  31  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
  32  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
  33  * of which use ARM any more).  See the "Databook" from Synopsys for
  34  * information beyond what licensees probably provide.
  35  *
  36  * The driver has currently been tested only with the Atmel AT32AP7000,
  37  * which does not support descriptor writeback.
  38  */
  39
  40 static inline bool is_request_line_unset(struct dw_dma_chan *dwc)
  41 {
  42         return dwc->request_line == (typeof(dwc->request_line))~0;
  43 }
  44
  45 static inline void dwc_set_masters(struct dw_dma_chan *dwc)
  46 {
  47         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
  48         struct dw_dma_slave *dws = dwc->chan.private;
  49         unsigned char mmax = dw->nr_masters - 1;
  50
  51         if (!is_request_line_unset(dwc))
  52                 return;
  53
  54         dwc->src_master = min_t(unsigned char, mmax, dwc_get_sms(dws));
  55         dwc->dst_master = min_t(unsigned char, mmax, dwc_get_dms(dws));
  56 }
  57
  58 #define DWC_DEFAULT_CTLLO(_chan) ({                             \
  59                 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
  60                 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
  61                 bool _is_slave = is_slave_direction(_dwc->direction);   \
  62                 u8 _smsize = _is_slave ? _sconfig->src_maxburst :       \
  63                         DW_DMA_MSIZE_16;                        \
  64                 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst :       \
  65                         DW_DMA_MSIZE_16;                        \
  66                                                                 \
  67                 (DWC_CTLL_DST_MSIZE(_dmsize)                    \
  68                  | DWC_CTLL_SRC_MSIZE(_smsize)                  \
  69                  | DWC_CTLL_LLP_D_EN                            \
  70                  | DWC_CTLL_LLP_S_EN                            \
  71                  | DWC_CTLL_DMS(_dwc->dst_master)               \
  72                  | DWC_CTLL_SMS(_dwc->src_master));             \
  73         })
  74
  75 /*
  76  * Number of descriptors to allocate for each channel. This should be
  77  * made configurable somehow; preferably, the clients (at least the
  78  * ones using slave transfers) should be able to give us a hint.
  79  */
  80 #define NR_DESCS_PER_CHANNEL    64
  81
  82 /*----------------------------------------------------------------------*/
  83
  84 static struct device *chan2dev(struct dma_chan *chan)
  85 {
  86         return &chan->dev->device;
  87 }
  88
  89 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
  90 {
  91         return to_dw_desc(dwc->active_list.next);
  92 }
  93
  94 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
  95 {
  96         struct dw_desc *desc, *_desc;
  97         struct dw_desc *ret = NULL;
  98         unsigned int i = 0;
  99         unsigned long flags;
 100
 101         spin_lock_irqsave(&dwc->lock, flags);
 102         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
 103                 i++;
 104                 if (async_tx_test_ack(&desc->txd)) {
 105                         list_del(&desc->desc_node);
 106                         ret = desc;
 107                         break;
 108                 }
 109                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
 110         }
 111         spin_unlock_irqrestore(&dwc->lock, flags);
 112
 113         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
 114
 115         return ret;
 116 }
 117
 118 /*
 119  * Move a descriptor, including any children, to the free list.
 120  * `desc' must not be on any lists.
 121  */
 122 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 123 {
 124         unsigned long flags;
 125
 126         if (desc) {
 127                 struct dw_desc *child;
 128
 129                 spin_lock_irqsave(&dwc->lock, flags);
 130                 list_for_each_entry(child, &desc->tx_list, desc_node)
 131                         dev_vdbg(chan2dev(&dwc->chan),
 132                                         "moving child desc %p to freelist\n",
 133                                         child);
 134                 list_splice_init(&desc->tx_list, &dwc->free_list);
 135                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
 136                 list_add(&desc->desc_node, &dwc->free_list);
 137                 spin_unlock_irqrestore(&dwc->lock, flags);
 138         }
 139 }
 140
 141 static void dwc_initialize(struct dw_dma_chan *dwc)
 142 {
 143         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 144         struct dw_dma_slave *dws = dwc->chan.private;
 145         u32 cfghi = DWC_CFGH_FIFO_MODE;
 146         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
 147
 148         if (dwc->initialized == true)
 149                 return;
 150
 151         if (dws) {
 152                 /*
 153                  * We need controller-specific data to set up slave
 154                  * transfers.
 155                  */
 156                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 157
 158                 cfghi = dws->cfg_hi;
 159                 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
 160         } else {
 161                 if (dwc->direction == DMA_MEM_TO_DEV)
 162                         cfghi = DWC_CFGH_DST_PER(dwc->request_line);
 163                 else if (dwc->direction == DMA_DEV_TO_MEM)
 164                         cfghi = DWC_CFGH_SRC_PER(dwc->request_line);
 165         }
 166
 167         channel_writel(dwc, CFG_LO, cfglo);
 168         channel_writel(dwc, CFG_HI, cfghi);
 169
 170         /* Enable interrupts */
 171         channel_set_bit(dw, MASK.XFER, dwc->mask);
 172         channel_set_bit(dw, MASK.ERROR, dwc->mask);
 173
 174         dwc->initialized = true;
 175 }
 176
 177 /*----------------------------------------------------------------------*/
 178
 179 static inline unsigned int dwc_fast_fls(unsigned long long v)
 180 {
 181         /*
 182          * We can be a lot more clever here, but this should take care
 183          * of the most common optimization.
 184          */
 185         if (!(v & 7))
 186                 return 3;
 187         else if (!(v & 3))
 188                 return 2;
 189         else if (!(v & 1))
 190                 return 1;
 191         return 0;
 192 }
 193
 194 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
 195 {
 196         dev_err(chan2dev(&dwc->chan),
 197                 "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 198                 channel_readl(dwc, SAR),
 199                 channel_readl(dwc, DAR),
 200                 channel_readl(dwc, LLP),
 201                 channel_readl(dwc, CTL_HI),
 202                 channel_readl(dwc, CTL_LO));
 203 }
 204
 205 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
 206 {
 207         channel_clear_bit(dw, CH_EN, dwc->mask);
 208         while (dma_readl(dw, CH_EN) & dwc->mask)
 209                 cpu_relax();
 210 }
 211
 212 /*----------------------------------------------------------------------*/
 213
 214 /* Perform single block transfer */
 215 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
 216                                        struct dw_desc *desc)
 217 {
 218         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 219         u32             ctllo;
 220
 221         /* Software emulation of LLP mode relies on interrupts to continue
 222          * multi block transfer. */
 223         ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
 224
 225         channel_writel(dwc, SAR, desc->lli.sar);
 226         channel_writel(dwc, DAR, desc->lli.dar);
 227         channel_writel(dwc, CTL_LO, ctllo);
 228         channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
 229         channel_set_bit(dw, CH_EN, dwc->mask);
 230
 231         /* Move pointer to next descriptor */
 232         dwc->tx_node_active = dwc->tx_node_active->next;
 233 }
 234
 235 /* Called with dwc->lock held and bh disabled */
 236 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 237 {
 238         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 239         unsigned long   was_soft_llp;
 240
 241         /* ASSERT:  channel is idle */
 242         if (dma_readl(dw, CH_EN) & dwc->mask) {
 243                 dev_err(chan2dev(&dwc->chan),
 244                         "BUG: Attempted to start non-idle channel\n");
 245                 dwc_dump_chan_regs(dwc);
 246
 247                 /* The tasklet will hopefully advance the queue... */
 248                 return;
 249         }
 250
 251         if (dwc->nollp) {
 252                 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
 253                                                 &dwc->flags);
 254                 if (was_soft_llp) {
 255                         dev_err(chan2dev(&dwc->chan),
 256                                 "BUG: Attempted to start new LLP transfer "
 257                                 "inside ongoing one\n");
 258                         return;
 259                 }
 260
 261                 dwc_initialize(dwc);
 262
 263                 dwc->residue = first->total_len;
 264                 dwc->tx_node_active = &first->tx_list;
 265
 266                 /* Submit first block */
 267                 dwc_do_single_block(dwc, first);
 268
 269                 return;
 270         }
 271
 272         dwc_initialize(dwc);
 273
 274         channel_writel(dwc, LLP, first->txd.phys);
 275         channel_writel(dwc, CTL_LO,
 276                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 277         channel_writel(dwc, CTL_HI, 0);
 278         channel_set_bit(dw, CH_EN, dwc->mask);
 279 }
 280
 281 /*----------------------------------------------------------------------*/
 282
 283 static void
 284 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 285                 bool callback_required)
 286 {
 287         dma_async_tx_callback           callback = NULL;
 288         void                            *param = NULL;
 289         struct dma_async_tx_descriptor  *txd = &desc->txd;
 290         struct dw_desc                  *child;
 291         unsigned long                   flags;
 292
 293         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 294
 295         spin_lock_irqsave(&dwc->lock, flags);
 296         dma_cookie_complete(txd);
 297         if (callback_required) {
 298                 callback = txd->callback;
 299                 param = txd->callback_param;
 300         }
 301
 302         /* async_tx_ack */
 303         list_for_each_entry(child, &desc->tx_list, desc_node)
 304                 async_tx_ack(&child->txd);
 305         async_tx_ack(&desc->txd);
 306
 307         list_splice_init(&desc->tx_list, &dwc->free_list);
 308         list_move(&desc->desc_node, &dwc->free_list);
 309
 310         dma_descriptor_unmap(txd);
 311         spin_unlock_irqrestore(&dwc->lock, flags);
 312
 313         if (callback)
 314                 callback(param);
 315 }
 316
 317 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
 318 {
 319         struct dw_desc *desc, *_desc;
 320         LIST_HEAD(list);
 321         unsigned long flags;
 322
 323         spin_lock_irqsave(&dwc->lock, flags);
 324         if (dma_readl(dw, CH_EN) & dwc->mask) {
 325                 dev_err(chan2dev(&dwc->chan),
 326                         "BUG: XFER bit set, but channel not idle!\n");
 327
 328                 /* Try to continue after resetting the channel... */
 329                 dwc_chan_disable(dw, dwc);
 330         }
 331
 332         /*
 333          * Submit queued descriptors ASAP, i.e. before we go through
 334          * the completed ones.
 335          */
 336         list_splice_init(&dwc->active_list, &list);
 337         if (!list_empty(&dwc->queue)) {
 338                 list_move(dwc->queue.next, &dwc->active_list);
 339                 dwc_dostart(dwc, dwc_first_active(dwc));
 340         }
 341
 342         spin_unlock_irqrestore(&dwc->lock, flags);
 343
 344         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 345                 dwc_descriptor_complete(dwc, desc, true);
 346 }
 347
 348 /* Returns how many bytes were already received from source */
 349 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
 350 {
 351         u32 ctlhi = channel_readl(dwc, CTL_HI);
 352         u32 ctllo = channel_readl(dwc, CTL_LO);
 353
 354         return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
 355 }
 356
 357 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 358 {
 359         dma_addr_t llp;
 360         struct dw_desc *desc, *_desc;
 361         struct dw_desc *child;
 362         u32 status_xfer;
 363         unsigned long flags;
 364
 365         spin_lock_irqsave(&dwc->lock, flags);
 366         llp = channel_readl(dwc, LLP);
 367         status_xfer = dma_readl(dw, RAW.XFER);
 368
 369         if (status_xfer & dwc->mask) {
 370                 /* Everything we've submitted is done */
 371                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 372
 373                 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 374                         struct list_head *head, *active = dwc->tx_node_active;
 375
 376                         /*
 377                          * We are inside first active descriptor.
 378                          * Otherwise something is really wrong.
 379                          */
 380                         desc = dwc_first_active(dwc);
 381
 382                         head = &desc->tx_list;
 383                         if (active != head) {
 384                                 /* Update desc to reflect last sent one */
 385                                 if (active != head->next)
 386                                         desc = to_dw_desc(active->prev);
 387
 388                                 dwc->residue -= desc->len;
 389
 390                                 child = to_dw_desc(active);
 391
 392                                 /* Submit next block */
 393                                 dwc_do_single_block(dwc, child);
 394
 395                                 spin_unlock_irqrestore(&dwc->lock, flags);
 396                                 return;
 397                         }
 398
 399                         /* We are done here */
 400                         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
 401                 }
 402
 403                 dwc->residue = 0;
 404
 405                 spin_unlock_irqrestore(&dwc->lock, flags);
 406
 407                 dwc_complete_all(dw, dwc);
 408                 return;
 409         }
 410
 411         if (list_empty(&dwc->active_list)) {
 412                 dwc->residue = 0;
 413                 spin_unlock_irqrestore(&dwc->lock, flags);
 414                 return;
 415         }
 416
 417         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 418                 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
 419                 spin_unlock_irqrestore(&dwc->lock, flags);
 420                 return;
 421         }
 422
 423         dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__,
 424                         (unsigned long long)llp);
 425
 426         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 427                 /* Initial residue value */
 428                 dwc->residue = desc->total_len;
 429
 430                 /* Check first descriptors addr */
 431                 if (desc->txd.phys == llp) {
 432                         spin_unlock_irqrestore(&dwc->lock, flags);
 433                         return;
 434                 }
 435
 436                 /* Check first descriptors llp */
 437                 if (desc->lli.llp == llp) {
 438                         /* This one is currently in progress */
 439                         dwc->residue -= dwc_get_sent(dwc);
 440                         spin_unlock_irqrestore(&dwc->lock, flags);
 441                         return;
 442                 }
 443
 444                 dwc->residue -= desc->len;
 445                 list_for_each_entry(child, &desc->tx_list, desc_node) {
 446                         if (child->lli.llp == llp) {
 447                                 /* Currently in progress */
 448                                 dwc->residue -= dwc_get_sent(dwc);
 449                                 spin_unlock_irqrestore(&dwc->lock, flags);
 450                                 return;
 451                         }
 452                         dwc->residue -= child->len;
 453                 }
 454
 455                 /*
 456                  * No descriptors so far seem to be in progress, i.e.
 457                  * this one must be done.
 458                  */
 459                 spin_unlock_irqrestore(&dwc->lock, flags);
 460                 dwc_descriptor_complete(dwc, desc, true);
 461                 spin_lock_irqsave(&dwc->lock, flags);
 462         }
 463
 464         dev_err(chan2dev(&dwc->chan),
 465                 "BUG: All descriptors done, but channel not idle!\n");
 466
 467         /* Try to continue after resetting the channel... */
 468         dwc_chan_disable(dw, dwc);
 469
 470         if (!list_empty(&dwc->queue)) {
 471                 list_move(dwc->queue.next, &dwc->active_list);
 472                 dwc_dostart(dwc, dwc_first_active(dwc));
 473         }
 474         spin_unlock_irqrestore(&dwc->lock, flags);
 475 }
 476
 477 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
 478 {
 479         dev_crit(chan2dev(&dwc->chan), "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
 480                  lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
 481 }
 482
 483 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
 484 {
 485         struct dw_desc *bad_desc;
 486         struct dw_desc *child;
 487         unsigned long flags;
 488
 489         dwc_scan_descriptors(dw, dwc);
 490
 491         spin_lock_irqsave(&dwc->lock, flags);
 492
 493         /*
 494          * The descriptor currently at the head of the active list is
 495          * borked. Since we don't have any way to report errors, we'll
 496          * just have to scream loudly and try to carry on.
 497          */
 498         bad_desc = dwc_first_active(dwc);
 499         list_del_init(&bad_desc->desc_node);
 500         list_move(dwc->queue.next, dwc->active_list.prev);
 501
 502         /* Clear the error flag and try to restart the controller */
 503         dma_writel(dw, CLEAR.ERROR, dwc->mask);
 504         if (!list_empty(&dwc->active_list))
 505                 dwc_dostart(dwc, dwc_first_active(dwc));
 506
 507         /*
 508          * WARN may seem harsh, but since this only happens
 509          * when someone submits a bad physical address in a
 510          * descriptor, we should consider ourselves lucky that the
 511          * controller flagged an error instead of scribbling over
 512          * random memory locations.
 513          */
 514         dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
 515                                        "  cookie: %d\n", bad_desc->txd.cookie);
 516         dwc_dump_lli(dwc, &bad_desc->lli);
 517         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 518                 dwc_dump_lli(dwc, &child->lli);
 519
 520         spin_unlock_irqrestore(&dwc->lock, flags);
 521
 522         /* Pretend the descriptor completed successfully */
 523         dwc_descriptor_complete(dwc, bad_desc, true);
 524 }
 525
 526 /* --------------------- Cyclic DMA API extensions -------------------- */
 527
 528 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
 529 {
 530         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 531         return channel_readl(dwc, SAR);
 532 }
 533 EXPORT_SYMBOL(dw_dma_get_src_addr);
 534
 535 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
 536 {
 537         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 538         return channel_readl(dwc, DAR);
 539 }
 540 EXPORT_SYMBOL(dw_dma_get_dst_addr);
 541
 542 /* Called with dwc->lock held and all DMAC interrupts disabled */
 543 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 544                 u32 status_err, u32 status_xfer)
 545 {
 546         unsigned long flags;
 547
 548         if (dwc->mask) {
 549                 void (*callback)(void *param);
 550                 void *callback_param;
 551
 552                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
 553                                 channel_readl(dwc, LLP));
 554
 555                 callback = dwc->cdesc->period_callback;
 556                 callback_param = dwc->cdesc->period_callback_param;
 557
 558                 if (callback)
 559                         callback(callback_param);
 560         }
 561
 562         /*
 563          * Error and transfer complete are highly unlikely, and will most
 564          * likely be due to a configuration error by the user.
 565          */
 566         if (unlikely(status_err & dwc->mask) ||
 567                         unlikely(status_xfer & dwc->mask)) {
 568                 int i;
 569
 570                 dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
 571                                 "interrupt, stopping DMA transfer\n",
 572                                 status_xfer ? "xfer" : "error");
 573
 574                 spin_lock_irqsave(&dwc->lock, flags);
 575
 576                 dwc_dump_chan_regs(dwc);
 577
 578                 dwc_chan_disable(dw, dwc);
 579
 580                 /* Make sure DMA does not restart by loading a new list */
 581                 channel_writel(dwc, LLP, 0);
 582                 channel_writel(dwc, CTL_LO, 0);
 583                 channel_writel(dwc, CTL_HI, 0);
 584
 585                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
 586                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 587
 588                 for (i = 0; i < dwc->cdesc->periods; i++)
 589                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
 590
 591                 spin_unlock_irqrestore(&dwc->lock, flags);
 592         }
 593 }
 594
 595 /* ------------------------------------------------------------------------- */
 596
 597 static void dw_dma_tasklet(unsigned long data)
 598 {
 599         struct dw_dma *dw = (struct dw_dma *)data;
 600         struct dw_dma_chan *dwc;
 601         u32 status_xfer;
 602         u32 status_err;
 603         int i;
 604
 605         status_xfer = dma_readl(dw, RAW.XFER);
 606         status_err = dma_readl(dw, RAW.ERROR);
 607
 608         dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
 609
 610         for (i = 0; i < dw->dma.chancnt; i++) {
 611                 dwc = &dw->chan[i];
 612                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
 613                         dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
 614                 else if (status_err & (1 << i))
 615                         dwc_handle_error(dw, dwc);
 616                 else if (status_xfer & (1 << i))
 617                         dwc_scan_descriptors(dw, dwc);
 618         }
 619
 620         /*
 621          * Re-enable interrupts.
 622          */
 623         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
 624         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 625 }
 626
 627 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 628 {
 629         struct dw_dma *dw = dev_id;
 630         u32 status = dma_readl(dw, STATUS_INT);
 631
 632         dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
 633
 634         /* Check if we have any interrupt from the DMAC */
 635         if (!status)
 636                 return IRQ_NONE;
 637
 638         /*
 639          * Just disable the interrupts. We'll turn them back on in the
 640          * softirq handler.
 641          */
 642         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
 643         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 644
 645         status = dma_readl(dw, STATUS_INT);
 646         if (status) {
 647                 dev_err(dw->dma.dev,
 648                         "BUG: Unexpected interrupts pending: 0x%x\n",
 649                         status);
 650
 651                 /* Try to recover */
 652                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
 653                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
 654                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
 655                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
 656         }
 657
 658         tasklet_schedule(&dw->tasklet);
 659
 660         return IRQ_HANDLED;
 661 }
 662
 663 /*----------------------------------------------------------------------*/
 664
 665 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 666 {
 667         struct dw_desc          *desc = txd_to_dw_desc(tx);
 668         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
 669         dma_cookie_t            cookie;
 670         unsigned long           flags;
 671
 672         spin_lock_irqsave(&dwc->lock, flags);
 673         cookie = dma_cookie_assign(tx);
 674
 675         /*
 676          * REVISIT: We should attempt to chain as many descriptors as
 677          * possible, perhaps even appending to those already submitted
 678          * for DMA. But this is hard to do in a race-free manner.
 679          */
 680         if (list_empty(&dwc->active_list)) {
 681                 dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__,
 682                                 desc->txd.cookie);
 683                 list_add_tail(&desc->desc_node, &dwc->active_list);
 684                 dwc_dostart(dwc, dwc_first_active(dwc));
 685         } else {
 686                 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__,
 687                                 desc->txd.cookie);
 688
 689                 list_add_tail(&desc->desc_node, &dwc->queue);
 690         }
 691
 692         spin_unlock_irqrestore(&dwc->lock, flags);
 693
 694         return cookie;
 695 }
 696
 697 static struct dma_async_tx_descriptor *
 698 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 699                 size_t len, unsigned long flags)
 700 {
 701         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 702         struct dw_dma           *dw = to_dw_dma(chan->device);
 703         struct dw_desc          *desc;
 704         struct dw_desc          *first;
 705         struct dw_desc          *prev;
 706         size_t                  xfer_count;
 707         size_t                  offset;
 708         unsigned int            src_width;
 709         unsigned int            dst_width;
 710         unsigned int            data_width;
 711         u32                     ctllo;
 712
 713         dev_vdbg(chan2dev(chan),
 714                         "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__,
 715                         (unsigned long long)dest, (unsigned long long)src,
 716                         len, flags);
 717
 718         if (unlikely(!len)) {
 719                 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
 720                 return NULL;
 721         }
 722
 723         dwc->direction = DMA_MEM_TO_MEM;
 724
 725         data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
 726                            dw->data_width[dwc->dst_master]);
 727
 728         src_width = dst_width = min_t(unsigned int, data_width,
 729                                       dwc_fast_fls(src | dest | len));
 730
 731         ctllo = DWC_DEFAULT_CTLLO(chan)
 732                         | DWC_CTLL_DST_WIDTH(dst_width)
 733                         | DWC_CTLL_SRC_WIDTH(src_width)
 734                         | DWC_CTLL_DST_INC
 735                         | DWC_CTLL_SRC_INC
 736                         | DWC_CTLL_FC_M2M;
 737         prev = first = NULL;
 738
 739         for (offset = 0; offset < len; offset += xfer_count << src_width) {
 740                 xfer_count = min_t(size_t, (len - offset) >> src_width,
 741                                            dwc->block_size);
 742
 743                 desc = dwc_desc_get(dwc);
 744                 if (!desc)
 745                         goto err_desc_get;
 746
 747                 desc->lli.sar = src + offset;
 748                 desc->lli.dar = dest + offset;
 749                 desc->lli.ctllo = ctllo;
 750                 desc->lli.ctlhi = xfer_count;
 751                 desc->len = xfer_count << src_width;
 752
 753                 if (!first) {
 754                         first = desc;
 755                 } else {
 756                         prev->lli.llp = desc->txd.phys;
 757                         list_add_tail(&desc->desc_node,
 758                                         &first->tx_list);
 759                 }
 760                 prev = desc;
 761         }
 762
 763         if (flags & DMA_PREP_INTERRUPT)
 764                 /* Trigger interrupt after last block */
 765                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 766
 767         prev->lli.llp = 0;
 768         first->txd.flags = flags;
 769         first->total_len = len;
 770
 771         return &first->txd;
 772
 773 err_desc_get:
 774         dwc_desc_put(dwc, first);
 775         return NULL;
 776 }
 777
 778 static struct dma_async_tx_descriptor *
 779 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 780                 unsigned int sg_len, enum dma_transfer_direction direction,
 781                 unsigned long flags, void *context)
 782 {
 783         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 784         struct dw_dma           *dw = to_dw_dma(chan->device);
 785         struct dma_slave_config *sconfig = &dwc->dma_sconfig;
 786         struct dw_desc          *prev;
 787         struct dw_desc          *first;
 788         u32                     ctllo;
 789         dma_addr_t              reg;
 790         unsigned int            reg_width;
 791         unsigned int            mem_width;
 792         unsigned int            data_width;
 793         unsigned int            i;
 794         struct scatterlist      *sg;
 795         size_t                  total_len = 0;
 796
 797         dev_vdbg(chan2dev(chan), "%s\n", __func__);
 798
 799         if (unlikely(!is_slave_direction(direction) || !sg_len))
 800                 return NULL;
 801
 802         dwc->direction = direction;
 803
 804         prev = first = NULL;
 805
 806         switch (direction) {
 807         case DMA_MEM_TO_DEV:
 808                 reg_width = __fls(sconfig->dst_addr_width);
 809                 reg = sconfig->dst_addr;
 810                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 811                                 | DWC_CTLL_DST_WIDTH(reg_width)
 812                                 | DWC_CTLL_DST_FIX
 813                                 | DWC_CTLL_SRC_INC);
 814
 815                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
 816                         DWC_CTLL_FC(DW_DMA_FC_D_M2P);
 817
 818                 data_width = dw->data_width[dwc->src_master];
 819
 820                 for_each_sg(sgl, sg, sg_len, i) {
 821                         struct dw_desc  *desc;
 822                         u32             len, dlen, mem;
 823
 824                         mem = sg_dma_address(sg);
 825                         len = sg_dma_len(sg);
 826
 827                         mem_width = min_t(unsigned int,
 828                                           data_width, dwc_fast_fls(mem | len));
 829
 830 slave_sg_todev_fill_desc:
 831                         desc = dwc_desc_get(dwc);
 832                         if (!desc) {
 833                                 dev_err(chan2dev(chan),
 834                                         "not enough descriptors available\n");
 835                                 goto err_desc_get;
 836                         }
 837
 838                         desc->lli.sar = mem;
 839                         desc->lli.dar = reg;
 840                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
 841                         if ((len >> mem_width) > dwc->block_size) {
 842                                 dlen = dwc->block_size << mem_width;
 843                                 mem += dlen;
 844                                 len -= dlen;
 845                         } else {
 846                                 dlen = len;
 847                                 len = 0;
 848                         }
 849
 850                         desc->lli.ctlhi = dlen >> mem_width;
 851                         desc->len = dlen;
 852
 853                         if (!first) {
 854                                 first = desc;
 855                         } else {
 856                                 prev->lli.llp = desc->txd.phys;
 857                                 list_add_tail(&desc->desc_node,
 858                                                 &first->tx_list);
 859                         }
 860                         prev = desc;
 861                         total_len += dlen;
 862
 863                         if (len)
 864                                 goto slave_sg_todev_fill_desc;
 865                 }
 866                 break;
 867         case DMA_DEV_TO_MEM:
 868                 reg_width = __fls(sconfig->src_addr_width);
 869                 reg = sconfig->src_addr;
 870                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 871                                 | DWC_CTLL_SRC_WIDTH(reg_width)
 872                                 | DWC_CTLL_DST_INC
 873                                 | DWC_CTLL_SRC_FIX);
 874
 875                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
 876                         DWC_CTLL_FC(DW_DMA_FC_D_P2M);
 877
 878                 data_width = dw->data_width[dwc->dst_master];
 879
 880                 for_each_sg(sgl, sg, sg_len, i) {
 881                         struct dw_desc  *desc;
 882                         u32             len, dlen, mem;
 883
 884                         mem = sg_dma_address(sg);
 885                         len = sg_dma_len(sg);
 886
 887                         mem_width = min_t(unsigned int,
 888                                           data_width, dwc_fast_fls(mem | len));
 889
 890 slave_sg_fromdev_fill_desc:
 891                         desc = dwc_desc_get(dwc);
 892                         if (!desc) {
 893                                 dev_err(chan2dev(chan),
 894                                                 "not enough descriptors available\n");
 895                                 goto err_desc_get;
 896                         }
 897
 898                         desc->lli.sar = reg;
 899                         desc->lli.dar = mem;
 900                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
 901                         if ((len >> reg_width) > dwc->block_size) {
 902                                 dlen = dwc->block_size << reg_width;
 903                                 mem += dlen;
 904                                 len -= dlen;
 905                         } else {
 906                                 dlen = len;
 907                                 len = 0;
 908                         }
 909                         desc->lli.ctlhi = dlen >> reg_width;
 910                         desc->len = dlen;
 911
 912                         if (!first) {
 913                                 first = desc;
 914                         } else {
 915                                 prev->lli.llp = desc->txd.phys;
 916                                 list_add_tail(&desc->desc_node,
 917                                                 &first->tx_list);
 918                         }
 919                         prev = desc;
 920                         total_len += dlen;
 921
 922                         if (len)
 923                                 goto slave_sg_fromdev_fill_desc;
 924                 }
 925                 break;
 926         default:
 927                 return NULL;
 928         }
 929
 930         if (flags & DMA_PREP_INTERRUPT)
 931                 /* Trigger interrupt after last block */
 932                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 933
 934         prev->lli.llp = 0;
 935         first->total_len = total_len;
 936
 937         return &first->txd;
 938
 939 err_desc_get:
 940         dwc_desc_put(dwc, first);
 941         return NULL;
 942 }
 943
 944 /*
 945  * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
 946  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 947  *
 948  * NOTE: burst size 2 is not supported by controller.
 949  *
 950  * This can be done by finding least significant bit set: n & (n - 1)
 951  */
 952 static inline void convert_burst(u32 *maxburst)
 953 {
 954         if (*maxburst > 1)
 955                 *maxburst = fls(*maxburst) - 2;
 956         else
 957                 *maxburst = 0;
 958 }
 959
 960 static int
 961 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
 962 {
 963         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 964
 965         /* Check if chan will be configured for slave transfers */
 966         if (!is_slave_direction(sconfig->direction))
 967                 return -EINVAL;
 968
 969         memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
 970         dwc->direction = sconfig->direction;
 971
 972         /* Take the request line from slave_id member */
 973         if (is_request_line_unset(dwc))
 974                 dwc->request_line = sconfig->slave_id;
 975
 976         convert_burst(&dwc->dma_sconfig.src_maxburst);
 977         convert_burst(&dwc->dma_sconfig.dst_maxburst);
 978
 979         return 0;
 980 }
 981
 982 static inline void dwc_chan_pause(struct dw_dma_chan *dwc)
 983 {
 984         u32 cfglo = channel_readl(dwc, CFG_LO);
 985         unsigned int count = 20;        /* timeout iterations */
 986
 987         channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
 988         while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
 989                 udelay(2);
 990
 991         dwc->paused = true;
 992 }
 993
 994 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
 995 {
 996         u32 cfglo = channel_readl(dwc, CFG_LO);
 997
 998         channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
 999
1000         dwc->paused = false;
1001 }
1002
1003 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1004                        unsigned long arg)
1005 {
1006         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1007         struct dw_dma           *dw = to_dw_dma(chan->device);
1008         struct dw_desc          *desc, *_desc;
1009         unsigned long           flags;
1010         LIST_HEAD(list);
1011
1012         if (cmd == DMA_PAUSE) {
1013                 spin_lock_irqsave(&dwc->lock, flags);
1014
1015                 dwc_chan_pause(dwc);
1016
1017                 spin_unlock_irqrestore(&dwc->lock, flags);
1018         } else if (cmd == DMA_RESUME) {
1019                 if (!dwc->paused)
1020                         return 0;
1021
1022                 spin_lock_irqsave(&dwc->lock, flags);
1023
1024                 dwc_chan_resume(dwc);
1025
1026                 spin_unlock_irqrestore(&dwc->lock, flags);
1027         } else if (cmd == DMA_TERMINATE_ALL) {
1028                 spin_lock_irqsave(&dwc->lock, flags);
1029
1030                 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1031
1032                 dwc_chan_disable(dw, dwc);
1033
1034                 dwc_chan_resume(dwc);
1035
1036                 /* active_list entries will end up before queued entries */
1037                 list_splice_init(&dwc->queue, &list);
1038                 list_splice_init(&dwc->active_list, &list);
1039
1040                 spin_unlock_irqrestore(&dwc->lock, flags);
1041
1042                 /* Flush all pending and queued descriptors */
1043                 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1044                         dwc_descriptor_complete(dwc, desc, false);
1045         } else if (cmd == DMA_SLAVE_CONFIG) {
1046                 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1047         } else {
1048                 return -ENXIO;
1049         }
1050
1051         return 0;
1052 }
1053
1054 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1055 {
1056         unsigned long flags;
1057         u32 residue;
1058
1059         spin_lock_irqsave(&dwc->lock, flags);
1060
1061         residue = dwc->residue;
1062         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1063                 residue -= dwc_get_sent(dwc);
1064
1065         spin_unlock_irqrestore(&dwc->lock, flags);
1066         return residue;
1067 }
1068
1069 static enum dma_status
1070 dwc_tx_status(struct dma_chan *chan,
1071               dma_cookie_t cookie,
1072               struct dma_tx_state *txstate)
1073 {
1074         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1075         enum dma_status         ret;
1076
1077         ret = dma_cookie_status(chan, cookie, txstate);
1078         if (ret == DMA_COMPLETE)
1079                 return ret;
1080
1081         dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1082
1083         ret = dma_cookie_status(chan, cookie, txstate);
1084         if (ret != DMA_COMPLETE)
1085                 dma_set_residue(txstate, dwc_get_residue(dwc));
1086
1087         if (dwc->paused && ret == DMA_IN_PROGRESS)
1088                 return DMA_PAUSED;
1089
1090         return ret;
1091 }
1092
1093 static void dwc_issue_pending(struct dma_chan *chan)
1094 {
1095         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1096
1097         if (!list_empty(&dwc->queue))
1098                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1099 }
1100
1101 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1102 {
1103         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1104         struct dw_dma           *dw = to_dw_dma(chan->device);
1105         struct dw_desc          *desc;
1106         int                     i;
1107         unsigned long           flags;
1108
1109         dev_vdbg(chan2dev(chan), "%s\n", __func__);
1110
1111         /* ASSERT:  channel is idle */
1112         if (dma_readl(dw, CH_EN) & dwc->mask) {
1113                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1114                 return -EIO;
1115         }
1116
1117         dma_cookie_init(chan);
1118
1119         /*
1120          * NOTE: some controllers may have additional features that we
1121          * need to initialize here, like "scatter-gather" (which
1122          * doesn't mean what you think it means), and status writeback.
1123          */
1124
1125         dwc_set_masters(dwc);
1126
1127         spin_lock_irqsave(&dwc->lock, flags);
1128         i = dwc->descs_allocated;
1129         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1130                 dma_addr_t phys;
1131
1132                 spin_unlock_irqrestore(&dwc->lock, flags);
1133
1134                 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1135                 if (!desc)
1136                         goto err_desc_alloc;
1137
1138                 memset(desc, 0, sizeof(struct dw_desc));
1139
1140                 INIT_LIST_HEAD(&desc->tx_list);
1141                 dma_async_tx_descriptor_init(&desc->txd, chan);
1142                 desc->txd.tx_submit = dwc_tx_submit;
1143                 desc->txd.flags = DMA_CTRL_ACK;
1144                 desc->txd.phys = phys;
1145
1146                 dwc_desc_put(dwc, desc);
1147
1148                 spin_lock_irqsave(&dwc->lock, flags);
1149                 i = ++dwc->descs_allocated;
1150         }
1151
1152         spin_unlock_irqrestore(&dwc->lock, flags);
1153
1154         dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1155
1156         return i;
1157
1158 err_desc_alloc:
1159         dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1160
1161         return i;
1162 }
1163
1164 static void dwc_free_chan_resources(struct dma_chan *chan)
1165 {
1166         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1167         struct dw_dma           *dw = to_dw_dma(chan->device);
1168         struct dw_desc          *desc, *_desc;
1169         unsigned long           flags;
1170         LIST_HEAD(list);
1171
1172         dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1173                         dwc->descs_allocated);
1174
1175         /* ASSERT:  channel is idle */
1176         BUG_ON(!list_empty(&dwc->active_list));
1177         BUG_ON(!list_empty(&dwc->queue));
1178         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1179
1180         spin_lock_irqsave(&dwc->lock, flags);
1181         list_splice_init(&dwc->free_list, &list);
1182         dwc->descs_allocated = 0;
1183         dwc->initialized = false;
1184         dwc->request_line = ~0;
1185
1186         /* Disable interrupts */
1187         channel_clear_bit(dw, MASK.XFER, dwc->mask);
1188         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1189
1190         spin_unlock_irqrestore(&dwc->lock, flags);
1191
1192         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1193                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1194                 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1195         }
1196
1197         dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1198 }
1199
1200 /* --------------------- Cyclic DMA API extensions -------------------- */
1201
1202 /**
1203  * dw_dma_cyclic_start - start the cyclic DMA transfer
1204  * @chan: the DMA channel to start
1205  *
1206  * Must be called with soft interrupts disabled. Returns zero on success or
1207  * -errno on failure.
1208  */
1209 int dw_dma_cyclic_start(struct dma_chan *chan)
1210 {
1211         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1212         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1213         unsigned long           flags;
1214
1215         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1216                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1217                 return -ENODEV;
1218         }
1219
1220         spin_lock_irqsave(&dwc->lock, flags);
1221
1222         /* Assert channel is idle */
1223         if (dma_readl(dw, CH_EN) & dwc->mask) {
1224                 dev_err(chan2dev(&dwc->chan),
1225                         "BUG: Attempted to start non-idle channel\n");
1226                 dwc_dump_chan_regs(dwc);
1227                 spin_unlock_irqrestore(&dwc->lock, flags);
1228                 return -EBUSY;
1229         }
1230
1231         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1232         dma_writel(dw, CLEAR.XFER, dwc->mask);
1233
1234         /* Setup DMAC channel registers */
1235         channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1236         channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1237         channel_writel(dwc, CTL_HI, 0);
1238
1239         channel_set_bit(dw, CH_EN, dwc->mask);
1240
1241         spin_unlock_irqrestore(&dwc->lock, flags);
1242
1243         return 0;
1244 }
1245 EXPORT_SYMBOL(dw_dma_cyclic_start);
1246
1247 /**
1248  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1249  * @chan: the DMA channel to stop
1250  *
1251  * Must be called with soft interrupts disabled.
1252  */
1253 void dw_dma_cyclic_stop(struct dma_chan *chan)
1254 {
1255         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1256         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1257         unsigned long           flags;
1258
1259         spin_lock_irqsave(&dwc->lock, flags);
1260
1261         dwc_chan_disable(dw, dwc);
1262
1263         spin_unlock_irqrestore(&dwc->lock, flags);
1264 }
1265 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1266
1267 /**
1268  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1269  * @chan: the DMA channel to prepare
1270  * @buf_addr: physical DMA address where the buffer starts
1271  * @buf_len: total number of bytes for the entire buffer
1272  * @period_len: number of bytes for each period
1273  * @direction: transfer direction, to or from device
1274  *
1275  * Must be called before trying to start the transfer. Returns a valid struct
1276  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1277  */
1278 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1279                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1280                 enum dma_transfer_direction direction)
1281 {
1282         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1283         struct dma_slave_config         *sconfig = &dwc->dma_sconfig;
1284         struct dw_cyclic_desc           *cdesc;
1285         struct dw_cyclic_desc           *retval = NULL;
1286         struct dw_desc                  *desc;
1287         struct dw_desc                  *last = NULL;
1288         unsigned long                   was_cyclic;
1289         unsigned int                    reg_width;
1290         unsigned int                    periods;
1291         unsigned int                    i;
1292         unsigned long                   flags;
1293
1294         spin_lock_irqsave(&dwc->lock, flags);
1295         if (dwc->nollp) {
1296                 spin_unlock_irqrestore(&dwc->lock, flags);
1297                 dev_dbg(chan2dev(&dwc->chan),
1298                                 "channel doesn't support LLP transfers\n");
1299                 return ERR_PTR(-EINVAL);
1300         }
1301
1302         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1303                 spin_unlock_irqrestore(&dwc->lock, flags);
1304                 dev_dbg(chan2dev(&dwc->chan),
1305                                 "queue and/or active list are not empty\n");
1306                 return ERR_PTR(-EBUSY);
1307         }
1308
1309         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1310         spin_unlock_irqrestore(&dwc->lock, flags);
1311         if (was_cyclic) {
1312                 dev_dbg(chan2dev(&dwc->chan),
1313                                 "channel already prepared for cyclic DMA\n");
1314                 return ERR_PTR(-EBUSY);
1315         }
1316
1317         retval = ERR_PTR(-EINVAL);
1318
1319         if (unlikely(!is_slave_direction(direction)))
1320                 goto out_err;
1321
1322         dwc->direction = direction;
1323
1324         if (direction == DMA_MEM_TO_DEV)
1325                 reg_width = __ffs(sconfig->dst_addr_width);
1326         else
1327                 reg_width = __ffs(sconfig->src_addr_width);
1328
1329         periods = buf_len / period_len;
1330
1331         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1332         if (period_len > (dwc->block_size << reg_width))
1333                 goto out_err;
1334         if (unlikely(period_len & ((1 << reg_width) - 1)))
1335                 goto out_err;
1336         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1337                 goto out_err;
1338
1339         retval = ERR_PTR(-ENOMEM);
1340
1341         if (periods > NR_DESCS_PER_CHANNEL)
1342                 goto out_err;
1343
1344         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1345         if (!cdesc)
1346                 goto out_err;
1347
1348         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1349         if (!cdesc->desc)
1350                 goto out_err_alloc;
1351
1352         for (i = 0; i < periods; i++) {
1353                 desc = dwc_desc_get(dwc);
1354                 if (!desc)
1355                         goto out_err_desc_get;
1356
1357                 switch (direction) {
1358                 case DMA_MEM_TO_DEV:
1359                         desc->lli.dar = sconfig->dst_addr;
1360                         desc->lli.sar = buf_addr + (period_len * i);
1361                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1362                                         | DWC_CTLL_DST_WIDTH(reg_width)
1363                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1364                                         | DWC_CTLL_DST_FIX
1365                                         | DWC_CTLL_SRC_INC
1366                                         | DWC_CTLL_INT_EN);
1367
1368                         desc->lli.ctllo |= sconfig->device_fc ?
1369                                 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1370                                 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1371
1372                         break;
1373                 case DMA_DEV_TO_MEM:
1374                         desc->lli.dar = buf_addr + (period_len * i);
1375                         desc->lli.sar = sconfig->src_addr;
1376                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1377                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1378                                         | DWC_CTLL_DST_WIDTH(reg_width)
1379                                         | DWC_CTLL_DST_INC
1380                                         | DWC_CTLL_SRC_FIX
1381                                         | DWC_CTLL_INT_EN);
1382
1383                         desc->lli.ctllo |= sconfig->device_fc ?
1384                                 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1385                                 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1386
1387                         break;
1388                 default:
1389                         break;
1390                 }
1391
1392                 desc->lli.ctlhi = (period_len >> reg_width);
1393                 cdesc->desc[i] = desc;
1394
1395                 if (last)
1396                         last->lli.llp = desc->txd.phys;
1397
1398                 last = desc;
1399         }
1400
1401         /* Let's make a cyclic list */
1402         last->lli.llp = cdesc->desc[0]->txd.phys;
1403
1404         dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu "
1405                         "period %zu periods %d\n", (unsigned long long)buf_addr,
1406                         buf_len, period_len, periods);
1407
1408         cdesc->periods = periods;
1409         dwc->cdesc = cdesc;
1410
1411         return cdesc;
1412
1413 out_err_desc_get:
1414         while (i--)
1415                 dwc_desc_put(dwc, cdesc->desc[i]);
1416 out_err_alloc:
1417         kfree(cdesc);
1418 out_err:
1419         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1420         return (struct dw_cyclic_desc *)retval;
1421 }
1422 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1423
1424 /**
1425  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1426  * @chan: the DMA channel to free
1427  */
1428 void dw_dma_cyclic_free(struct dma_chan *chan)
1429 {
1430         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1431         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1432         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1433         int                     i;
1434         unsigned long           flags;
1435
1436         dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1437
1438         if (!cdesc)
1439                 return;
1440
1441         spin_lock_irqsave(&dwc->lock, flags);
1442
1443         dwc_chan_disable(dw, dwc);
1444
1445         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1446         dma_writel(dw, CLEAR.XFER, dwc->mask);
1447
1448         spin_unlock_irqrestore(&dwc->lock, flags);
1449
1450         for (i = 0; i < cdesc->periods; i++)
1451                 dwc_desc_put(dwc, cdesc->desc[i]);
1452
1453         kfree(cdesc->desc);
1454         kfree(cdesc);
1455
1456         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1457 }
1458 EXPORT_SYMBOL(dw_dma_cyclic_free);
1459
1460 /*----------------------------------------------------------------------*/
1461
1462 static void dw_dma_off(struct dw_dma *dw)
1463 {
1464         int i;
1465
1466         dma_writel(dw, CFG, 0);
1467
1468         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1469         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1470         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1471         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1472
1473         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1474                 cpu_relax();
1475
1476         for (i = 0; i < dw->dma.chancnt; i++)
1477                 dw->chan[i].initialized = false;
1478 }
1479
1480 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1481 {
1482         struct dw_dma           *dw;
1483         size_t                  size;
1484         bool                    autocfg;
1485         unsigned int            dw_params;
1486         unsigned int            nr_channels;
1487         unsigned int            max_blk_size = 0;
1488         int                     err;
1489         int                     i;
1490
1491         dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1492         autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1493
1494         dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1495
1496         if (!pdata && autocfg) {
1497                 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
1498                 if (!pdata)
1499                         return -ENOMEM;
1500
1501                 /* Fill platform data with the default values */
1502                 pdata->is_private = true;
1503                 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1504                 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1505         } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1506                 return -EINVAL;
1507
1508         if (autocfg)
1509                 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1510         else
1511                 nr_channels = pdata->nr_channels;
1512
1513         size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan);
1514         dw = devm_kzalloc(chip->dev, size, GFP_KERNEL);
1515         if (!dw)
1516                 return -ENOMEM;
1517
1518         dw->clk = devm_clk_get(chip->dev, "hclk");
1519         if (IS_ERR(dw->clk))
1520                 return PTR_ERR(dw->clk);
1521         clk_prepare_enable(dw->clk);
1522
1523         dw->regs = chip->regs;
1524         chip->dw = dw;
1525
1526         /* Get hardware configuration parameters */
1527         if (autocfg) {
1528                 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1529
1530                 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1531                 for (i = 0; i < dw->nr_masters; i++) {
1532                         dw->data_width[i] =
1533                                 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1534                 }
1535         } else {
1536                 dw->nr_masters = pdata->nr_masters;
1537                 memcpy(dw->data_width, pdata->data_width, 4);
1538         }
1539
1540         /* Calculate all channel mask before DMA setup */
1541         dw->all_chan_mask = (1 << nr_channels) - 1;
1542
1543         /* Force dma off, just in case */
1544         dw_dma_off(dw);
1545
1546         /* Disable BLOCK interrupts as well */
1547         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1548
1549         err = devm_request_irq(chip->dev, chip->irq, dw_dma_interrupt,
1550                                IRQF_SHARED, "dw_dmac", dw);
1551         if (err)
1552                 return err;
1553
1554         /* Create a pool of consistent memory blocks for hardware descriptors */
1555         dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1556                                          sizeof(struct dw_desc), 4, 0);
1557         if (!dw->desc_pool) {
1558                 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1559                 return -ENOMEM;
1560         }
1561
1562         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1563
1564         INIT_LIST_HEAD(&dw->dma.channels);
1565         for (i = 0; i < nr_channels; i++) {
1566                 struct dw_dma_chan      *dwc = &dw->chan[i];
1567                 int                     r = nr_channels - i - 1;
1568
1569                 dwc->chan.device = &dw->dma;
1570                 dma_cookie_init(&dwc->chan);
1571                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1572                         list_add_tail(&dwc->chan.device_node,
1573                                         &dw->dma.channels);
1574                 else
1575                         list_add(&dwc->chan.device_node, &dw->dma.channels);
1576
1577                 /* 7 is highest priority & 0 is lowest. */
1578                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1579                         dwc->priority = r;
1580                 else
1581                         dwc->priority = i;
1582
1583                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1584                 spin_lock_init(&dwc->lock);
1585                 dwc->mask = 1 << i;
1586
1587                 INIT_LIST_HEAD(&dwc->active_list);
1588                 INIT_LIST_HEAD(&dwc->queue);
1589                 INIT_LIST_HEAD(&dwc->free_list);
1590
1591                 channel_clear_bit(dw, CH_EN, dwc->mask);
1592
1593                 dwc->direction = DMA_TRANS_NONE;
1594                 dwc->request_line = ~0;
1595
1596                 /* Hardware configuration */
1597                 if (autocfg) {
1598                         unsigned int dwc_params;
1599                         void __iomem *addr = chip->regs + r * sizeof(u32);
1600
1601                         dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
1602
1603                         dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1604                                            dwc_params);
1605
1606                         /* Decode maximum block size for given channel. The
1607                          * stored 4 bit value represents blocks from 0x00 for 3
1608                          * up to 0x0a for 4095. */
1609                         dwc->block_size =
1610                                 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1611                         dwc->nollp =
1612                                 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1613                 } else {
1614                         dwc->block_size = pdata->block_size;
1615
1616                         /* Check if channel supports multi block transfer */
1617                         channel_writel(dwc, LLP, 0xfffffffc);
1618                         dwc->nollp =
1619                                 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1620                         channel_writel(dwc, LLP, 0);
1621                 }
1622         }
1623
1624         /* Clear all interrupts on all channels. */
1625         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1626         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1627         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1628         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1629         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1630
1631         dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1632         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1633         if (pdata->is_private)
1634                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1635         dw->dma.dev = chip->dev;
1636         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1637         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1638
1639         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1640
1641         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1642         dw->dma.device_control = dwc_control;
1643
1644         dw->dma.device_tx_status = dwc_tx_status;
1645         dw->dma.device_issue_pending = dwc_issue_pending;
1646
1647         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1648
1649         dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1650                  nr_channels);
1651
1652         dma_async_device_register(&dw->dma);
1653
1654         return 0;
1655 }
1656 EXPORT_SYMBOL_GPL(dw_dma_probe);
1657
1658 int dw_dma_remove(struct dw_dma_chip *chip)
1659 {
1660         struct dw_dma           *dw = chip->dw;
1661         struct dw_dma_chan      *dwc, *_dwc;
1662
1663         dw_dma_off(dw);
1664         dma_async_device_unregister(&dw->dma);
1665
1666         tasklet_kill(&dw->tasklet);
1667
1668         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1669                         chan.device_node) {
1670                 list_del(&dwc->chan.device_node);
1671                 channel_clear_bit(dw, CH_EN, dwc->mask);
1672         }
1673
1674         return 0;
1675 }
1676 EXPORT_SYMBOL_GPL(dw_dma_remove);
1677
1678 void dw_dma_shutdown(struct dw_dma_chip *chip)
1679 {
1680         struct dw_dma *dw = chip->dw;
1681
1682         dw_dma_off(dw);
1683         clk_disable_unprepare(dw->clk);
1684 }
1685 EXPORT_SYMBOL_GPL(dw_dma_shutdown);
1686
1687 #ifdef CONFIG_PM_SLEEP
1688
1689 int dw_dma_suspend(struct dw_dma_chip *chip)
1690 {
1691         struct dw_dma *dw = chip->dw;
1692
1693         dw_dma_off(dw);
1694         clk_disable_unprepare(dw->clk);
1695
1696         return 0;
1697 }
1698 EXPORT_SYMBOL_GPL(dw_dma_suspend);
1699
1700 int dw_dma_resume(struct dw_dma_chip *chip)
1701 {
1702         struct dw_dma *dw = chip->dw;
1703
1704         clk_prepare_enable(dw->clk);
1705         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1706
1707         return 0;
1708 }
1709 EXPORT_SYMBOL_GPL(dw_dma_resume);
1710
1711 #endif /* CONFIG_PM_SLEEP */
1712
1713 MODULE_LICENSE("GPL v2");
1714 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1715 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1716 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");