drivers/dma/dma-jz4780.c

   1 /*
   2  * Ingenic JZ4780 DMA controller
   3  *
   4  * Copyright (c) 2015 Imagination Technologies
   5  * Author: Alex Smith <alex@alex-smith.me.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/dmapool.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/of_dma.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22
  23 #include "dmaengine.h"
  24 #include "virt-dma.h"
  25
  26 #define JZ_DMA_NR_CHANNELS      32
  27
  28 /* Global registers. */
  29 #define JZ_DMA_REG_DMAC         0x1000
  30 #define JZ_DMA_REG_DIRQP        0x1004
  31 #define JZ_DMA_REG_DDR          0x1008
  32 #define JZ_DMA_REG_DDRS         0x100c
  33 #define JZ_DMA_REG_DMACP        0x101c
  34 #define JZ_DMA_REG_DSIRQP       0x1020
  35 #define JZ_DMA_REG_DSIRQM       0x1024
  36 #define JZ_DMA_REG_DCIRQP       0x1028
  37 #define JZ_DMA_REG_DCIRQM       0x102c
  38
  39 /* Per-channel registers. */
  40 #define JZ_DMA_REG_CHAN(n)      (n * 0x20)
  41 #define JZ_DMA_REG_DSA(n)       (0x00 + JZ_DMA_REG_CHAN(n))
  42 #define JZ_DMA_REG_DTA(n)       (0x04 + JZ_DMA_REG_CHAN(n))
  43 #define JZ_DMA_REG_DTC(n)       (0x08 + JZ_DMA_REG_CHAN(n))
  44 #define JZ_DMA_REG_DRT(n)       (0x0c + JZ_DMA_REG_CHAN(n))
  45 #define JZ_DMA_REG_DCS(n)       (0x10 + JZ_DMA_REG_CHAN(n))
  46 #define JZ_DMA_REG_DCM(n)       (0x14 + JZ_DMA_REG_CHAN(n))
  47 #define JZ_DMA_REG_DDA(n)       (0x18 + JZ_DMA_REG_CHAN(n))
  48 #define JZ_DMA_REG_DSD(n)       (0x1c + JZ_DMA_REG_CHAN(n))
  49
  50 #define JZ_DMA_DMAC_DMAE        BIT(0)
  51 #define JZ_DMA_DMAC_AR          BIT(2)
  52 #define JZ_DMA_DMAC_HLT         BIT(3)
  53 #define JZ_DMA_DMAC_FMSC        BIT(31)
  54
  55 #define JZ_DMA_DRT_AUTO         0x8
  56
  57 #define JZ_DMA_DCS_CTE          BIT(0)
  58 #define JZ_DMA_DCS_HLT          BIT(2)
  59 #define JZ_DMA_DCS_TT           BIT(3)
  60 #define JZ_DMA_DCS_AR           BIT(4)
  61 #define JZ_DMA_DCS_DES8         BIT(30)
  62
  63 #define JZ_DMA_DCM_LINK         BIT(0)
  64 #define JZ_DMA_DCM_TIE          BIT(1)
  65 #define JZ_DMA_DCM_STDE         BIT(2)
  66 #define JZ_DMA_DCM_TSZ_SHIFT    8
  67 #define JZ_DMA_DCM_TSZ_MASK     (0x7 << JZ_DMA_DCM_TSZ_SHIFT)
  68 #define JZ_DMA_DCM_DP_SHIFT     12
  69 #define JZ_DMA_DCM_SP_SHIFT     14
  70 #define JZ_DMA_DCM_DAI          BIT(22)
  71 #define JZ_DMA_DCM_SAI          BIT(23)
  72
  73 #define JZ_DMA_SIZE_4_BYTE      0x0
  74 #define JZ_DMA_SIZE_1_BYTE      0x1
  75 #define JZ_DMA_SIZE_2_BYTE      0x2
  76 #define JZ_DMA_SIZE_16_BYTE     0x3
  77 #define JZ_DMA_SIZE_32_BYTE     0x4
  78 #define JZ_DMA_SIZE_64_BYTE     0x5
  79 #define JZ_DMA_SIZE_128_BYTE    0x6
  80
  81 #define JZ_DMA_WIDTH_32_BIT     0x0
  82 #define JZ_DMA_WIDTH_8_BIT      0x1
  83 #define JZ_DMA_WIDTH_16_BIT     0x2
  84
  85 #define JZ_DMA_BUSWIDTHS        (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE)  | \
  86                                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
  87                                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
  88
  89 /**
  90  * struct jz4780_dma_hwdesc - descriptor structure read by the DMA controller.
  91  * @dcm: value for the DCM (channel command) register
  92  * @dsa: source address
  93  * @dta: target address
  94  * @dtc: transfer count (number of blocks of the transfer size specified in DCM
  95  * to transfer) in the low 24 bits, offset of the next descriptor from the
  96  * descriptor base address in the upper 8 bits.
  97  * @sd: target/source stride difference (in stride transfer mode).
  98  * @drt: request type
  99  */
 100 struct jz4780_dma_hwdesc {
 101         uint32_t dcm;
 102         uint32_t dsa;
 103         uint32_t dta;
 104         uint32_t dtc;
 105         uint32_t sd;
 106         uint32_t drt;
 107         uint32_t reserved[2];
 108 };
 109
 110 /* Size of allocations for hardware descriptor blocks. */
 111 #define JZ_DMA_DESC_BLOCK_SIZE  PAGE_SIZE
 112 #define JZ_DMA_MAX_DESC         \
 113         (JZ_DMA_DESC_BLOCK_SIZE / sizeof(struct jz4780_dma_hwdesc))
 114
 115 struct jz4780_dma_desc {
 116         struct virt_dma_desc vdesc;
 117
 118         struct jz4780_dma_hwdesc *desc;
 119         dma_addr_t desc_phys;
 120         unsigned int count;
 121         enum dma_transaction_type type;
 122         uint32_t status;
 123 };
 124
 125 struct jz4780_dma_chan {
 126         struct virt_dma_chan vchan;
 127         unsigned int id;
 128         struct dma_pool *desc_pool;
 129
 130         uint32_t transfer_type;
 131         uint32_t transfer_shift;
 132         struct dma_slave_config config;
 133
 134         struct jz4780_dma_desc *desc;
 135         unsigned int curr_hwdesc;
 136 };
 137
 138 struct jz4780_dma_dev {
 139         struct dma_device dma_device;
 140         void __iomem *base;
 141         struct clk *clk;
 142         unsigned int irq;
 143
 144         uint32_t chan_reserved;
 145         struct jz4780_dma_chan chan[JZ_DMA_NR_CHANNELS];
 146 };
 147
 148 struct jz4780_dma_data {
 149         uint32_t transfer_type;
 150         int channel;
 151 };
 152
 153 static inline struct jz4780_dma_chan *to_jz4780_dma_chan(struct dma_chan *chan)
 154 {
 155         return container_of(chan, struct jz4780_dma_chan, vchan.chan);
 156 }
 157
 158 static inline struct jz4780_dma_desc *to_jz4780_dma_desc(
 159         struct virt_dma_desc *vdesc)
 160 {
 161         return container_of(vdesc, struct jz4780_dma_desc, vdesc);
 162 }
 163
 164 static inline struct jz4780_dma_dev *jz4780_dma_chan_parent(
 165         struct jz4780_dma_chan *jzchan)
 166 {
 167         return container_of(jzchan->vchan.chan.device, struct jz4780_dma_dev,
 168                             dma_device);
 169 }
 170
 171 static inline uint32_t jz4780_dma_readl(struct jz4780_dma_dev *jzdma,
 172         unsigned int reg)
 173 {
 174         return readl(jzdma->base + reg);
 175 }
 176
 177 static inline void jz4780_dma_writel(struct jz4780_dma_dev *jzdma,
 178         unsigned int reg, uint32_t val)
 179 {
 180         writel(val, jzdma->base + reg);
 181 }
 182
 183 static struct jz4780_dma_desc *jz4780_dma_desc_alloc(
 184         struct jz4780_dma_chan *jzchan, unsigned int count,
 185         enum dma_transaction_type type)
 186 {
 187         struct jz4780_dma_desc *desc;
 188
 189         if (count > JZ_DMA_MAX_DESC)
 190                 return NULL;
 191
 192         desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
 193         if (!desc)
 194                 return NULL;
 195
 196         desc->desc = dma_pool_alloc(jzchan->desc_pool, GFP_NOWAIT,
 197                                     &desc->desc_phys);
 198         if (!desc->desc) {
 199                 kfree(desc);
 200                 return NULL;
 201         }
 202
 203         desc->count = count;
 204         desc->type = type;
 205         return desc;
 206 }
 207
 208 static void jz4780_dma_desc_free(struct virt_dma_desc *vdesc)
 209 {
 210         struct jz4780_dma_desc *desc = to_jz4780_dma_desc(vdesc);
 211         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(vdesc->tx.chan);
 212
 213         dma_pool_free(jzchan->desc_pool, desc->desc, desc->desc_phys);
 214         kfree(desc);
 215 }
 216
 217 static uint32_t jz4780_dma_transfer_size(unsigned long val, int *ord)
 218 {
 219         *ord = ffs(val) - 1;
 220
 221         switch (*ord) {
 222         case 0:
 223                 return JZ_DMA_SIZE_1_BYTE;
 224         case 1:
 225                 return JZ_DMA_SIZE_2_BYTE;
 226         case 2:
 227                 return JZ_DMA_SIZE_4_BYTE;
 228         case 4:
 229                 return JZ_DMA_SIZE_16_BYTE;
 230         case 5:
 231                 return JZ_DMA_SIZE_32_BYTE;
 232         case 6:
 233                 return JZ_DMA_SIZE_64_BYTE;
 234         case 7:
 235                 return JZ_DMA_SIZE_128_BYTE;
 236         default:
 237                 return -EINVAL;
 238         }
 239 }
 240
 241 static uint32_t jz4780_dma_setup_hwdesc(struct jz4780_dma_chan *jzchan,
 242         struct jz4780_dma_hwdesc *desc, dma_addr_t addr, size_t len,
 243         enum dma_transfer_direction direction)
 244 {
 245         struct dma_slave_config *config = &jzchan->config;
 246         uint32_t width, maxburst, tsz;
 247         int ord;
 248
 249         if (direction == DMA_MEM_TO_DEV) {
 250                 desc->dcm = JZ_DMA_DCM_SAI;
 251                 desc->dsa = addr;
 252                 desc->dta = config->dst_addr;
 253                 desc->drt = jzchan->transfer_type;
 254
 255                 width = config->dst_addr_width;
 256                 maxburst = config->dst_maxburst;
 257         } else {
 258                 desc->dcm = JZ_DMA_DCM_DAI;
 259                 desc->dsa = config->src_addr;
 260                 desc->dta = addr;
 261                 desc->drt = jzchan->transfer_type;
 262
 263                 width = config->src_addr_width;
 264                 maxburst = config->src_maxburst;
 265         }
 266
 267         /*
 268          * This calculates the maximum transfer size that can be used with the
 269          * given address, length, width and maximum burst size. The address
 270          * must be aligned to the transfer size, the total length must be
 271          * divisible by the transfer size, and we must not use more than the
 272          * maximum burst specified by the user.
 273          */
 274         tsz = jz4780_dma_transfer_size(addr | len | (width * maxburst), &ord);
 275         jzchan->transfer_shift = ord;
 276
 277         switch (width) {
 278         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 279         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 280                 break;
 281         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 282                 width = JZ_DMA_WIDTH_32_BIT;
 283                 break;
 284         default:
 285                 return -EINVAL;
 286         }
 287
 288         desc->dcm |= tsz << JZ_DMA_DCM_TSZ_SHIFT;
 289         desc->dcm |= width << JZ_DMA_DCM_SP_SHIFT;
 290         desc->dcm |= width << JZ_DMA_DCM_DP_SHIFT;
 291
 292         desc->dtc = len >> ord;
 293 }
 294
 295 static struct dma_async_tx_descriptor *jz4780_dma_prep_slave_sg(
 296         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
 297         enum dma_transfer_direction direction, unsigned long flags,
 298         void *context)
 299 {
 300         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 301         struct jz4780_dma_desc *desc;
 302         unsigned int i;
 303         int err;
 304
 305         desc = jz4780_dma_desc_alloc(jzchan, sg_len, DMA_SLAVE);
 306         if (!desc)
 307                 return NULL;
 308
 309         for (i = 0; i < sg_len; i++) {
 310                 err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i],
 311                                         sg_dma_address(&sgl[i]),
 312                                         sg_dma_len(&sgl[i]),
 313                                         direction);
 314                 if (err < 0)
 315                         return ERR_PTR(err);
 316
 317
 318                 desc->desc[i].dcm |= JZ_DMA_DCM_TIE;
 319
 320                 if (i != (sg_len - 1)) {
 321                         /* Automatically proceeed to the next descriptor. */
 322                         desc->desc[i].dcm |= JZ_DMA_DCM_LINK;
 323
 324                         /*
 325                          * The upper 8 bits of the DTC field in the descriptor
 326                          * must be set to (offset from descriptor base of next
 327                          * descriptor >> 4).
 328                          */
 329                         desc->desc[i].dtc |=
 330                                 (((i + 1) * sizeof(*desc->desc)) >> 4) << 24;
 331                 }
 332         }
 333
 334         return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags);
 335 }
 336
 337 static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_cyclic(
 338         struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 339         size_t period_len, enum dma_transfer_direction direction,
 340         unsigned long flags)
 341 {
 342         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 343         struct jz4780_dma_desc *desc;
 344         unsigned int periods, i;
 345         int err;
 346
 347         if (buf_len % period_len)
 348                 return NULL;
 349
 350         periods = buf_len / period_len;
 351
 352         desc = jz4780_dma_desc_alloc(jzchan, periods, DMA_CYCLIC);
 353         if (!desc)
 354                 return NULL;
 355
 356         for (i = 0; i < periods; i++) {
 357                 err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i], buf_addr,
 358                                         period_len, direction);
 359                 if (err < 0)
 360                         return ERR_PTR(err);
 361
 362                 buf_addr += period_len;
 363
 364                 /*
 365                  * Set the link bit to indicate that the controller should
 366                  * automatically proceed to the next descriptor. In
 367                  * jz4780_dma_begin(), this will be cleared if we need to issue
 368                  * an interrupt after each period.
 369                  */
 370                 desc->desc[i].dcm |= JZ_DMA_DCM_TIE | JZ_DMA_DCM_LINK;
 371
 372                 /*
 373                  * The upper 8 bits of the DTC field in the descriptor must be
 374                  * set to (offset from descriptor base of next descriptor >> 4).
 375                  * If this is the last descriptor, link it back to the first,
 376                  * i.e. leave offset set to 0, otherwise point to the next one.
 377                  */
 378                 if (i != (periods - 1)) {
 379                         desc->desc[i].dtc |=
 380                                 (((i + 1) * sizeof(*desc->desc)) >> 4) << 24;
 381                 }
 382         }
 383
 384         return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags);
 385 }
 386
 387 struct dma_async_tx_descriptor *jz4780_dma_prep_dma_memcpy(
 388         struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 389         size_t len, unsigned long flags)
 390 {
 391         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 392         struct jz4780_dma_desc *desc;
 393         uint32_t tsz;
 394         int ord;
 395
 396         desc = jz4780_dma_desc_alloc(jzchan, 1, DMA_MEMCPY);
 397         if (!desc)
 398                 return NULL;
 399
 400         tsz = jz4780_dma_transfer_size(dest | src | len, &ord);
 401         if (tsz < 0)
 402                 return ERR_PTR(tsz);
 403
 404         desc->desc[0].dsa = src;
 405         desc->desc[0].dta = dest;
 406         desc->desc[0].drt = JZ_DMA_DRT_AUTO;
 407         desc->desc[0].dcm = JZ_DMA_DCM_TIE | JZ_DMA_DCM_SAI | JZ_DMA_DCM_DAI |
 408                             tsz << JZ_DMA_DCM_TSZ_SHIFT |
 409                             JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_SP_SHIFT |
 410                             JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_DP_SHIFT;
 411         desc->desc[0].dtc = len >> ord;
 412
 413         return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags);
 414 }
 415
 416 static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan)
 417 {
 418         struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
 419         struct virt_dma_desc *vdesc;
 420         unsigned int i;
 421         dma_addr_t desc_phys;
 422
 423         if (!jzchan->desc) {
 424                 vdesc = vchan_next_desc(&jzchan->vchan);
 425                 if (!vdesc)
 426                         return;
 427
 428                 list_del(&vdesc->node);
 429
 430                 jzchan->desc = to_jz4780_dma_desc(vdesc);
 431                 jzchan->curr_hwdesc = 0;
 432
 433                 if (jzchan->desc->type == DMA_CYCLIC && vdesc->tx.callback) {
 434                         /*
 435                          * The DMA controller doesn't support triggering an
 436                          * interrupt after processing each descriptor, only
 437                          * after processing an entire terminated list of
 438                          * descriptors. For a cyclic DMA setup the list of
 439                          * descriptors is not terminated so we can never get an
 440                          * interrupt.
 441                          *
 442                          * If the user requested a callback for a cyclic DMA
 443                          * setup then we workaround this hardware limitation
 444                          * here by degrading to a set of unlinked descriptors
 445                          * which we will submit in sequence in response to the
 446                          * completion of processing the previous descriptor.
 447                          */
 448                         for (i = 0; i < jzchan->desc->count; i++)
 449                                 jzchan->desc->desc[i].dcm &= ~JZ_DMA_DCM_LINK;
 450                 }
 451         } else {
 452                 /*
 453                  * There is an existing transfer, therefore this must be one
 454                  * for which we unlinked the descriptors above. Advance to the
 455                  * next one in the list.
 456                  */
 457                 jzchan->curr_hwdesc =
 458                         (jzchan->curr_hwdesc + 1) % jzchan->desc->count;
 459         }
 460
 461         /* Use 8-word descriptors. */
 462         jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), JZ_DMA_DCS_DES8);
 463
 464         /* Write descriptor address and initiate descriptor fetch. */
 465         desc_phys = jzchan->desc->desc_phys +
 466                     (jzchan->curr_hwdesc * sizeof(*jzchan->desc->desc));
 467         jz4780_dma_writel(jzdma, JZ_DMA_REG_DDA(jzchan->id), desc_phys);
 468         jz4780_dma_writel(jzdma, JZ_DMA_REG_DDRS, BIT(jzchan->id));
 469
 470         /* Enable the channel. */
 471         jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id),
 472                           JZ_DMA_DCS_DES8 | JZ_DMA_DCS_CTE);
 473 }
 474
 475 static void jz4780_dma_issue_pending(struct dma_chan *chan)
 476 {
 477         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 478         unsigned long flags;
 479
 480         spin_lock_irqsave(&jzchan->vchan.lock, flags);
 481
 482         if (vchan_issue_pending(&jzchan->vchan) && !jzchan->desc)
 483                 jz4780_dma_begin(jzchan);
 484
 485         spin_unlock_irqrestore(&jzchan->vchan.lock, flags);
 486 }
 487
 488 static int jz4780_dma_terminate_all(struct dma_chan *chan)
 489 {
 490         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 491         struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
 492         unsigned long flags;
 493         LIST_HEAD(head);
 494
 495         spin_lock_irqsave(&jzchan->vchan.lock, flags);
 496
 497         /* Clear the DMA status and stop the transfer. */
 498         jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), 0);
 499         if (jzchan->desc) {
 500                 jz4780_dma_desc_free(&jzchan->desc->vdesc);
 501                 jzchan->desc = NULL;
 502         }
 503
 504         vchan_get_all_descriptors(&jzchan->vchan, &head);
 505
 506         spin_unlock_irqrestore(&jzchan->vchan.lock, flags);
 507
 508         vchan_dma_desc_free_list(&jzchan->vchan, &head);
 509         return 0;
 510 }
 511
 512 static int jz4780_dma_config(struct dma_chan *chan,
 513         struct dma_slave_config *config)
 514 {
 515         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 516
 517         if ((config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
 518            || (config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES))
 519                 return -EINVAL;
 520
 521         /* Copy the reset of the slave configuration, it is used later. */
 522         memcpy(&jzchan->config, config, sizeof(jzchan->config));
 523
 524         return 0;
 525 }
 526
 527 static size_t jz4780_dma_desc_residue(struct jz4780_dma_chan *jzchan,
 528         struct jz4780_dma_desc *desc, unsigned int next_sg)
 529 {
 530         struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
 531         unsigned int residue, count;
 532         unsigned int i;
 533
 534         residue = 0;
 535
 536         for (i = next_sg; i < desc->count; i++)
 537                 residue += desc->desc[i].dtc << jzchan->transfer_shift;
 538
 539         if (next_sg != 0) {
 540                 count = jz4780_dma_readl(jzdma,
 541                                          JZ_DMA_REG_DTC(jzchan->id));
 542                 residue += count << jzchan->transfer_shift;
 543         }
 544
 545         return residue;
 546 }
 547
 548 static enum dma_status jz4780_dma_tx_status(struct dma_chan *chan,
 549         dma_cookie_t cookie, struct dma_tx_state *txstate)
 550 {
 551         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 552         struct virt_dma_desc *vdesc;
 553         enum dma_status status;
 554         unsigned long flags;
 555
 556         status = dma_cookie_status(chan, cookie, txstate);
 557         if ((status == DMA_COMPLETE) || (txstate == NULL))
 558                 return status;
 559
 560         spin_lock_irqsave(&jzchan->vchan.lock, flags);
 561
 562         vdesc = vchan_find_desc(&jzchan->vchan, cookie);
 563         if (vdesc) {
 564                 /* On the issued list, so hasn't been processed yet */
 565                 txstate->residue = jz4780_dma_desc_residue(jzchan,
 566                                         to_jz4780_dma_desc(vdesc), 0);
 567         } else if (cookie == jzchan->desc->vdesc.tx.cookie) {
 568                 txstate->residue = jz4780_dma_desc_residue(jzchan, jzchan->desc,
 569                           (jzchan->curr_hwdesc + 1) % jzchan->desc->count);
 570         } else
 571                 txstate->residue = 0;
 572
 573         if (vdesc && jzchan->desc && vdesc == &jzchan->desc->vdesc
 574                 && jzchan->desc->status & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT))
 575                         status = DMA_ERROR;
 576
 577         spin_unlock_irqrestore(&jzchan->vchan.lock, flags);
 578         return status;
 579 }
 580
 581 static void jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma,
 582         struct jz4780_dma_chan *jzchan)
 583 {
 584         uint32_t dcs;
 585
 586         spin_lock(&jzchan->vchan.lock);
 587
 588         dcs = jz4780_dma_readl(jzdma, JZ_DMA_REG_DCS(jzchan->id));
 589         jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), 0);
 590
 591         if (dcs & JZ_DMA_DCS_AR) {
 592                 dev_warn(&jzchan->vchan.chan.dev->device,
 593                          "address error (DCS=0x%x)\n", dcs);
 594         }
 595
 596         if (dcs & JZ_DMA_DCS_HLT) {
 597                 dev_warn(&jzchan->vchan.chan.dev->device,
 598                          "channel halt (DCS=0x%x)\n", dcs);
 599         }
 600
 601         if (jzchan->desc) {
 602                 jzchan->desc->status = dcs;
 603
 604                 if ((dcs & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT)) == 0) {
 605                         if (jzchan->desc->type == DMA_CYCLIC) {
 606                                 vchan_cyclic_callback(&jzchan->desc->vdesc);
 607                         } else {
 608                                 vchan_cookie_complete(&jzchan->desc->vdesc);
 609                                 jzchan->desc = NULL;
 610                         }
 611
 612                         jz4780_dma_begin(jzchan);
 613                 }
 614         } else {
 615                 dev_err(&jzchan->vchan.chan.dev->device,
 616                         "channel IRQ with no active transfer\n");
 617         }
 618
 619         spin_unlock(&jzchan->vchan.lock);
 620 }
 621
 622 static irqreturn_t jz4780_dma_irq_handler(int irq, void *data)
 623 {
 624         struct jz4780_dma_dev *jzdma = data;
 625         uint32_t pending, dmac;
 626         int i;
 627
 628         pending = jz4780_dma_readl(jzdma, JZ_DMA_REG_DIRQP);
 629
 630         for (i = 0; i < JZ_DMA_NR_CHANNELS; i++) {
 631                 if (!(pending & (1<<i)))
 632                         continue;
 633
 634                 jz4780_dma_chan_irq(jzdma, &jzdma->chan[i]);
 635         }
 636
 637         /* Clear halt and address error status of all channels. */
 638         dmac = jz4780_dma_readl(jzdma, JZ_DMA_REG_DMAC);
 639         dmac &= ~(JZ_DMA_DMAC_HLT | JZ_DMA_DMAC_AR);
 640         jz4780_dma_writel(jzdma, JZ_DMA_REG_DMAC, dmac);
 641
 642         /* Clear interrupt pending status. */
 643         jz4780_dma_writel(jzdma, JZ_DMA_REG_DIRQP, 0);
 644
 645         return IRQ_HANDLED;
 646 }
 647
 648 static int jz4780_dma_alloc_chan_resources(struct dma_chan *chan)
 649 {
 650         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 651
 652         jzchan->desc_pool = dma_pool_create(dev_name(&chan->dev->device),
 653                                             chan->device->dev,
 654                                             JZ_DMA_DESC_BLOCK_SIZE,
 655                                             PAGE_SIZE, 0);
 656         if (!jzchan->desc_pool) {
 657                 dev_err(&chan->dev->device,
 658                         "failed to allocate descriptor pool\n");
 659                 return -ENOMEM;
 660         }
 661
 662         return 0;
 663 }
 664
 665 static void jz4780_dma_free_chan_resources(struct dma_chan *chan)
 666 {
 667         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 668
 669         vchan_free_chan_resources(&jzchan->vchan);
 670         dma_pool_destroy(jzchan->desc_pool);
 671         jzchan->desc_pool = NULL;
 672 }
 673
 674 static bool jz4780_dma_filter_fn(struct dma_chan *chan, void *param)
 675 {
 676         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 677         struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
 678         struct jz4780_dma_data *data = param;
 679
 680         if (data->channel > -1) {
 681                 if (data->channel != jzchan->id)
 682                         return false;
 683         } else if (jzdma->chan_reserved & BIT(jzchan->id)) {
 684                 return false;
 685         }
 686
 687         jzchan->transfer_type = data->transfer_type;
 688
 689         return true;
 690 }
 691
 692 static struct dma_chan *jz4780_of_dma_xlate(struct of_phandle_args *dma_spec,
 693         struct of_dma *ofdma)
 694 {
 695         struct jz4780_dma_dev *jzdma = ofdma->of_dma_data;
 696         dma_cap_mask_t mask = jzdma->dma_device.cap_mask;
 697         struct jz4780_dma_data data;
 698
 699         if (dma_spec->args_count != 2)
 700                 return NULL;
 701
 702         data.transfer_type = dma_spec->args[0];
 703         data.channel = dma_spec->args[1];
 704
 705         if (data.channel > -1) {
 706                 if (data.channel >= JZ_DMA_NR_CHANNELS) {
 707                         dev_err(jzdma->dma_device.dev,
 708                                 "device requested non-existent channel %u\n",
 709                                 data.channel);
 710                         return NULL;
 711                 }
 712
 713                 /* Can only select a channel marked as reserved. */
 714                 if (!(jzdma->chan_reserved & BIT(data.channel))) {
 715                         dev_err(jzdma->dma_device.dev,
 716                                 "device requested unreserved channel %u\n",
 717                                 data.channel);
 718                         return NULL;
 719                 }
 720         }
 721
 722         return dma_request_channel(mask, jz4780_dma_filter_fn, &data);
 723 }
 724
 725 static int jz4780_dma_probe(struct platform_device *pdev)
 726 {
 727         struct device *dev = &pdev->dev;
 728         struct jz4780_dma_dev *jzdma;
 729         struct jz4780_dma_chan *jzchan;
 730         struct dma_device *dd;
 731         struct resource *res;
 732         int i, ret;
 733
 734         jzdma = devm_kzalloc(dev, sizeof(*jzdma), GFP_KERNEL);
 735         if (!jzdma)
 736                 return -ENOMEM;
 737
 738         platform_set_drvdata(pdev, jzdma);
 739
 740         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 741         if (!res) {
 742                 dev_err(dev, "failed to get I/O memory\n");
 743                 return -EINVAL;
 744         }
 745
 746         jzdma->base = devm_ioremap_resource(dev, res);
 747         if (IS_ERR(jzdma->base))
 748                 return PTR_ERR(jzdma->base);
 749
 750         jzdma->irq = platform_get_irq(pdev, 0);
 751         if (jzdma->irq < 0) {
 752                 dev_err(dev, "failed to get IRQ: %d\n", ret);
 753                 return jzdma->irq;
 754         }
 755
 756         ret = devm_request_irq(dev, jzdma->irq, jz4780_dma_irq_handler, 0,
 757                                dev_name(dev), jzdma);
 758         if (ret) {
 759                 dev_err(dev, "failed to request IRQ %u!\n", jzdma->irq);
 760                 return -EINVAL;
 761         }
 762
 763         jzdma->clk = devm_clk_get(dev, NULL);
 764         if (IS_ERR(jzdma->clk)) {
 765                 dev_err(dev, "failed to get clock\n");
 766                 return PTR_ERR(jzdma->clk);
 767         }
 768
 769         clk_prepare_enable(jzdma->clk);
 770
 771         /* Property is optional, if it doesn't exist the value will remain 0. */
 772         of_property_read_u32_index(dev->of_node, "ingenic,reserved-channels",
 773                                    0, &jzdma->chan_reserved);
 774
 775         dd = &jzdma->dma_device;
 776
 777         dma_cap_set(DMA_MEMCPY, dd->cap_mask);
 778         dma_cap_set(DMA_SLAVE, dd->cap_mask);
 779         dma_cap_set(DMA_CYCLIC, dd->cap_mask);
 780
 781         dd->dev = dev;
 782         dd->copy_align = DMAENGINE_ALIGN_4_BYTES;
 783         dd->device_alloc_chan_resources = jz4780_dma_alloc_chan_resources;
 784         dd->device_free_chan_resources = jz4780_dma_free_chan_resources;
 785         dd->device_prep_slave_sg = jz4780_dma_prep_slave_sg;
 786         dd->device_prep_dma_cyclic = jz4780_dma_prep_dma_cyclic;
 787         dd->device_prep_dma_memcpy = jz4780_dma_prep_dma_memcpy;
 788         dd->device_config = jz4780_dma_config;
 789         dd->device_terminate_all = jz4780_dma_terminate_all;
 790         dd->device_tx_status = jz4780_dma_tx_status;
 791         dd->device_issue_pending = jz4780_dma_issue_pending;
 792         dd->src_addr_widths = JZ_DMA_BUSWIDTHS;
 793         dd->dst_addr_widths = JZ_DMA_BUSWIDTHS;
 794         dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
 795         dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
 796
 797
 798         /*
 799          * Enable DMA controller, mark all channels as not programmable.
 800          * Also set the FMSC bit - it increases MSC performance, so it makes
 801          * little sense not to enable it.
 802          */
 803         jz4780_dma_writel(jzdma, JZ_DMA_REG_DMAC,
 804                           JZ_DMA_DMAC_DMAE | JZ_DMA_DMAC_FMSC);
 805         jz4780_dma_writel(jzdma, JZ_DMA_REG_DMACP, 0);
 806
 807         INIT_LIST_HEAD(&dd->channels);
 808
 809         for (i = 0; i < JZ_DMA_NR_CHANNELS; i++) {
 810                 jzchan = &jzdma->chan[i];
 811                 jzchan->id = i;
 812
 813                 vchan_init(&jzchan->vchan, dd);
 814                 jzchan->vchan.desc_free = jz4780_dma_desc_free;
 815         }
 816
 817         ret = dma_async_device_register(dd);
 818         if (ret) {
 819                 dev_err(dev, "failed to register device\n");
 820                 goto err_disable_clk;
 821         }
 822
 823         /* Register with OF DMA helpers. */
 824         ret = of_dma_controller_register(dev->of_node, jz4780_of_dma_xlate,
 825                                          jzdma);
 826         if (ret) {
 827                 dev_err(dev, "failed to register OF DMA controller\n");
 828                 goto err_unregister_dev;
 829         }
 830
 831         dev_info(dev, "JZ4780 DMA controller initialised\n");
 832         return 0;
 833
 834 err_unregister_dev:
 835         dma_async_device_unregister(dd);
 836
 837 err_disable_clk:
 838         clk_disable_unprepare(jzdma->clk);
 839         return ret;
 840 }
 841
 842 static int jz4780_dma_remove(struct platform_device *pdev)
 843 {
 844         struct jz4780_dma_dev *jzdma = platform_get_drvdata(pdev);
 845
 846         of_dma_controller_free(pdev->dev.of_node);
 847         devm_free_irq(&pdev->dev, jzdma->irq, jzdma);
 848         dma_async_device_unregister(&jzdma->dma_device);
 849         return 0;
 850 }
 851
 852 static const struct of_device_id jz4780_dma_dt_match[] = {
 853         { .compatible = "ingenic,jz4780-dma", .data = NULL },
 854         {},
 855 };
 856 MODULE_DEVICE_TABLE(of, jz4780_dma_dt_match);
 857
 858 static struct platform_driver jz4780_dma_driver = {
 859         .probe          = jz4780_dma_probe,
 860         .remove         = jz4780_dma_remove,
 861         .driver = {
 862                 .name   = "jz4780-dma",
 863                 .of_match_table = of_match_ptr(jz4780_dma_dt_match),
 864         },
 865 };
 866
 867 static int __init jz4780_dma_init(void)
 868 {
 869         return platform_driver_register(&jz4780_dma_driver);
 870 }
 871 subsys_initcall(jz4780_dma_init);
 872
 873 static void __exit jz4780_dma_exit(void)
 874 {
 875         platform_driver_unregister(&jz4780_dma_driver);
 876 }
 877 module_exit(jz4780_dma_exit);
 878
 879 MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
 880 MODULE_DESCRIPTION("Ingenic JZ4780 DMA controller driver");
 881 MODULE_LICENSE("GPL");