drivers/dma/dma-jz4780.c

   1 /*
   2  * Ingenic JZ4780 DMA controller
   3  *
   4  * Copyright (c) 2015 Imagination Technologies
   5  * Author: Alex Smith <alex@alex-smith.me.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/dmapool.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/of_dma.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22
  23 #include "dmaengine.h"
  24 #include "virt-dma.h"
  25
  26 #define JZ_DMA_NR_CHANNELS      32
  27
  28 /* Global registers. */
  29 #define JZ_DMA_REG_DMAC         0x1000
  30 #define JZ_DMA_REG_DIRQP        0x1004
  31 #define JZ_DMA_REG_DDR          0x1008
  32 #define JZ_DMA_REG_DDRS         0x100c
  33 #define JZ_DMA_REG_DMACP        0x101c
  34 #define JZ_DMA_REG_DSIRQP       0x1020
  35 #define JZ_DMA_REG_DSIRQM       0x1024
  36 #define JZ_DMA_REG_DCIRQP       0x1028
  37 #define JZ_DMA_REG_DCIRQM       0x102c
  38
  39 /* Per-channel registers. */
  40 #define JZ_DMA_REG_CHAN(n)      (n * 0x20)
  41 #define JZ_DMA_REG_DSA(n)       (0x00 + JZ_DMA_REG_CHAN(n))
  42 #define JZ_DMA_REG_DTA(n)       (0x04 + JZ_DMA_REG_CHAN(n))
  43 #define JZ_DMA_REG_DTC(n)       (0x08 + JZ_DMA_REG_CHAN(n))
  44 #define JZ_DMA_REG_DRT(n)       (0x0c + JZ_DMA_REG_CHAN(n))
  45 #define JZ_DMA_REG_DCS(n)       (0x10 + JZ_DMA_REG_CHAN(n))
  46 #define JZ_DMA_REG_DCM(n)       (0x14 + JZ_DMA_REG_CHAN(n))
  47 #define JZ_DMA_REG_DDA(n)       (0x18 + JZ_DMA_REG_CHAN(n))
  48 #define JZ_DMA_REG_DSD(n)       (0x1c + JZ_DMA_REG_CHAN(n))
  49
  50 #define JZ_DMA_DMAC_DMAE        BIT(0)
  51 #define JZ_DMA_DMAC_AR          BIT(2)
  52 #define JZ_DMA_DMAC_HLT         BIT(3)
  53 #define JZ_DMA_DMAC_FMSC        BIT(31)
  54
  55 #define JZ_DMA_DRT_AUTO         0x8
  56
  57 #define JZ_DMA_DCS_CTE          BIT(0)
  58 #define JZ_DMA_DCS_HLT          BIT(2)
  59 #define JZ_DMA_DCS_TT           BIT(3)
  60 #define JZ_DMA_DCS_AR           BIT(4)
  61 #define JZ_DMA_DCS_DES8         BIT(30)
  62
  63 #define JZ_DMA_DCM_LINK         BIT(0)
  64 #define JZ_DMA_DCM_TIE          BIT(1)
  65 #define JZ_DMA_DCM_STDE         BIT(2)
  66 #define JZ_DMA_DCM_TSZ_SHIFT    8
  67 #define JZ_DMA_DCM_TSZ_MASK     (0x7 << JZ_DMA_DCM_TSZ_SHIFT)
  68 #define JZ_DMA_DCM_DP_SHIFT     12
  69 #define JZ_DMA_DCM_SP_SHIFT     14
  70 #define JZ_DMA_DCM_DAI          BIT(22)
  71 #define JZ_DMA_DCM_SAI          BIT(23)
  72
  73 #define JZ_DMA_SIZE_4_BYTE      0x0
  74 #define JZ_DMA_SIZE_1_BYTE      0x1
  75 #define JZ_DMA_SIZE_2_BYTE      0x2
  76 #define JZ_DMA_SIZE_16_BYTE     0x3
  77 #define JZ_DMA_SIZE_32_BYTE     0x4
  78 #define JZ_DMA_SIZE_64_BYTE     0x5
  79 #define JZ_DMA_SIZE_128_BYTE    0x6
  80
  81 #define JZ_DMA_WIDTH_32_BIT     0x0
  82 #define JZ_DMA_WIDTH_8_BIT      0x1
  83 #define JZ_DMA_WIDTH_16_BIT     0x2
  84
  85 #define JZ_DMA_BUSWIDTHS        (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE)  | \
  86                                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
  87                                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
  88
  89 /**
  90  * struct jz4780_dma_hwdesc - descriptor structure read by the DMA controller.
  91  * @dcm: value for the DCM (channel command) register
  92  * @dsa: source address
  93  * @dta: target address
  94  * @dtc: transfer count (number of blocks of the transfer size specified in DCM
  95  * to transfer) in the low 24 bits, offset of the next descriptor from the
  96  * descriptor base address in the upper 8 bits.
  97  * @sd: target/source stride difference (in stride transfer mode).
  98  * @drt: request type
  99  */
 100 struct jz4780_dma_hwdesc {
 101         uint32_t dcm;
 102         uint32_t dsa;
 103         uint32_t dta;
 104         uint32_t dtc;
 105         uint32_t sd;
 106         uint32_t drt;
 107         uint32_t reserved[2];
 108 };
 109
 110 /* Size of allocations for hardware descriptor blocks. */
 111 #define JZ_DMA_DESC_BLOCK_SIZE  PAGE_SIZE
 112 #define JZ_DMA_MAX_DESC         \
 113         (JZ_DMA_DESC_BLOCK_SIZE / sizeof(struct jz4780_dma_hwdesc))
 114
 115 struct jz4780_dma_desc {
 116         struct virt_dma_desc vdesc;
 117
 118         struct jz4780_dma_hwdesc *desc;
 119         dma_addr_t desc_phys;
 120         unsigned int count;
 121         enum dma_transaction_type type;
 122         uint32_t status;
 123 };
 124
 125 struct jz4780_dma_chan {
 126         struct virt_dma_chan vchan;
 127         unsigned int id;
 128         struct dma_pool *desc_pool;
 129
 130         uint32_t transfer_type;
 131         uint32_t transfer_shift;
 132         struct dma_slave_config config;
 133
 134         struct jz4780_dma_desc *desc;
 135         unsigned int curr_hwdesc;
 136 };
 137
 138 struct jz4780_dma_dev {
 139         struct dma_device dma_device;
 140         void __iomem *base;
 141         struct clk *clk;
 142         unsigned int irq;
 143
 144         uint32_t chan_reserved;
 145         struct jz4780_dma_chan chan[JZ_DMA_NR_CHANNELS];
 146 };
 147
 148 struct jz4780_dma_data {
 149         uint32_t transfer_type;
 150         int channel;
 151 };
 152
 153 static inline struct jz4780_dma_chan *to_jz4780_dma_chan(struct dma_chan *chan)
 154 {
 155         return container_of(chan, struct jz4780_dma_chan, vchan.chan);
 156 }
 157
 158 static inline struct jz4780_dma_desc *to_jz4780_dma_desc(
 159         struct virt_dma_desc *vdesc)
 160 {
 161         return container_of(vdesc, struct jz4780_dma_desc, vdesc);
 162 }
 163
 164 static inline struct jz4780_dma_dev *jz4780_dma_chan_parent(
 165         struct jz4780_dma_chan *jzchan)
 166 {
 167         return container_of(jzchan->vchan.chan.device, struct jz4780_dma_dev,
 168                             dma_device);
 169 }
 170
 171 static inline uint32_t jz4780_dma_readl(struct jz4780_dma_dev *jzdma,
 172         unsigned int reg)
 173 {
 174         return readl(jzdma->base + reg);
 175 }
 176
 177 static inline void jz4780_dma_writel(struct jz4780_dma_dev *jzdma,
 178         unsigned int reg, uint32_t val)
 179 {
 180         writel(val, jzdma->base + reg);
 181 }
 182
 183 static struct jz4780_dma_desc *jz4780_dma_desc_alloc(
 184         struct jz4780_dma_chan *jzchan, unsigned int count,
 185         enum dma_transaction_type type)
 186 {
 187         struct jz4780_dma_desc *desc;
 188
 189         if (count > JZ_DMA_MAX_DESC)
 190                 return NULL;
 191
 192         desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
 193         if (!desc)
 194                 return NULL;
 195
 196         desc->desc = dma_pool_alloc(jzchan->desc_pool, GFP_NOWAIT,
 197                                     &desc->desc_phys);
 198         if (!desc->desc) {
 199                 kfree(desc);
 200                 return NULL;
 201         }
 202
 203         desc->count = count;
 204         desc->type = type;
 205         return desc;
 206 }
 207
 208 static void jz4780_dma_desc_free(struct virt_dma_desc *vdesc)
 209 {
 210         struct jz4780_dma_desc *desc = to_jz4780_dma_desc(vdesc);
 211         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(vdesc->tx.chan);
 212
 213         dma_pool_free(jzchan->desc_pool, desc->desc, desc->desc_phys);
 214         kfree(desc);
 215 }
 216
 217 static uint32_t jz4780_dma_transfer_size(unsigned long val, uint32_t *shift)
 218 {
 219         int ord = ffs(val) - 1;
 220
 221         /*
 222          * 8 byte transfer sizes unsupported so fall back on 4. If it's larger
 223          * than the maximum, just limit it. It is perfectly safe to fall back
 224          * in this way since we won't exceed the maximum burst size supported
 225          * by the device, the only effect is reduced efficiency. This is better
 226          * than refusing to perform the request at all.
 227          */
 228         if (ord == 3)
 229                 ord = 2;
 230         else if (ord > 7)
 231                 ord = 7;
 232
 233         *shift = ord;
 234
 235         switch (ord) {
 236         case 0:
 237                 return JZ_DMA_SIZE_1_BYTE;
 238         case 1:
 239                 return JZ_DMA_SIZE_2_BYTE;
 240         case 2:
 241                 return JZ_DMA_SIZE_4_BYTE;
 242         case 4:
 243                 return JZ_DMA_SIZE_16_BYTE;
 244         case 5:
 245                 return JZ_DMA_SIZE_32_BYTE;
 246         case 6:
 247                 return JZ_DMA_SIZE_64_BYTE;
 248         default:
 249                 return JZ_DMA_SIZE_128_BYTE;
 250         }
 251 }
 252
 253 static int jz4780_dma_setup_hwdesc(struct jz4780_dma_chan *jzchan,
 254         struct jz4780_dma_hwdesc *desc, dma_addr_t addr, size_t len,
 255         enum dma_transfer_direction direction)
 256 {
 257         struct dma_slave_config *config = &jzchan->config;
 258         uint32_t width, maxburst, tsz;
 259
 260         if (direction == DMA_MEM_TO_DEV) {
 261                 desc->dcm = JZ_DMA_DCM_SAI;
 262                 desc->dsa = addr;
 263                 desc->dta = config->dst_addr;
 264                 desc->drt = jzchan->transfer_type;
 265
 266                 width = config->dst_addr_width;
 267                 maxburst = config->dst_maxburst;
 268         } else {
 269                 desc->dcm = JZ_DMA_DCM_DAI;
 270                 desc->dsa = config->src_addr;
 271                 desc->dta = addr;
 272                 desc->drt = jzchan->transfer_type;
 273
 274                 width = config->src_addr_width;
 275                 maxburst = config->src_maxburst;
 276         }
 277
 278         /*
 279          * This calculates the maximum transfer size that can be used with the
 280          * given address, length, width and maximum burst size. The address
 281          * must be aligned to the transfer size, the total length must be
 282          * divisible by the transfer size, and we must not use more than the
 283          * maximum burst specified by the user.
 284          */
 285         tsz = jz4780_dma_transfer_size(addr | len | (width * maxburst),
 286                                        &jzchan->transfer_shift);
 287
 288         switch (width) {
 289         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 290         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 291                 break;
 292         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 293                 width = JZ_DMA_WIDTH_32_BIT;
 294                 break;
 295         default:
 296                 return -EINVAL;
 297         }
 298
 299         desc->dcm |= tsz << JZ_DMA_DCM_TSZ_SHIFT;
 300         desc->dcm |= width << JZ_DMA_DCM_SP_SHIFT;
 301         desc->dcm |= width << JZ_DMA_DCM_DP_SHIFT;
 302
 303         desc->dtc = len >> jzchan->transfer_shift;
 304         return 0;
 305 }
 306
 307 static struct dma_async_tx_descriptor *jz4780_dma_prep_slave_sg(
 308         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
 309         enum dma_transfer_direction direction, unsigned long flags,
 310         void *context)
 311 {
 312         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 313         struct jz4780_dma_desc *desc;
 314         unsigned int i;
 315         int err;
 316
 317         desc = jz4780_dma_desc_alloc(jzchan, sg_len, DMA_SLAVE);
 318         if (!desc)
 319                 return NULL;
 320
 321         for (i = 0; i < sg_len; i++) {
 322                 err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i],
 323                                               sg_dma_address(&sgl[i]),
 324                                               sg_dma_len(&sgl[i]),
 325                                               direction);
 326                 if (err < 0)
 327                         return NULL;
 328
 329                 desc->desc[i].dcm |= JZ_DMA_DCM_TIE;
 330
 331                 if (i != (sg_len - 1)) {
 332                         /* Automatically proceeed to the next descriptor. */
 333                         desc->desc[i].dcm |= JZ_DMA_DCM_LINK;
 334
 335                         /*
 336                          * The upper 8 bits of the DTC field in the descriptor
 337                          * must be set to (offset from descriptor base of next
 338                          * descriptor >> 4).
 339                          */
 340                         desc->desc[i].dtc |=
 341                                 (((i + 1) * sizeof(*desc->desc)) >> 4) << 24;
 342                 }
 343         }
 344
 345         return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags);
 346 }
 347
 348 static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_cyclic(
 349         struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 350         size_t period_len, enum dma_transfer_direction direction,
 351         unsigned long flags)
 352 {
 353         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 354         struct jz4780_dma_desc *desc;
 355         unsigned int periods, i;
 356         int err;
 357
 358         if (buf_len % period_len)
 359                 return NULL;
 360
 361         periods = buf_len / period_len;
 362
 363         desc = jz4780_dma_desc_alloc(jzchan, periods, DMA_CYCLIC);
 364         if (!desc)
 365                 return NULL;
 366
 367         for (i = 0; i < periods; i++) {
 368                 err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i], buf_addr,
 369                                               period_len, direction);
 370                 if (err < 0)
 371                         return NULL;
 372
 373                 buf_addr += period_len;
 374
 375                 /*
 376                  * Set the link bit to indicate that the controller should
 377                  * automatically proceed to the next descriptor. In
 378                  * jz4780_dma_begin(), this will be cleared if we need to issue
 379                  * an interrupt after each period.
 380                  */
 381                 desc->desc[i].dcm |= JZ_DMA_DCM_TIE | JZ_DMA_DCM_LINK;
 382
 383                 /*
 384                  * The upper 8 bits of the DTC field in the descriptor must be
 385                  * set to (offset from descriptor base of next descriptor >> 4).
 386                  * If this is the last descriptor, link it back to the first,
 387                  * i.e. leave offset set to 0, otherwise point to the next one.
 388                  */
 389                 if (i != (periods - 1)) {
 390                         desc->desc[i].dtc |=
 391                                 (((i + 1) * sizeof(*desc->desc)) >> 4) << 24;
 392                 }
 393         }
 394
 395         return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags);
 396 }
 397
 398 struct dma_async_tx_descriptor *jz4780_dma_prep_dma_memcpy(
 399         struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 400         size_t len, unsigned long flags)
 401 {
 402         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 403         struct jz4780_dma_desc *desc;
 404         uint32_t tsz;
 405
 406         desc = jz4780_dma_desc_alloc(jzchan, 1, DMA_MEMCPY);
 407         if (!desc)
 408                 return NULL;
 409
 410         tsz = jz4780_dma_transfer_size(dest | src | len,
 411                                        &jzchan->transfer_shift);
 412
 413         desc->desc[0].dsa = src;
 414         desc->desc[0].dta = dest;
 415         desc->desc[0].drt = JZ_DMA_DRT_AUTO;
 416         desc->desc[0].dcm = JZ_DMA_DCM_TIE | JZ_DMA_DCM_SAI | JZ_DMA_DCM_DAI |
 417                             tsz << JZ_DMA_DCM_TSZ_SHIFT |
 418                             JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_SP_SHIFT |
 419                             JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_DP_SHIFT;
 420         desc->desc[0].dtc = len >> jzchan->transfer_shift;
 421
 422         return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags);
 423 }
 424
 425 static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan)
 426 {
 427         struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
 428         struct virt_dma_desc *vdesc;
 429         unsigned int i;
 430         dma_addr_t desc_phys;
 431
 432         if (!jzchan->desc) {
 433                 vdesc = vchan_next_desc(&jzchan->vchan);
 434                 if (!vdesc)
 435                         return;
 436
 437                 list_del(&vdesc->node);
 438
 439                 jzchan->desc = to_jz4780_dma_desc(vdesc);
 440                 jzchan->curr_hwdesc = 0;
 441
 442                 if (jzchan->desc->type == DMA_CYCLIC && vdesc->tx.callback) {
 443                         /*
 444                          * The DMA controller doesn't support triggering an
 445                          * interrupt after processing each descriptor, only
 446                          * after processing an entire terminated list of
 447                          * descriptors. For a cyclic DMA setup the list of
 448                          * descriptors is not terminated so we can never get an
 449                          * interrupt.
 450                          *
 451                          * If the user requested a callback for a cyclic DMA
 452                          * setup then we workaround this hardware limitation
 453                          * here by degrading to a set of unlinked descriptors
 454                          * which we will submit in sequence in response to the
 455                          * completion of processing the previous descriptor.
 456                          */
 457                         for (i = 0; i < jzchan->desc->count; i++)
 458                                 jzchan->desc->desc[i].dcm &= ~JZ_DMA_DCM_LINK;
 459                 }
 460         } else {
 461                 /*
 462                  * There is an existing transfer, therefore this must be one
 463                  * for which we unlinked the descriptors above. Advance to the
 464                  * next one in the list.
 465                  */
 466                 jzchan->curr_hwdesc =
 467                         (jzchan->curr_hwdesc + 1) % jzchan->desc->count;
 468         }
 469
 470         /* Use 8-word descriptors. */
 471         jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), JZ_DMA_DCS_DES8);
 472
 473         /* Write descriptor address and initiate descriptor fetch. */
 474         desc_phys = jzchan->desc->desc_phys +
 475                     (jzchan->curr_hwdesc * sizeof(*jzchan->desc->desc));
 476         jz4780_dma_writel(jzdma, JZ_DMA_REG_DDA(jzchan->id), desc_phys);
 477         jz4780_dma_writel(jzdma, JZ_DMA_REG_DDRS, BIT(jzchan->id));
 478
 479         /* Enable the channel. */
 480         jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id),
 481                           JZ_DMA_DCS_DES8 | JZ_DMA_DCS_CTE);
 482 }
 483
 484 static void jz4780_dma_issue_pending(struct dma_chan *chan)
 485 {
 486         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 487         unsigned long flags;
 488
 489         spin_lock_irqsave(&jzchan->vchan.lock, flags);
 490
 491         if (vchan_issue_pending(&jzchan->vchan) && !jzchan->desc)
 492                 jz4780_dma_begin(jzchan);
 493
 494         spin_unlock_irqrestore(&jzchan->vchan.lock, flags);
 495 }
 496
 497 static int jz4780_dma_terminate_all(struct dma_chan *chan)
 498 {
 499         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 500         struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
 501         unsigned long flags;
 502         LIST_HEAD(head);
 503
 504         spin_lock_irqsave(&jzchan->vchan.lock, flags);
 505
 506         /* Clear the DMA status and stop the transfer. */
 507         jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), 0);
 508         if (jzchan->desc) {
 509                 jz4780_dma_desc_free(&jzchan->desc->vdesc);
 510                 jzchan->desc = NULL;
 511         }
 512
 513         vchan_get_all_descriptors(&jzchan->vchan, &head);
 514
 515         spin_unlock_irqrestore(&jzchan->vchan.lock, flags);
 516
 517         vchan_dma_desc_free_list(&jzchan->vchan, &head);
 518         return 0;
 519 }
 520
 521 static int jz4780_dma_config(struct dma_chan *chan,
 522         struct dma_slave_config *config)
 523 {
 524         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 525
 526         if ((config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
 527            || (config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES))
 528                 return -EINVAL;
 529
 530         /* Copy the reset of the slave configuration, it is used later. */
 531         memcpy(&jzchan->config, config, sizeof(jzchan->config));
 532
 533         return 0;
 534 }
 535
 536 static size_t jz4780_dma_desc_residue(struct jz4780_dma_chan *jzchan,
 537         struct jz4780_dma_desc *desc, unsigned int next_sg)
 538 {
 539         struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
 540         unsigned int residue, count;
 541         unsigned int i;
 542
 543         residue = 0;
 544
 545         for (i = next_sg; i < desc->count; i++)
 546                 residue += desc->desc[i].dtc << jzchan->transfer_shift;
 547
 548         if (next_sg != 0) {
 549                 count = jz4780_dma_readl(jzdma,
 550                                          JZ_DMA_REG_DTC(jzchan->id));
 551                 residue += count << jzchan->transfer_shift;
 552         }
 553
 554         return residue;
 555 }
 556
 557 static enum dma_status jz4780_dma_tx_status(struct dma_chan *chan,
 558         dma_cookie_t cookie, struct dma_tx_state *txstate)
 559 {
 560         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 561         struct virt_dma_desc *vdesc;
 562         enum dma_status status;
 563         unsigned long flags;
 564
 565         status = dma_cookie_status(chan, cookie, txstate);
 566         if ((status == DMA_COMPLETE) || (txstate == NULL))
 567                 return status;
 568
 569         spin_lock_irqsave(&jzchan->vchan.lock, flags);
 570
 571         vdesc = vchan_find_desc(&jzchan->vchan, cookie);
 572         if (vdesc) {
 573                 /* On the issued list, so hasn't been processed yet */
 574                 txstate->residue = jz4780_dma_desc_residue(jzchan,
 575                                         to_jz4780_dma_desc(vdesc), 0);
 576         } else if (cookie == jzchan->desc->vdesc.tx.cookie) {
 577                 txstate->residue = jz4780_dma_desc_residue(jzchan, jzchan->desc,
 578                           (jzchan->curr_hwdesc + 1) % jzchan->desc->count);
 579         } else
 580                 txstate->residue = 0;
 581
 582         if (vdesc && jzchan->desc && vdesc == &jzchan->desc->vdesc
 583             && jzchan->desc->status & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT))
 584                 status = DMA_ERROR;
 585
 586         spin_unlock_irqrestore(&jzchan->vchan.lock, flags);
 587         return status;
 588 }
 589
 590 static void jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma,
 591         struct jz4780_dma_chan *jzchan)
 592 {
 593         uint32_t dcs;
 594
 595         spin_lock(&jzchan->vchan.lock);
 596
 597         dcs = jz4780_dma_readl(jzdma, JZ_DMA_REG_DCS(jzchan->id));
 598         jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), 0);
 599
 600         if (dcs & JZ_DMA_DCS_AR) {
 601                 dev_warn(&jzchan->vchan.chan.dev->device,
 602                          "address error (DCS=0x%x)\n", dcs);
 603         }
 604
 605         if (dcs & JZ_DMA_DCS_HLT) {
 606                 dev_warn(&jzchan->vchan.chan.dev->device,
 607                          "channel halt (DCS=0x%x)\n", dcs);
 608         }
 609
 610         if (jzchan->desc) {
 611                 jzchan->desc->status = dcs;
 612
 613                 if ((dcs & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT)) == 0) {
 614                         if (jzchan->desc->type == DMA_CYCLIC) {
 615                                 vchan_cyclic_callback(&jzchan->desc->vdesc);
 616                         } else {
 617                                 vchan_cookie_complete(&jzchan->desc->vdesc);
 618                                 jzchan->desc = NULL;
 619                         }
 620
 621                         jz4780_dma_begin(jzchan);
 622                 }
 623         } else {
 624                 dev_err(&jzchan->vchan.chan.dev->device,
 625                         "channel IRQ with no active transfer\n");
 626         }
 627
 628         spin_unlock(&jzchan->vchan.lock);
 629 }
 630
 631 static irqreturn_t jz4780_dma_irq_handler(int irq, void *data)
 632 {
 633         struct jz4780_dma_dev *jzdma = data;
 634         uint32_t pending, dmac;
 635         int i;
 636
 637         pending = jz4780_dma_readl(jzdma, JZ_DMA_REG_DIRQP);
 638
 639         for (i = 0; i < JZ_DMA_NR_CHANNELS; i++) {
 640                 if (!(pending & (1<<i)))
 641                         continue;
 642
 643                 jz4780_dma_chan_irq(jzdma, &jzdma->chan[i]);
 644         }
 645
 646         /* Clear halt and address error status of all channels. */
 647         dmac = jz4780_dma_readl(jzdma, JZ_DMA_REG_DMAC);
 648         dmac &= ~(JZ_DMA_DMAC_HLT | JZ_DMA_DMAC_AR);
 649         jz4780_dma_writel(jzdma, JZ_DMA_REG_DMAC, dmac);
 650
 651         /* Clear interrupt pending status. */
 652         jz4780_dma_writel(jzdma, JZ_DMA_REG_DIRQP, 0);
 653
 654         return IRQ_HANDLED;
 655 }
 656
 657 static int jz4780_dma_alloc_chan_resources(struct dma_chan *chan)
 658 {
 659         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 660
 661         jzchan->desc_pool = dma_pool_create(dev_name(&chan->dev->device),
 662                                             chan->device->dev,
 663                                             JZ_DMA_DESC_BLOCK_SIZE,
 664                                             PAGE_SIZE, 0);
 665         if (!jzchan->desc_pool) {
 666                 dev_err(&chan->dev->device,
 667                         "failed to allocate descriptor pool\n");
 668                 return -ENOMEM;
 669         }
 670
 671         return 0;
 672 }
 673
 674 static void jz4780_dma_free_chan_resources(struct dma_chan *chan)
 675 {
 676         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 677
 678         vchan_free_chan_resources(&jzchan->vchan);
 679         dma_pool_destroy(jzchan->desc_pool);
 680         jzchan->desc_pool = NULL;
 681 }
 682
 683 static bool jz4780_dma_filter_fn(struct dma_chan *chan, void *param)
 684 {
 685         struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
 686         struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
 687         struct jz4780_dma_data *data = param;
 688
 689         if (data->channel > -1) {
 690                 if (data->channel != jzchan->id)
 691                         return false;
 692         } else if (jzdma->chan_reserved & BIT(jzchan->id)) {
 693                 return false;
 694         }
 695
 696         jzchan->transfer_type = data->transfer_type;
 697
 698         return true;
 699 }
 700
 701 static struct dma_chan *jz4780_of_dma_xlate(struct of_phandle_args *dma_spec,
 702         struct of_dma *ofdma)
 703 {
 704         struct jz4780_dma_dev *jzdma = ofdma->of_dma_data;
 705         dma_cap_mask_t mask = jzdma->dma_device.cap_mask;
 706         struct jz4780_dma_data data;
 707
 708         if (dma_spec->args_count != 2)
 709                 return NULL;
 710
 711         data.transfer_type = dma_spec->args[0];
 712         data.channel = dma_spec->args[1];
 713
 714         if (data.channel > -1) {
 715                 if (data.channel >= JZ_DMA_NR_CHANNELS) {
 716                         dev_err(jzdma->dma_device.dev,
 717                                 "device requested non-existent channel %u\n",
 718                                 data.channel);
 719                         return NULL;
 720                 }
 721
 722                 /* Can only select a channel marked as reserved. */
 723                 if (!(jzdma->chan_reserved & BIT(data.channel))) {
 724                         dev_err(jzdma->dma_device.dev,
 725                                 "device requested unreserved channel %u\n",
 726                                 data.channel);
 727                         return NULL;
 728                 }
 729
 730                 jzdma->chan[data.channel].transfer_type = data.transfer_type;
 731
 732                 return dma_get_slave_channel(
 733                         &jzdma->chan[data.channel].vchan.chan);
 734         } else {
 735                 return dma_request_channel(mask, jz4780_dma_filter_fn, &data);
 736         }
 737 }
 738
 739 static int jz4780_dma_probe(struct platform_device *pdev)
 740 {
 741         struct device *dev = &pdev->dev;
 742         struct jz4780_dma_dev *jzdma;
 743         struct jz4780_dma_chan *jzchan;
 744         struct dma_device *dd;
 745         struct resource *res;
 746         int i, ret;
 747
 748         jzdma = devm_kzalloc(dev, sizeof(*jzdma), GFP_KERNEL);
 749         if (!jzdma)
 750                 return -ENOMEM;
 751
 752         platform_set_drvdata(pdev, jzdma);
 753
 754         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 755         if (!res) {
 756                 dev_err(dev, "failed to get I/O memory\n");
 757                 return -EINVAL;
 758         }
 759
 760         jzdma->base = devm_ioremap_resource(dev, res);
 761         if (IS_ERR(jzdma->base))
 762                 return PTR_ERR(jzdma->base);
 763
 764         ret = platform_get_irq(pdev, 0);
 765         if (ret < 0) {
 766                 dev_err(dev, "failed to get IRQ: %d\n", ret);
 767                 return ret;
 768         }
 769
 770         jzdma->irq = ret;
 771
 772         ret = devm_request_irq(dev, jzdma->irq, jz4780_dma_irq_handler, 0,
 773                                dev_name(dev), jzdma);
 774         if (ret) {
 775                 dev_err(dev, "failed to request IRQ %u!\n", jzdma->irq);
 776                 return ret;
 777         }
 778
 779         jzdma->clk = devm_clk_get(dev, NULL);
 780         if (IS_ERR(jzdma->clk)) {
 781                 dev_err(dev, "failed to get clock\n");
 782                 return PTR_ERR(jzdma->clk);
 783         }
 784
 785         clk_prepare_enable(jzdma->clk);
 786
 787         /* Property is optional, if it doesn't exist the value will remain 0. */
 788         of_property_read_u32_index(dev->of_node, "ingenic,reserved-channels",
 789                                    0, &jzdma->chan_reserved);
 790
 791         dd = &jzdma->dma_device;
 792
 793         dma_cap_set(DMA_MEMCPY, dd->cap_mask);
 794         dma_cap_set(DMA_SLAVE, dd->cap_mask);
 795         dma_cap_set(DMA_CYCLIC, dd->cap_mask);
 796
 797         dd->dev = dev;
 798         dd->copy_align = DMAENGINE_ALIGN_4_BYTES;
 799         dd->device_alloc_chan_resources = jz4780_dma_alloc_chan_resources;
 800         dd->device_free_chan_resources = jz4780_dma_free_chan_resources;
 801         dd->device_prep_slave_sg = jz4780_dma_prep_slave_sg;
 802         dd->device_prep_dma_cyclic = jz4780_dma_prep_dma_cyclic;
 803         dd->device_prep_dma_memcpy = jz4780_dma_prep_dma_memcpy;
 804         dd->device_config = jz4780_dma_config;
 805         dd->device_terminate_all = jz4780_dma_terminate_all;
 806         dd->device_tx_status = jz4780_dma_tx_status;
 807         dd->device_issue_pending = jz4780_dma_issue_pending;
 808         dd->src_addr_widths = JZ_DMA_BUSWIDTHS;
 809         dd->dst_addr_widths = JZ_DMA_BUSWIDTHS;
 810         dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
 811         dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
 812
 813         /*
 814          * Enable DMA controller, mark all channels as not programmable.
 815          * Also set the FMSC bit - it increases MSC performance, so it makes
 816          * little sense not to enable it.
 817          */
 818         jz4780_dma_writel(jzdma, JZ_DMA_REG_DMAC,
 819                           JZ_DMA_DMAC_DMAE | JZ_DMA_DMAC_FMSC);
 820         jz4780_dma_writel(jzdma, JZ_DMA_REG_DMACP, 0);
 821
 822         INIT_LIST_HEAD(&dd->channels);
 823
 824         for (i = 0; i < JZ_DMA_NR_CHANNELS; i++) {
 825                 jzchan = &jzdma->chan[i];
 826                 jzchan->id = i;
 827
 828                 vchan_init(&jzchan->vchan, dd);
 829                 jzchan->vchan.desc_free = jz4780_dma_desc_free;
 830         }
 831
 832         ret = dma_async_device_register(dd);
 833         if (ret) {
 834                 dev_err(dev, "failed to register device\n");
 835                 goto err_disable_clk;
 836         }
 837
 838         /* Register with OF DMA helpers. */
 839         ret = of_dma_controller_register(dev->of_node, jz4780_of_dma_xlate,
 840                                          jzdma);
 841         if (ret) {
 842                 dev_err(dev, "failed to register OF DMA controller\n");
 843                 goto err_unregister_dev;
 844         }
 845
 846         dev_info(dev, "JZ4780 DMA controller initialised\n");
 847         return 0;
 848
 849 err_unregister_dev:
 850         dma_async_device_unregister(dd);
 851
 852 err_disable_clk:
 853         clk_disable_unprepare(jzdma->clk);
 854         return ret;
 855 }
 856
 857 static int jz4780_dma_remove(struct platform_device *pdev)
 858 {
 859         struct jz4780_dma_dev *jzdma = platform_get_drvdata(pdev);
 860
 861         of_dma_controller_free(pdev->dev.of_node);
 862         devm_free_irq(&pdev->dev, jzdma->irq, jzdma);
 863         dma_async_device_unregister(&jzdma->dma_device);
 864         return 0;
 865 }
 866
 867 static const struct of_device_id jz4780_dma_dt_match[] = {
 868         { .compatible = "ingenic,jz4780-dma", .data = NULL },
 869         {},
 870 };
 871 MODULE_DEVICE_TABLE(of, jz4780_dma_dt_match);
 872
 873 static struct platform_driver jz4780_dma_driver = {
 874         .probe          = jz4780_dma_probe,
 875         .remove         = jz4780_dma_remove,
 876         .driver = {
 877                 .name   = "jz4780-dma",
 878                 .of_match_table = of_match_ptr(jz4780_dma_dt_match),
 879         },
 880 };
 881
 882 static int __init jz4780_dma_init(void)
 883 {
 884         return platform_driver_register(&jz4780_dma_driver);
 885 }
 886 subsys_initcall(jz4780_dma_init);
 887
 888 static void __exit jz4780_dma_exit(void)
 889 {
 890         platform_driver_unregister(&jz4780_dma_driver);
 891 }
 892 module_exit(jz4780_dma_exit);
 893
 894 MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
 895 MODULE_DESCRIPTION("Ingenic JZ4780 DMA controller driver");
 896 MODULE_LICENSE("GPL");