drivers/crypto/talitos.c

   1 /*
   2  * talitos - Freescale Integrated Security Engine (SEC) device driver
   3  *
   4  * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
   5  *
   6  * Scatterlist Crypto API glue code copied from files with the following:
   7  * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
   8  *
   9  * Crypto algorithm registration code copied from hifn driver:
  10  * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
  11  * All rights reserved.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/device.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/crypto.h>
  34 #include <linux/hw_random.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_irq.h>
  37 #include <linux/of_platform.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/io.h>
  40 #include <linux/spinlock.h>
  41 #include <linux/rtnetlink.h>
  42 #include <linux/slab.h>
  43
  44 #include <crypto/algapi.h>
  45 #include <crypto/aes.h>
  46 #include <crypto/des.h>
  47 #include <crypto/sha.h>
  48 #include <crypto/md5.h>
  49 #include <crypto/aead.h>
  50 #include <crypto/authenc.h>
  51 #include <crypto/skcipher.h>
  52 #include <crypto/hash.h>
  53 #include <crypto/internal/hash.h>
  54 #include <crypto/scatterwalk.h>
  55
  56 #include "talitos.h"
  57
  58 static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
  59 {
  60         talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
  61         talitos_ptr->eptr = upper_32_bits(dma_addr);
  62 }
  63
  64 /*
  65  * map virtual single (contiguous) pointer to h/w descriptor pointer
  66  */
  67 static void map_single_talitos_ptr(struct device *dev,
  68                                    struct talitos_ptr *talitos_ptr,
  69                                    unsigned short len, void *data,
  70                                    unsigned char extent,
  71                                    enum dma_data_direction dir)
  72 {
  73         dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
  74
  75         talitos_ptr->len = cpu_to_be16(len);
  76         to_talitos_ptr(talitos_ptr, dma_addr);
  77         talitos_ptr->j_extent = extent;
  78 }
  79
  80 /*
  81  * unmap bus single (contiguous) h/w descriptor pointer
  82  */
  83 static void unmap_single_talitos_ptr(struct device *dev,
  84                                      struct talitos_ptr *talitos_ptr,
  85                                      enum dma_data_direction dir)
  86 {
  87         dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
  88                          be16_to_cpu(talitos_ptr->len), dir);
  89 }
  90
  91 static int reset_channel(struct device *dev, int ch)
  92 {
  93         struct talitos_private *priv = dev_get_drvdata(dev);
  94         unsigned int timeout = TALITOS_TIMEOUT;
  95
  96         setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET);
  97
  98         while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & TALITOS_CCCR_RESET)
  99                && --timeout)
 100                 cpu_relax();
 101
 102         if (timeout == 0) {
 103                 dev_err(dev, "failed to reset channel %d\n", ch);
 104                 return -EIO;
 105         }
 106
 107         /* set 36-bit addressing, done writeback enable and done IRQ enable */
 108         setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
 109                   TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
 110
 111         /* and ICCR writeback, if available */
 112         if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
 113                 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
 114                           TALITOS_CCCR_LO_IWSE);
 115
 116         return 0;
 117 }
 118
 119 static int reset_device(struct device *dev)
 120 {
 121         struct talitos_private *priv = dev_get_drvdata(dev);
 122         unsigned int timeout = TALITOS_TIMEOUT;
 123         u32 mcr = TALITOS_MCR_SWR;
 124
 125         setbits32(priv->reg + TALITOS_MCR, mcr);
 126
 127         while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
 128                && --timeout)
 129                 cpu_relax();
 130
 131         if (priv->irq[1]) {
 132                 mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3;
 133                 setbits32(priv->reg + TALITOS_MCR, mcr);
 134         }
 135
 136         if (timeout == 0) {
 137                 dev_err(dev, "failed to reset device\n");
 138                 return -EIO;
 139         }
 140
 141         return 0;
 142 }
 143
 144 /*
 145  * Reset and initialize the device
 146  */
 147 static int init_device(struct device *dev)
 148 {
 149         struct talitos_private *priv = dev_get_drvdata(dev);
 150         int ch, err;
 151
 152         /*
 153          * Master reset
 154          * errata documentation: warning: certain SEC interrupts
 155          * are not fully cleared by writing the MCR:SWR bit,
 156          * set bit twice to completely reset
 157          */
 158         err = reset_device(dev);
 159         if (err)
 160                 return err;
 161
 162         err = reset_device(dev);
 163         if (err)
 164                 return err;
 165
 166         /* reset channels */
 167         for (ch = 0; ch < priv->num_channels; ch++) {
 168                 err = reset_channel(dev, ch);
 169                 if (err)
 170                         return err;
 171         }
 172
 173         /* enable channel done and error interrupts */
 174         setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
 175         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
 176
 177         /* disable integrity check error interrupts (use writeback instead) */
 178         if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
 179                 setbits32(priv->reg + TALITOS_MDEUICR_LO,
 180                           TALITOS_MDEUICR_LO_ICE);
 181
 182         return 0;
 183 }
 184
 185 /**
 186  * talitos_submit - submits a descriptor to the device for processing
 187  * @dev:        the SEC device to be used
 188  * @ch:         the SEC device channel to be used
 189  * @desc:       the descriptor to be processed by the device
 190  * @callback:   whom to call when processing is complete
 191  * @context:    a handle for use by caller (optional)
 192  *
 193  * desc must contain valid dma-mapped (bus physical) address pointers.
 194  * callback must check err and feedback in descriptor header
 195  * for device processing status.
 196  */
 197 int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
 198                    void (*callback)(struct device *dev,
 199                                     struct talitos_desc *desc,
 200                                     void *context, int error),
 201                    void *context)
 202 {
 203         struct talitos_private *priv = dev_get_drvdata(dev);
 204         struct talitos_request *request;
 205         unsigned long flags;
 206         int head;
 207
 208         spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
 209
 210         if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
 211                 /* h/w fifo is full */
 212                 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
 213                 return -EAGAIN;
 214         }
 215
 216         head = priv->chan[ch].head;
 217         request = &priv->chan[ch].fifo[head];
 218
 219         /* map descriptor and save caller data */
 220         request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
 221                                            DMA_BIDIRECTIONAL);
 222         request->callback = callback;
 223         request->context = context;
 224
 225         /* increment fifo head */
 226         priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
 227
 228         smp_wmb();
 229         request->desc = desc;
 230
 231         /* GO! */
 232         wmb();
 233         out_be32(priv->chan[ch].reg + TALITOS_FF,
 234                  upper_32_bits(request->dma_desc));
 235         out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
 236                  lower_32_bits(request->dma_desc));
 237
 238         spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
 239
 240         return -EINPROGRESS;
 241 }
 242 EXPORT_SYMBOL(talitos_submit);
 243
 244 /*
 245  * process what was done, notify callback of error if not
 246  */
 247 static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
 248 {
 249         struct talitos_private *priv = dev_get_drvdata(dev);
 250         struct talitos_request *request, saved_req;
 251         unsigned long flags;
 252         int tail, status;
 253
 254         spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
 255
 256         tail = priv->chan[ch].tail;
 257         while (priv->chan[ch].fifo[tail].desc) {
 258                 request = &priv->chan[ch].fifo[tail];
 259
 260                 /* descriptors with their done bits set don't get the error */
 261                 rmb();
 262                 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
 263                         status = 0;
 264                 else
 265                         if (!error)
 266                                 break;
 267                         else
 268                                 status = error;
 269
 270                 dma_unmap_single(dev, request->dma_desc,
 271                                  sizeof(struct talitos_desc),
 272                                  DMA_BIDIRECTIONAL);
 273
 274                 /* copy entries so we can call callback outside lock */
 275                 saved_req.desc = request->desc;
 276                 saved_req.callback = request->callback;
 277                 saved_req.context = request->context;
 278
 279                 /* release request entry in fifo */
 280                 smp_wmb();
 281                 request->desc = NULL;
 282
 283                 /* increment fifo tail */
 284                 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
 285
 286                 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
 287
 288                 atomic_dec(&priv->chan[ch].submit_count);
 289
 290                 saved_req.callback(dev, saved_req.desc, saved_req.context,
 291                                    status);
 292                 /* channel may resume processing in single desc error case */
 293                 if (error && !reset_ch && status == error)
 294                         return;
 295                 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
 296                 tail = priv->chan[ch].tail;
 297         }
 298
 299         spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
 300 }
 301
 302 /*
 303  * process completed requests for channels that have done status
 304  */
 305 #define DEF_TALITOS_DONE(name, ch_done_mask)                            \
 306 static void talitos_done_##name(unsigned long data)                     \
 307 {                                                                       \
 308         struct device *dev = (struct device *)data;                     \
 309         struct talitos_private *priv = dev_get_drvdata(dev);            \
 310         unsigned long flags;                                            \
 311                                                                         \
 312         if (ch_done_mask & 1)                                           \
 313                 flush_channel(dev, 0, 0, 0);                            \
 314         if (priv->num_channels == 1)                                    \
 315                 goto out;                                               \
 316         if (ch_done_mask & (1 << 2))                                    \
 317                 flush_channel(dev, 1, 0, 0);                            \
 318         if (ch_done_mask & (1 << 4))                                    \
 319                 flush_channel(dev, 2, 0, 0);                            \
 320         if (ch_done_mask & (1 << 6))                                    \
 321                 flush_channel(dev, 3, 0, 0);                            \
 322                                                                         \
 323 out:                                                                    \
 324         /* At this point, all completed channels have been processed */ \
 325         /* Unmask done interrupts for channels completed later on. */   \
 326         spin_lock_irqsave(&priv->reg_lock, flags);                      \
 327         setbits32(priv->reg + TALITOS_IMR, ch_done_mask);               \
 328         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);     \
 329         spin_unlock_irqrestore(&priv->reg_lock, flags);                 \
 330 }
 331 DEF_TALITOS_DONE(4ch, TALITOS_ISR_4CHDONE)
 332 DEF_TALITOS_DONE(ch0_2, TALITOS_ISR_CH_0_2_DONE)
 333 DEF_TALITOS_DONE(ch1_3, TALITOS_ISR_CH_1_3_DONE)
 334
 335 /*
 336  * locate current (offending) descriptor
 337  */
 338 static u32 current_desc_hdr(struct device *dev, int ch)
 339 {
 340         struct talitos_private *priv = dev_get_drvdata(dev);
 341         int tail = priv->chan[ch].tail;
 342         dma_addr_t cur_desc;
 343
 344         cur_desc = in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
 345
 346         while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
 347                 tail = (tail + 1) & (priv->fifo_len - 1);
 348                 if (tail == priv->chan[ch].tail) {
 349                         dev_err(dev, "couldn't locate current descriptor\n");
 350                         return 0;
 351                 }
 352         }
 353
 354         return priv->chan[ch].fifo[tail].desc->hdr;
 355 }
 356
 357 /*
 358  * user diagnostics; report root cause of error based on execution unit status
 359  */
 360 static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
 361 {
 362         struct talitos_private *priv = dev_get_drvdata(dev);
 363         int i;
 364
 365         if (!desc_hdr)
 366                 desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);
 367
 368         switch (desc_hdr & DESC_HDR_SEL0_MASK) {
 369         case DESC_HDR_SEL0_AFEU:
 370                 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
 371                         in_be32(priv->reg + TALITOS_AFEUISR),
 372                         in_be32(priv->reg + TALITOS_AFEUISR_LO));
 373                 break;
 374         case DESC_HDR_SEL0_DEU:
 375                 dev_err(dev, "DEUISR 0x%08x_%08x\n",
 376                         in_be32(priv->reg + TALITOS_DEUISR),
 377                         in_be32(priv->reg + TALITOS_DEUISR_LO));
 378                 break;
 379         case DESC_HDR_SEL0_MDEUA:
 380         case DESC_HDR_SEL0_MDEUB:
 381                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
 382                         in_be32(priv->reg + TALITOS_MDEUISR),
 383                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
 384                 break;
 385         case DESC_HDR_SEL0_RNG:
 386                 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
 387                         in_be32(priv->reg + TALITOS_RNGUISR),
 388                         in_be32(priv->reg + TALITOS_RNGUISR_LO));
 389                 break;
 390         case DESC_HDR_SEL0_PKEU:
 391                 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
 392                         in_be32(priv->reg + TALITOS_PKEUISR),
 393                         in_be32(priv->reg + TALITOS_PKEUISR_LO));
 394                 break;
 395         case DESC_HDR_SEL0_AESU:
 396                 dev_err(dev, "AESUISR 0x%08x_%08x\n",
 397                         in_be32(priv->reg + TALITOS_AESUISR),
 398                         in_be32(priv->reg + TALITOS_AESUISR_LO));
 399                 break;
 400         case DESC_HDR_SEL0_CRCU:
 401                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
 402                         in_be32(priv->reg + TALITOS_CRCUISR),
 403                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
 404                 break;
 405         case DESC_HDR_SEL0_KEU:
 406                 dev_err(dev, "KEUISR 0x%08x_%08x\n",
 407                         in_be32(priv->reg + TALITOS_KEUISR),
 408                         in_be32(priv->reg + TALITOS_KEUISR_LO));
 409                 break;
 410         }
 411
 412         switch (desc_hdr & DESC_HDR_SEL1_MASK) {
 413         case DESC_HDR_SEL1_MDEUA:
 414         case DESC_HDR_SEL1_MDEUB:
 415                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
 416                         in_be32(priv->reg + TALITOS_MDEUISR),
 417                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
 418                 break;
 419         case DESC_HDR_SEL1_CRCU:
 420                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
 421                         in_be32(priv->reg + TALITOS_CRCUISR),
 422                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
 423                 break;
 424         }
 425
 426         for (i = 0; i < 8; i++)
 427                 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
 428                         in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
 429                         in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
 430 }
 431
 432 /*
 433  * recover from error interrupts
 434  */
 435 static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
 436 {
 437         struct talitos_private *priv = dev_get_drvdata(dev);
 438         unsigned int timeout = TALITOS_TIMEOUT;
 439         int ch, error, reset_dev = 0, reset_ch = 0;
 440         u32 v, v_lo;
 441
 442         for (ch = 0; ch < priv->num_channels; ch++) {
 443                 /* skip channels without errors */
 444                 if (!(isr & (1 << (ch * 2 + 1))))
 445                         continue;
 446
 447                 error = -EINVAL;
 448
 449                 v = in_be32(priv->chan[ch].reg + TALITOS_CCPSR);
 450                 v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
 451
 452                 if (v_lo & TALITOS_CCPSR_LO_DOF) {
 453                         dev_err(dev, "double fetch fifo overflow error\n");
 454                         error = -EAGAIN;
 455                         reset_ch = 1;
 456                 }
 457                 if (v_lo & TALITOS_CCPSR_LO_SOF) {
 458                         /* h/w dropped descriptor */
 459                         dev_err(dev, "single fetch fifo overflow error\n");
 460                         error = -EAGAIN;
 461                 }
 462                 if (v_lo & TALITOS_CCPSR_LO_MDTE)
 463                         dev_err(dev, "master data transfer error\n");
 464                 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
 465                         dev_err(dev, "s/g data length zero error\n");
 466                 if (v_lo & TALITOS_CCPSR_LO_FPZ)
 467                         dev_err(dev, "fetch pointer zero error\n");
 468                 if (v_lo & TALITOS_CCPSR_LO_IDH)
 469                         dev_err(dev, "illegal descriptor header error\n");
 470                 if (v_lo & TALITOS_CCPSR_LO_IEU)
 471                         dev_err(dev, "invalid execution unit error\n");
 472                 if (v_lo & TALITOS_CCPSR_LO_EU)
 473                         report_eu_error(dev, ch, current_desc_hdr(dev, ch));
 474                 if (v_lo & TALITOS_CCPSR_LO_GB)
 475                         dev_err(dev, "gather boundary error\n");
 476                 if (v_lo & TALITOS_CCPSR_LO_GRL)
 477                         dev_err(dev, "gather return/length error\n");
 478                 if (v_lo & TALITOS_CCPSR_LO_SB)
 479                         dev_err(dev, "scatter boundary error\n");
 480                 if (v_lo & TALITOS_CCPSR_LO_SRL)
 481                         dev_err(dev, "scatter return/length error\n");
 482
 483                 flush_channel(dev, ch, error, reset_ch);
 484
 485                 if (reset_ch) {
 486                         reset_channel(dev, ch);
 487                 } else {
 488                         setbits32(priv->chan[ch].reg + TALITOS_CCCR,
 489                                   TALITOS_CCCR_CONT);
 490                         setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
 491                         while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
 492                                TALITOS_CCCR_CONT) && --timeout)
 493                                 cpu_relax();
 494                         if (timeout == 0) {
 495                                 dev_err(dev, "failed to restart channel %d\n",
 496                                         ch);
 497                                 reset_dev = 1;
 498                         }
 499                 }
 500         }
 501         if (reset_dev || isr & ~TALITOS_ISR_4CHERR || isr_lo) {
 502                 dev_err(dev, "done overflow, internal time out, or rngu error: "
 503                         "ISR 0x%08x_%08x\n", isr, isr_lo);
 504
 505                 /* purge request queues */
 506                 for (ch = 0; ch < priv->num_channels; ch++)
 507                         flush_channel(dev, ch, -EIO, 1);
 508
 509                 /* reset and reinitialize the device */
 510                 init_device(dev);
 511         }
 512 }
 513
 514 #define DEF_TALITOS_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet)           \
 515 static irqreturn_t talitos_interrupt_##name(int irq, void *data)               \
 516 {                                                                              \
 517         struct device *dev = data;                                             \
 518         struct talitos_private *priv = dev_get_drvdata(dev);                   \
 519         u32 isr, isr_lo;                                                       \
 520         unsigned long flags;                                                   \
 521                                                                                \
 522         spin_lock_irqsave(&priv->reg_lock, flags);                             \
 523         isr = in_be32(priv->reg + TALITOS_ISR);                                \
 524         isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);                          \
 525         /* Acknowledge interrupt */                                            \
 526         out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
 527         out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);                          \
 528                                                                                \
 529         if (unlikely(isr & ch_err_mask || isr_lo)) {                           \
 530                 spin_unlock_irqrestore(&priv->reg_lock, flags);                \
 531                 talitos_error(dev, isr & ch_err_mask, isr_lo);                 \
 532         }                                                                      \
 533         else {                                                                 \
 534                 if (likely(isr & ch_done_mask)) {                              \
 535                         /* mask further done interrupts. */                    \
 536                         clrbits32(priv->reg + TALITOS_IMR, ch_done_mask);      \
 537                         /* done_task will unmask done interrupts at exit */    \
 538                         tasklet_schedule(&priv->done_task[tlet]);              \
 539                 }                                                              \
 540                 spin_unlock_irqrestore(&priv->reg_lock, flags);                \
 541         }                                                                      \
 542                                                                                \
 543         return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED :  \
 544                                                                 IRQ_NONE;      \
 545 }
 546 DEF_TALITOS_INTERRUPT(4ch, TALITOS_ISR_4CHDONE, TALITOS_ISR_4CHERR, 0)
 547 DEF_TALITOS_INTERRUPT(ch0_2, TALITOS_ISR_CH_0_2_DONE, TALITOS_ISR_CH_0_2_ERR, 0)
 548 DEF_TALITOS_INTERRUPT(ch1_3, TALITOS_ISR_CH_1_3_DONE, TALITOS_ISR_CH_1_3_ERR, 1)
 549
 550 /*
 551  * hwrng
 552  */
 553 static int talitos_rng_data_present(struct hwrng *rng, int wait)
 554 {
 555         struct device *dev = (struct device *)rng->priv;
 556         struct talitos_private *priv = dev_get_drvdata(dev);
 557         u32 ofl;
 558         int i;
 559
 560         for (i = 0; i < 20; i++) {
 561                 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
 562                       TALITOS_RNGUSR_LO_OFL;
 563                 if (ofl || !wait)
 564                         break;
 565                 udelay(10);
 566         }
 567
 568         return !!ofl;
 569 }
 570
 571 static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
 572 {
 573         struct device *dev = (struct device *)rng->priv;
 574         struct talitos_private *priv = dev_get_drvdata(dev);
 575
 576         /* rng fifo requires 64-bit accesses */
 577         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
 578         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
 579
 580         return sizeof(u32);
 581 }
 582
 583 static int talitos_rng_init(struct hwrng *rng)
 584 {
 585         struct device *dev = (struct device *)rng->priv;
 586         struct talitos_private *priv = dev_get_drvdata(dev);
 587         unsigned int timeout = TALITOS_TIMEOUT;
 588
 589         setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
 590         while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
 591                && --timeout)
 592                 cpu_relax();
 593         if (timeout == 0) {
 594                 dev_err(dev, "failed to reset rng hw\n");
 595                 return -ENODEV;
 596         }
 597
 598         /* start generating */
 599         setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
 600
 601         return 0;
 602 }
 603
 604 static int talitos_register_rng(struct device *dev)
 605 {
 606         struct talitos_private *priv = dev_get_drvdata(dev);
 607
 608         priv->rng.name          = dev_driver_string(dev),
 609         priv->rng.init          = talitos_rng_init,
 610         priv->rng.data_present  = talitos_rng_data_present,
 611         priv->rng.data_read     = talitos_rng_data_read,
 612         priv->rng.priv          = (unsigned long)dev;
 613
 614         return hwrng_register(&priv->rng);
 615 }
 616
 617 static void talitos_unregister_rng(struct device *dev)
 618 {
 619         struct talitos_private *priv = dev_get_drvdata(dev);
 620
 621         hwrng_unregister(&priv->rng);
 622 }
 623
 624 /*
 625  * crypto alg
 626  */
 627 #define TALITOS_CRA_PRIORITY            3000
 628 #define TALITOS_MAX_KEY_SIZE            96
 629 #define TALITOS_MAX_IV_LENGTH           16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
 630
 631 #define MD5_BLOCK_SIZE    64
 632
 633 struct talitos_ctx {
 634         struct device *dev;
 635         int ch;
 636         __be32 desc_hdr_template;
 637         u8 key[TALITOS_MAX_KEY_SIZE];
 638         u8 iv[TALITOS_MAX_IV_LENGTH];
 639         unsigned int keylen;
 640         unsigned int enckeylen;
 641         unsigned int authkeylen;
 642         unsigned int authsize;
 643 };
 644
 645 #define HASH_MAX_BLOCK_SIZE             SHA512_BLOCK_SIZE
 646 #define TALITOS_MDEU_MAX_CONTEXT_SIZE   TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
 647
 648 struct talitos_ahash_req_ctx {
 649         u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
 650         unsigned int hw_context_size;
 651         u8 buf[HASH_MAX_BLOCK_SIZE];
 652         u8 bufnext[HASH_MAX_BLOCK_SIZE];
 653         unsigned int swinit;
 654         unsigned int first;
 655         unsigned int last;
 656         unsigned int to_hash_later;
 657         u64 nbuf;
 658         struct scatterlist bufsl[2];
 659         struct scatterlist *psrc;
 660 };
 661
 662 static int aead_setauthsize(struct crypto_aead *authenc,
 663                             unsigned int authsize)
 664 {
 665         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 666
 667         ctx->authsize = authsize;
 668
 669         return 0;
 670 }
 671
 672 static int aead_setkey(struct crypto_aead *authenc,
 673                        const u8 *key, unsigned int keylen)
 674 {
 675         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 676         struct crypto_authenc_keys keys;
 677
 678         if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
 679                 goto badkey;
 680
 681         if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
 682                 goto badkey;
 683
 684         memcpy(ctx->key, keys.authkey, keys.authkeylen);
 685         memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
 686
 687         ctx->keylen = keys.authkeylen + keys.enckeylen;
 688         ctx->enckeylen = keys.enckeylen;
 689         ctx->authkeylen = keys.authkeylen;
 690
 691         return 0;
 692
 693 badkey:
 694         crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
 695         return -EINVAL;
 696 }
 697
 698 /*
 699  * talitos_edesc - s/w-extended descriptor
 700  * @assoc_nents: number of segments in associated data scatterlist
 701  * @src_nents: number of segments in input scatterlist
 702  * @dst_nents: number of segments in output scatterlist
 703  * @assoc_chained: whether assoc is chained or not
 704  * @src_chained: whether src is chained or not
 705  * @dst_chained: whether dst is chained or not
 706  * @iv_dma: dma address of iv for checking continuity and link table
 707  * @dma_len: length of dma mapped link_tbl space
 708  * @dma_link_tbl: bus physical address of link_tbl
 709  * @desc: h/w descriptor
 710  * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
 711  *
 712  * if decrypting (with authcheck), or either one of src_nents or dst_nents
 713  * is greater than 1, an integrity check value is concatenated to the end
 714  * of link_tbl data
 715  */
 716 struct talitos_edesc {
 717         int assoc_nents;
 718         int src_nents;
 719         int dst_nents;
 720         bool assoc_chained;
 721         bool src_chained;
 722         bool dst_chained;
 723         dma_addr_t iv_dma;
 724         int dma_len;
 725         dma_addr_t dma_link_tbl;
 726         struct talitos_desc desc;
 727         struct talitos_ptr link_tbl[0];
 728 };
 729
 730 static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
 731                           unsigned int nents, enum dma_data_direction dir,
 732                           bool chained)
 733 {
 734         if (unlikely(chained))
 735                 while (sg) {
 736                         dma_map_sg(dev, sg, 1, dir);
 737                         sg = scatterwalk_sg_next(sg);
 738                 }
 739         else
 740                 dma_map_sg(dev, sg, nents, dir);
 741         return nents;
 742 }
 743
 744 static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
 745                                    enum dma_data_direction dir)
 746 {
 747         while (sg) {
 748                 dma_unmap_sg(dev, sg, 1, dir);
 749                 sg = scatterwalk_sg_next(sg);
 750         }
 751 }
 752
 753 static void talitos_sg_unmap(struct device *dev,
 754                              struct talitos_edesc *edesc,
 755                              struct scatterlist *src,
 756                              struct scatterlist *dst)
 757 {
 758         unsigned int src_nents = edesc->src_nents ? : 1;
 759         unsigned int dst_nents = edesc->dst_nents ? : 1;
 760
 761         if (src != dst) {
 762                 if (edesc->src_chained)
 763                         talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
 764                 else
 765                         dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
 766
 767                 if (dst) {
 768                         if (edesc->dst_chained)
 769                                 talitos_unmap_sg_chain(dev, dst,
 770                                                        DMA_FROM_DEVICE);
 771                         else
 772                                 dma_unmap_sg(dev, dst, dst_nents,
 773                                              DMA_FROM_DEVICE);
 774                 }
 775         } else
 776                 if (edesc->src_chained)
 777                         talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
 778                 else
 779                         dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
 780 }
 781
 782 static void ipsec_esp_unmap(struct device *dev,
 783                             struct talitos_edesc *edesc,
 784                             struct aead_request *areq)
 785 {
 786         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
 787         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
 788         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
 789         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
 790
 791         if (edesc->assoc_chained)
 792                 talitos_unmap_sg_chain(dev, areq->assoc, DMA_TO_DEVICE);
 793         else if (areq->assoclen)
 794                 /* assoc_nents counts also for IV in non-contiguous cases */
 795                 dma_unmap_sg(dev, areq->assoc,
 796                              edesc->assoc_nents ? edesc->assoc_nents - 1 : 1,
 797                              DMA_TO_DEVICE);
 798
 799         talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
 800
 801         if (edesc->dma_len)
 802                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
 803                                  DMA_BIDIRECTIONAL);
 804 }
 805
 806 /*
 807  * ipsec_esp descriptor callbacks
 808  */
 809 static void ipsec_esp_encrypt_done(struct device *dev,
 810                                    struct talitos_desc *desc, void *context,
 811                                    int err)
 812 {
 813         struct aead_request *areq = context;
 814         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
 815         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 816         struct talitos_edesc *edesc;
 817         struct scatterlist *sg;
 818         void *icvdata;
 819
 820         edesc = container_of(desc, struct talitos_edesc, desc);
 821
 822         ipsec_esp_unmap(dev, edesc, areq);
 823
 824         /* copy the generated ICV to dst */
 825         if (edesc->dst_nents) {
 826                 icvdata = &edesc->link_tbl[edesc->src_nents +
 827                                            edesc->dst_nents + 2 +
 828                                            edesc->assoc_nents];
 829                 sg = sg_last(areq->dst, edesc->dst_nents);
 830                 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
 831                        icvdata, ctx->authsize);
 832         }
 833
 834         kfree(edesc);
 835
 836         aead_request_complete(areq, err);
 837 }
 838
 839 static void ipsec_esp_decrypt_swauth_done(struct device *dev,
 840                                           struct talitos_desc *desc,
 841                                           void *context, int err)
 842 {
 843         struct aead_request *req = context;
 844         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
 845         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 846         struct talitos_edesc *edesc;
 847         struct scatterlist *sg;
 848         void *icvdata;
 849
 850         edesc = container_of(desc, struct talitos_edesc, desc);
 851
 852         ipsec_esp_unmap(dev, edesc, req);
 853
 854         if (!err) {
 855                 /* auth check */
 856                 if (edesc->dma_len)
 857                         icvdata = &edesc->link_tbl[edesc->src_nents +
 858                                                    edesc->dst_nents + 2 +
 859                                                    edesc->assoc_nents];
 860                 else
 861                         icvdata = &edesc->link_tbl[0];
 862
 863                 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
 864                 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
 865                              ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
 866         }
 867
 868         kfree(edesc);
 869
 870         aead_request_complete(req, err);
 871 }
 872
 873 static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
 874                                           struct talitos_desc *desc,
 875                                           void *context, int err)
 876 {
 877         struct aead_request *req = context;
 878         struct talitos_edesc *edesc;
 879
 880         edesc = container_of(desc, struct talitos_edesc, desc);
 881
 882         ipsec_esp_unmap(dev, edesc, req);
 883
 884         /* check ICV auth status */
 885         if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
 886                      DESC_HDR_LO_ICCR1_PASS))
 887                 err = -EBADMSG;
 888
 889         kfree(edesc);
 890
 891         aead_request_complete(req, err);
 892 }
 893
 894 /*
 895  * convert scatterlist to SEC h/w link table format
 896  * stop at cryptlen bytes
 897  */
 898 static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
 899                            int cryptlen, struct talitos_ptr *link_tbl_ptr)
 900 {
 901         int n_sg = sg_count;
 902
 903         while (n_sg--) {
 904                 to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
 905                 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
 906                 link_tbl_ptr->j_extent = 0;
 907                 link_tbl_ptr++;
 908                 cryptlen -= sg_dma_len(sg);
 909                 sg = scatterwalk_sg_next(sg);
 910         }
 911
 912         /* adjust (decrease) last one (or two) entry's len to cryptlen */
 913         link_tbl_ptr--;
 914         while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
 915                 /* Empty this entry, and move to previous one */
 916                 cryptlen += be16_to_cpu(link_tbl_ptr->len);
 917                 link_tbl_ptr->len = 0;
 918                 sg_count--;
 919                 link_tbl_ptr--;
 920         }
 921         be16_add_cpu(&link_tbl_ptr->len, cryptlen);
 922
 923         /* tag end of link table */
 924         link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
 925
 926         return sg_count;
 927 }
 928
 929 /*
 930  * fill in and submit ipsec_esp descriptor
 931  */
 932 static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
 933                      u64 seq, void (*callback) (struct device *dev,
 934                                                 struct talitos_desc *desc,
 935                                                 void *context, int error))
 936 {
 937         struct crypto_aead *aead = crypto_aead_reqtfm(areq);
 938         struct talitos_ctx *ctx = crypto_aead_ctx(aead);
 939         struct device *dev = ctx->dev;
 940         struct talitos_desc *desc = &edesc->desc;
 941         unsigned int cryptlen = areq->cryptlen;
 942         unsigned int authsize = ctx->authsize;
 943         unsigned int ivsize = crypto_aead_ivsize(aead);
 944         int sg_count, ret;
 945         int sg_link_tbl_len;
 946
 947         /* hmac key */
 948         map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
 949                                0, DMA_TO_DEVICE);
 950
 951         /* hmac data */
 952         desc->ptr[1].len = cpu_to_be16(areq->assoclen + ivsize);
 953         if (edesc->assoc_nents) {
 954                 int tbl_off = edesc->src_nents + edesc->dst_nents + 2;
 955                 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
 956
 957                 to_talitos_ptr(&desc->ptr[1], edesc->dma_link_tbl + tbl_off *
 958                                sizeof(struct talitos_ptr));
 959                 desc->ptr[1].j_extent = DESC_PTR_LNKTBL_JUMP;
 960
 961                 /* assoc_nents - 1 entries for assoc, 1 for IV */
 962                 sg_count = sg_to_link_tbl(areq->assoc, edesc->assoc_nents - 1,
 963                                           areq->assoclen, tbl_ptr);
 964
 965                 /* add IV to link table */
 966                 tbl_ptr += sg_count - 1;
 967                 tbl_ptr->j_extent = 0;
 968                 tbl_ptr++;
 969                 to_talitos_ptr(tbl_ptr, edesc->iv_dma);
 970                 tbl_ptr->len = cpu_to_be16(ivsize);
 971                 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
 972
 973                 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
 974                                            edesc->dma_len, DMA_BIDIRECTIONAL);
 975         } else {
 976                 if (areq->assoclen)
 977                         to_talitos_ptr(&desc->ptr[1],
 978                                        sg_dma_address(areq->assoc));
 979                 else
 980                         to_talitos_ptr(&desc->ptr[1], edesc->iv_dma);
 981                 desc->ptr[1].j_extent = 0;
 982         }
 983
 984         /* cipher iv */
 985         to_talitos_ptr(&desc->ptr[2], edesc->iv_dma);
 986         desc->ptr[2].len = cpu_to_be16(ivsize);
 987         desc->ptr[2].j_extent = 0;
 988         /* Sync needed for the aead_givencrypt case */
 989         dma_sync_single_for_device(dev, edesc->iv_dma, ivsize, DMA_TO_DEVICE);
 990
 991         /* cipher key */
 992         map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
 993                                (char *)&ctx->key + ctx->authkeylen, 0,
 994                                DMA_TO_DEVICE);
 995
 996         /*
 997          * cipher in
 998          * map and adjust cipher len to aead request cryptlen.
 999          * extent is bytes of HMAC postpended to ciphertext,
1000          * typically 12 for ipsec
1001          */
1002         desc->ptr[4].len = cpu_to_be16(cryptlen);
1003         desc->ptr[4].j_extent = authsize;
1004
1005         sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1006                                   (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1007                                                            : DMA_TO_DEVICE,
1008                                   edesc->src_chained);
1009
1010         if (sg_count == 1) {
1011                 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
1012         } else {
1013                 sg_link_tbl_len = cryptlen;
1014
1015                 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
1016                         sg_link_tbl_len = cryptlen + authsize;
1017
1018                 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
1019                                           &edesc->link_tbl[0]);
1020                 if (sg_count > 1) {
1021                         desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1022                         to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
1023                         dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1024                                                    edesc->dma_len,
1025                                                    DMA_BIDIRECTIONAL);
1026                 } else {
1027                         /* Only one segment now, so no link tbl needed */
1028                         to_talitos_ptr(&desc->ptr[4],
1029                                        sg_dma_address(areq->src));
1030                 }
1031         }
1032
1033         /* cipher out */
1034         desc->ptr[5].len = cpu_to_be16(cryptlen);
1035         desc->ptr[5].j_extent = authsize;
1036
1037         if (areq->src != areq->dst)
1038                 sg_count = talitos_map_sg(dev, areq->dst,
1039                                           edesc->dst_nents ? : 1,
1040                                           DMA_FROM_DEVICE, edesc->dst_chained);
1041
1042         if (sg_count == 1) {
1043                 to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
1044         } else {
1045                 int tbl_off = edesc->src_nents + 1;
1046                 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
1047
1048                 to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
1049                                tbl_off * sizeof(struct talitos_ptr));
1050                 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1051                                           tbl_ptr);
1052
1053                 /* Add an entry to the link table for ICV data */
1054                 tbl_ptr += sg_count - 1;
1055                 tbl_ptr->j_extent = 0;
1056                 tbl_ptr++;
1057                 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1058                 tbl_ptr->len = cpu_to_be16(authsize);
1059
1060                 /* icv data follows link tables */
1061                 to_talitos_ptr(tbl_ptr, edesc->dma_link_tbl +
1062                                (tbl_off + edesc->dst_nents + 1 +
1063                                 edesc->assoc_nents) *
1064                                sizeof(struct talitos_ptr));
1065                 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1066                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1067                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1068         }
1069
1070         /* iv out */
1071         map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1072                                DMA_FROM_DEVICE);
1073
1074         ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1075         if (ret != -EINPROGRESS) {
1076                 ipsec_esp_unmap(dev, edesc, areq);
1077                 kfree(edesc);
1078         }
1079         return ret;
1080 }
1081
1082 /*
1083  * derive number of elements in scatterlist
1084  */
1085 static int sg_count(struct scatterlist *sg_list, int nbytes, bool *chained)
1086 {
1087         struct scatterlist *sg = sg_list;
1088         int sg_nents = 0;
1089
1090         *chained = false;
1091         while (nbytes > 0) {
1092                 sg_nents++;
1093                 nbytes -= sg->length;
1094                 if (!sg_is_last(sg) && (sg + 1)->length == 0)
1095                         *chained = true;
1096                 sg = scatterwalk_sg_next(sg);
1097         }
1098
1099         return sg_nents;
1100 }
1101
1102 /*
1103  * allocate and map the extended descriptor
1104  */
1105 static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1106                                                  struct scatterlist *assoc,
1107                                                  struct scatterlist *src,
1108                                                  struct scatterlist *dst,
1109                                                  u8 *iv,
1110                                                  unsigned int assoclen,
1111                                                  unsigned int cryptlen,
1112                                                  unsigned int authsize,
1113                                                  unsigned int ivsize,
1114                                                  int icv_stashing,
1115                                                  u32 cryptoflags,
1116                                                  bool encrypt)
1117 {
1118         struct talitos_edesc *edesc;
1119         int assoc_nents = 0, src_nents, dst_nents, alloc_len, dma_len;
1120         bool assoc_chained = false, src_chained = false, dst_chained = false;
1121         dma_addr_t iv_dma = 0;
1122         gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
1123                       GFP_ATOMIC;
1124
1125         if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1126                 dev_err(dev, "length exceeds h/w max limit\n");
1127                 return ERR_PTR(-EINVAL);
1128         }
1129
1130         if (ivsize)
1131                 iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
1132
1133         if (assoclen) {
1134                 /*
1135                  * Currently it is assumed that iv is provided whenever assoc
1136                  * is.
1137                  */
1138                 BUG_ON(!iv);
1139
1140                 assoc_nents = sg_count(assoc, assoclen, &assoc_chained);
1141                 talitos_map_sg(dev, assoc, assoc_nents, DMA_TO_DEVICE,
1142                                assoc_chained);
1143                 assoc_nents = (assoc_nents == 1) ? 0 : assoc_nents;
1144
1145                 if (assoc_nents || sg_dma_address(assoc) + assoclen != iv_dma)
1146                         assoc_nents = assoc_nents ? assoc_nents + 1 : 2;
1147         }
1148
1149         if (!dst || dst == src) {
1150                 src_nents = sg_count(src, cryptlen + authsize, &src_chained);
1151                 src_nents = (src_nents == 1) ? 0 : src_nents;
1152                 dst_nents = dst ? src_nents : 0;
1153         } else { /* dst && dst != src*/
1154                 src_nents = sg_count(src, cryptlen + (encrypt ? 0 : authsize),
1155                                      &src_chained);
1156                 src_nents = (src_nents == 1) ? 0 : src_nents;
1157                 dst_nents = sg_count(dst, cryptlen + (encrypt ? authsize : 0),
1158                                      &dst_chained);
1159                 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1160         }
1161
1162         /*
1163          * allocate space for base edesc plus the link tables,
1164          * allowing for two separate entries for ICV and generated ICV (+ 2),
1165          * and the ICV data itself
1166          */
1167         alloc_len = sizeof(struct talitos_edesc);
1168         if (assoc_nents || src_nents || dst_nents) {
1169                 dma_len = (src_nents + dst_nents + 2 + assoc_nents) *
1170                           sizeof(struct talitos_ptr) + authsize;
1171                 alloc_len += dma_len;
1172         } else {
1173                 dma_len = 0;
1174                 alloc_len += icv_stashing ? authsize : 0;
1175         }
1176
1177         edesc = kmalloc(alloc_len, GFP_DMA | flags);
1178         if (!edesc) {
1179                 if (assoc_chained)
1180                         talitos_unmap_sg_chain(dev, assoc, DMA_TO_DEVICE);
1181                 else if (assoclen)
1182                         dma_unmap_sg(dev, assoc,
1183                                      assoc_nents ? assoc_nents - 1 : 1,
1184                                      DMA_TO_DEVICE);
1185
1186                 if (iv_dma)
1187                         dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
1188
1189                 dev_err(dev, "could not allocate edescriptor\n");
1190                 return ERR_PTR(-ENOMEM);
1191         }
1192
1193         edesc->assoc_nents = assoc_nents;
1194         edesc->src_nents = src_nents;
1195         edesc->dst_nents = dst_nents;
1196         edesc->assoc_chained = assoc_chained;
1197         edesc->src_chained = src_chained;
1198         edesc->dst_chained = dst_chained;
1199         edesc->iv_dma = iv_dma;
1200         edesc->dma_len = dma_len;
1201         if (dma_len)
1202                 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
1203                                                      edesc->dma_len,
1204                                                      DMA_BIDIRECTIONAL);
1205
1206         return edesc;
1207 }
1208
1209 static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
1210                                               int icv_stashing, bool encrypt)
1211 {
1212         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1213         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1214         unsigned int ivsize = crypto_aead_ivsize(authenc);
1215
1216         return talitos_edesc_alloc(ctx->dev, areq->assoc, areq->src, areq->dst,
1217                                    iv, areq->assoclen, areq->cryptlen,
1218                                    ctx->authsize, ivsize, icv_stashing,
1219                                    areq->base.flags, encrypt);
1220 }
1221
1222 static int aead_encrypt(struct aead_request *req)
1223 {
1224         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1225         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1226         struct talitos_edesc *edesc;
1227
1228         /* allocate extended descriptor */
1229         edesc = aead_edesc_alloc(req, req->iv, 0, true);
1230         if (IS_ERR(edesc))
1231                 return PTR_ERR(edesc);
1232
1233         /* set encrypt */
1234         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1235
1236         return ipsec_esp(edesc, req, 0, ipsec_esp_encrypt_done);
1237 }
1238
1239 static int aead_decrypt(struct aead_request *req)
1240 {
1241         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1242         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1243         unsigned int authsize = ctx->authsize;
1244         struct talitos_private *priv = dev_get_drvdata(ctx->dev);
1245         struct talitos_edesc *edesc;
1246         struct scatterlist *sg;
1247         void *icvdata;
1248
1249         req->cryptlen -= authsize;
1250
1251         /* allocate extended descriptor */
1252         edesc = aead_edesc_alloc(req, req->iv, 1, false);
1253         if (IS_ERR(edesc))
1254                 return PTR_ERR(edesc);
1255
1256         if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
1257             ((!edesc->src_nents && !edesc->dst_nents) ||
1258              priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
1259
1260                 /* decrypt and check the ICV */
1261                 edesc->desc.hdr = ctx->desc_hdr_template |
1262                                   DESC_HDR_DIR_INBOUND |
1263                                   DESC_HDR_MODE1_MDEU_CICV;
1264
1265                 /* reset integrity check result bits */
1266                 edesc->desc.hdr_lo = 0;
1267
1268                 return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_hwauth_done);
1269         }
1270
1271         /* Have to check the ICV with software */
1272         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1273
1274         /* stash incoming ICV for later cmp with ICV generated by the h/w */
1275         if (edesc->dma_len)
1276                 icvdata = &edesc->link_tbl[edesc->src_nents +
1277                                            edesc->dst_nents + 2 +
1278                                            edesc->assoc_nents];
1279         else
1280                 icvdata = &edesc->link_tbl[0];
1281
1282         sg = sg_last(req->src, edesc->src_nents ? : 1);
1283
1284         memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1285                ctx->authsize);
1286
1287         return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_swauth_done);
1288 }
1289
1290 static int aead_givencrypt(struct aead_givcrypt_request *req)
1291 {
1292         struct aead_request *areq = &req->areq;
1293         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1294         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1295         struct talitos_edesc *edesc;
1296
1297         /* allocate extended descriptor */
1298         edesc = aead_edesc_alloc(areq, req->giv, 0, true);
1299         if (IS_ERR(edesc))
1300                 return PTR_ERR(edesc);
1301
1302         /* set encrypt */
1303         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1304
1305         memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
1306         /* avoid consecutive packets going out with same IV */
1307         *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
1308
1309         return ipsec_esp(edesc, areq, req->seq, ipsec_esp_encrypt_done);
1310 }
1311
1312 static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1313                              const u8 *key, unsigned int keylen)
1314 {
1315         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1316
1317         memcpy(&ctx->key, key, keylen);
1318         ctx->keylen = keylen;
1319
1320         return 0;
1321 }
1322
1323 static void common_nonsnoop_unmap(struct device *dev,
1324                                   struct talitos_edesc *edesc,
1325                                   struct ablkcipher_request *areq)
1326 {
1327         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1328         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1329         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1330
1331         talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1332
1333         if (edesc->dma_len)
1334                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1335                                  DMA_BIDIRECTIONAL);
1336 }
1337
1338 static void ablkcipher_done(struct device *dev,
1339                             struct talitos_desc *desc, void *context,
1340                             int err)
1341 {
1342         struct ablkcipher_request *areq = context;
1343         struct talitos_edesc *edesc;
1344
1345         edesc = container_of(desc, struct talitos_edesc, desc);
1346
1347         common_nonsnoop_unmap(dev, edesc, areq);
1348
1349         kfree(edesc);
1350
1351         areq->base.complete(&areq->base, err);
1352 }
1353
1354 static int common_nonsnoop(struct talitos_edesc *edesc,
1355                            struct ablkcipher_request *areq,
1356                            void (*callback) (struct device *dev,
1357                                              struct talitos_desc *desc,
1358                                              void *context, int error))
1359 {
1360         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1361         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1362         struct device *dev = ctx->dev;
1363         struct talitos_desc *desc = &edesc->desc;
1364         unsigned int cryptlen = areq->nbytes;
1365         unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
1366         int sg_count, ret;
1367
1368         /* first DWORD empty */
1369         desc->ptr[0].len = 0;
1370         to_talitos_ptr(&desc->ptr[0], 0);
1371         desc->ptr[0].j_extent = 0;
1372
1373         /* cipher iv */
1374         to_talitos_ptr(&desc->ptr[1], edesc->iv_dma);
1375         desc->ptr[1].len = cpu_to_be16(ivsize);
1376         desc->ptr[1].j_extent = 0;
1377
1378         /* cipher key */
1379         map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1380                                (char *)&ctx->key, 0, DMA_TO_DEVICE);
1381
1382         /*
1383          * cipher in
1384          */
1385         desc->ptr[3].len = cpu_to_be16(cryptlen);
1386         desc->ptr[3].j_extent = 0;
1387
1388         sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1389                                   (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1390                                                            : DMA_TO_DEVICE,
1391                                   edesc->src_chained);
1392
1393         if (sg_count == 1) {
1394                 to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
1395         } else {
1396                 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1397                                           &edesc->link_tbl[0]);
1398                 if (sg_count > 1) {
1399                         to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1400                         desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1401                         dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1402                                                    edesc->dma_len,
1403                                                    DMA_BIDIRECTIONAL);
1404                 } else {
1405                         /* Only one segment now, so no link tbl needed */
1406                         to_talitos_ptr(&desc->ptr[3],
1407                                        sg_dma_address(areq->src));
1408                 }
1409         }
1410
1411         /* cipher out */
1412         desc->ptr[4].len = cpu_to_be16(cryptlen);
1413         desc->ptr[4].j_extent = 0;
1414
1415         if (areq->src != areq->dst)
1416                 sg_count = talitos_map_sg(dev, areq->dst,
1417                                           edesc->dst_nents ? : 1,
1418                                           DMA_FROM_DEVICE, edesc->dst_chained);
1419
1420         if (sg_count == 1) {
1421                 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
1422         } else {
1423                 struct talitos_ptr *link_tbl_ptr =
1424                         &edesc->link_tbl[edesc->src_nents + 1];
1425
1426                 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
1427                                               (edesc->src_nents + 1) *
1428                                               sizeof(struct talitos_ptr));
1429                 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1430                 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1431                                           link_tbl_ptr);
1432                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1433                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1434         }
1435
1436         /* iv out */
1437         map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1438                                DMA_FROM_DEVICE);
1439
1440         /* last DWORD empty */
1441         desc->ptr[6].len = 0;
1442         to_talitos_ptr(&desc->ptr[6], 0);
1443         desc->ptr[6].j_extent = 0;
1444
1445         ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1446         if (ret != -EINPROGRESS) {
1447                 common_nonsnoop_unmap(dev, edesc, areq);
1448                 kfree(edesc);
1449         }
1450         return ret;
1451 }
1452
1453 static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1454                                                     areq, bool encrypt)
1455 {
1456         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1457         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1458         unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
1459
1460         return talitos_edesc_alloc(ctx->dev, NULL, areq->src, areq->dst,
1461                                    areq->info, 0, areq->nbytes, 0, ivsize, 0,
1462                                    areq->base.flags, encrypt);
1463 }
1464
1465 static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1466 {
1467         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1468         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1469         struct talitos_edesc *edesc;
1470
1471         /* allocate extended descriptor */
1472         edesc = ablkcipher_edesc_alloc(areq, true);
1473         if (IS_ERR(edesc))
1474                 return PTR_ERR(edesc);
1475
1476         /* set encrypt */
1477         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1478
1479         return common_nonsnoop(edesc, areq, ablkcipher_done);
1480 }
1481
1482 static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1483 {
1484         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1485         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1486         struct talitos_edesc *edesc;
1487
1488         /* allocate extended descriptor */
1489         edesc = ablkcipher_edesc_alloc(areq, false);
1490         if (IS_ERR(edesc))
1491                 return PTR_ERR(edesc);
1492
1493         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1494
1495         return common_nonsnoop(edesc, areq, ablkcipher_done);
1496 }
1497
1498 static void common_nonsnoop_hash_unmap(struct device *dev,
1499                                        struct talitos_edesc *edesc,
1500                                        struct ahash_request *areq)
1501 {
1502         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1503
1504         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1505
1506         /* When using hashctx-in, must unmap it. */
1507         if (edesc->desc.ptr[1].len)
1508                 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
1509                                          DMA_TO_DEVICE);
1510
1511         if (edesc->desc.ptr[2].len)
1512                 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
1513                                          DMA_TO_DEVICE);
1514
1515         talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL);
1516
1517         if (edesc->dma_len)
1518                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1519                                  DMA_BIDIRECTIONAL);
1520
1521 }
1522
1523 static void ahash_done(struct device *dev,
1524                        struct talitos_desc *desc, void *context,
1525                        int err)
1526 {
1527         struct ahash_request *areq = context;
1528         struct talitos_edesc *edesc =
1529                  container_of(desc, struct talitos_edesc, desc);
1530         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1531
1532         if (!req_ctx->last && req_ctx->to_hash_later) {
1533                 /* Position any partial block for next update/final/finup */
1534                 memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
1535                 req_ctx->nbuf = req_ctx->to_hash_later;
1536         }
1537         common_nonsnoop_hash_unmap(dev, edesc, areq);
1538
1539         kfree(edesc);
1540
1541         areq->base.complete(&areq->base, err);
1542 }
1543
1544 static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1545                                 struct ahash_request *areq, unsigned int length,
1546                                 void (*callback) (struct device *dev,
1547                                                   struct talitos_desc *desc,
1548                                                   void *context, int error))
1549 {
1550         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1551         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1552         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1553         struct device *dev = ctx->dev;
1554         struct talitos_desc *desc = &edesc->desc;
1555         int sg_count, ret;
1556
1557         /* first DWORD empty */
1558         desc->ptr[0] = zero_entry;
1559
1560         /* hash context in */
1561         if (!req_ctx->first || req_ctx->swinit) {
1562                 map_single_talitos_ptr(dev, &desc->ptr[1],
1563                                        req_ctx->hw_context_size,
1564                                        (char *)req_ctx->hw_context, 0,
1565                                        DMA_TO_DEVICE);
1566                 req_ctx->swinit = 0;
1567         } else {
1568                 desc->ptr[1] = zero_entry;
1569                 /* Indicate next op is not the first. */
1570                 req_ctx->first = 0;
1571         }
1572
1573         /* HMAC key */
1574         if (ctx->keylen)
1575                 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1576                                        (char *)&ctx->key, 0, DMA_TO_DEVICE);
1577         else
1578                 desc->ptr[2] = zero_entry;
1579
1580         /*
1581          * data in
1582          */
1583         desc->ptr[3].len = cpu_to_be16(length);
1584         desc->ptr[3].j_extent = 0;
1585
1586         sg_count = talitos_map_sg(dev, req_ctx->psrc,
1587                                   edesc->src_nents ? : 1,
1588                                   DMA_TO_DEVICE, edesc->src_chained);
1589
1590         if (sg_count == 1) {
1591                 to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc));
1592         } else {
1593                 sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length,
1594                                           &edesc->link_tbl[0]);
1595                 if (sg_count > 1) {
1596                         desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1597                         to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1598                         dma_sync_single_for_device(ctx->dev,
1599                                                    edesc->dma_link_tbl,
1600                                                    edesc->dma_len,
1601                                                    DMA_BIDIRECTIONAL);
1602                 } else {
1603                         /* Only one segment now, so no link tbl needed */
1604                         to_talitos_ptr(&desc->ptr[3],
1605                                        sg_dma_address(req_ctx->psrc));
1606                 }
1607         }
1608
1609         /* fifth DWORD empty */
1610         desc->ptr[4] = zero_entry;
1611
1612         /* hash/HMAC out -or- hash context out */
1613         if (req_ctx->last)
1614                 map_single_talitos_ptr(dev, &desc->ptr[5],
1615                                        crypto_ahash_digestsize(tfm),
1616                                        areq->result, 0, DMA_FROM_DEVICE);
1617         else
1618                 map_single_talitos_ptr(dev, &desc->ptr[5],
1619                                        req_ctx->hw_context_size,
1620                                        req_ctx->hw_context, 0, DMA_FROM_DEVICE);
1621
1622         /* last DWORD empty */
1623         desc->ptr[6] = zero_entry;
1624
1625         ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1626         if (ret != -EINPROGRESS) {
1627                 common_nonsnoop_hash_unmap(dev, edesc, areq);
1628                 kfree(edesc);
1629         }
1630         return ret;
1631 }
1632
1633 static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1634                                                unsigned int nbytes)
1635 {
1636         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1637         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1638         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1639
1640         return talitos_edesc_alloc(ctx->dev, NULL, req_ctx->psrc, NULL, NULL, 0,
1641                                    nbytes, 0, 0, 0, areq->base.flags, false);
1642 }
1643
1644 static int ahash_init(struct ahash_request *areq)
1645 {
1646         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1647         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1648
1649         /* Initialize the context */
1650         req_ctx->nbuf = 0;
1651         req_ctx->first = 1; /* first indicates h/w must init its context */
1652         req_ctx->swinit = 0; /* assume h/w init of context */
1653         req_ctx->hw_context_size =
1654                 (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
1655                         ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
1656                         : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
1657
1658         return 0;
1659 }
1660
1661 /*
1662  * on h/w without explicit sha224 support, we initialize h/w context
1663  * manually with sha224 constants, and tell it to run sha256.
1664  */
1665 static int ahash_init_sha224_swinit(struct ahash_request *areq)
1666 {
1667         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1668
1669         ahash_init(areq);
1670         req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
1671
1672         req_ctx->hw_context[0] = SHA224_H0;
1673         req_ctx->hw_context[1] = SHA224_H1;
1674         req_ctx->hw_context[2] = SHA224_H2;
1675         req_ctx->hw_context[3] = SHA224_H3;
1676         req_ctx->hw_context[4] = SHA224_H4;
1677         req_ctx->hw_context[5] = SHA224_H5;
1678         req_ctx->hw_context[6] = SHA224_H6;
1679         req_ctx->hw_context[7] = SHA224_H7;
1680
1681         /* init 64-bit count */
1682         req_ctx->hw_context[8] = 0;
1683         req_ctx->hw_context[9] = 0;
1684
1685         return 0;
1686 }
1687
1688 static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
1689 {
1690         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1691         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1692         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1693         struct talitos_edesc *edesc;
1694         unsigned int blocksize =
1695                         crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1696         unsigned int nbytes_to_hash;
1697         unsigned int to_hash_later;
1698         unsigned int nsg;
1699         bool chained;
1700
1701         if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
1702                 /* Buffer up to one whole block */
1703                 sg_copy_to_buffer(areq->src,
1704                                   sg_count(areq->src, nbytes, &chained),
1705                                   req_ctx->buf + req_ctx->nbuf, nbytes);
1706                 req_ctx->nbuf += nbytes;
1707                 return 0;
1708         }
1709
1710         /* At least (blocksize + 1) bytes are available to hash */
1711         nbytes_to_hash = nbytes + req_ctx->nbuf;
1712         to_hash_later = nbytes_to_hash & (blocksize - 1);
1713
1714         if (req_ctx->last)
1715                 to_hash_later = 0;
1716         else if (to_hash_later)
1717                 /* There is a partial block. Hash the full block(s) now */
1718                 nbytes_to_hash -= to_hash_later;
1719         else {
1720                 /* Keep one block buffered */
1721                 nbytes_to_hash -= blocksize;
1722                 to_hash_later = blocksize;
1723         }
1724
1725         /* Chain in any previously buffered data */
1726         if (req_ctx->nbuf) {
1727                 nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
1728                 sg_init_table(req_ctx->bufsl, nsg);
1729                 sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
1730                 if (nsg > 1)
1731                         scatterwalk_sg_chain(req_ctx->bufsl, 2, areq->src);
1732                 req_ctx->psrc = req_ctx->bufsl;
1733         } else
1734                 req_ctx->psrc = areq->src;
1735
1736         if (to_hash_later) {
1737                 int nents = sg_count(areq->src, nbytes, &chained);
1738                 sg_pcopy_to_buffer(areq->src, nents,
1739                                       req_ctx->bufnext,
1740                                       to_hash_later,
1741                                       nbytes - to_hash_later);
1742         }
1743         req_ctx->to_hash_later = to_hash_later;
1744
1745         /* Allocate extended descriptor */
1746         edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
1747         if (IS_ERR(edesc))
1748                 return PTR_ERR(edesc);
1749
1750         edesc->desc.hdr = ctx->desc_hdr_template;
1751
1752         /* On last one, request SEC to pad; otherwise continue */
1753         if (req_ctx->last)
1754                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
1755         else
1756                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
1757
1758         /* request SEC to INIT hash. */
1759         if (req_ctx->first && !req_ctx->swinit)
1760                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
1761
1762         /* When the tfm context has a keylen, it's an HMAC.
1763          * A first or last (ie. not middle) descriptor must request HMAC.
1764          */
1765         if (ctx->keylen && (req_ctx->first || req_ctx->last))
1766                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
1767
1768         return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
1769                                     ahash_done);
1770 }
1771
1772 static int ahash_update(struct ahash_request *areq)
1773 {
1774         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1775
1776         req_ctx->last = 0;
1777
1778         return ahash_process_req(areq, areq->nbytes);
1779 }
1780
1781 static int ahash_final(struct ahash_request *areq)
1782 {
1783         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1784
1785         req_ctx->last = 1;
1786
1787         return ahash_process_req(areq, 0);
1788 }
1789
1790 static int ahash_finup(struct ahash_request *areq)
1791 {
1792         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1793
1794         req_ctx->last = 1;
1795
1796         return ahash_process_req(areq, areq->nbytes);
1797 }
1798
1799 static int ahash_digest(struct ahash_request *areq)
1800 {
1801         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1802         struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
1803
1804         ahash->init(areq);
1805         req_ctx->last = 1;
1806
1807         return ahash_process_req(areq, areq->nbytes);
1808 }
1809
1810 struct keyhash_result {
1811         struct completion completion;
1812         int err;
1813 };
1814
1815 static void keyhash_complete(struct crypto_async_request *req, int err)
1816 {
1817         struct keyhash_result *res = req->data;
1818
1819         if (err == -EINPROGRESS)
1820                 return;
1821
1822         res->err = err;
1823         complete(&res->completion);
1824 }
1825
1826 static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
1827                    u8 *hash)
1828 {
1829         struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1830
1831         struct scatterlist sg[1];
1832         struct ahash_request *req;
1833         struct keyhash_result hresult;
1834         int ret;
1835
1836         init_completion(&hresult.completion);
1837
1838         req = ahash_request_alloc(tfm, GFP_KERNEL);
1839         if (!req)
1840                 return -ENOMEM;
1841
1842         /* Keep tfm keylen == 0 during hash of the long key */
1843         ctx->keylen = 0;
1844         ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1845                                    keyhash_complete, &hresult);
1846
1847         sg_init_one(&sg[0], key, keylen);
1848
1849         ahash_request_set_crypt(req, sg, hash, keylen);
1850         ret = crypto_ahash_digest(req);
1851         switch (ret) {
1852         case 0:
1853                 break;
1854         case -EINPROGRESS:
1855         case -EBUSY:
1856                 ret = wait_for_completion_interruptible(
1857                         &hresult.completion);
1858                 if (!ret)
1859                         ret = hresult.err;
1860                 break;
1861         default:
1862                 break;
1863         }
1864         ahash_request_free(req);
1865
1866         return ret;
1867 }
1868
1869 static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
1870                         unsigned int keylen)
1871 {
1872         struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1873         unsigned int blocksize =
1874                         crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1875         unsigned int digestsize = crypto_ahash_digestsize(tfm);
1876         unsigned int keysize = keylen;
1877         u8 hash[SHA512_DIGEST_SIZE];
1878         int ret;
1879
1880         if (keylen <= blocksize)
1881                 memcpy(ctx->key, key, keysize);
1882         else {
1883                 /* Must get the hash of the long key */
1884                 ret = keyhash(tfm, key, keylen, hash);
1885
1886                 if (ret) {
1887                         crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1888                         return -EINVAL;
1889                 }
1890
1891                 keysize = digestsize;
1892                 memcpy(ctx->key, hash, digestsize);
1893         }
1894
1895         ctx->keylen = keysize;
1896
1897         return 0;
1898 }
1899
1900
1901 struct talitos_alg_template {
1902         u32 type;
1903         union {
1904                 struct crypto_alg crypto;
1905                 struct ahash_alg hash;
1906         } alg;
1907         __be32 desc_hdr_template;
1908 };
1909
1910 static struct talitos_alg_template driver_algs[] = {
1911         /* AEAD algorithms.  These use a single-pass ipsec_esp descriptor */
1912         {       .type = CRYPTO_ALG_TYPE_AEAD,
1913                 .alg.crypto = {
1914                         .cra_name = "authenc(hmac(sha1),cbc(aes))",
1915                         .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1916                         .cra_blocksize = AES_BLOCK_SIZE,
1917                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1918                         .cra_aead = {
1919                                 .ivsize = AES_BLOCK_SIZE,
1920                                 .maxauthsize = SHA1_DIGEST_SIZE,
1921                         }
1922                 },
1923                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1924                                      DESC_HDR_SEL0_AESU |
1925                                      DESC_HDR_MODE0_AESU_CBC |
1926                                      DESC_HDR_SEL1_MDEUA |
1927                                      DESC_HDR_MODE1_MDEU_INIT |
1928                                      DESC_HDR_MODE1_MDEU_PAD |
1929                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1930         },
1931         {       .type = CRYPTO_ALG_TYPE_AEAD,
1932                 .alg.crypto = {
1933                         .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1934                         .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1935                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1936                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1937                         .cra_aead = {
1938                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1939                                 .maxauthsize = SHA1_DIGEST_SIZE,
1940                         }
1941                 },
1942                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1943                                      DESC_HDR_SEL0_DEU |
1944                                      DESC_HDR_MODE0_DEU_CBC |
1945                                      DESC_HDR_MODE0_DEU_3DES |
1946                                      DESC_HDR_SEL1_MDEUA |
1947                                      DESC_HDR_MODE1_MDEU_INIT |
1948                                      DESC_HDR_MODE1_MDEU_PAD |
1949                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1950         },
1951         {       .type = CRYPTO_ALG_TYPE_AEAD,
1952                 .alg.crypto = {
1953                         .cra_name = "authenc(hmac(sha224),cbc(aes))",
1954                         .cra_driver_name = "authenc-hmac-sha224-cbc-aes-talitos",
1955                         .cra_blocksize = AES_BLOCK_SIZE,
1956                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1957                         .cra_aead = {
1958                                 .ivsize = AES_BLOCK_SIZE,
1959                                 .maxauthsize = SHA224_DIGEST_SIZE,
1960                         }
1961                 },
1962                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1963                                      DESC_HDR_SEL0_AESU |
1964                                      DESC_HDR_MODE0_AESU_CBC |
1965                                      DESC_HDR_SEL1_MDEUA |
1966                                      DESC_HDR_MODE1_MDEU_INIT |
1967                                      DESC_HDR_MODE1_MDEU_PAD |
1968                                      DESC_HDR_MODE1_MDEU_SHA224_HMAC,
1969         },
1970         {       .type = CRYPTO_ALG_TYPE_AEAD,
1971                 .alg.crypto = {
1972                         .cra_name = "authenc(hmac(sha224),cbc(des3_ede))",
1973                         .cra_driver_name = "authenc-hmac-sha224-cbc-3des-talitos",
1974                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1975                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1976                         .cra_aead = {
1977                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1978                                 .maxauthsize = SHA224_DIGEST_SIZE,
1979                         }
1980                 },
1981                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1982                                      DESC_HDR_SEL0_DEU |
1983                                      DESC_HDR_MODE0_DEU_CBC |
1984                                      DESC_HDR_MODE0_DEU_3DES |
1985                                      DESC_HDR_SEL1_MDEUA |
1986                                      DESC_HDR_MODE1_MDEU_INIT |
1987                                      DESC_HDR_MODE1_MDEU_PAD |
1988                                      DESC_HDR_MODE1_MDEU_SHA224_HMAC,
1989         },
1990         {       .type = CRYPTO_ALG_TYPE_AEAD,
1991                 .alg.crypto = {
1992                         .cra_name = "authenc(hmac(sha256),cbc(aes))",
1993                         .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
1994                         .cra_blocksize = AES_BLOCK_SIZE,
1995                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1996                         .cra_aead = {
1997                                 .ivsize = AES_BLOCK_SIZE,
1998                                 .maxauthsize = SHA256_DIGEST_SIZE,
1999                         }
2000                 },
2001                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2002                                      DESC_HDR_SEL0_AESU |
2003                                      DESC_HDR_MODE0_AESU_CBC |
2004                                      DESC_HDR_SEL1_MDEUA |
2005                                      DESC_HDR_MODE1_MDEU_INIT |
2006                                      DESC_HDR_MODE1_MDEU_PAD |
2007                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2008         },
2009         {       .type = CRYPTO_ALG_TYPE_AEAD,
2010                 .alg.crypto = {
2011                         .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
2012                         .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
2013                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2014                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2015                         .cra_aead = {
2016                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2017                                 .maxauthsize = SHA256_DIGEST_SIZE,
2018                         }
2019                 },
2020                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2021                                      DESC_HDR_SEL0_DEU |
2022                                      DESC_HDR_MODE0_DEU_CBC |
2023                                      DESC_HDR_MODE0_DEU_3DES |
2024                                      DESC_HDR_SEL1_MDEUA |
2025                                      DESC_HDR_MODE1_MDEU_INIT |
2026                                      DESC_HDR_MODE1_MDEU_PAD |
2027                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2028         },
2029         {       .type = CRYPTO_ALG_TYPE_AEAD,
2030                 .alg.crypto = {
2031                         .cra_name = "authenc(hmac(sha384),cbc(aes))",
2032                         .cra_driver_name = "authenc-hmac-sha384-cbc-aes-talitos",
2033                         .cra_blocksize = AES_BLOCK_SIZE,
2034                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2035                         .cra_aead = {
2036                                 .ivsize = AES_BLOCK_SIZE,
2037                                 .maxauthsize = SHA384_DIGEST_SIZE,
2038                         }
2039                 },
2040                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2041                                      DESC_HDR_SEL0_AESU |
2042                                      DESC_HDR_MODE0_AESU_CBC |
2043                                      DESC_HDR_SEL1_MDEUB |
2044                                      DESC_HDR_MODE1_MDEU_INIT |
2045                                      DESC_HDR_MODE1_MDEU_PAD |
2046                                      DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2047         },
2048         {       .type = CRYPTO_ALG_TYPE_AEAD,
2049                 .alg.crypto = {
2050                         .cra_name = "authenc(hmac(sha384),cbc(des3_ede))",
2051                         .cra_driver_name = "authenc-hmac-sha384-cbc-3des-talitos",
2052                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2053                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2054                         .cra_aead = {
2055                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2056                                 .maxauthsize = SHA384_DIGEST_SIZE,
2057                         }
2058                 },
2059                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2060                                      DESC_HDR_SEL0_DEU |
2061                                      DESC_HDR_MODE0_DEU_CBC |
2062                                      DESC_HDR_MODE0_DEU_3DES |
2063                                      DESC_HDR_SEL1_MDEUB |
2064                                      DESC_HDR_MODE1_MDEU_INIT |
2065                                      DESC_HDR_MODE1_MDEU_PAD |
2066                                      DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2067         },
2068         {       .type = CRYPTO_ALG_TYPE_AEAD,
2069                 .alg.crypto = {
2070                         .cra_name = "authenc(hmac(sha512),cbc(aes))",
2071                         .cra_driver_name = "authenc-hmac-sha512-cbc-aes-talitos",
2072                         .cra_blocksize = AES_BLOCK_SIZE,
2073                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2074                         .cra_aead = {
2075                                 .ivsize = AES_BLOCK_SIZE,
2076                                 .maxauthsize = SHA512_DIGEST_SIZE,
2077                         }
2078                 },
2079                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2080                                      DESC_HDR_SEL0_AESU |
2081                                      DESC_HDR_MODE0_AESU_CBC |
2082                                      DESC_HDR_SEL1_MDEUB |
2083                                      DESC_HDR_MODE1_MDEU_INIT |
2084                                      DESC_HDR_MODE1_MDEU_PAD |
2085                                      DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2086         },
2087         {       .type = CRYPTO_ALG_TYPE_AEAD,
2088                 .alg.crypto = {
2089                         .cra_name = "authenc(hmac(sha512),cbc(des3_ede))",
2090                         .cra_driver_name = "authenc-hmac-sha512-cbc-3des-talitos",
2091                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2092                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2093                         .cra_aead = {
2094                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2095                                 .maxauthsize = SHA512_DIGEST_SIZE,
2096                         }
2097                 },
2098                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2099                                      DESC_HDR_SEL0_DEU |
2100                                      DESC_HDR_MODE0_DEU_CBC |
2101                                      DESC_HDR_MODE0_DEU_3DES |
2102                                      DESC_HDR_SEL1_MDEUB |
2103                                      DESC_HDR_MODE1_MDEU_INIT |
2104                                      DESC_HDR_MODE1_MDEU_PAD |
2105                                      DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2106         },
2107         {       .type = CRYPTO_ALG_TYPE_AEAD,
2108                 .alg.crypto = {
2109                         .cra_name = "authenc(hmac(md5),cbc(aes))",
2110                         .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
2111                         .cra_blocksize = AES_BLOCK_SIZE,
2112                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2113                         .cra_aead = {
2114                                 .ivsize = AES_BLOCK_SIZE,
2115                                 .maxauthsize = MD5_DIGEST_SIZE,
2116                         }
2117                 },
2118                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2119                                      DESC_HDR_SEL0_AESU |
2120                                      DESC_HDR_MODE0_AESU_CBC |
2121                                      DESC_HDR_SEL1_MDEUA |
2122                                      DESC_HDR_MODE1_MDEU_INIT |
2123                                      DESC_HDR_MODE1_MDEU_PAD |
2124                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
2125         },
2126         {       .type = CRYPTO_ALG_TYPE_AEAD,
2127                 .alg.crypto = {
2128                         .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2129                         .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
2130                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2131                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2132                         .cra_aead = {
2133                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2134                                 .maxauthsize = MD5_DIGEST_SIZE,
2135                         }
2136                 },
2137                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2138                                      DESC_HDR_SEL0_DEU |
2139                                      DESC_HDR_MODE0_DEU_CBC |
2140                                      DESC_HDR_MODE0_DEU_3DES |
2141                                      DESC_HDR_SEL1_MDEUA |
2142                                      DESC_HDR_MODE1_MDEU_INIT |
2143                                      DESC_HDR_MODE1_MDEU_PAD |
2144                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
2145         },
2146         /* ABLKCIPHER algorithms. */
2147         {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2148                 .alg.crypto = {
2149                         .cra_name = "cbc(aes)",
2150                         .cra_driver_name = "cbc-aes-talitos",
2151                         .cra_blocksize = AES_BLOCK_SIZE,
2152                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2153                                      CRYPTO_ALG_ASYNC,
2154                         .cra_ablkcipher = {
2155                                 .min_keysize = AES_MIN_KEY_SIZE,
2156                                 .max_keysize = AES_MAX_KEY_SIZE,
2157                                 .ivsize = AES_BLOCK_SIZE,
2158                         }
2159                 },
2160                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2161                                      DESC_HDR_SEL0_AESU |
2162                                      DESC_HDR_MODE0_AESU_CBC,
2163         },
2164         {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2165                 .alg.crypto = {
2166                         .cra_name = "cbc(des3_ede)",
2167                         .cra_driver_name = "cbc-3des-talitos",
2168                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2169                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2170                                      CRYPTO_ALG_ASYNC,
2171                         .cra_ablkcipher = {
2172                                 .min_keysize = DES3_EDE_KEY_SIZE,
2173                                 .max_keysize = DES3_EDE_KEY_SIZE,
2174                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2175                         }
2176                 },
2177                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2178                                      DESC_HDR_SEL0_DEU |
2179                                      DESC_HDR_MODE0_DEU_CBC |
2180                                      DESC_HDR_MODE0_DEU_3DES,
2181         },
2182         /* AHASH algorithms. */
2183         {       .type = CRYPTO_ALG_TYPE_AHASH,
2184                 .alg.hash = {
2185                         .halg.digestsize = MD5_DIGEST_SIZE,
2186                         .halg.base = {
2187                                 .cra_name = "md5",
2188                                 .cra_driver_name = "md5-talitos",
2189                                 .cra_blocksize = MD5_BLOCK_SIZE,
2190                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2191                                              CRYPTO_ALG_ASYNC,
2192                         }
2193                 },
2194                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2195                                      DESC_HDR_SEL0_MDEUA |
2196                                      DESC_HDR_MODE0_MDEU_MD5,
2197         },
2198         {       .type = CRYPTO_ALG_TYPE_AHASH,
2199                 .alg.hash = {
2200                         .halg.digestsize = SHA1_DIGEST_SIZE,
2201                         .halg.base = {
2202                                 .cra_name = "sha1",
2203                                 .cra_driver_name = "sha1-talitos",
2204                                 .cra_blocksize = SHA1_BLOCK_SIZE,
2205                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2206                                              CRYPTO_ALG_ASYNC,
2207                         }
2208                 },
2209                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2210                                      DESC_HDR_SEL0_MDEUA |
2211                                      DESC_HDR_MODE0_MDEU_SHA1,
2212         },
2213         {       .type = CRYPTO_ALG_TYPE_AHASH,
2214                 .alg.hash = {
2215                         .halg.digestsize = SHA224_DIGEST_SIZE,
2216                         .halg.base = {
2217                                 .cra_name = "sha224",
2218                                 .cra_driver_name = "sha224-talitos",
2219                                 .cra_blocksize = SHA224_BLOCK_SIZE,
2220                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2221                                              CRYPTO_ALG_ASYNC,
2222                         }
2223                 },
2224                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2225                                      DESC_HDR_SEL0_MDEUA |
2226                                      DESC_HDR_MODE0_MDEU_SHA224,
2227         },
2228         {       .type = CRYPTO_ALG_TYPE_AHASH,
2229                 .alg.hash = {
2230                         .halg.digestsize = SHA256_DIGEST_SIZE,
2231                         .halg.base = {
2232                                 .cra_name = "sha256",
2233                                 .cra_driver_name = "sha256-talitos",
2234                                 .cra_blocksize = SHA256_BLOCK_SIZE,
2235                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2236                                              CRYPTO_ALG_ASYNC,
2237                         }
2238                 },
2239                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2240                                      DESC_HDR_SEL0_MDEUA |
2241                                      DESC_HDR_MODE0_MDEU_SHA256,
2242         },
2243         {       .type = CRYPTO_ALG_TYPE_AHASH,
2244                 .alg.hash = {
2245                         .halg.digestsize = SHA384_DIGEST_SIZE,
2246                         .halg.base = {
2247                                 .cra_name = "sha384",
2248                                 .cra_driver_name = "sha384-talitos",
2249                                 .cra_blocksize = SHA384_BLOCK_SIZE,
2250                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2251                                              CRYPTO_ALG_ASYNC,
2252                         }
2253                 },
2254                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2255                                      DESC_HDR_SEL0_MDEUB |
2256                                      DESC_HDR_MODE0_MDEUB_SHA384,
2257         },
2258         {       .type = CRYPTO_ALG_TYPE_AHASH,
2259                 .alg.hash = {
2260                         .halg.digestsize = SHA512_DIGEST_SIZE,
2261                         .halg.base = {
2262                                 .cra_name = "sha512",
2263                                 .cra_driver_name = "sha512-talitos",
2264                                 .cra_blocksize = SHA512_BLOCK_SIZE,
2265                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2266                                              CRYPTO_ALG_ASYNC,
2267                         }
2268                 },
2269                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2270                                      DESC_HDR_SEL0_MDEUB |
2271                                      DESC_HDR_MODE0_MDEUB_SHA512,
2272         },
2273         {       .type = CRYPTO_ALG_TYPE_AHASH,
2274                 .alg.hash = {
2275                         .halg.digestsize = MD5_DIGEST_SIZE,
2276                         .halg.base = {
2277                                 .cra_name = "hmac(md5)",
2278                                 .cra_driver_name = "hmac-md5-talitos",
2279                                 .cra_blocksize = MD5_BLOCK_SIZE,
2280                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2281                                              CRYPTO_ALG_ASYNC,
2282                         }
2283                 },
2284                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2285                                      DESC_HDR_SEL0_MDEUA |
2286                                      DESC_HDR_MODE0_MDEU_MD5,
2287         },
2288         {       .type = CRYPTO_ALG_TYPE_AHASH,
2289                 .alg.hash = {
2290                         .halg.digestsize = SHA1_DIGEST_SIZE,
2291                         .halg.base = {
2292                                 .cra_name = "hmac(sha1)",
2293                                 .cra_driver_name = "hmac-sha1-talitos",
2294                                 .cra_blocksize = SHA1_BLOCK_SIZE,
2295                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2296                                              CRYPTO_ALG_ASYNC,
2297                         }
2298                 },
2299                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2300                                      DESC_HDR_SEL0_MDEUA |
2301                                      DESC_HDR_MODE0_MDEU_SHA1,
2302         },
2303         {       .type = CRYPTO_ALG_TYPE_AHASH,
2304                 .alg.hash = {
2305                         .halg.digestsize = SHA224_DIGEST_SIZE,
2306                         .halg.base = {
2307                                 .cra_name = "hmac(sha224)",
2308                                 .cra_driver_name = "hmac-sha224-talitos",
2309                                 .cra_blocksize = SHA224_BLOCK_SIZE,
2310                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2311                                              CRYPTO_ALG_ASYNC,
2312                         }
2313                 },
2314                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2315                                      DESC_HDR_SEL0_MDEUA |
2316                                      DESC_HDR_MODE0_MDEU_SHA224,
2317         },
2318         {       .type = CRYPTO_ALG_TYPE_AHASH,
2319                 .alg.hash = {
2320                         .halg.digestsize = SHA256_DIGEST_SIZE,
2321                         .halg.base = {
2322                                 .cra_name = "hmac(sha256)",
2323                                 .cra_driver_name = "hmac-sha256-talitos",
2324                                 .cra_blocksize = SHA256_BLOCK_SIZE,
2325                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2326                                              CRYPTO_ALG_ASYNC,
2327                         }
2328                 },
2329                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2330                                      DESC_HDR_SEL0_MDEUA |
2331                                      DESC_HDR_MODE0_MDEU_SHA256,
2332         },
2333         {       .type = CRYPTO_ALG_TYPE_AHASH,
2334                 .alg.hash = {
2335                         .halg.digestsize = SHA384_DIGEST_SIZE,
2336                         .halg.base = {
2337                                 .cra_name = "hmac(sha384)",
2338                                 .cra_driver_name = "hmac-sha384-talitos",
2339                                 .cra_blocksize = SHA384_BLOCK_SIZE,
2340                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2341                                              CRYPTO_ALG_ASYNC,
2342                         }
2343                 },
2344                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2345                                      DESC_HDR_SEL0_MDEUB |
2346                                      DESC_HDR_MODE0_MDEUB_SHA384,
2347         },
2348         {       .type = CRYPTO_ALG_TYPE_AHASH,
2349                 .alg.hash = {
2350                         .halg.digestsize = SHA512_DIGEST_SIZE,
2351                         .halg.base = {
2352                                 .cra_name = "hmac(sha512)",
2353                                 .cra_driver_name = "hmac-sha512-talitos",
2354                                 .cra_blocksize = SHA512_BLOCK_SIZE,
2355                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2356                                              CRYPTO_ALG_ASYNC,
2357                         }
2358                 },
2359                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2360                                      DESC_HDR_SEL0_MDEUB |
2361                                      DESC_HDR_MODE0_MDEUB_SHA512,
2362         }
2363 };
2364
2365 struct talitos_crypto_alg {
2366         struct list_head entry;
2367         struct device *dev;
2368         struct talitos_alg_template algt;
2369 };
2370
2371 static int talitos_cra_init(struct crypto_tfm *tfm)
2372 {
2373         struct crypto_alg *alg = tfm->__crt_alg;
2374         struct talitos_crypto_alg *talitos_alg;
2375         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2376         struct talitos_private *priv;
2377
2378         if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
2379                 talitos_alg = container_of(__crypto_ahash_alg(alg),
2380                                            struct talitos_crypto_alg,
2381                                            algt.alg.hash);
2382         else
2383                 talitos_alg = container_of(alg, struct talitos_crypto_alg,
2384                                            algt.alg.crypto);
2385
2386         /* update context with ptr to dev */
2387         ctx->dev = talitos_alg->dev;
2388
2389         /* assign SEC channel to tfm in round-robin fashion */
2390         priv = dev_get_drvdata(ctx->dev);
2391         ctx->ch = atomic_inc_return(&priv->last_chan) &
2392                   (priv->num_channels - 1);
2393
2394         /* copy descriptor header template value */
2395         ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
2396
2397         /* select done notification */
2398         ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
2399
2400         return 0;
2401 }
2402
2403 static int talitos_cra_init_aead(struct crypto_tfm *tfm)
2404 {
2405         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2406
2407         talitos_cra_init(tfm);
2408
2409         /* random first IV */
2410         get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
2411
2412         return 0;
2413 }
2414
2415 static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
2416 {
2417         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2418
2419         talitos_cra_init(tfm);
2420
2421         ctx->keylen = 0;
2422         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2423                                  sizeof(struct talitos_ahash_req_ctx));
2424
2425         return 0;
2426 }
2427
2428 /*
2429  * given the alg's descriptor header template, determine whether descriptor
2430  * type and primary/secondary execution units required match the hw
2431  * capabilities description provided in the device tree node.
2432  */
2433 static int hw_supports(struct device *dev, __be32 desc_hdr_template)
2434 {
2435         struct talitos_private *priv = dev_get_drvdata(dev);
2436         int ret;
2437
2438         ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
2439               (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
2440
2441         if (SECONDARY_EU(desc_hdr_template))
2442                 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
2443                               & priv->exec_units);
2444
2445         return ret;
2446 }
2447
2448 static int talitos_remove(struct platform_device *ofdev)
2449 {
2450         struct device *dev = &ofdev->dev;
2451         struct talitos_private *priv = dev_get_drvdata(dev);
2452         struct talitos_crypto_alg *t_alg, *n;
2453         int i;
2454
2455         list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
2456                 switch (t_alg->algt.type) {
2457                 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2458                 case CRYPTO_ALG_TYPE_AEAD:
2459                         crypto_unregister_alg(&t_alg->algt.alg.crypto);
2460                         break;
2461                 case CRYPTO_ALG_TYPE_AHASH:
2462                         crypto_unregister_ahash(&t_alg->algt.alg.hash);
2463                         break;
2464                 }
2465                 list_del(&t_alg->entry);
2466                 kfree(t_alg);
2467         }
2468
2469         if (hw_supports(dev, DESC_HDR_SEL0_RNG))
2470                 talitos_unregister_rng(dev);
2471
2472         for (i = 0; i < priv->num_channels; i++)
2473                 kfree(priv->chan[i].fifo);
2474
2475         kfree(priv->chan);
2476
2477         for (i = 0; i < 2; i++)
2478                 if (priv->irq[i]) {
2479                         free_irq(priv->irq[i], dev);
2480                         irq_dispose_mapping(priv->irq[i]);
2481                 }
2482
2483         tasklet_kill(&priv->done_task[0]);
2484         if (priv->irq[1])
2485                 tasklet_kill(&priv->done_task[1]);
2486
2487         iounmap(priv->reg);
2488
2489         dev_set_drvdata(dev, NULL);
2490
2491         kfree(priv);
2492
2493         return 0;
2494 }
2495
2496 static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
2497                                                     struct talitos_alg_template
2498                                                            *template)
2499 {
2500         struct talitos_private *priv = dev_get_drvdata(dev);
2501         struct talitos_crypto_alg *t_alg;
2502         struct crypto_alg *alg;
2503
2504         t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
2505         if (!t_alg)
2506                 return ERR_PTR(-ENOMEM);
2507
2508         t_alg->algt = *template;
2509
2510         switch (t_alg->algt.type) {
2511         case CRYPTO_ALG_TYPE_ABLKCIPHER:
2512                 alg = &t_alg->algt.alg.crypto;
2513                 alg->cra_init = talitos_cra_init;
2514                 alg->cra_type = &crypto_ablkcipher_type;
2515                 alg->cra_ablkcipher.setkey = ablkcipher_setkey;
2516                 alg->cra_ablkcipher.encrypt = ablkcipher_encrypt;
2517                 alg->cra_ablkcipher.decrypt = ablkcipher_decrypt;
2518                 alg->cra_ablkcipher.geniv = "eseqiv";
2519                 break;
2520         case CRYPTO_ALG_TYPE_AEAD:
2521                 alg = &t_alg->algt.alg.crypto;
2522                 alg->cra_init = talitos_cra_init_aead;
2523                 alg->cra_type = &crypto_aead_type;
2524                 alg->cra_aead.setkey = aead_setkey;
2525                 alg->cra_aead.setauthsize = aead_setauthsize;
2526                 alg->cra_aead.encrypt = aead_encrypt;
2527                 alg->cra_aead.decrypt = aead_decrypt;
2528                 alg->cra_aead.givencrypt = aead_givencrypt;
2529                 alg->cra_aead.geniv = "<built-in>";
2530                 break;
2531         case CRYPTO_ALG_TYPE_AHASH:
2532                 alg = &t_alg->algt.alg.hash.halg.base;
2533                 alg->cra_init = talitos_cra_init_ahash;
2534                 alg->cra_type = &crypto_ahash_type;
2535                 t_alg->algt.alg.hash.init = ahash_init;
2536                 t_alg->algt.alg.hash.update = ahash_update;
2537                 t_alg->algt.alg.hash.final = ahash_final;
2538                 t_alg->algt.alg.hash.finup = ahash_finup;
2539                 t_alg->algt.alg.hash.digest = ahash_digest;
2540                 t_alg->algt.alg.hash.setkey = ahash_setkey;
2541
2542                 if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
2543                     !strncmp(alg->cra_name, "hmac", 4)) {
2544                         kfree(t_alg);
2545                         return ERR_PTR(-ENOTSUPP);
2546                 }
2547                 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
2548                     (!strcmp(alg->cra_name, "sha224") ||
2549                      !strcmp(alg->cra_name, "hmac(sha224)"))) {
2550                         t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
2551                         t_alg->algt.desc_hdr_template =
2552                                         DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2553                                         DESC_HDR_SEL0_MDEUA |
2554                                         DESC_HDR_MODE0_MDEU_SHA256;
2555                 }
2556                 break;
2557         default:
2558                 dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
2559                 return ERR_PTR(-EINVAL);
2560         }
2561
2562         alg->cra_module = THIS_MODULE;
2563         alg->cra_priority = TALITOS_CRA_PRIORITY;
2564         alg->cra_alignmask = 0;
2565         alg->cra_ctxsize = sizeof(struct talitos_ctx);
2566         alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
2567
2568         t_alg->dev = dev;
2569
2570         return t_alg;
2571 }
2572
2573 static int talitos_probe_irq(struct platform_device *ofdev)
2574 {
2575         struct device *dev = &ofdev->dev;
2576         struct device_node *np = ofdev->dev.of_node;
2577         struct talitos_private *priv = dev_get_drvdata(dev);
2578         int err;
2579
2580         priv->irq[0] = irq_of_parse_and_map(np, 0);
2581         if (!priv->irq[0]) {
2582                 dev_err(dev, "failed to map irq\n");
2583                 return -EINVAL;
2584         }
2585
2586         priv->irq[1] = irq_of_parse_and_map(np, 1);
2587
2588         /* get the primary irq line */
2589         if (!priv->irq[1]) {
2590                 err = request_irq(priv->irq[0], talitos_interrupt_4ch, 0,
2591                                   dev_driver_string(dev), dev);
2592                 goto primary_out;
2593         }
2594
2595         err = request_irq(priv->irq[0], talitos_interrupt_ch0_2, 0,
2596                           dev_driver_string(dev), dev);
2597         if (err)
2598                 goto primary_out;
2599
2600         /* get the secondary irq line */
2601         err = request_irq(priv->irq[1], talitos_interrupt_ch1_3, 0,
2602                           dev_driver_string(dev), dev);
2603         if (err) {
2604                 dev_err(dev, "failed to request secondary irq\n");
2605                 irq_dispose_mapping(priv->irq[1]);
2606                 priv->irq[1] = 0;
2607         }
2608
2609         return err;
2610
2611 primary_out:
2612         if (err) {
2613                 dev_err(dev, "failed to request primary irq\n");
2614                 irq_dispose_mapping(priv->irq[0]);
2615                 priv->irq[0] = 0;
2616         }
2617
2618         return err;
2619 }
2620
2621 static int talitos_probe(struct platform_device *ofdev)
2622 {
2623         struct device *dev = &ofdev->dev;
2624         struct device_node *np = ofdev->dev.of_node;
2625         struct talitos_private *priv;
2626         const unsigned int *prop;
2627         int i, err;
2628
2629         priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
2630         if (!priv)
2631                 return -ENOMEM;
2632
2633         dev_set_drvdata(dev, priv);
2634
2635         priv->ofdev = ofdev;
2636
2637         spin_lock_init(&priv->reg_lock);
2638
2639         err = talitos_probe_irq(ofdev);
2640         if (err)
2641                 goto err_out;
2642
2643         if (!priv->irq[1]) {
2644                 tasklet_init(&priv->done_task[0], talitos_done_4ch,
2645                              (unsigned long)dev);
2646         } else {
2647                 tasklet_init(&priv->done_task[0], talitos_done_ch0_2,
2648                              (unsigned long)dev);
2649                 tasklet_init(&priv->done_task[1], talitos_done_ch1_3,
2650                              (unsigned long)dev);
2651         }
2652
2653         INIT_LIST_HEAD(&priv->alg_list);
2654
2655         priv->reg = of_iomap(np, 0);
2656         if (!priv->reg) {
2657                 dev_err(dev, "failed to of_iomap\n");
2658                 err = -ENOMEM;
2659                 goto err_out;
2660         }
2661
2662         /* get SEC version capabilities from device tree */
2663         prop = of_get_property(np, "fsl,num-channels", NULL);
2664         if (prop)
2665                 priv->num_channels = *prop;
2666
2667         prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
2668         if (prop)
2669                 priv->chfifo_len = *prop;
2670
2671         prop = of_get_property(np, "fsl,exec-units-mask", NULL);
2672         if (prop)
2673                 priv->exec_units = *prop;
2674
2675         prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
2676         if (prop)
2677                 priv->desc_types = *prop;
2678
2679         if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
2680             !priv->exec_units || !priv->desc_types) {
2681                 dev_err(dev, "invalid property data in device tree node\n");
2682                 err = -EINVAL;
2683                 goto err_out;
2684         }
2685
2686         if (of_device_is_compatible(np, "fsl,sec3.0"))
2687                 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
2688
2689         if (of_device_is_compatible(np, "fsl,sec2.1"))
2690                 priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
2691                                   TALITOS_FTR_SHA224_HWINIT |
2692                                   TALITOS_FTR_HMAC_OK;
2693
2694         priv->chan = kzalloc(sizeof(struct talitos_channel) *
2695                              priv->num_channels, GFP_KERNEL);
2696         if (!priv->chan) {
2697                 dev_err(dev, "failed to allocate channel management space\n");
2698                 err = -ENOMEM;
2699                 goto err_out;
2700         }
2701
2702         for (i = 0; i < priv->num_channels; i++) {
2703                 priv->chan[i].reg = priv->reg + TALITOS_CH_STRIDE * (i + 1);
2704                 if (!priv->irq[1] || !(i & 1))
2705                         priv->chan[i].reg += TALITOS_CH_BASE_OFFSET;
2706         }
2707
2708         for (i = 0; i < priv->num_channels; i++) {
2709                 spin_lock_init(&priv->chan[i].head_lock);
2710                 spin_lock_init(&priv->chan[i].tail_lock);
2711         }
2712
2713         priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2714
2715         for (i = 0; i < priv->num_channels; i++) {
2716                 priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
2717                                              priv->fifo_len, GFP_KERNEL);
2718                 if (!priv->chan[i].fifo) {
2719                         dev_err(dev, "failed to allocate request fifo %d\n", i);
2720                         err = -ENOMEM;
2721                         goto err_out;
2722                 }
2723         }
2724
2725         for (i = 0; i < priv->num_channels; i++)
2726                 atomic_set(&priv->chan[i].submit_count,
2727                            -(priv->chfifo_len - 1));
2728
2729         dma_set_mask(dev, DMA_BIT_MASK(36));
2730
2731         /* reset and initialize the h/w */
2732         err = init_device(dev);
2733         if (err) {
2734                 dev_err(dev, "failed to initialize device\n");
2735                 goto err_out;
2736         }
2737
2738         /* register the RNG, if available */
2739         if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
2740                 err = talitos_register_rng(dev);
2741                 if (err) {
2742                         dev_err(dev, "failed to register hwrng: %d\n", err);
2743                         goto err_out;
2744                 } else
2745                         dev_info(dev, "hwrng\n");
2746         }
2747
2748         /* register crypto algorithms the device supports */
2749         for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2750                 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
2751                         struct talitos_crypto_alg *t_alg;
2752                         char *name = NULL;
2753
2754                         t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
2755                         if (IS_ERR(t_alg)) {
2756                                 err = PTR_ERR(t_alg);
2757                                 if (err == -ENOTSUPP)
2758                                         continue;
2759                                 goto err_out;
2760                         }
2761
2762                         switch (t_alg->algt.type) {
2763                         case CRYPTO_ALG_TYPE_ABLKCIPHER:
2764                         case CRYPTO_ALG_TYPE_AEAD:
2765                                 err = crypto_register_alg(
2766                                                 &t_alg->algt.alg.crypto);
2767                                 name = t_alg->algt.alg.crypto.cra_driver_name;
2768                                 break;
2769                         case CRYPTO_ALG_TYPE_AHASH:
2770                                 err = crypto_register_ahash(
2771                                                 &t_alg->algt.alg.hash);
2772                                 name =
2773                                  t_alg->algt.alg.hash.halg.base.cra_driver_name;
2774                                 break;
2775                         }
2776                         if (err) {
2777                                 dev_err(dev, "%s alg registration failed\n",
2778                                         name);
2779                                 kfree(t_alg);
2780                         } else
2781                                 list_add_tail(&t_alg->entry, &priv->alg_list);
2782                 }
2783         }
2784         if (!list_empty(&priv->alg_list))
2785                 dev_info(dev, "%s algorithms registered in /proc/crypto\n",
2786                          (char *)of_get_property(np, "compatible", NULL));
2787
2788         return 0;
2789
2790 err_out:
2791         talitos_remove(ofdev);
2792
2793         return err;
2794 }
2795
2796 static const struct of_device_id talitos_match[] = {
2797         {
2798                 .compatible = "fsl,sec2.0",
2799         },
2800         {},
2801 };
2802 MODULE_DEVICE_TABLE(of, talitos_match);
2803
2804 static struct platform_driver talitos_driver = {
2805         .driver = {
2806                 .name = "talitos",
2807                 .owner = THIS_MODULE,
2808                 .of_match_table = talitos_match,
2809         },
2810         .probe = talitos_probe,
2811         .remove = talitos_remove,
2812 };
2813
2814 module_platform_driver(talitos_driver);
2815
2816 MODULE_LICENSE("GPL");
2817 MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2818 MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");