drivers/crypto/nx/nx-sha512.c

   1 /**
   2  * SHA-512 routines supporting the Power 7+ Nest Accelerators driver
   3  *
   4  * Copyright (C) 2011-2012 International Business Machines Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 only.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  *
  19  * Author: Kent Yoder <yoder1@us.ibm.com>
  20  */
  21
  22 #include <crypto/internal/hash.h>
  23 #include <crypto/sha.h>
  24 #include <linux/module.h>
  25 #include <asm/vio.h>
  26
  27 #include "nx_csbcpb.h"
  28 #include "nx.h"
  29
  30
  31 static int nx_crypto_ctx_sha512_init(struct crypto_tfm *tfm)
  32 {
  33         struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(tfm);
  34         int err;
  35
  36         err = nx_crypto_ctx_sha_init(tfm);
  37         if (err)
  38                 return err;
  39
  40         nx_ctx_init(nx_ctx, HCOP_FC_SHA);
  41
  42         nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA512];
  43
  44         NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA512);
  45
  46         return 0;
  47 }
  48
  49 static int nx_sha512_init(struct shash_desc *desc)
  50 {
  51         struct sha512_state *sctx = shash_desc_ctx(desc);
  52
  53         memset(sctx, 0, sizeof *sctx);
  54
  55         sctx->state[0] = __cpu_to_be64(SHA512_H0);
  56         sctx->state[1] = __cpu_to_be64(SHA512_H1);
  57         sctx->state[2] = __cpu_to_be64(SHA512_H2);
  58         sctx->state[3] = __cpu_to_be64(SHA512_H3);
  59         sctx->state[4] = __cpu_to_be64(SHA512_H4);
  60         sctx->state[5] = __cpu_to_be64(SHA512_H5);
  61         sctx->state[6] = __cpu_to_be64(SHA512_H6);
  62         sctx->state[7] = __cpu_to_be64(SHA512_H7);
  63         sctx->count[0] = 0;
  64
  65         return 0;
  66 }
  67
  68 static int nx_sha512_update(struct shash_desc *desc, const u8 *data,
  69                             unsigned int len)
  70 {
  71         struct sha512_state *sctx = shash_desc_ctx(desc);
  72         struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
  73         struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
  74         struct nx_sg *in_sg;
  75         struct nx_sg *out_sg;
  76         u64 to_process, leftover = 0, total;
  77         unsigned long irq_flags;
  78         int rc = 0;
  79         int data_len;
  80         u32 max_sg_len;
  81         u64 buf_len = (sctx->count[0] % SHA512_BLOCK_SIZE);
  82
  83         spin_lock_irqsave(&nx_ctx->lock, irq_flags);
  84
  85         /* 2 cases for total data len:
  86          *  1: < SHA512_BLOCK_SIZE: copy into state, return 0
  87          *  2: >= SHA512_BLOCK_SIZE: process X blocks, copy in leftover
  88          */
  89         total = (sctx->count[0] % SHA512_BLOCK_SIZE) + len;
  90         if (total < SHA512_BLOCK_SIZE) {
  91                 memcpy(sctx->buf + buf_len, data, len);
  92                 sctx->count[0] += len;
  93                 goto out;
  94         }
  95
  96         memcpy(csbcpb->cpb.sha512.message_digest, sctx->state, SHA512_DIGEST_SIZE);
  97         NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE;
  98         NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
  99
 100         in_sg = nx_ctx->in_sg;
 101         max_sg_len = min_t(u64, nx_ctx->ap->sglen,
 102                         nx_driver.of.max_sg_len/sizeof(struct nx_sg));
 103         max_sg_len = min_t(u64, max_sg_len,
 104                         nx_ctx->ap->databytelen/NX_PAGE_SIZE);
 105
 106         data_len = SHA512_DIGEST_SIZE;
 107         out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state,
 108                                   &data_len, max_sg_len);
 109         nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
 110
 111         if (data_len != SHA512_DIGEST_SIZE) {
 112                 rc = -EINVAL;
 113                 goto out;
 114         }
 115
 116         do {
 117                 /*
 118                  * to_process: the SHA512_BLOCK_SIZE data chunk to process in
 119                  * this update. This value is also restricted by the sg list
 120                  * limits.
 121                  */
 122                 to_process = total - leftover;
 123                 to_process = to_process & ~(SHA512_BLOCK_SIZE - 1);
 124                 leftover = total - to_process;
 125
 126                 if (buf_len) {
 127                         data_len = buf_len;
 128                         in_sg = nx_build_sg_list(nx_ctx->in_sg,
 129                                                  (u8 *) sctx->buf,
 130                                                  &data_len, max_sg_len);
 131
 132                         if (data_len != buf_len) {
 133                                 rc = -EINVAL;
 134                                 goto out;
 135                         }
 136                 }
 137
 138                 data_len = to_process - buf_len;
 139                 in_sg = nx_build_sg_list(in_sg, (u8 *) data,
 140                                          &data_len, max_sg_len);
 141
 142                 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
 143
 144                 if (data_len != (to_process - buf_len)) {
 145                         rc = -EINVAL;
 146                         goto out;
 147                 }
 148
 149                 to_process = (data_len + buf_len);
 150                 leftover = total - to_process;
 151
 152                 /*
 153                  * we've hit the nx chip previously and we're updating
 154                  * again, so copy over the partial digest.
 155                  */
 156                 memcpy(csbcpb->cpb.sha512.input_partial_digest,
 157                                csbcpb->cpb.sha512.message_digest,
 158                                SHA512_DIGEST_SIZE);
 159
 160                 if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) {
 161                         rc = -EINVAL;
 162                         goto out;
 163                 }
 164
 165                 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
 166                                    desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
 167                 if (rc)
 168                         goto out;
 169
 170                 atomic_inc(&(nx_ctx->stats->sha512_ops));
 171
 172                 total -= to_process;
 173                 data += to_process - buf_len;
 174                 buf_len = 0;
 175
 176         } while (leftover >= SHA512_BLOCK_SIZE);
 177
 178         /* copy the leftover back into the state struct */
 179         if (leftover)
 180                 memcpy(sctx->buf, data, leftover);
 181         sctx->count[0] += len;
 182         memcpy(sctx->state, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
 183 out:
 184         spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
 185         return rc;
 186 }
 187
 188 static int nx_sha512_final(struct shash_desc *desc, u8 *out)
 189 {
 190         struct sha512_state *sctx = shash_desc_ctx(desc);
 191         struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
 192         struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
 193         struct nx_sg *in_sg, *out_sg;
 194         u32 max_sg_len;
 195         u64 count0;
 196         unsigned long irq_flags;
 197         int rc = 0;
 198         int len;
 199
 200         spin_lock_irqsave(&nx_ctx->lock, irq_flags);
 201
 202         max_sg_len = min_t(u64, nx_ctx->ap->sglen,
 203                         nx_driver.of.max_sg_len/sizeof(struct nx_sg));
 204         max_sg_len = min_t(u64, max_sg_len,
 205                         nx_ctx->ap->databytelen/NX_PAGE_SIZE);
 206
 207         /* final is represented by continuing the operation and indicating that
 208          * this is not an intermediate operation */
 209         if (sctx->count[0] >= SHA512_BLOCK_SIZE) {
 210                 /* we've hit the nx chip previously, now we're finalizing,
 211                  * so copy over the partial digest */
 212                 memcpy(csbcpb->cpb.sha512.input_partial_digest, sctx->state,
 213                                                         SHA512_DIGEST_SIZE);
 214                 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
 215                 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
 216         } else {
 217                 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
 218                 NX_CPB_FDM(csbcpb) &= ~NX_FDM_CONTINUATION;
 219         }
 220
 221         NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
 222
 223         count0 = sctx->count[0] * 8;
 224
 225         csbcpb->cpb.sha512.message_bit_length_lo = count0;
 226
 227         len = sctx->count[0] & (SHA512_BLOCK_SIZE - 1);
 228         in_sg = nx_build_sg_list(nx_ctx->in_sg, sctx->buf, &len,
 229                                  max_sg_len);
 230
 231         if (len != (sctx->count[0] & (SHA512_BLOCK_SIZE - 1))) {
 232                 rc = -EINVAL;
 233                 goto out;
 234         }
 235
 236         len = SHA512_DIGEST_SIZE;
 237         out_sg = nx_build_sg_list(nx_ctx->out_sg, out, &len,
 238                                  max_sg_len);
 239
 240         nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
 241         nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
 242
 243         if (!nx_ctx->op.outlen) {
 244                 rc = -EINVAL;
 245                 goto out;
 246         }
 247
 248         rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
 249                            desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
 250         if (rc)
 251                 goto out;
 252
 253         atomic_inc(&(nx_ctx->stats->sha512_ops));
 254         atomic64_add(sctx->count[0], &(nx_ctx->stats->sha512_bytes));
 255
 256         memcpy(out, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
 257 out:
 258         spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
 259         return rc;
 260 }
 261
 262 static int nx_sha512_export(struct shash_desc *desc, void *out)
 263 {
 264         struct sha512_state *sctx = shash_desc_ctx(desc);
 265
 266         memcpy(out, sctx, sizeof(*sctx));
 267
 268         return 0;
 269 }
 270
 271 static int nx_sha512_import(struct shash_desc *desc, const void *in)
 272 {
 273         struct sha512_state *sctx = shash_desc_ctx(desc);
 274
 275         memcpy(sctx, in, sizeof(*sctx));
 276
 277         return 0;
 278 }
 279
 280 struct shash_alg nx_shash_sha512_alg = {
 281         .digestsize = SHA512_DIGEST_SIZE,
 282         .init       = nx_sha512_init,
 283         .update     = nx_sha512_update,
 284         .final      = nx_sha512_final,
 285         .export     = nx_sha512_export,
 286         .import     = nx_sha512_import,
 287         .descsize   = sizeof(struct sha512_state),
 288         .statesize  = sizeof(struct sha512_state),
 289         .base       = {
 290                 .cra_name        = "sha512",
 291                 .cra_driver_name = "sha512-nx",
 292                 .cra_priority    = 300,
 293                 .cra_flags       = CRYPTO_ALG_TYPE_SHASH,
 294                 .cra_blocksize   = SHA512_BLOCK_SIZE,
 295                 .cra_module      = THIS_MODULE,
 296                 .cra_ctxsize     = sizeof(struct nx_crypto_ctx),
 297                 .cra_init        = nx_crypto_ctx_sha512_init,
 298                 .cra_exit        = nx_crypto_ctx_exit,
 299         }
 300 };