drivers/char/agp/sis-agp.c

   1 /*
   2  * SiS AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/agp_backend.h>
   9 #include <linux/delay.h>
  10 #include "agp.h"
  11
  12 #define SIS_ATTBASE     0x90
  13 #define SIS_APSIZE      0x94
  14 #define SIS_TLBCNTRL    0x97
  15 #define SIS_TLBFLUSH    0x98
  16
  17 static int __devinitdata agp_sis_force_delay = 0;
  18 static int __devinitdata agp_sis_agp_spec = -1;
  19
  20 static int sis_fetch_size(void)
  21 {
  22         u8 temp_size;
  23         int i;
  24         struct aper_size_info_8 *values;
  25
  26         pci_read_config_byte(agp_bridge->dev, SIS_APSIZE, &temp_size);
  27         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
  28         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
  29                 if ((temp_size == values[i].size_value) ||
  30                     ((temp_size & ~(0x03)) ==
  31                      (values[i].size_value & ~(0x03)))) {
  32                         agp_bridge->previous_size =
  33                             agp_bridge->current_size = (void *) (values + i);
  34
  35                         agp_bridge->aperture_size_idx = i;
  36                         return values[i].size;
  37                 }
  38         }
  39
  40         return 0;
  41 }
  42
  43 static void sis_tlbflush(struct agp_memory *mem)
  44 {
  45         pci_write_config_byte(agp_bridge->dev, SIS_TLBFLUSH, 0x02);
  46 }
  47
  48 static int sis_configure(void)
  49 {
  50         u32 temp;
  51         struct aper_size_info_8 *current_size;
  52
  53         current_size = A_SIZE_8(agp_bridge->current_size);
  54         pci_write_config_byte(agp_bridge->dev, SIS_TLBCNTRL, 0x05);
  55         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
  56         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
  57         pci_write_config_dword(agp_bridge->dev, SIS_ATTBASE,
  58                                agp_bridge->gatt_bus_addr);
  59         pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
  60                               current_size->size_value);
  61         return 0;
  62 }
  63
  64 static void sis_cleanup(void)
  65 {
  66         struct aper_size_info_8 *previous_size;
  67
  68         previous_size = A_SIZE_8(agp_bridge->previous_size);
  69         pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
  70                               (previous_size->size_value & ~(0x03)));
  71 }
  72
  73 static void sis_delayed_enable(struct agp_bridge_data *bridge, u32 mode)
  74 {
  75         struct pci_dev *device = NULL;
  76         u32 command;
  77         int rate;
  78
  79         printk(KERN_INFO PFX "Found an AGP %d.%d compliant device at %s.\n",
  80                 agp_bridge->major_version,
  81                 agp_bridge->minor_version,
  82                 pci_name(agp_bridge->dev));
  83
  84         pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + PCI_AGP_STATUS, &command);
  85         command = agp_collect_device_status(bridge, mode, command);
  86         command |= AGPSTAT_AGP_ENABLE;
  87         rate = (command & 0x7) << 2;
  88
  89         for_each_pci_dev(device) {
  90                 u8 agp = pci_find_capability(device, PCI_CAP_ID_AGP);
  91                 if (!agp)
  92                         continue;
  93
  94                 printk(KERN_INFO PFX "Putting AGP V3 device at %s into %dx mode\n",
  95                         pci_name(device), rate);
  96
  97                 pci_write_config_dword(device, agp + PCI_AGP_COMMAND, command);
  98
  99                 /*
 100                  * Weird: on some sis chipsets any rate change in the target
 101                  * command register triggers a 5ms screwup during which the master
 102                  * cannot be configured
 103                  */
 104                 if (device->device == bridge->dev->device) {
 105                         printk(KERN_INFO PFX "SiS delay workaround: giving bridge time to recover.\n");
 106                         msleep(10);
 107                 }
 108         }
 109 }
 110
 111 static struct aper_size_info_8 sis_generic_sizes[7] =
 112 {
 113         {256, 65536, 6, 99},
 114         {128, 32768, 5, 83},
 115         {64, 16384, 4, 67},
 116         {32, 8192, 3, 51},
 117         {16, 4096, 2, 35},
 118         {8, 2048, 1, 19},
 119         {4, 1024, 0, 3}
 120 };
 121
 122 static struct agp_bridge_driver sis_driver = {
 123         .owner                  = THIS_MODULE,
 124         .aperture_sizes         = sis_generic_sizes,
 125         .size_type              = U8_APER_SIZE,
 126         .num_aperture_sizes     = 7,
 127         .configure              = sis_configure,
 128         .fetch_size             = sis_fetch_size,
 129         .cleanup                = sis_cleanup,
 130         .tlb_flush              = sis_tlbflush,
 131         .mask_memory            = agp_generic_mask_memory,
 132         .masks                  = NULL,
 133         .agp_enable             = agp_generic_enable,
 134         .cache_flush            = global_cache_flush,
 135         .create_gatt_table      = agp_generic_create_gatt_table,
 136         .free_gatt_table        = agp_generic_free_gatt_table,
 137         .insert_memory          = agp_generic_insert_memory,
 138         .remove_memory          = agp_generic_remove_memory,
 139         .alloc_by_type          = agp_generic_alloc_by_type,
 140         .free_by_type           = agp_generic_free_by_type,
 141         .agp_alloc_page         = agp_generic_alloc_page,
 142         .agp_destroy_page       = agp_generic_destroy_page,
 143         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
 144 };
 145
 146 static struct agp_device_ids sis_agp_device_ids[] __devinitdata =
 147 {
 148         {
 149                 .device_id      = PCI_DEVICE_ID_SI_5591_AGP,
 150                 .chipset_name   = "5591",
 151         },
 152         {
 153                 .device_id      = PCI_DEVICE_ID_SI_530,
 154                 .chipset_name   = "530",
 155         },
 156         {
 157                 .device_id      = PCI_DEVICE_ID_SI_540,
 158                 .chipset_name   = "540",
 159         },
 160         {
 161                 .device_id      = PCI_DEVICE_ID_SI_550,
 162                 .chipset_name   = "550",
 163         },
 164         {
 165                 .device_id      = PCI_DEVICE_ID_SI_620,
 166                 .chipset_name   = "620",
 167         },
 168         {
 169                 .device_id      = PCI_DEVICE_ID_SI_630,
 170                 .chipset_name   = "630",
 171         },
 172         {
 173                 .device_id      = PCI_DEVICE_ID_SI_635,
 174                 .chipset_name   = "635",
 175         },
 176         {
 177                 .device_id      = PCI_DEVICE_ID_SI_645,
 178                 .chipset_name   = "645",
 179         },
 180         {
 181                 .device_id      = PCI_DEVICE_ID_SI_646,
 182                 .chipset_name   = "646",
 183         },
 184         {
 185                 .device_id      = PCI_DEVICE_ID_SI_648,
 186                 .chipset_name   = "648",
 187         },
 188         {
 189                 .device_id      = PCI_DEVICE_ID_SI_650,
 190                 .chipset_name   = "650",
 191         },
 192         {
 193                 .device_id  = PCI_DEVICE_ID_SI_651,
 194                 .chipset_name   = "651",
 195         },
 196         {
 197                 .device_id      = PCI_DEVICE_ID_SI_655,
 198                 .chipset_name   = "655",
 199         },
 200         {
 201                 .device_id      = PCI_DEVICE_ID_SI_661,
 202                 .chipset_name   = "661",
 203         },
 204         {
 205                 .device_id      = PCI_DEVICE_ID_SI_730,
 206                 .chipset_name   = "730",
 207         },
 208         {
 209                 .device_id      = PCI_DEVICE_ID_SI_735,
 210                 .chipset_name   = "735",
 211         },
 212         {
 213                 .device_id      = PCI_DEVICE_ID_SI_740,
 214                 .chipset_name   = "740",
 215         },
 216         {
 217                 .device_id      = PCI_DEVICE_ID_SI_741,
 218                 .chipset_name   = "741",
 219         },
 220         {
 221                 .device_id      = PCI_DEVICE_ID_SI_745,
 222                 .chipset_name   = "745",
 223         },
 224         {
 225                 .device_id      = PCI_DEVICE_ID_SI_746,
 226                 .chipset_name   = "746",
 227         },
 228         {
 229                 .device_id      = PCI_DEVICE_ID_SI_760,
 230                 .chipset_name   = "760",
 231         },
 232         { }, /* dummy final entry, always present */
 233 };
 234
 235
 236 // chipsets that require the 'delay hack'
 237 static int sis_broken_chipsets[] __devinitdata = {
 238         PCI_DEVICE_ID_SI_648,
 239         PCI_DEVICE_ID_SI_746,
 240         0 // terminator
 241 };
 242
 243 static void __devinit sis_get_driver(struct agp_bridge_data *bridge)
 244 {
 245         int i;
 246
 247         for (i=0; sis_broken_chipsets[i]!=0; ++i)
 248                 if (bridge->dev->device==sis_broken_chipsets[i])
 249                         break;
 250
 251         if (sis_broken_chipsets[i] || agp_sis_force_delay)
 252                 sis_driver.agp_enable=sis_delayed_enable;
 253
 254         // sis chipsets that indicate less than agp3.5
 255         // are not actually fully agp3 compliant
 256         if ((agp_bridge->major_version == 3 && agp_bridge->minor_version >= 5
 257              && agp_sis_agp_spec!=0) || agp_sis_agp_spec==1) {
 258                 sis_driver.aperture_sizes = agp3_generic_sizes;
 259                 sis_driver.size_type = U16_APER_SIZE;
 260                 sis_driver.num_aperture_sizes = AGP_GENERIC_SIZES_ENTRIES;
 261                 sis_driver.configure = agp3_generic_configure;
 262                 sis_driver.fetch_size = agp3_generic_fetch_size;
 263                 sis_driver.cleanup = agp3_generic_cleanup;
 264                 sis_driver.tlb_flush = agp3_generic_tlbflush;
 265         }
 266 }
 267
 268
 269 static int __devinit agp_sis_probe(struct pci_dev *pdev,
 270                                    const struct pci_device_id *ent)
 271 {
 272         struct agp_device_ids *devs = sis_agp_device_ids;
 273         struct agp_bridge_data *bridge;
 274         u8 cap_ptr;
 275         int j;
 276
 277         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
 278         if (!cap_ptr)
 279                 return -ENODEV;
 280
 281         /* probe for known chipsets */
 282         for (j = 0; devs[j].chipset_name; j++) {
 283                 if (pdev->device == devs[j].device_id) {
 284                         printk(KERN_INFO PFX "Detected SiS %s chipset\n",
 285                                         devs[j].chipset_name);
 286                         goto found;
 287                 }
 288         }
 289
 290         printk(KERN_ERR PFX "Unsupported SiS chipset (device id: %04x)\n",
 291                     pdev->device);
 292         return -ENODEV;
 293
 294 found:
 295         bridge = agp_alloc_bridge();
 296         if (!bridge)
 297                 return -ENOMEM;
 298
 299         bridge->driver = &sis_driver;
 300         bridge->dev = pdev;
 301         bridge->capndx = cap_ptr;
 302
 303         get_agp_version(bridge);
 304
 305         /* Fill in the mode register */
 306         pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
 307         sis_get_driver(bridge);
 308
 309         pci_set_drvdata(pdev, bridge);
 310         return agp_add_bridge(bridge);
 311 }
 312
 313 static void __devexit agp_sis_remove(struct pci_dev *pdev)
 314 {
 315         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
 316
 317         agp_remove_bridge(bridge);
 318         agp_put_bridge(bridge);
 319 }
 320
 321 static struct pci_device_id agp_sis_pci_table[] = {
 322         {
 323         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 324         .class_mask     = ~0,
 325         .vendor         = PCI_VENDOR_ID_SI,
 326         .device         = PCI_ANY_ID,
 327         .subvendor      = PCI_ANY_ID,
 328         .subdevice      = PCI_ANY_ID,
 329         },
 330         { }
 331 };
 332
 333 MODULE_DEVICE_TABLE(pci, agp_sis_pci_table);
 334
 335 static struct pci_driver agp_sis_pci_driver = {
 336         .name           = "agpgart-sis",
 337         .id_table       = agp_sis_pci_table,
 338         .probe          = agp_sis_probe,
 339         .remove         = agp_sis_remove,
 340 };
 341
 342 static int __init agp_sis_init(void)
 343 {
 344         if (agp_off)
 345                 return -EINVAL;
 346         return pci_register_driver(&agp_sis_pci_driver);
 347 }
 348
 349 static void __exit agp_sis_cleanup(void)
 350 {
 351         pci_unregister_driver(&agp_sis_pci_driver);
 352 }
 353
 354 module_init(agp_sis_init);
 355 module_exit(agp_sis_cleanup);
 356
 357 module_param(agp_sis_force_delay, bool, 0);
 358 MODULE_PARM_DESC(agp_sis_force_delay,"forces sis delay hack");
 359 module_param(agp_sis_agp_spec, int, 0);
 360 MODULE_PARM_DESC(agp_sis_agp_spec,"0=force sis init, 1=force generic agp3 init, default: autodetect");
 361 MODULE_LICENSE("GPL and additional rights");