drivers/char/agp/intel-agp.c

   1 /*
   2  * Intel AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/pagemap.h>
   9 #include <linux/agp_backend.h>
  10 #include "agp.h"
  11
  12 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
  13 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
  14 #define PCI_DEVICE_ID_INTEL_82965G_1_HB     0x2980
  15 #define PCI_DEVICE_ID_INTEL_82965G_1_IG     0x2982
  16 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
  17 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
  18 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
  19 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
  20
  21 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
  22                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
  23                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
  24                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB)
  25
  26
  27 /* Intel 815 register */
  28 #define INTEL_815_APCONT        0x51
  29 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
  30
  31 /* Intel i820 registers */
  32 #define INTEL_I820_RDCR         0x51
  33 #define INTEL_I820_ERRSTS       0xc8
  34
  35 /* Intel i840 registers */
  36 #define INTEL_I840_MCHCFG       0x50
  37 #define INTEL_I840_ERRSTS       0xc8
  38
  39 /* Intel i850 registers */
  40 #define INTEL_I850_MCHCFG       0x50
  41 #define INTEL_I850_ERRSTS       0xc8
  42
  43 /* intel 915G registers */
  44 #define I915_GMADDR     0x18
  45 #define I915_MMADDR     0x10
  46 #define I915_PTEADDR    0x1C
  47 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
  48 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
  49
  50 /* Intel 965G registers */
  51 #define I965_MSAC 0x62
  52
  53 /* Intel 7505 registers */
  54 #define INTEL_I7505_APSIZE      0x74
  55 #define INTEL_I7505_NCAPID      0x60
  56 #define INTEL_I7505_NISTAT      0x6c
  57 #define INTEL_I7505_ATTBASE     0x78
  58 #define INTEL_I7505_ERRSTS      0x42
  59 #define INTEL_I7505_AGPCTRL     0x70
  60 #define INTEL_I7505_MCHCFG      0x50
  61
  62 static struct aper_size_info_fixed intel_i810_sizes[] =
  63 {
  64         {64, 16384, 4},
  65         /* The 32M mode still requires a 64k gatt */
  66         {32, 8192, 4}
  67 };
  68
  69 #define AGP_DCACHE_MEMORY       1
  70 #define AGP_PHYS_MEMORY         2
  71
  72 static struct gatt_mask intel_i810_masks[] =
  73 {
  74         {.mask = I810_PTE_VALID, .type = 0},
  75         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
  76         {.mask = I810_PTE_VALID, .type = 0}
  77 };
  78
  79 static struct _intel_i810_private {
  80         struct pci_dev *i810_dev;       /* device one */
  81         volatile u8 __iomem *registers;
  82         int num_dcache_entries;
  83 } intel_i810_private;
  84
  85 static int intel_i810_fetch_size(void)
  86 {
  87         u32 smram_miscc;
  88         struct aper_size_info_fixed *values;
  89
  90         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
  91         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
  92
  93         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
  94                 printk(KERN_WARNING PFX "i810 is disabled\n");
  95                 return 0;
  96         }
  97         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
  98                 agp_bridge->previous_size =
  99                         agp_bridge->current_size = (void *) (values + 1);
 100                 agp_bridge->aperture_size_idx = 1;
 101                 return values[1].size;
 102         } else {
 103                 agp_bridge->previous_size =
 104                         agp_bridge->current_size = (void *) (values);
 105                 agp_bridge->aperture_size_idx = 0;
 106                 return values[0].size;
 107         }
 108
 109         return 0;
 110 }
 111
 112 static int intel_i810_configure(void)
 113 {
 114         struct aper_size_info_fixed *current_size;
 115         u32 temp;
 116         int i;
 117
 118         current_size = A_SIZE_FIX(agp_bridge->current_size);
 119
 120         pci_read_config_dword(intel_i810_private.i810_dev, I810_MMADDR, &temp);
 121         temp &= 0xfff80000;
 122
 123         intel_i810_private.registers = ioremap(temp, 128 * 4096);
 124         if (!intel_i810_private.registers) {
 125                 printk(KERN_ERR PFX "Unable to remap memory.\n");
 126                 return -ENOMEM;
 127         }
 128
 129         if ((readl(intel_i810_private.registers+I810_DRAM_CTL)
 130                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 131                 /* This will need to be dynamically assigned */
 132                 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
 133                 intel_i810_private.num_dcache_entries = 1024;
 134         }
 135         pci_read_config_dword(intel_i810_private.i810_dev, I810_GMADDR, &temp);
 136         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 137         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_i810_private.registers+I810_PGETBL_CTL);
 138         readl(intel_i810_private.registers+I810_PGETBL_CTL);    /* PCI Posting. */
 139
 140         if (agp_bridge->driver->needs_scratch_page) {
 141                 for (i = 0; i < current_size->num_entries; i++) {
 142                         writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4));
 143                         readl(intel_i810_private.registers+I810_PTE_BASE+(i*4));        /* PCI posting. */
 144                 }
 145         }
 146         global_cache_flush();
 147         return 0;
 148 }
 149
 150 static void intel_i810_cleanup(void)
 151 {
 152         writel(0, intel_i810_private.registers+I810_PGETBL_CTL);
 153         readl(intel_i810_private.registers);    /* PCI Posting. */
 154         iounmap(intel_i810_private.registers);
 155 }
 156
 157 static void intel_i810_tlbflush(struct agp_memory *mem)
 158 {
 159         return;
 160 }
 161
 162 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 163 {
 164         return;
 165 }
 166
 167 /* Exists to support ARGB cursors */
 168 static void *i8xx_alloc_pages(void)
 169 {
 170         struct page * page;
 171
 172         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 173         if (page == NULL)
 174                 return NULL;
 175
 176         if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) {
 177                 global_flush_tlb();
 178                 __free_page(page);
 179                 return NULL;
 180         }
 181         global_flush_tlb();
 182         get_page(page);
 183         SetPageLocked(page);
 184         atomic_inc(&agp_bridge->current_memory_agp);
 185         return page_address(page);
 186 }
 187
 188 static void i8xx_destroy_pages(void *addr)
 189 {
 190         struct page *page;
 191
 192         if (addr == NULL)
 193                 return;
 194
 195         page = virt_to_page(addr);
 196         change_page_attr(page, 4, PAGE_KERNEL);
 197         global_flush_tlb();
 198         put_page(page);
 199         unlock_page(page);
 200         free_pages((unsigned long)addr, 2);
 201         atomic_dec(&agp_bridge->current_memory_agp);
 202 }
 203
 204 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 205                                 int type)
 206 {
 207         int i, j, num_entries;
 208         void *temp;
 209
 210         temp = agp_bridge->current_size;
 211         num_entries = A_SIZE_FIX(temp)->num_entries;
 212
 213         if ((pg_start + mem->page_count) > num_entries)
 214                 return -EINVAL;
 215
 216         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 217                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
 218                         return -EBUSY;
 219         }
 220
 221         if (type != 0 || mem->type != 0) {
 222                 if ((type == AGP_DCACHE_MEMORY) && (mem->type == AGP_DCACHE_MEMORY)) {
 223                         /* special insert */
 224                         global_cache_flush();
 225                         for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 226                                 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, intel_i810_private.registers+I810_PTE_BASE+(i*4));
 227                                 readl(intel_i810_private.registers+I810_PTE_BASE+(i*4));        /* PCI Posting. */
 228                         }
 229                         global_cache_flush();
 230                         agp_bridge->driver->tlb_flush(mem);
 231                         return 0;
 232                 }
 233                 if ((type == AGP_PHYS_MEMORY) && (mem->type == AGP_PHYS_MEMORY))
 234                         goto insert;
 235                 return -EINVAL;
 236         }
 237
 238 insert:
 239         global_cache_flush();
 240         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 241                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 242                         mem->memory[i], mem->type),
 243                         intel_i810_private.registers+I810_PTE_BASE+(j*4));
 244                 readl(intel_i810_private.registers+I810_PTE_BASE+(j*4));        /* PCI Posting. */
 245         }
 246         global_cache_flush();
 247
 248         agp_bridge->driver->tlb_flush(mem);
 249         return 0;
 250 }
 251
 252 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 253                                 int type)
 254 {
 255         int i;
 256
 257         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 258                 writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4));
 259                 readl(intel_i810_private.registers+I810_PTE_BASE+(i*4));        /* PCI Posting. */
 260         }
 261
 262         global_cache_flush();
 263         agp_bridge->driver->tlb_flush(mem);
 264         return 0;
 265 }
 266
 267 /*
 268  * The i810/i830 requires a physical address to program its mouse
 269  * pointer into hardware.
 270  * However the Xserver still writes to it through the agp aperture.
 271  */
 272 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 273 {
 274         struct agp_memory *new;
 275         void *addr;
 276
 277         if (pg_count != 1 && pg_count != 4)
 278                 return NULL;
 279
 280         switch (pg_count) {
 281         case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
 282                 global_flush_tlb();
 283                 break;
 284         case 4:
 285                 /* kludge to get 4 physical pages for ARGB cursor */
 286                 addr = i8xx_alloc_pages();
 287                 break;
 288         default:
 289                 return NULL;
 290         }
 291
 292         if (addr == NULL)
 293                 return NULL;
 294
 295         new = agp_create_memory(pg_count);
 296         if (new == NULL)
 297                 return NULL;
 298
 299         new->memory[0] = virt_to_gart(addr);
 300         if (pg_count == 4) {
 301                 /* kludge to get 4 physical pages for ARGB cursor */
 302                 new->memory[1] = new->memory[0] + PAGE_SIZE;
 303                 new->memory[2] = new->memory[1] + PAGE_SIZE;
 304                 new->memory[3] = new->memory[2] + PAGE_SIZE;
 305         }
 306         new->page_count = pg_count;
 307         new->num_scratch_pages = pg_count;
 308         new->type = AGP_PHYS_MEMORY;
 309         new->physical = new->memory[0];
 310         return new;
 311 }
 312
 313 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 314 {
 315         struct agp_memory *new;
 316
 317         if (type == AGP_DCACHE_MEMORY) {
 318                 if (pg_count != intel_i810_private.num_dcache_entries)
 319                         return NULL;
 320
 321                 new = agp_create_memory(1);
 322                 if (new == NULL)
 323                         return NULL;
 324
 325                 new->type = AGP_DCACHE_MEMORY;
 326                 new->page_count = pg_count;
 327                 new->num_scratch_pages = 0;
 328                 vfree(new->memory);
 329                 return new;
 330         }
 331         if (type == AGP_PHYS_MEMORY)
 332                 return alloc_agpphysmem_i8xx(pg_count, type);
 333
 334         return NULL;
 335 }
 336
 337 static void intel_i810_free_by_type(struct agp_memory *curr)
 338 {
 339         agp_free_key(curr->key);
 340         if (curr->type == AGP_PHYS_MEMORY) {
 341                 if (curr->page_count == 4)
 342                         i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
 343                 else {
 344                         agp_bridge->driver->agp_destroy_page(
 345                                  gart_to_virt(curr->memory[0]));
 346                         global_flush_tlb();
 347                 }
 348                 vfree(curr->memory);
 349         }
 350         kfree(curr);
 351 }
 352
 353 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 354         unsigned long addr, int type)
 355 {
 356         /* Type checking must be done elsewhere */
 357         return addr | bridge->driver->masks[type].mask;
 358 }
 359
 360 static struct aper_size_info_fixed intel_i830_sizes[] =
 361 {
 362         {128, 32768, 5},
 363         /* The 64M mode still requires a 128k gatt */
 364         {64, 16384, 5},
 365         {256, 65536, 6},
 366         {512, 131072, 7},
 367 };
 368
 369 static struct _intel_i830_private {
 370         struct pci_dev *i830_dev;               /* device one */
 371         volatile u8 __iomem *registers;
 372         volatile u32 __iomem *gtt;              /* I915G */
 373         int gtt_entries;
 374 } intel_i830_private;
 375
 376 static void intel_i830_init_gtt_entries(void)
 377 {
 378         u16 gmch_ctrl;
 379         int gtt_entries;
 380         u8 rdct;
 381         int local = 0;
 382         static const int ddt[4] = { 0, 16, 32, 64 };
 383         int size;
 384
 385         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 386
 387         /* We obtain the size of the GTT, which is also stored (for some
 388          * reason) at the top of stolen memory. Then we add 4KB to that
 389          * for the video BIOS popup, which is also stored in there. */
 390         size = agp_bridge->driver->fetch_size() + 4;
 391
 392         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 393             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 394                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 395                 case I830_GMCH_GMS_STOLEN_512:
 396                         gtt_entries = KB(512) - KB(size);
 397                         break;
 398                 case I830_GMCH_GMS_STOLEN_1024:
 399                         gtt_entries = MB(1) - KB(size);
 400                         break;
 401                 case I830_GMCH_GMS_STOLEN_8192:
 402                         gtt_entries = MB(8) - KB(size);
 403                         break;
 404                 case I830_GMCH_GMS_LOCAL:
 405                         rdct = readb(intel_i830_private.registers+I830_RDRAM_CHANNEL_TYPE);
 406                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
 407                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 408                         local = 1;
 409                         break;
 410                 default:
 411                         gtt_entries = 0;
 412                         break;
 413                 }
 414         } else {
 415                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 416                 case I855_GMCH_GMS_STOLEN_1M:
 417                         gtt_entries = MB(1) - KB(size);
 418                         break;
 419                 case I855_GMCH_GMS_STOLEN_4M:
 420                         gtt_entries = MB(4) - KB(size);
 421                         break;
 422                 case I855_GMCH_GMS_STOLEN_8M:
 423                         gtt_entries = MB(8) - KB(size);
 424                         break;
 425                 case I855_GMCH_GMS_STOLEN_16M:
 426                         gtt_entries = MB(16) - KB(size);
 427                         break;
 428                 case I855_GMCH_GMS_STOLEN_32M:
 429                         gtt_entries = MB(32) - KB(size);
 430                         break;
 431                 case I915_GMCH_GMS_STOLEN_48M:
 432                         /* Check it's really I915G */
 433                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
 434                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
 435                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
 436                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || IS_I965 )
 437                                 gtt_entries = MB(48) - KB(size);
 438                         else
 439                                 gtt_entries = 0;
 440                         break;
 441                 case I915_GMCH_GMS_STOLEN_64M:
 442                         /* Check it's really I915G */
 443                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
 444                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
 445                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
 446                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || IS_I965)
 447                                 gtt_entries = MB(64) - KB(size);
 448                         else
 449                                 gtt_entries = 0;
 450                 default:
 451                         gtt_entries = 0;
 452                         break;
 453                 }
 454         }
 455         if (gtt_entries > 0)
 456                 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
 457                        gtt_entries / KB(1), local ? "local" : "stolen");
 458         else
 459                 printk(KERN_INFO PFX
 460                        "No pre-allocated video memory detected.\n");
 461         gtt_entries /= KB(4);
 462
 463         intel_i830_private.gtt_entries = gtt_entries;
 464 }
 465
 466 /* The intel i830 automatically initializes the agp aperture during POST.
 467  * Use the memory already set aside for in the GTT.
 468  */
 469 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 470 {
 471         int page_order;
 472         struct aper_size_info_fixed *size;
 473         int num_entries;
 474         u32 temp;
 475
 476         size = agp_bridge->current_size;
 477         page_order = size->page_order;
 478         num_entries = size->num_entries;
 479         agp_bridge->gatt_table_real = NULL;
 480
 481         pci_read_config_dword(intel_i830_private.i830_dev,I810_MMADDR,&temp);
 482         temp &= 0xfff80000;
 483
 484         intel_i830_private.registers = ioremap(temp,128 * 4096);
 485         if (!intel_i830_private.registers)
 486                 return -ENOMEM;
 487
 488         temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 489         global_cache_flush();   /* FIXME: ?? */
 490
 491         /* we have to call this as early as possible after the MMIO base address is known */
 492         intel_i830_init_gtt_entries();
 493
 494         agp_bridge->gatt_table = NULL;
 495
 496         agp_bridge->gatt_bus_addr = temp;
 497
 498         return 0;
 499 }
 500
 501 /* Return the gatt table to a sane state. Use the top of stolen
 502  * memory for the GTT.
 503  */
 504 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
 505 {
 506         return 0;
 507 }
 508
 509 static int intel_i830_fetch_size(void)
 510 {
 511         u16 gmch_ctrl;
 512         struct aper_size_info_fixed *values;
 513
 514         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 515
 516         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
 517             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
 518                 /* 855GM/852GM/865G has 128MB aperture size */
 519                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 520                 agp_bridge->aperture_size_idx = 0;
 521                 return values[0].size;
 522         }
 523
 524         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 525
 526         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
 527                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 528                 agp_bridge->aperture_size_idx = 0;
 529                 return values[0].size;
 530         } else {
 531                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
 532                 agp_bridge->aperture_size_idx = 1;
 533                 return values[1].size;
 534         }
 535
 536         return 0;
 537 }
 538
 539 static int intel_i830_configure(void)
 540 {
 541         struct aper_size_info_fixed *current_size;
 542         u32 temp;
 543         u16 gmch_ctrl;
 544         int i;
 545
 546         current_size = A_SIZE_FIX(agp_bridge->current_size);
 547
 548         pci_read_config_dword(intel_i830_private.i830_dev,I810_GMADDR,&temp);
 549         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 550
 551         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 552         gmch_ctrl |= I830_GMCH_ENABLED;
 553         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
 554
 555         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL);
 556         readl(intel_i830_private.registers+I810_PGETBL_CTL);    /* PCI Posting. */
 557
 558         if (agp_bridge->driver->needs_scratch_page) {
 559                 for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) {
 560                         writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4));
 561                         readl(intel_i830_private.registers+I810_PTE_BASE+(i*4));        /* PCI Posting. */
 562                 }
 563         }
 564
 565         global_cache_flush();
 566         return 0;
 567 }
 568
 569 static void intel_i830_cleanup(void)
 570 {
 571         iounmap(intel_i830_private.registers);
 572 }
 573
 574 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
 575 {
 576         int i,j,num_entries;
 577         void *temp;
 578
 579         temp = agp_bridge->current_size;
 580         num_entries = A_SIZE_FIX(temp)->num_entries;
 581
 582         if (pg_start < intel_i830_private.gtt_entries) {
 583                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n",
 584                                 pg_start,intel_i830_private.gtt_entries);
 585
 586                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
 587                 return -EINVAL;
 588         }
 589
 590         if ((pg_start + mem->page_count) > num_entries)
 591                 return -EINVAL;
 592
 593         /* The i830 can't check the GTT for entries since its read only,
 594          * depend on the caller to make the correct offset decisions.
 595          */
 596
 597         if ((type != 0 && type != AGP_PHYS_MEMORY) ||
 598                 (mem->type != 0 && mem->type != AGP_PHYS_MEMORY))
 599                 return -EINVAL;
 600
 601         global_cache_flush();   /* FIXME: Necessary ?*/
 602
 603         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 604                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 605                         mem->memory[i], mem->type),
 606                         intel_i830_private.registers+I810_PTE_BASE+(j*4));
 607                 readl(intel_i830_private.registers+I810_PTE_BASE+(j*4));        /* PCI Posting. */
 608         }
 609
 610         global_cache_flush();
 611         agp_bridge->driver->tlb_flush(mem);
 612         return 0;
 613 }
 614
 615 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
 616                                 int type)
 617 {
 618         int i;
 619
 620         global_cache_flush();
 621
 622         if (pg_start < intel_i830_private.gtt_entries) {
 623                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
 624                 return -EINVAL;
 625         }
 626
 627         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 628                 writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4));
 629                 readl(intel_i830_private.registers+I810_PTE_BASE+(i*4));        /* PCI Posting. */
 630         }
 631
 632         global_cache_flush();
 633         agp_bridge->driver->tlb_flush(mem);
 634         return 0;
 635 }
 636
 637 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
 638 {
 639         if (type == AGP_PHYS_MEMORY)
 640                 return alloc_agpphysmem_i8xx(pg_count, type);
 641
 642         /* always return NULL for other allocation types for now */
 643         return NULL;
 644 }
 645
 646 static int intel_i915_configure(void)
 647 {
 648         struct aper_size_info_fixed *current_size;
 649         u32 temp;
 650         u16 gmch_ctrl;
 651         int i;
 652
 653         current_size = A_SIZE_FIX(agp_bridge->current_size);
 654
 655         pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp);
 656
 657         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 658
 659         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 660         gmch_ctrl |= I830_GMCH_ENABLED;
 661         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
 662
 663         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL);
 664         readl(intel_i830_private.registers+I810_PGETBL_CTL);    /* PCI Posting. */
 665
 666         if (agp_bridge->driver->needs_scratch_page) {
 667                 for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) {
 668                         writel(agp_bridge->scratch_page, intel_i830_private.gtt+i);
 669                         readl(intel_i830_private.gtt+i);        /* PCI Posting. */
 670                 }
 671         }
 672
 673         global_cache_flush();
 674         return 0;
 675 }
 676
 677 static void intel_i915_cleanup(void)
 678 {
 679         iounmap(intel_i830_private.gtt);
 680         iounmap(intel_i830_private.registers);
 681 }
 682
 683 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
 684                                 int type)
 685 {
 686         int i,j,num_entries;
 687         void *temp;
 688
 689         temp = agp_bridge->current_size;
 690         num_entries = A_SIZE_FIX(temp)->num_entries;
 691
 692         if (pg_start < intel_i830_private.gtt_entries) {
 693                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n",
 694                                 pg_start,intel_i830_private.gtt_entries);
 695
 696                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
 697                 return -EINVAL;
 698         }
 699
 700         if ((pg_start + mem->page_count) > num_entries)
 701                 return -EINVAL;
 702
 703         /* The i830 can't check the GTT for entries since its read only,
 704          * depend on the caller to make the correct offset decisions.
 705          */
 706
 707         if ((type != 0 && type != AGP_PHYS_MEMORY) ||
 708                 (mem->type != 0 && mem->type != AGP_PHYS_MEMORY))
 709                 return -EINVAL;
 710
 711         global_cache_flush();
 712
 713         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 714                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 715                         mem->memory[i], mem->type), intel_i830_private.gtt+j);
 716                 readl(intel_i830_private.gtt+j);        /* PCI Posting. */
 717         }
 718
 719         global_cache_flush();
 720         agp_bridge->driver->tlb_flush(mem);
 721         return 0;
 722 }
 723
 724 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
 725                                 int type)
 726 {
 727         int i;
 728
 729         global_cache_flush();
 730
 731         if (pg_start < intel_i830_private.gtt_entries) {
 732                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
 733                 return -EINVAL;
 734         }
 735
 736         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 737                 writel(agp_bridge->scratch_page, intel_i830_private.gtt+i);
 738                 readl(intel_i830_private.gtt+i);
 739         }
 740
 741         global_cache_flush();
 742         agp_bridge->driver->tlb_flush(mem);
 743         return 0;
 744 }
 745
 746 static int intel_i915_fetch_size(void)
 747 {
 748         struct aper_size_info_fixed *values;
 749         u32 temp, offset;
 750
 751 #define I915_256MB_ADDRESS_MASK (1<<27)
 752
 753         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 754
 755         pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp);
 756         if (temp & I915_256MB_ADDRESS_MASK)
 757                 offset = 0;     /* 128MB aperture */
 758         else
 759                 offset = 2;     /* 256MB aperture */
 760         agp_bridge->previous_size = agp_bridge->current_size = (void *)(values + offset);
 761         return values[offset].size;
 762 }
 763
 764 /* The intel i915 automatically initializes the agp aperture during POST.
 765  * Use the memory already set aside for in the GTT.
 766  */
 767 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
 768 {
 769         int page_order;
 770         struct aper_size_info_fixed *size;
 771         int num_entries;
 772         u32 temp, temp2;
 773
 774         size = agp_bridge->current_size;
 775         page_order = size->page_order;
 776         num_entries = size->num_entries;
 777         agp_bridge->gatt_table_real = NULL;
 778
 779         pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp);
 780         pci_read_config_dword(intel_i830_private.i830_dev, I915_PTEADDR,&temp2);
 781
 782         intel_i830_private.gtt = ioremap(temp2, 256 * 1024);
 783         if (!intel_i830_private.gtt)
 784                 return -ENOMEM;
 785
 786         temp &= 0xfff80000;
 787
 788         intel_i830_private.registers = ioremap(temp,128 * 4096);
 789         if (!intel_i830_private.registers)
 790                 return -ENOMEM;
 791
 792         temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 793         global_cache_flush();   /* FIXME: ? */
 794
 795         /* we have to call this as early as possible after the MMIO base address is known */
 796         intel_i830_init_gtt_entries();
 797
 798         agp_bridge->gatt_table = NULL;
 799
 800         agp_bridge->gatt_bus_addr = temp;
 801
 802         return 0;
 803 }
 804
 805 /*
 806  * The i965 supports 36-bit physical addresses, but to keep
 807  * the format of the GTT the same, the bits that don't fit
 808  * in a 32-bit word are shifted down to bits 4..7.
 809  *
 810  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
 811  * is always zero on 32-bit architectures, so no need to make
 812  * this conditional.
 813  */
 814 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
 815         unsigned long addr, int type)
 816 {
 817         /* Shift high bits down */
 818         addr |= (addr >> 28) & 0xf0;
 819
 820         /* Type checking must be done elsewhere */
 821         return addr | bridge->driver->masks[type].mask;
 822 }
 823
 824 static int intel_i965_fetch_size(void)
 825 {
 826        struct aper_size_info_fixed *values;
 827        u32 offset = 0;
 828        u8 temp;
 829
 830 #define I965_512MB_ADDRESS_MASK (3<<1)
 831
 832        values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 833
 834        pci_read_config_byte(intel_i830_private.i830_dev, I965_MSAC, &temp);
 835        temp &= I965_512MB_ADDRESS_MASK;
 836        switch (temp) {
 837        case 0x00:
 838                offset = 0; /* 128MB */
 839                break;
 840        case 0x06:
 841                offset = 3; /* 512MB */
 842                break;
 843        default:
 844        case 0x02:
 845                offset = 2; /* 256MB */
 846                break;
 847        }
 848
 849        agp_bridge->previous_size = agp_bridge->current_size = (void *)(values + offset);
 850
 851         /* The i965 GTT is always sized as if it had a 512kB aperture size */
 852         return 512;
 853 }
 854
 855 /* The intel i965 automatically initializes the agp aperture during POST.
 856 + * Use the memory already set aside for in the GTT.
 857 + */
 858 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
 859 {
 860        int page_order;
 861        struct aper_size_info_fixed *size;
 862        int num_entries;
 863        u32 temp;
 864
 865        size = agp_bridge->current_size;
 866        page_order = size->page_order;
 867        num_entries = size->num_entries;
 868        agp_bridge->gatt_table_real = NULL;
 869
 870        pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp);
 871
 872        temp &= 0xfff00000;
 873        intel_i830_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
 874
 875        if (!intel_i830_private.gtt)
 876                return -ENOMEM;
 877
 878
 879        intel_i830_private.registers = ioremap(temp,128 * 4096);
 880        if (!intel_i830_private.registers)
 881                return -ENOMEM;
 882
 883        temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 884        global_cache_flush();   /* FIXME: ? */
 885
 886        /* we have to call this as early as possible after the MMIO base address is known */
 887        intel_i830_init_gtt_entries();
 888
 889        agp_bridge->gatt_table = NULL;
 890
 891        agp_bridge->gatt_bus_addr = temp;
 892
 893        return 0;
 894 }
 895
 896
 897 static int intel_fetch_size(void)
 898 {
 899         int i;
 900         u16 temp;
 901         struct aper_size_info_16 *values;
 902
 903         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
 904         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
 905
 906         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 907                 if (temp == values[i].size_value) {
 908                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
 909                         agp_bridge->aperture_size_idx = i;
 910                         return values[i].size;
 911                 }
 912         }
 913
 914         return 0;
 915 }
 916
 917 static int __intel_8xx_fetch_size(u8 temp)
 918 {
 919         int i;
 920         struct aper_size_info_8 *values;
 921
 922         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
 923
 924         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 925                 if (temp == values[i].size_value) {
 926                         agp_bridge->previous_size =
 927                                 agp_bridge->current_size = (void *) (values + i);
 928                         agp_bridge->aperture_size_idx = i;
 929                         return values[i].size;
 930                 }
 931         }
 932         return 0;
 933 }
 934
 935 static int intel_8xx_fetch_size(void)
 936 {
 937         u8 temp;
 938
 939         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
 940         return __intel_8xx_fetch_size(temp);
 941 }
 942
 943 static int intel_815_fetch_size(void)
 944 {
 945         u8 temp;
 946
 947         /* Intel 815 chipsets have a _weird_ APSIZE register with only
 948          * one non-reserved bit, so mask the others out ... */
 949         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
 950         temp &= (1 << 3);
 951
 952         return __intel_8xx_fetch_size(temp);
 953 }
 954
 955 static void intel_tlbflush(struct agp_memory *mem)
 956 {
 957         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
 958         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
 959 }
 960
 961
 962 static void intel_8xx_tlbflush(struct agp_memory *mem)
 963 {
 964         u32 temp;
 965         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
 966         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
 967         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
 968         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
 969 }
 970
 971
 972 static void intel_cleanup(void)
 973 {
 974         u16 temp;
 975         struct aper_size_info_16 *previous_size;
 976
 977         previous_size = A_SIZE_16(agp_bridge->previous_size);
 978         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
 979         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
 980         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
 981 }
 982
 983
 984 static void intel_8xx_cleanup(void)
 985 {
 986         u16 temp;
 987         struct aper_size_info_8 *previous_size;
 988
 989         previous_size = A_SIZE_8(agp_bridge->previous_size);
 990         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
 991         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
 992         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
 993 }
 994
 995
 996 static int intel_configure(void)
 997 {
 998         u32 temp;
 999         u16 temp2;
1000         struct aper_size_info_16 *current_size;
1001
1002         current_size = A_SIZE_16(agp_bridge->current_size);
1003
1004         /* aperture size */
1005         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1006
1007         /* address to map to */
1008         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1009         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1010
1011         /* attbase - aperture base */
1012         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1013
1014         /* agpctrl */
1015         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1016
1017         /* paccfg/nbxcfg */
1018         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1019         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1020                         (temp2 & ~(1 << 10)) | (1 << 9));
1021         /* clear any possible error conditions */
1022         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1023         return 0;
1024 }
1025
1026 static int intel_815_configure(void)
1027 {
1028         u32 temp, addr;
1029         u8 temp2;
1030         struct aper_size_info_8 *current_size;
1031
1032         /* attbase - aperture base */
1033         /* the Intel 815 chipset spec. says that bits 29-31 in the
1034         * ATTBASE register are reserved -> try not to write them */
1035         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1036                 printk (KERN_EMERG PFX "gatt bus addr too high");
1037                 return -EINVAL;
1038         }
1039
1040         current_size = A_SIZE_8(agp_bridge->current_size);
1041
1042         /* aperture size */
1043         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1044                         current_size->size_value);
1045
1046         /* address to map to */
1047         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1048         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1049
1050         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1051         addr &= INTEL_815_ATTBASE_MASK;
1052         addr |= agp_bridge->gatt_bus_addr;
1053         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1054
1055         /* agpctrl */
1056         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1057
1058         /* apcont */
1059         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1060         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1061
1062         /* clear any possible error conditions */
1063         /* Oddness : this chipset seems to have no ERRSTS register ! */
1064         return 0;
1065 }
1066
1067 static void intel_820_tlbflush(struct agp_memory *mem)
1068 {
1069         return;
1070 }
1071
1072 static void intel_820_cleanup(void)
1073 {
1074         u8 temp;
1075         struct aper_size_info_8 *previous_size;
1076
1077         previous_size = A_SIZE_8(agp_bridge->previous_size);
1078         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1079         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1080                         temp & ~(1 << 1));
1081         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1082                         previous_size->size_value);
1083 }
1084
1085
1086 static int intel_820_configure(void)
1087 {
1088         u32 temp;
1089         u8 temp2;
1090         struct aper_size_info_8 *current_size;
1091
1092         current_size = A_SIZE_8(agp_bridge->current_size);
1093
1094         /* aperture size */
1095         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1096
1097         /* address to map to */
1098         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1099         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1100
1101         /* attbase - aperture base */
1102         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1103
1104         /* agpctrl */
1105         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1106
1107         /* global enable aperture access */
1108         /* This flag is not accessed through MCHCFG register as in */
1109         /* i850 chipset. */
1110         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1111         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1112         /* clear any possible AGP-related error conditions */
1113         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1114         return 0;
1115 }
1116
1117 static int intel_840_configure(void)
1118 {
1119         u32 temp;
1120         u16 temp2;
1121         struct aper_size_info_8 *current_size;
1122
1123         current_size = A_SIZE_8(agp_bridge->current_size);
1124
1125         /* aperture size */
1126         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1127
1128         /* address to map to */
1129         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1130         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1131
1132         /* attbase - aperture base */
1133         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1134
1135         /* agpctrl */
1136         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1137
1138         /* mcgcfg */
1139         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1140         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1141         /* clear any possible error conditions */
1142         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1143         return 0;
1144 }
1145
1146 static int intel_845_configure(void)
1147 {
1148         u32 temp;
1149         u8 temp2;
1150         struct aper_size_info_8 *current_size;
1151
1152         current_size = A_SIZE_8(agp_bridge->current_size);
1153
1154         /* aperture size */
1155         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1156
1157         if (agp_bridge->apbase_config != 0) {
1158                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1159                                        agp_bridge->apbase_config);
1160         } else {
1161                 /* address to map to */
1162                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1163                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1164                 agp_bridge->apbase_config = temp;
1165         }
1166
1167         /* attbase - aperture base */
1168         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1169
1170         /* agpctrl */
1171         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1172
1173         /* agpm */
1174         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1175         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1176         /* clear any possible error conditions */
1177         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1178         return 0;
1179 }
1180
1181 static int intel_850_configure(void)
1182 {
1183         u32 temp;
1184         u16 temp2;
1185         struct aper_size_info_8 *current_size;
1186
1187         current_size = A_SIZE_8(agp_bridge->current_size);
1188
1189         /* aperture size */
1190         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1191
1192         /* address to map to */
1193         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1194         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1195
1196         /* attbase - aperture base */
1197         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1198
1199         /* agpctrl */
1200         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1201
1202         /* mcgcfg */
1203         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1204         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1205         /* clear any possible AGP-related error conditions */
1206         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1207         return 0;
1208 }
1209
1210 static int intel_860_configure(void)
1211 {
1212         u32 temp;
1213         u16 temp2;
1214         struct aper_size_info_8 *current_size;
1215
1216         current_size = A_SIZE_8(agp_bridge->current_size);
1217
1218         /* aperture size */
1219         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1220
1221         /* address to map to */
1222         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1223         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1224
1225         /* attbase - aperture base */
1226         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1227
1228         /* agpctrl */
1229         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1230
1231         /* mcgcfg */
1232         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1233         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1234         /* clear any possible AGP-related error conditions */
1235         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1236         return 0;
1237 }
1238
1239 static int intel_830mp_configure(void)
1240 {
1241         u32 temp;
1242         u16 temp2;
1243         struct aper_size_info_8 *current_size;
1244
1245         current_size = A_SIZE_8(agp_bridge->current_size);
1246
1247         /* aperture size */
1248         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1249
1250         /* address to map to */
1251         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1252         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1253
1254         /* attbase - aperture base */
1255         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1256
1257         /* agpctrl */
1258         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1259
1260         /* gmch */
1261         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1262         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1263         /* clear any possible AGP-related error conditions */
1264         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1265         return 0;
1266 }
1267
1268 static int intel_7505_configure(void)
1269 {
1270         u32 temp;
1271         u16 temp2;
1272         struct aper_size_info_8 *current_size;
1273
1274         current_size = A_SIZE_8(agp_bridge->current_size);
1275
1276         /* aperture size */
1277         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1278
1279         /* address to map to */
1280         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1281         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1282
1283         /* attbase - aperture base */
1284         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1285
1286         /* agpctrl */
1287         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1288
1289         /* mchcfg */
1290         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1291         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1292
1293         return 0;
1294 }
1295
1296 /* Setup function */
1297 static struct gatt_mask intel_generic_masks[] =
1298 {
1299         {.mask = 0x00000017, .type = 0}
1300 };
1301
1302 static struct aper_size_info_8 intel_815_sizes[2] =
1303 {
1304         {64, 16384, 4, 0},
1305         {32, 8192, 3, 8},
1306 };
1307
1308 static struct aper_size_info_8 intel_8xx_sizes[7] =
1309 {
1310         {256, 65536, 6, 0},
1311         {128, 32768, 5, 32},
1312         {64, 16384, 4, 48},
1313         {32, 8192, 3, 56},
1314         {16, 4096, 2, 60},
1315         {8, 2048, 1, 62},
1316         {4, 1024, 0, 63}
1317 };
1318
1319 static struct aper_size_info_16 intel_generic_sizes[7] =
1320 {
1321         {256, 65536, 6, 0},
1322         {128, 32768, 5, 32},
1323         {64, 16384, 4, 48},
1324         {32, 8192, 3, 56},
1325         {16, 4096, 2, 60},
1326         {8, 2048, 1, 62},
1327         {4, 1024, 0, 63}
1328 };
1329
1330 static struct aper_size_info_8 intel_830mp_sizes[4] =
1331 {
1332         {256, 65536, 6, 0},
1333         {128, 32768, 5, 32},
1334         {64, 16384, 4, 48},
1335         {32, 8192, 3, 56}
1336 };
1337
1338 static struct agp_bridge_driver intel_generic_driver = {
1339         .owner                  = THIS_MODULE,
1340         .aperture_sizes         = intel_generic_sizes,
1341         .size_type              = U16_APER_SIZE,
1342         .num_aperture_sizes     = 7,
1343         .configure              = intel_configure,
1344         .fetch_size             = intel_fetch_size,
1345         .cleanup                = intel_cleanup,
1346         .tlb_flush              = intel_tlbflush,
1347         .mask_memory            = agp_generic_mask_memory,
1348         .masks                  = intel_generic_masks,
1349         .agp_enable             = agp_generic_enable,
1350         .cache_flush            = global_cache_flush,
1351         .create_gatt_table      = agp_generic_create_gatt_table,
1352         .free_gatt_table        = agp_generic_free_gatt_table,
1353         .insert_memory          = agp_generic_insert_memory,
1354         .remove_memory          = agp_generic_remove_memory,
1355         .alloc_by_type          = agp_generic_alloc_by_type,
1356         .free_by_type           = agp_generic_free_by_type,
1357         .agp_alloc_page         = agp_generic_alloc_page,
1358         .agp_destroy_page       = agp_generic_destroy_page,
1359 };
1360
1361 static struct agp_bridge_driver intel_810_driver = {
1362         .owner                  = THIS_MODULE,
1363         .aperture_sizes         = intel_i810_sizes,
1364         .size_type              = FIXED_APER_SIZE,
1365         .num_aperture_sizes     = 2,
1366         .needs_scratch_page     = TRUE,
1367         .configure              = intel_i810_configure,
1368         .fetch_size             = intel_i810_fetch_size,
1369         .cleanup                = intel_i810_cleanup,
1370         .tlb_flush              = intel_i810_tlbflush,
1371         .mask_memory            = intel_i810_mask_memory,
1372         .masks                  = intel_i810_masks,
1373         .agp_enable             = intel_i810_agp_enable,
1374         .cache_flush            = global_cache_flush,
1375         .create_gatt_table      = agp_generic_create_gatt_table,
1376         .free_gatt_table        = agp_generic_free_gatt_table,
1377         .insert_memory          = intel_i810_insert_entries,
1378         .remove_memory          = intel_i810_remove_entries,
1379         .alloc_by_type          = intel_i810_alloc_by_type,
1380         .free_by_type           = intel_i810_free_by_type,
1381         .agp_alloc_page         = agp_generic_alloc_page,
1382         .agp_destroy_page       = agp_generic_destroy_page,
1383 };
1384
1385 static struct agp_bridge_driver intel_815_driver = {
1386         .owner                  = THIS_MODULE,
1387         .aperture_sizes         = intel_815_sizes,
1388         .size_type              = U8_APER_SIZE,
1389         .num_aperture_sizes     = 2,
1390         .configure              = intel_815_configure,
1391         .fetch_size             = intel_815_fetch_size,
1392         .cleanup                = intel_8xx_cleanup,
1393         .tlb_flush              = intel_8xx_tlbflush,
1394         .mask_memory            = agp_generic_mask_memory,
1395         .masks                  = intel_generic_masks,
1396         .agp_enable             = agp_generic_enable,
1397         .cache_flush            = global_cache_flush,
1398         .create_gatt_table      = agp_generic_create_gatt_table,
1399         .free_gatt_table        = agp_generic_free_gatt_table,
1400         .insert_memory          = agp_generic_insert_memory,
1401         .remove_memory          = agp_generic_remove_memory,
1402         .alloc_by_type          = agp_generic_alloc_by_type,
1403         .free_by_type           = agp_generic_free_by_type,
1404         .agp_alloc_page         = agp_generic_alloc_page,
1405         .agp_destroy_page       = agp_generic_destroy_page,
1406 };
1407
1408 static struct agp_bridge_driver intel_830_driver = {
1409         .owner                  = THIS_MODULE,
1410         .aperture_sizes         = intel_i830_sizes,
1411         .size_type              = FIXED_APER_SIZE,
1412         .num_aperture_sizes     = 4,
1413         .needs_scratch_page     = TRUE,
1414         .configure              = intel_i830_configure,
1415         .fetch_size             = intel_i830_fetch_size,
1416         .cleanup                = intel_i830_cleanup,
1417         .tlb_flush              = intel_i810_tlbflush,
1418         .mask_memory            = intel_i810_mask_memory,
1419         .masks                  = intel_i810_masks,
1420         .agp_enable             = intel_i810_agp_enable,
1421         .cache_flush            = global_cache_flush,
1422         .create_gatt_table      = intel_i830_create_gatt_table,
1423         .free_gatt_table        = intel_i830_free_gatt_table,
1424         .insert_memory          = intel_i830_insert_entries,
1425         .remove_memory          = intel_i830_remove_entries,
1426         .alloc_by_type          = intel_i830_alloc_by_type,
1427         .free_by_type           = intel_i810_free_by_type,
1428         .agp_alloc_page         = agp_generic_alloc_page,
1429         .agp_destroy_page       = agp_generic_destroy_page,
1430 };
1431
1432 static struct agp_bridge_driver intel_820_driver = {
1433         .owner                  = THIS_MODULE,
1434         .aperture_sizes         = intel_8xx_sizes,
1435         .size_type              = U8_APER_SIZE,
1436         .num_aperture_sizes     = 7,
1437         .configure              = intel_820_configure,
1438         .fetch_size             = intel_8xx_fetch_size,
1439         .cleanup                = intel_820_cleanup,
1440         .tlb_flush              = intel_820_tlbflush,
1441         .mask_memory            = agp_generic_mask_memory,
1442         .masks                  = intel_generic_masks,
1443         .agp_enable             = agp_generic_enable,
1444         .cache_flush            = global_cache_flush,
1445         .create_gatt_table      = agp_generic_create_gatt_table,
1446         .free_gatt_table        = agp_generic_free_gatt_table,
1447         .insert_memory          = agp_generic_insert_memory,
1448         .remove_memory          = agp_generic_remove_memory,
1449         .alloc_by_type          = agp_generic_alloc_by_type,
1450         .free_by_type           = agp_generic_free_by_type,
1451         .agp_alloc_page         = agp_generic_alloc_page,
1452         .agp_destroy_page       = agp_generic_destroy_page,
1453 };
1454
1455 static struct agp_bridge_driver intel_830mp_driver = {
1456         .owner                  = THIS_MODULE,
1457         .aperture_sizes         = intel_830mp_sizes,
1458         .size_type              = U8_APER_SIZE,
1459         .num_aperture_sizes     = 4,
1460         .configure              = intel_830mp_configure,
1461         .fetch_size             = intel_8xx_fetch_size,
1462         .cleanup                = intel_8xx_cleanup,
1463         .tlb_flush              = intel_8xx_tlbflush,
1464         .mask_memory            = agp_generic_mask_memory,
1465         .masks                  = intel_generic_masks,
1466         .agp_enable             = agp_generic_enable,
1467         .cache_flush            = global_cache_flush,
1468         .create_gatt_table      = agp_generic_create_gatt_table,
1469         .free_gatt_table        = agp_generic_free_gatt_table,
1470         .insert_memory          = agp_generic_insert_memory,
1471         .remove_memory          = agp_generic_remove_memory,
1472         .alloc_by_type          = agp_generic_alloc_by_type,
1473         .free_by_type           = agp_generic_free_by_type,
1474         .agp_alloc_page         = agp_generic_alloc_page,
1475         .agp_destroy_page       = agp_generic_destroy_page,
1476 };
1477
1478 static struct agp_bridge_driver intel_840_driver = {
1479         .owner                  = THIS_MODULE,
1480         .aperture_sizes         = intel_8xx_sizes,
1481         .size_type              = U8_APER_SIZE,
1482         .num_aperture_sizes     = 7,
1483         .configure              = intel_840_configure,
1484         .fetch_size             = intel_8xx_fetch_size,
1485         .cleanup                = intel_8xx_cleanup,
1486         .tlb_flush              = intel_8xx_tlbflush,
1487         .mask_memory            = agp_generic_mask_memory,
1488         .masks                  = intel_generic_masks,
1489         .agp_enable             = agp_generic_enable,
1490         .cache_flush            = global_cache_flush,
1491         .create_gatt_table      = agp_generic_create_gatt_table,
1492         .free_gatt_table        = agp_generic_free_gatt_table,
1493         .insert_memory          = agp_generic_insert_memory,
1494         .remove_memory          = agp_generic_remove_memory,
1495         .alloc_by_type          = agp_generic_alloc_by_type,
1496         .free_by_type           = agp_generic_free_by_type,
1497         .agp_alloc_page         = agp_generic_alloc_page,
1498         .agp_destroy_page       = agp_generic_destroy_page,
1499 };
1500
1501 static struct agp_bridge_driver intel_845_driver = {
1502         .owner                  = THIS_MODULE,
1503         .aperture_sizes         = intel_8xx_sizes,
1504         .size_type              = U8_APER_SIZE,
1505         .num_aperture_sizes     = 7,
1506         .configure              = intel_845_configure,
1507         .fetch_size             = intel_8xx_fetch_size,
1508         .cleanup                = intel_8xx_cleanup,
1509         .tlb_flush              = intel_8xx_tlbflush,
1510         .mask_memory            = agp_generic_mask_memory,
1511         .masks                  = intel_generic_masks,
1512         .agp_enable             = agp_generic_enable,
1513         .cache_flush            = global_cache_flush,
1514         .create_gatt_table      = agp_generic_create_gatt_table,
1515         .free_gatt_table        = agp_generic_free_gatt_table,
1516         .insert_memory          = agp_generic_insert_memory,
1517         .remove_memory          = agp_generic_remove_memory,
1518         .alloc_by_type          = agp_generic_alloc_by_type,
1519         .free_by_type           = agp_generic_free_by_type,
1520         .agp_alloc_page         = agp_generic_alloc_page,
1521         .agp_destroy_page       = agp_generic_destroy_page,
1522 };
1523
1524 static struct agp_bridge_driver intel_850_driver = {
1525         .owner                  = THIS_MODULE,
1526         .aperture_sizes         = intel_8xx_sizes,
1527         .size_type              = U8_APER_SIZE,
1528         .num_aperture_sizes     = 7,
1529         .configure              = intel_850_configure,
1530         .fetch_size             = intel_8xx_fetch_size,
1531         .cleanup                = intel_8xx_cleanup,
1532         .tlb_flush              = intel_8xx_tlbflush,
1533         .mask_memory            = agp_generic_mask_memory,
1534         .masks                  = intel_generic_masks,
1535         .agp_enable             = agp_generic_enable,
1536         .cache_flush            = global_cache_flush,
1537         .create_gatt_table      = agp_generic_create_gatt_table,
1538         .free_gatt_table        = agp_generic_free_gatt_table,
1539         .insert_memory          = agp_generic_insert_memory,
1540         .remove_memory          = agp_generic_remove_memory,
1541         .alloc_by_type          = agp_generic_alloc_by_type,
1542         .free_by_type           = agp_generic_free_by_type,
1543         .agp_alloc_page         = agp_generic_alloc_page,
1544         .agp_destroy_page       = agp_generic_destroy_page,
1545 };
1546
1547 static struct agp_bridge_driver intel_860_driver = {
1548         .owner                  = THIS_MODULE,
1549         .aperture_sizes         = intel_8xx_sizes,
1550         .size_type              = U8_APER_SIZE,
1551         .num_aperture_sizes     = 7,
1552         .configure              = intel_860_configure,
1553         .fetch_size             = intel_8xx_fetch_size,
1554         .cleanup                = intel_8xx_cleanup,
1555         .tlb_flush              = intel_8xx_tlbflush,
1556         .mask_memory            = agp_generic_mask_memory,
1557         .masks                  = intel_generic_masks,
1558         .agp_enable             = agp_generic_enable,
1559         .cache_flush            = global_cache_flush,
1560         .create_gatt_table      = agp_generic_create_gatt_table,
1561         .free_gatt_table        = agp_generic_free_gatt_table,
1562         .insert_memory          = agp_generic_insert_memory,
1563         .remove_memory          = agp_generic_remove_memory,
1564         .alloc_by_type          = agp_generic_alloc_by_type,
1565         .free_by_type           = agp_generic_free_by_type,
1566         .agp_alloc_page         = agp_generic_alloc_page,
1567         .agp_destroy_page       = agp_generic_destroy_page,
1568 };
1569
1570 static struct agp_bridge_driver intel_915_driver = {
1571         .owner                  = THIS_MODULE,
1572         .aperture_sizes         = intel_i830_sizes,
1573         .size_type              = FIXED_APER_SIZE,
1574         .num_aperture_sizes     = 4,
1575         .needs_scratch_page     = TRUE,
1576         .configure              = intel_i915_configure,
1577         .fetch_size             = intel_i915_fetch_size,
1578         .cleanup                = intel_i915_cleanup,
1579         .tlb_flush              = intel_i810_tlbflush,
1580         .mask_memory            = intel_i810_mask_memory,
1581         .masks                  = intel_i810_masks,
1582         .agp_enable             = intel_i810_agp_enable,
1583         .cache_flush            = global_cache_flush,
1584         .create_gatt_table      = intel_i915_create_gatt_table,
1585         .free_gatt_table        = intel_i830_free_gatt_table,
1586         .insert_memory          = intel_i915_insert_entries,
1587         .remove_memory          = intel_i915_remove_entries,
1588         .alloc_by_type          = intel_i830_alloc_by_type,
1589         .free_by_type           = intel_i810_free_by_type,
1590         .agp_alloc_page         = agp_generic_alloc_page,
1591         .agp_destroy_page       = agp_generic_destroy_page,
1592 };
1593
1594 static struct agp_bridge_driver intel_i965_driver = {
1595        .owner                  = THIS_MODULE,
1596        .aperture_sizes         = intel_i830_sizes,
1597        .size_type              = FIXED_APER_SIZE,
1598        .num_aperture_sizes     = 4,
1599        .needs_scratch_page     = TRUE,
1600        .configure              = intel_i915_configure,
1601        .fetch_size             = intel_i965_fetch_size,
1602        .cleanup                = intel_i915_cleanup,
1603        .tlb_flush              = intel_i810_tlbflush,
1604        .mask_memory            = intel_i965_mask_memory,
1605        .masks                  = intel_i810_masks,
1606        .agp_enable             = intel_i810_agp_enable,
1607        .cache_flush            = global_cache_flush,
1608        .create_gatt_table      = intel_i965_create_gatt_table,
1609        .free_gatt_table        = intel_i830_free_gatt_table,
1610        .insert_memory          = intel_i915_insert_entries,
1611        .remove_memory          = intel_i915_remove_entries,
1612        .alloc_by_type          = intel_i830_alloc_by_type,
1613        .free_by_type           = intel_i810_free_by_type,
1614        .agp_alloc_page         = agp_generic_alloc_page,
1615        .agp_destroy_page       = agp_generic_destroy_page,
1616 };
1617
1618 static struct agp_bridge_driver intel_7505_driver = {
1619         .owner                  = THIS_MODULE,
1620         .aperture_sizes         = intel_8xx_sizes,
1621         .size_type              = U8_APER_SIZE,
1622         .num_aperture_sizes     = 7,
1623         .configure              = intel_7505_configure,
1624         .fetch_size             = intel_8xx_fetch_size,
1625         .cleanup                = intel_8xx_cleanup,
1626         .tlb_flush              = intel_8xx_tlbflush,
1627         .mask_memory            = agp_generic_mask_memory,
1628         .masks                  = intel_generic_masks,
1629         .agp_enable             = agp_generic_enable,
1630         .cache_flush            = global_cache_flush,
1631         .create_gatt_table      = agp_generic_create_gatt_table,
1632         .free_gatt_table        = agp_generic_free_gatt_table,
1633         .insert_memory          = agp_generic_insert_memory,
1634         .remove_memory          = agp_generic_remove_memory,
1635         .alloc_by_type          = agp_generic_alloc_by_type,
1636         .free_by_type           = agp_generic_free_by_type,
1637         .agp_alloc_page         = agp_generic_alloc_page,
1638         .agp_destroy_page       = agp_generic_destroy_page,
1639 };
1640
1641 static int find_i810(u16 device)
1642 {
1643         struct pci_dev *i810_dev;
1644
1645         i810_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1646         if (!i810_dev)
1647                 return 0;
1648         intel_i810_private.i810_dev = i810_dev;
1649         return 1;
1650 }
1651
1652 static int find_i830(u16 device)
1653 {
1654         struct pci_dev *i830_dev;
1655
1656         i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1657         if (i830_dev && PCI_FUNC(i830_dev->devfn) != 0) {
1658                 i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
1659                                 device, i830_dev);
1660         }
1661
1662         if (!i830_dev)
1663                 return 0;
1664
1665         intel_i830_private.i830_dev = i830_dev;
1666         return 1;
1667 }
1668
1669 static int __devinit agp_intel_probe(struct pci_dev *pdev,
1670                                      const struct pci_device_id *ent)
1671 {
1672         struct agp_bridge_data *bridge;
1673         char *name = "(unknown)";
1674         u8 cap_ptr = 0;
1675         struct resource *r;
1676
1677         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
1678
1679         bridge = agp_alloc_bridge();
1680         if (!bridge)
1681                 return -ENOMEM;
1682
1683         switch (pdev->device) {
1684         case PCI_DEVICE_ID_INTEL_82443LX_0:
1685                 bridge->driver = &intel_generic_driver;
1686                 name = "440LX";
1687                 break;
1688         case PCI_DEVICE_ID_INTEL_82443BX_0:
1689                 bridge->driver = &intel_generic_driver;
1690                 name = "440BX";
1691                 break;
1692         case PCI_DEVICE_ID_INTEL_82443GX_0:
1693                 bridge->driver = &intel_generic_driver;
1694                 name = "440GX";
1695                 break;
1696         case PCI_DEVICE_ID_INTEL_82810_MC1:
1697                 name = "i810";
1698                 if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG1))
1699                         goto fail;
1700                 bridge->driver = &intel_810_driver;
1701                 break;
1702         case PCI_DEVICE_ID_INTEL_82810_MC3:
1703                 name = "i810 DC100";
1704                 if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG3))
1705                         goto fail;
1706                 bridge->driver = &intel_810_driver;
1707                 break;
1708         case PCI_DEVICE_ID_INTEL_82810E_MC:
1709                 name = "i810 E";
1710                 if (!find_i810(PCI_DEVICE_ID_INTEL_82810E_IG))
1711                         goto fail;
1712                 bridge->driver = &intel_810_driver;
1713                 break;
1714          case PCI_DEVICE_ID_INTEL_82815_MC:
1715                 /*
1716                  * The i815 can operate either as an i810 style
1717                  * integrated device, or as an AGP4X motherboard.
1718                  */
1719                 if (find_i810(PCI_DEVICE_ID_INTEL_82815_CGC))
1720                         bridge->driver = &intel_810_driver;
1721                 else
1722                         bridge->driver = &intel_815_driver;
1723                 name = "i815";
1724                 break;
1725         case PCI_DEVICE_ID_INTEL_82820_HB:
1726         case PCI_DEVICE_ID_INTEL_82820_UP_HB:
1727                 bridge->driver = &intel_820_driver;
1728                 name = "i820";
1729                 break;
1730         case PCI_DEVICE_ID_INTEL_82830_HB:
1731                 if (find_i830(PCI_DEVICE_ID_INTEL_82830_CGC))
1732                         bridge->driver = &intel_830_driver;
1733                 else
1734                         bridge->driver = &intel_830mp_driver;
1735                 name = "830M";
1736                 break;
1737         case PCI_DEVICE_ID_INTEL_82840_HB:
1738                 bridge->driver = &intel_840_driver;
1739                 name = "i840";
1740                 break;
1741         case PCI_DEVICE_ID_INTEL_82845_HB:
1742                 bridge->driver = &intel_845_driver;
1743                 name = "i845";
1744                 break;
1745         case PCI_DEVICE_ID_INTEL_82845G_HB:
1746                 if (find_i830(PCI_DEVICE_ID_INTEL_82845G_IG))
1747                         bridge->driver = &intel_830_driver;
1748                 else
1749                         bridge->driver = &intel_845_driver;
1750                 name = "845G";
1751                 break;
1752         case PCI_DEVICE_ID_INTEL_82850_HB:
1753                 bridge->driver = &intel_850_driver;
1754                 name = "i850";
1755                 break;
1756         case PCI_DEVICE_ID_INTEL_82855PM_HB:
1757                 bridge->driver = &intel_845_driver;
1758                 name = "855PM";
1759                 break;
1760         case PCI_DEVICE_ID_INTEL_82855GM_HB:
1761                 if (find_i830(PCI_DEVICE_ID_INTEL_82855GM_IG)) {
1762                         bridge->driver = &intel_830_driver;
1763                         name = "855";
1764                 } else {
1765                         bridge->driver = &intel_845_driver;
1766                         name = "855GM";
1767                 }
1768                 break;
1769         case PCI_DEVICE_ID_INTEL_82860_HB:
1770                 bridge->driver = &intel_860_driver;
1771                 name = "i860";
1772                 break;
1773         case PCI_DEVICE_ID_INTEL_82865_HB:
1774                 if (find_i830(PCI_DEVICE_ID_INTEL_82865_IG))
1775                         bridge->driver = &intel_830_driver;
1776                 else
1777                         bridge->driver = &intel_845_driver;
1778                 name = "865";
1779                 break;
1780         case PCI_DEVICE_ID_INTEL_82875_HB:
1781                 bridge->driver = &intel_845_driver;
1782                 name = "i875";
1783                 break;
1784         case PCI_DEVICE_ID_INTEL_82915G_HB:
1785                 if (find_i830(PCI_DEVICE_ID_INTEL_82915G_IG))
1786                         bridge->driver = &intel_915_driver;
1787                 else
1788                         bridge->driver = &intel_845_driver;
1789                 name = "915G";
1790                 break;
1791         case PCI_DEVICE_ID_INTEL_82915GM_HB:
1792                 if (find_i830(PCI_DEVICE_ID_INTEL_82915GM_IG))
1793                         bridge->driver = &intel_915_driver;
1794                 else
1795                         bridge->driver = &intel_845_driver;
1796                 name = "915GM";
1797                 break;
1798         case PCI_DEVICE_ID_INTEL_82945G_HB:
1799                 if (find_i830(PCI_DEVICE_ID_INTEL_82945G_IG))
1800                         bridge->driver = &intel_915_driver;
1801                 else
1802                         bridge->driver = &intel_845_driver;
1803                 name = "945G";
1804                 break;
1805         case PCI_DEVICE_ID_INTEL_82945GM_HB:
1806                 if (find_i830(PCI_DEVICE_ID_INTEL_82945GM_IG))
1807                         bridge->driver = &intel_915_driver;
1808                 else
1809                         bridge->driver = &intel_845_driver;
1810                 name = "945GM";
1811                 break;
1812         case PCI_DEVICE_ID_INTEL_82946GZ_HB:
1813                 if (find_i830(PCI_DEVICE_ID_INTEL_82946GZ_IG))
1814                         bridge->driver = &intel_i965_driver;
1815                 else
1816                         bridge->driver = &intel_845_driver;
1817                 name = "946GZ";
1818                 break;
1819         case PCI_DEVICE_ID_INTEL_82965G_1_HB:
1820                 if (find_i830(PCI_DEVICE_ID_INTEL_82965G_1_IG))
1821                         bridge->driver = &intel_i965_driver;
1822                 else
1823                         bridge->driver = &intel_845_driver;
1824                 name = "965G";
1825                 break;
1826         case PCI_DEVICE_ID_INTEL_82965Q_HB:
1827                 if (find_i830(PCI_DEVICE_ID_INTEL_82965Q_IG))
1828                         bridge->driver = &intel_i965_driver;
1829                 else
1830                         bridge->driver = &intel_845_driver;
1831                 name = "965Q";
1832                 break;
1833         case PCI_DEVICE_ID_INTEL_82965G_HB:
1834                 if (find_i830(PCI_DEVICE_ID_INTEL_82965G_IG))
1835                         bridge->driver = &intel_i965_driver;
1836                 else
1837                         bridge->driver = &intel_845_driver;
1838                 name = "965G";
1839                 break;
1840
1841         case PCI_DEVICE_ID_INTEL_7505_0:
1842                 bridge->driver = &intel_7505_driver;
1843                 name = "E7505";
1844                 break;
1845         case PCI_DEVICE_ID_INTEL_7205_0:
1846                 bridge->driver = &intel_7505_driver;
1847                 name = "E7205";
1848                 break;
1849         default:
1850                 if (cap_ptr)
1851                         printk(KERN_WARNING PFX "Unsupported Intel chipset (device id: %04x)\n",
1852                             pdev->device);
1853                 agp_put_bridge(bridge);
1854                 return -ENODEV;
1855         };
1856
1857         bridge->dev = pdev;
1858         bridge->capndx = cap_ptr;
1859
1860         if (bridge->driver == &intel_810_driver)
1861                 bridge->dev_private_data = &intel_i810_private;
1862         else if (bridge->driver == &intel_830_driver)
1863                 bridge->dev_private_data = &intel_i830_private;
1864
1865         printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n", name);
1866
1867         /*
1868         * The following fixes the case where the BIOS has "forgotten" to
1869         * provide an address range for the GART.
1870         * 20030610 - hamish@zot.org
1871         */
1872         r = &pdev->resource[0];
1873         if (!r->start && r->end) {
1874                 if (pci_assign_resource(pdev, 0)) {
1875                         printk(KERN_ERR PFX "could not assign resource 0\n");
1876                         agp_put_bridge(bridge);
1877                         return -ENODEV;
1878                 }
1879         }
1880
1881         /*
1882         * If the device has not been properly setup, the following will catch
1883         * the problem and should stop the system from crashing.
1884         * 20030610 - hamish@zot.org
1885         */
1886         if (pci_enable_device(pdev)) {
1887                 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
1888                 agp_put_bridge(bridge);
1889                 return -ENODEV;
1890         }
1891
1892         /* Fill in the mode register */
1893         if (cap_ptr) {
1894                 pci_read_config_dword(pdev,
1895                                 bridge->capndx+PCI_AGP_STATUS,
1896                                 &bridge->mode);
1897         }
1898
1899         pci_set_drvdata(pdev, bridge);
1900         return agp_add_bridge(bridge);
1901
1902 fail:
1903         printk(KERN_ERR PFX "Detected an Intel %s chipset, "
1904                 "but could not find the secondary device.\n", name);
1905         agp_put_bridge(bridge);
1906         return -ENODEV;
1907 }
1908
1909 static void __devexit agp_intel_remove(struct pci_dev *pdev)
1910 {
1911         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1912
1913         agp_remove_bridge(bridge);
1914
1915         if (intel_i810_private.i810_dev)
1916                 pci_dev_put(intel_i810_private.i810_dev);
1917         if (intel_i830_private.i830_dev)
1918                 pci_dev_put(intel_i830_private.i830_dev);
1919
1920         agp_put_bridge(bridge);
1921 }
1922
1923 #ifdef CONFIG_PM
1924 static int agp_intel_resume(struct pci_dev *pdev)
1925 {
1926         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1927
1928         pci_restore_state(pdev);
1929
1930         if (bridge->driver == &intel_generic_driver)
1931                 intel_configure();
1932         else if (bridge->driver == &intel_850_driver)
1933                 intel_850_configure();
1934         else if (bridge->driver == &intel_845_driver)
1935                 intel_845_configure();
1936         else if (bridge->driver == &intel_830mp_driver)
1937                 intel_830mp_configure();
1938         else if (bridge->driver == &intel_915_driver)
1939                 intel_i915_configure();
1940         else if (bridge->driver == &intel_830_driver)
1941                 intel_i830_configure();
1942         else if (bridge->driver == &intel_810_driver)
1943                 intel_i810_configure();
1944         else if (bridge->driver == &intel_i965_driver)
1945                 intel_i915_configure();
1946
1947         return 0;
1948 }
1949 #endif
1950
1951 static struct pci_device_id agp_intel_pci_table[] = {
1952 #define ID(x)                                           \
1953         {                                               \
1954         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
1955         .class_mask     = ~0,                           \
1956         .vendor         = PCI_VENDOR_ID_INTEL,          \
1957         .device         = x,                            \
1958         .subvendor      = PCI_ANY_ID,                   \
1959         .subdevice      = PCI_ANY_ID,                   \
1960         }
1961         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
1962         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
1963         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
1964         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
1965         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
1966         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
1967         ID(PCI_DEVICE_ID_INTEL_82815_MC),
1968         ID(PCI_DEVICE_ID_INTEL_82820_HB),
1969         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
1970         ID(PCI_DEVICE_ID_INTEL_82830_HB),
1971         ID(PCI_DEVICE_ID_INTEL_82840_HB),
1972         ID(PCI_DEVICE_ID_INTEL_82845_HB),
1973         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
1974         ID(PCI_DEVICE_ID_INTEL_82850_HB),
1975         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
1976         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
1977         ID(PCI_DEVICE_ID_INTEL_82860_HB),
1978         ID(PCI_DEVICE_ID_INTEL_82865_HB),
1979         ID(PCI_DEVICE_ID_INTEL_82875_HB),
1980         ID(PCI_DEVICE_ID_INTEL_7505_0),
1981         ID(PCI_DEVICE_ID_INTEL_7205_0),
1982         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
1983         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
1984         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
1985         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
1986         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
1987         ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
1988         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
1989         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
1990         { }
1991 };
1992
1993 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
1994
1995 static struct pci_driver agp_intel_pci_driver = {
1996         .name           = "agpgart-intel",
1997         .id_table       = agp_intel_pci_table,
1998         .probe          = agp_intel_probe,
1999         .remove         = __devexit_p(agp_intel_remove),
2000 #ifdef CONFIG_PM
2001         .resume         = agp_intel_resume,
2002 #endif
2003 };
2004
2005 static int __init agp_intel_init(void)
2006 {
2007         if (agp_off)
2008                 return -EINVAL;
2009         return pci_register_driver(&agp_intel_pci_driver);
2010 }
2011
2012 static void __exit agp_intel_cleanup(void)
2013 {
2014         pci_unregister_driver(&agp_intel_pci_driver);
2015 }
2016
2017 module_init(agp_intel_init);
2018 module_exit(agp_intel_cleanup);
2019
2020 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2021 MODULE_LICENSE("GPL and additional rights");