arch/sparc64/kernel/pci_fire.c

   1 /* pci_fire.c: Sun4u platform PCI-E controller support.
   2  *
   3  * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
   4  */
   5 #include <linux/kernel.h>
   6 #include <linux/pci.h>
   7 #include <linux/slab.h>
   8 #include <linux/init.h>
   9
  10 #include <asm/pbm.h>
  11 #include <asm/oplib.h>
  12 #include <asm/prom.h>
  13
  14 #include "pci_impl.h"
  15
  16 #define fire_read(__reg) \
  17 ({      u64 __ret; \
  18         __asm__ __volatile__("ldxa [%1] %2, %0" \
  19                              : "=r" (__ret) \
  20                              : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
  21                              : "memory"); \
  22         __ret; \
  23 })
  24 #define fire_write(__reg, __val) \
  25         __asm__ __volatile__("stxa %0, [%1] %2" \
  26                              : /* no outputs */ \
  27                              : "r" (__val), "r" (__reg), \
  28                                "i" (ASI_PHYS_BYPASS_EC_E) \
  29                              : "memory")
  30
  31 /* Fire config space address format is nearly identical to
  32  * that of SCHIZO and PSYCHO, except that in order to accomodate
  33  * PCI-E extended config space the encoding can handle 12 bits
  34  * of register address:
  35  *
  36  *  32     28 27 20 19    15 14      12 11  2  1 0
  37  * -------------------------------------------------
  38  * |0 0 0 0 0| bus | device | function | reg | 0 0 |
  39  * -------------------------------------------------
  40  */
  41 #define FIRE_CONFIG_BASE(PBM)   ((PBM)->config_space)
  42 #define FIRE_CONFIG_ENCODE(BUS, DEVFN, REG)     \
  43         (((unsigned long)(BUS)   << 20) |       \
  44          ((unsigned long)(DEVFN) << 12)  |      \
  45          ((unsigned long)(REG)))
  46
  47 static void *fire_pci_config_mkaddr(struct pci_pbm_info *pbm,
  48                                       unsigned char bus,
  49                                       unsigned int devfn,
  50                                       int where)
  51 {
  52         if (!pbm)
  53                 return NULL;
  54         return (void *)
  55                 (FIRE_CONFIG_BASE(pbm) |
  56                  FIRE_CONFIG_ENCODE(bus, devfn, where));
  57 }
  58
  59 /* FIRE PCI configuration space accessors. */
  60
  61 static int fire_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
  62                              int where, int size, u32 *value)
  63 {
  64         struct pci_pbm_info *pbm = bus_dev->sysdata;
  65         unsigned char bus = bus_dev->number;
  66         u32 *addr;
  67         u16 tmp16;
  68         u8 tmp8;
  69
  70         if (bus_dev == pbm->pci_bus && devfn == 0x00)
  71                 return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
  72                                                     size, value);
  73         switch (size) {
  74         case 1:
  75                 *value = 0xff;
  76                 break;
  77         case 2:
  78                 *value = 0xffff;
  79                 break;
  80         case 4:
  81                 *value = 0xffffffff;
  82                 break;
  83         }
  84
  85         addr = fire_pci_config_mkaddr(pbm, bus, devfn, where);
  86         if (!addr)
  87                 return PCIBIOS_SUCCESSFUL;
  88
  89         switch (size) {
  90         case 1:
  91                 pci_config_read8((u8 *)addr, &tmp8);
  92                 *value = tmp8;
  93                 break;
  94
  95         case 2:
  96                 if (where & 0x01) {
  97                         printk("pci_read_config_word: misaligned reg [%x]\n",
  98                                where);
  99                         return PCIBIOS_SUCCESSFUL;
 100                 }
 101                 pci_config_read16((u16 *)addr, &tmp16);
 102                 *value = tmp16;
 103                 break;
 104
 105         case 4:
 106                 if (where & 0x03) {
 107                         printk("pci_read_config_dword: misaligned reg [%x]\n",
 108                                where);
 109                         return PCIBIOS_SUCCESSFUL;
 110                 }
 111
 112                 pci_config_read32(addr, value);
 113                 break;
 114         }
 115         return PCIBIOS_SUCCESSFUL;
 116 }
 117
 118 static int fire_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 119                               int where, int size, u32 value)
 120 {
 121         struct pci_pbm_info *pbm = bus_dev->sysdata;
 122         unsigned char bus = bus_dev->number;
 123         u32 *addr;
 124
 125         if (bus_dev == pbm->pci_bus && devfn == 0x00)
 126                 return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
 127                                                      size, value);
 128         addr = fire_pci_config_mkaddr(pbm, bus, devfn, where);
 129         if (!addr)
 130                 return PCIBIOS_SUCCESSFUL;
 131
 132         switch (size) {
 133         case 1:
 134                 pci_config_write8((u8 *)addr, value);
 135                 break;
 136
 137         case 2:
 138                 if (where & 0x01) {
 139                         printk("pci_write_config_word: misaligned reg [%x]\n",
 140                                where);
 141                         return PCIBIOS_SUCCESSFUL;
 142                 }
 143                 pci_config_write16((u16 *)addr, value);
 144                 break;
 145
 146         case 4:
 147                 if (where & 0x03) {
 148                         printk("pci_write_config_dword: misaligned reg [%x]\n",
 149                                where);
 150                         return PCIBIOS_SUCCESSFUL;
 151                 }
 152
 153                 pci_config_write32(addr, value);
 154         }
 155         return PCIBIOS_SUCCESSFUL;
 156 }
 157
 158 static struct pci_ops pci_fire_ops = {
 159         .read   =       fire_read_pci_cfg,
 160         .write  =       fire_write_pci_cfg,
 161 };
 162
 163 static void pbm_scan_bus(struct pci_controller_info *p,
 164                          struct pci_pbm_info *pbm)
 165 {
 166         pbm->pci_bus = pci_scan_one_pbm(pbm);
 167 }
 168
 169 static void pci_fire_scan_bus(struct pci_controller_info *p)
 170 {
 171         struct device_node *dp;
 172
 173         if ((dp = p->pbm_A.prom_node) != NULL)
 174                 pbm_scan_bus(p, &p->pbm_A);
 175
 176         if ((dp = p->pbm_B.prom_node) != NULL)
 177                 pbm_scan_bus(p, &p->pbm_B);
 178
 179         /* XXX register error interrupt handlers XXX */
 180 }
 181
 182 #define FIRE_IOMMU_CONTROL      0x40000UL
 183 #define FIRE_IOMMU_TSBBASE      0x40008UL
 184 #define FIRE_IOMMU_FLUSH        0x40100UL
 185 #define FIRE_IOMMU_FLUSHINV     0x40100UL
 186
 187 static void pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
 188 {
 189         struct iommu *iommu = pbm->iommu;
 190         u32 vdma[2], dma_mask;
 191         u64 control;
 192         int tsbsize;
 193
 194         /* No virtual-dma property on these guys, use largest size.  */
 195         vdma[0] = 0xc0000000; /* base */
 196         vdma[1] = 0x40000000; /* size */
 197         dma_mask = 0xffffffff;
 198         tsbsize = 128;
 199
 200         /* Register addresses. */
 201         iommu->iommu_control  = pbm->pbm_regs + FIRE_IOMMU_CONTROL;
 202         iommu->iommu_tsbbase  = pbm->pbm_regs + FIRE_IOMMU_TSBBASE;
 203         iommu->iommu_flush    = pbm->pbm_regs + FIRE_IOMMU_FLUSH;
 204         iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV;
 205
 206         /* We use the main control/status register of FIRE as the write
 207          * completion register.
 208          */
 209         iommu->write_complete_reg = pbm->controller_regs + 0x410000UL;
 210
 211         /*
 212          * Invalidate TLB Entries.
 213          */
 214         fire_write(iommu->iommu_flushinv, ~(u64)0);
 215
 216         pci_iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask);
 217
 218         fire_write(iommu->iommu_tsbbase, __pa(iommu->page_table) | 0x7UL);
 219
 220         control = fire_read(iommu->iommu_control);
 221         control |= (0x00000400 /* TSB cache snoop enable */     |
 222                     0x00000300 /* Cache mode */                 |
 223                     0x00000002 /* Bypass enable */              |
 224                     0x00000001 /* Translation enable */);
 225         fire_write(iommu->iommu_control, control);
 226 }
 227
 228 /* Based at pbm->controller_regs */
 229 #define FIRE_PARITY_CONTROL     0x470010UL
 230 #define  FIRE_PARITY_ENAB       0x8000000000000000UL
 231 #define FIRE_FATAL_RESET_CTL    0x471028UL
 232 #define  FIRE_FATAL_RESET_SPARE 0x0000000004000000UL
 233 #define  FIRE_FATAL_RESET_MB    0x0000000002000000UL
 234 #define  FIRE_FATAL_RESET_CPE   0x0000000000008000UL
 235 #define  FIRE_FATAL_RESET_APE   0x0000000000004000UL
 236 #define  FIRE_FATAL_RESET_PIO   0x0000000000000040UL
 237 #define  FIRE_FATAL_RESET_JW    0x0000000000000004UL
 238 #define  FIRE_FATAL_RESET_JI    0x0000000000000002UL
 239 #define  FIRE_FATAL_RESET_JR    0x0000000000000001UL
 240 #define FIRE_CORE_INTR_ENABLE   0x471800UL
 241
 242 /* Based at pbm->pbm_regs */
 243 #define FIRE_TLU_CTRL           0x80000UL
 244 #define  FIRE_TLU_CTRL_TIM      0x00000000da000000UL
 245 #define  FIRE_TLU_CTRL_QDET     0x0000000000000100UL
 246 #define  FIRE_TLU_CTRL_CFG      0x0000000000000001UL
 247 #define FIRE_TLU_DEV_CTRL       0x90008UL
 248 #define FIRE_TLU_LINK_CTRL      0x90020UL
 249 #define FIRE_TLU_LINK_CTRL_CLK  0x0000000000000040UL
 250 #define FIRE_LPU_RESET          0xe2008UL
 251 #define FIRE_LPU_LLCFG          0xe2200UL
 252 #define  FIRE_LPU_LLCFG_VC0     0x0000000000000100UL
 253 #define FIRE_LPU_FCTRL_UCTRL    0xe2240UL
 254 #define  FIRE_LPU_FCTRL_UCTRL_N 0x0000000000000002UL
 255 #define  FIRE_LPU_FCTRL_UCTRL_P 0x0000000000000001UL
 256 #define FIRE_LPU_TXL_FIFOP      0xe2430UL
 257 #define FIRE_LPU_LTSSM_CFG2     0xe2788UL
 258 #define FIRE_LPU_LTSSM_CFG3     0xe2790UL
 259 #define FIRE_LPU_LTSSM_CFG4     0xe2798UL
 260 #define FIRE_LPU_LTSSM_CFG5     0xe27a0UL
 261 #define FIRE_DMC_IENAB          0x31800UL
 262 #define FIRE_DMC_DBG_SEL_A      0x53000UL
 263 #define FIRE_DMC_DBG_SEL_B      0x53008UL
 264 #define FIRE_PEC_IENAB          0x51800UL
 265
 266 static void pci_fire_hw_init(struct pci_pbm_info *pbm)
 267 {
 268         u64 val;
 269
 270         fire_write(pbm->controller_regs + FIRE_PARITY_CONTROL,
 271                    FIRE_PARITY_ENAB);
 272
 273         fire_write(pbm->controller_regs + FIRE_FATAL_RESET_CTL,
 274                    (FIRE_FATAL_RESET_SPARE |
 275                     FIRE_FATAL_RESET_MB |
 276                     FIRE_FATAL_RESET_CPE |
 277                     FIRE_FATAL_RESET_APE |
 278                     FIRE_FATAL_RESET_PIO |
 279                     FIRE_FATAL_RESET_JW |
 280                     FIRE_FATAL_RESET_JI |
 281                     FIRE_FATAL_RESET_JR));
 282
 283         fire_write(pbm->controller_regs + FIRE_CORE_INTR_ENABLE, ~(u64)0);
 284
 285         val = fire_read(pbm->pbm_regs + FIRE_TLU_CTRL);
 286         val |= (FIRE_TLU_CTRL_TIM |
 287                 FIRE_TLU_CTRL_QDET |
 288                 FIRE_TLU_CTRL_CFG);
 289         fire_write(pbm->pbm_regs + FIRE_TLU_CTRL, val);
 290         fire_write(pbm->pbm_regs + FIRE_TLU_DEV_CTRL, 0);
 291         fire_write(pbm->pbm_regs + FIRE_TLU_LINK_CTRL,
 292                    FIRE_TLU_LINK_CTRL_CLK);
 293
 294         fire_write(pbm->pbm_regs + FIRE_LPU_RESET, 0);
 295         fire_write(pbm->pbm_regs + FIRE_LPU_LLCFG,
 296                    FIRE_LPU_LLCFG_VC0);
 297         fire_write(pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL,
 298                    (FIRE_LPU_FCTRL_UCTRL_N |
 299                     FIRE_LPU_FCTRL_UCTRL_P));
 300         fire_write(pbm->pbm_regs + FIRE_LPU_TXL_FIFOP,
 301                    ((0xffff << 16) | (0x0000 << 0)));
 302         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2, 3000000);
 303         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3, 500000);
 304         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4,
 305                    (2 << 16) | (140 << 8));
 306         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5, 0);
 307
 308         fire_write(pbm->pbm_regs + FIRE_DMC_IENAB, ~(u64)0);
 309         fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_A, 0);
 310         fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_B, 0);
 311
 312         fire_write(pbm->pbm_regs + FIRE_PEC_IENAB, ~(u64)0);
 313 }
 314
 315 static void pci_fire_pbm_init(struct pci_controller_info *p,
 316                                 struct device_node *dp, u32 portid)
 317 {
 318         const struct linux_prom64_registers *regs;
 319         struct pci_pbm_info *pbm;
 320         const u32 *ino_bitmap;
 321         const unsigned int *busrange;
 322
 323         if ((portid & 1) == 0)
 324                 pbm = &p->pbm_A;
 325         else
 326                 pbm = &p->pbm_B;
 327
 328         pbm->portid = portid;
 329         pbm->parent = p;
 330         pbm->prom_node = dp;
 331         pbm->name = dp->full_name;
 332
 333         regs = of_get_property(dp, "reg", NULL);
 334         pbm->pbm_regs = regs[0].phys_addr;
 335         pbm->controller_regs = regs[1].phys_addr - 0x410000UL;
 336
 337         printk("%s: SUN4U PCIE Bus Module\n", pbm->name);
 338
 339         pci_determine_mem_io_space(pbm);
 340
 341         ino_bitmap = of_get_property(dp, "ino-bitmap", NULL);
 342         pbm->ino_bitmap = (((u64)ino_bitmap[1] << 32UL) |
 343                            ((u64)ino_bitmap[0] <<  0UL));
 344
 345         busrange = of_get_property(dp, "bus-range", NULL);
 346         pbm->pci_first_busno = busrange[0];
 347         pbm->pci_last_busno = busrange[1];
 348
 349         pci_fire_hw_init(pbm);
 350         pci_fire_pbm_iommu_init(pbm);
 351 }
 352
 353 static inline int portid_compare(u32 x, u32 y)
 354 {
 355         if (x == (y ^ 1))
 356                 return 1;
 357         return 0;
 358 }
 359
 360 void fire_pci_init(struct device_node *dp, const char *model_name)
 361 {
 362         struct pci_controller_info *p;
 363         u32 portid = of_getintprop_default(dp, "portid", 0xff);
 364         struct iommu *iommu;
 365
 366         for (p = pci_controller_root; p; p = p->next) {
 367                 struct pci_pbm_info *pbm;
 368
 369                 if (p->pbm_A.prom_node && p->pbm_B.prom_node)
 370                         continue;
 371
 372                 pbm = (p->pbm_A.prom_node ?
 373                        &p->pbm_A :
 374                        &p->pbm_B);
 375
 376                 if (portid_compare(pbm->portid, portid)) {
 377                         pci_fire_pbm_init(p, dp, portid);
 378                         return;
 379                 }
 380         }
 381
 382         p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
 383         if (!p)
 384                 goto fatal_memory_error;
 385
 386         iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
 387         if (!iommu)
 388                 goto fatal_memory_error;
 389
 390         p->pbm_A.iommu = iommu;
 391
 392         iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
 393         if (!iommu)
 394                 goto fatal_memory_error;
 395
 396         p->pbm_B.iommu = iommu;
 397
 398         p->next = pci_controller_root;
 399         pci_controller_root = p;
 400
 401         p->index = pci_num_controllers++;
 402
 403         p->scan_bus = pci_fire_scan_bus;
 404         /* XXX MSI support XXX */
 405         p->pci_ops = &pci_fire_ops;
 406
 407         /* Like PSYCHO and SCHIZO we have a 2GB aligned area
 408          * for memory space.
 409          */
 410         pci_memspace_mask = 0x7fffffffUL;
 411
 412         pci_fire_pbm_init(p, dp, portid);
 413         return;
 414
 415 fatal_memory_error:
 416         prom_printf("PCI_FIRE: Fatal memory allocation error.\n");
 417         prom_halt();
 418 }