arch/sh/kernel/cpu/sh4/probe.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4/probe.c
   3  *
   4  * CPU Subtype Probing for SH-4.
   5  *
   6  * Copyright (C) 2001 - 2006  Paul Mundt
   7  * Copyright (C) 2003  Richard Curnow
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/io.h>
  15 #include <asm/processor.h>
  16 #include <asm/cache.h>
  17
  18 int __init detect_cpu_and_cache_system(void)
  19 {
  20         unsigned long pvr, prr, cvr;
  21         unsigned long size;
  22
  23         static unsigned long sizes[16] = {
  24                 [1] = (1 << 12),
  25                 [2] = (1 << 13),
  26                 [4] = (1 << 14),
  27                 [8] = (1 << 15),
  28                 [9] = (1 << 16)
  29         };
  30
  31         pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff;
  32         prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
  33         cvr = (ctrl_inl(CCN_CVR));
  34
  35         /*
  36          * Setup some sane SH-4 defaults for the icache
  37          */
  38         current_cpu_data.icache.way_incr        = (1 << 13);
  39         current_cpu_data.icache.entry_shift     = 5;
  40         current_cpu_data.icache.sets            = 256;
  41         current_cpu_data.icache.ways            = 1;
  42         current_cpu_data.icache.linesz          = L1_CACHE_BYTES;
  43
  44         /*
  45          * And again for the dcache ..
  46          */
  47         current_cpu_data.dcache.way_incr        = (1 << 14);
  48         current_cpu_data.dcache.entry_shift     = 5;
  49         current_cpu_data.dcache.sets            = 512;
  50         current_cpu_data.dcache.ways            = 1;
  51         current_cpu_data.dcache.linesz          = L1_CACHE_BYTES;
  52
  53         /*
  54          * Setup some generic flags we can probe
  55          * (L2 and DSP detection only work on SH-4A)
  56          */
  57         if (((pvr >> 16) & 0xff) == 0x10) {
  58                 if ((cvr & 0x02000000) == 0)
  59                         current_cpu_data.flags |= CPU_HAS_L2_CACHE;
  60                 if ((cvr & 0x10000000) == 0)
  61                         current_cpu_data.flags |= CPU_HAS_DSP;
  62
  63                 current_cpu_data.flags |= CPU_HAS_LLSC;
  64         }
  65
  66         /* FPU detection works for everyone */
  67         if ((cvr & 0x20000000) == 1)
  68                 current_cpu_data.flags |= CPU_HAS_FPU;
  69
  70         /* Mask off the upper chip ID */
  71         pvr &= 0xffff;
  72
  73         /*
  74          * Probe the underlying processor version/revision and
  75          * adjust cpu_data setup accordingly.
  76          */
  77         switch (pvr) {
  78         case 0x205:
  79                 current_cpu_data.type = CPU_SH7750;
  80                 current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
  81                                    CPU_HAS_PERF_COUNTER;
  82                 break;
  83         case 0x206:
  84                 current_cpu_data.type = CPU_SH7750S;
  85                 current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
  86                                    CPU_HAS_PERF_COUNTER;
  87                 break;
  88         case 0x1100:
  89                 current_cpu_data.type = CPU_SH7751;
  90                 current_cpu_data.flags |= CPU_HAS_FPU;
  91                 break;
  92         case 0x2000:
  93                 current_cpu_data.type = CPU_SH73180;
  94                 current_cpu_data.icache.ways = 4;
  95                 current_cpu_data.dcache.ways = 4;
  96                 current_cpu_data.flags |= CPU_HAS_LLSC;
  97                 break;
  98         case 0x2001:
  99         case 0x2004:
 100                 current_cpu_data.type = CPU_SH7770;
 101                 current_cpu_data.icache.ways = 4;
 102                 current_cpu_data.dcache.ways = 4;
 103
 104                 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
 105                 break;
 106         case 0x2006:
 107         case 0x200A:
 108                 if (prr == 0x61)
 109                         current_cpu_data.type = CPU_SH7781;
 110                 else
 111                         current_cpu_data.type = CPU_SH7780;
 112
 113                 current_cpu_data.icache.ways = 4;
 114                 current_cpu_data.dcache.ways = 4;
 115
 116                 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
 117                                    CPU_HAS_LLSC;
 118                 break;
 119         case 0x3000:
 120         case 0x3003:
 121         case 0x3009:
 122                 current_cpu_data.type = CPU_SH7343;
 123                 current_cpu_data.icache.ways = 4;
 124                 current_cpu_data.dcache.ways = 4;
 125                 current_cpu_data.flags |= CPU_HAS_LLSC;
 126                 break;
 127         case 0x3004:
 128         case 0x3007:
 129                 current_cpu_data.type = CPU_SH7785;
 130                 current_cpu_data.icache.ways = 4;
 131                 current_cpu_data.dcache.ways = 4;
 132                 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
 133                                           CPU_HAS_LLSC;
 134                 break;
 135         case 0x3008:
 136                 if (prr == 0xa0) {
 137                         current_cpu_data.type = CPU_SH7722;
 138                         current_cpu_data.icache.ways = 4;
 139                         current_cpu_data.dcache.ways = 4;
 140                         current_cpu_data.flags |= CPU_HAS_LLSC;
 141                 }
 142                 break;
 143         case 0x8000:
 144                 current_cpu_data.type = CPU_ST40RA;
 145                 current_cpu_data.flags |= CPU_HAS_FPU;
 146                 break;
 147         case 0x8100:
 148                 current_cpu_data.type = CPU_ST40GX1;
 149                 current_cpu_data.flags |= CPU_HAS_FPU;
 150                 break;
 151         case 0x700:
 152                 current_cpu_data.type = CPU_SH4_501;
 153                 current_cpu_data.icache.ways = 2;
 154                 current_cpu_data.dcache.ways = 2;
 155                 break;
 156         case 0x600:
 157                 current_cpu_data.type = CPU_SH4_202;
 158                 current_cpu_data.icache.ways = 2;
 159                 current_cpu_data.dcache.ways = 2;
 160                 current_cpu_data.flags |= CPU_HAS_FPU;
 161                 break;
 162         case 0x500 ... 0x501:
 163                 switch (prr) {
 164                 case 0x10:
 165                         current_cpu_data.type = CPU_SH7750R;
 166                         break;
 167                 case 0x11:
 168                         current_cpu_data.type = CPU_SH7751R;
 169                         break;
 170                 case 0x50 ... 0x5f:
 171                         current_cpu_data.type = CPU_SH7760;
 172                         break;
 173                 }
 174
 175                 current_cpu_data.icache.ways = 2;
 176                 current_cpu_data.dcache.ways = 2;
 177
 178                 current_cpu_data.flags |= CPU_HAS_FPU;
 179
 180                 break;
 181         default:
 182                 current_cpu_data.type = CPU_SH_NONE;
 183                 break;
 184         }
 185
 186 #ifdef CONFIG_SH_DIRECT_MAPPED
 187         current_cpu_data.icache.ways = 1;
 188         current_cpu_data.dcache.ways = 1;
 189 #endif
 190
 191 #ifdef CONFIG_CPU_HAS_PTEA
 192         current_cpu_data.flags |= CPU_HAS_PTEA;
 193 #endif
 194
 195         /*
 196          * On anything that's not a direct-mapped cache, look to the CVR
 197          * for I/D-cache specifics.
 198          */
 199         if (current_cpu_data.icache.ways > 1) {
 200                 size = sizes[(cvr >> 20) & 0xf];
 201                 current_cpu_data.icache.way_incr        = (size >> 1);
 202                 current_cpu_data.icache.sets            = (size >> 6);
 203
 204         }
 205
 206         /* And the rest of the D-cache */
 207         if (current_cpu_data.dcache.ways > 1) {
 208                 size = sizes[(cvr >> 16) & 0xf];
 209                 current_cpu_data.dcache.way_incr        = (size >> 1);
 210                 current_cpu_data.dcache.sets            = (size >> 6);
 211         }
 212
 213         /*
 214          * Setup the L2 cache desc
 215          *
 216          * SH-4A's have an optional PIPT L2.
 217          */
 218         if (current_cpu_data.flags & CPU_HAS_L2_CACHE) {
 219                 /*
 220                  * Size calculation is much more sensible
 221                  * than it is for the L1.
 222                  *
 223                  * Sizes are 128KB, 258KB, 512KB, and 1MB.
 224                  */
 225                 size = (cvr & 0xf) << 17;
 226
 227                 BUG_ON(!size);
 228
 229                 current_cpu_data.scache.way_incr        = (1 << 16);
 230                 current_cpu_data.scache.entry_shift     = 5;
 231                 current_cpu_data.scache.ways            = 4;
 232                 current_cpu_data.scache.linesz          = L1_CACHE_BYTES;
 233
 234                 current_cpu_data.scache.entry_mask      =
 235                         (current_cpu_data.scache.way_incr -
 236                          current_cpu_data.scache.linesz);
 237
 238                 current_cpu_data.scache.sets            = size /
 239                         (current_cpu_data.scache.linesz *
 240                          current_cpu_data.scache.ways);
 241
 242                 current_cpu_data.scache.way_size        =
 243                         (current_cpu_data.scache.sets *
 244                          current_cpu_data.scache.linesz);
 245         }
 246
 247         return 0;
 248 }