2 * Copyright 2008-2011 IBM Corporation.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #include <linux/cpu.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/kernel.h>
15 #include <linux/msi.h>
17 #include <linux/slab.h>
18 #include <linux/smp.h>
19 #include <linux/spinlock.h>
20 #include <linux/types.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
36 struct device_node *dn;
39 unsigned long *bitmap;
50 #define to_wsp_ics(ics) container_of(ics, struct wsp_ics, ics)
52 #define INT_SRC_LAYER_BUID_REG(base) ((base) + 0x00)
53 #define IODA_TBL_ADDR_REG(base) ((base) + 0x18)
54 #define IODA_TBL_DATA_REG(base) ((base) + 0x20)
55 #define XIVE_UPDATE_REG(base) ((base) + 0x28)
56 #define ICS_INT_CAPS_REG(base) ((base) + 0x30)
58 #define TBL_AUTO_INCREMENT ((1UL << 63) | (1UL << 15))
59 #define TBL_SELECT_XIST (1UL << 48)
60 #define TBL_SELECT_XIVT (1UL << 49)
62 #define IODA_IRQ(irq) ((irq) & (0x7FFULL)) /* HRM 5.1.3.4 */
64 #define XIST_REQUIRED 0x8
65 #define XIST_REJECTED 0x4
66 #define XIST_PRESENTED 0x2
67 #define XIST_PENDING 0x1
69 #define XIVE_SERVER_SHIFT 42
70 #define XIVE_SERVER_MASK 0xFFFFULL
71 #define XIVE_PRIORITY_MASK 0xFFULL
72 #define XIVE_PRIORITY_SHIFT 32
73 #define XIVE_WRITE_ENABLE (1ULL << 63)
76 * The docs refer to a 6 bit field called ChipID, which consists of a
77 * 3 bit NodeID and a 3 bit ChipID. On WSP the ChipID is always zero
78 * so we ignore it, and every where we use "chip id" in this code we
81 #define WSP_ICS_CHIP_SHIFT 17
84 static struct wsp_ics *ics_list;
87 /* ICS Source controller accessors */
89 static u64 wsp_ics_get_xive(struct wsp_ics *ics, unsigned int irq)
94 spin_lock_irqsave(&ics->lock, flags);
95 out_be64(IODA_TBL_ADDR_REG(ics->regs), TBL_SELECT_XIVT | IODA_IRQ(irq));
96 xive = in_be64(IODA_TBL_DATA_REG(ics->regs));
97 spin_unlock_irqrestore(&ics->lock, flags);
102 static void wsp_ics_set_xive(struct wsp_ics *ics, unsigned int irq, u64 xive)
104 xive &= ~XIVE_ADDR_MASK;
105 xive |= (irq & XIVE_ADDR_MASK);
106 xive |= XIVE_WRITE_ENABLE;
108 out_be64(XIVE_UPDATE_REG(ics->regs), xive);
111 static u64 xive_set_server(u64 xive, unsigned int server)
113 u64 mask = ~(XIVE_SERVER_MASK << XIVE_SERVER_SHIFT);
116 xive |= (server & XIVE_SERVER_MASK) << XIVE_SERVER_SHIFT;
121 static u64 xive_set_priority(u64 xive, unsigned int priority)
123 u64 mask = ~(XIVE_PRIORITY_MASK << XIVE_PRIORITY_SHIFT);
126 xive |= (priority & XIVE_PRIORITY_MASK) << XIVE_PRIORITY_SHIFT;
133 /* Find logical CPUs within mask on a given chip and store result in ret */
134 void cpus_on_chip(int chip_id, cpumask_t *mask, cpumask_t *ret)
137 struct device_node *cpu_dn, *dn;
141 for_each_cpu(cpu, mask) {
142 cpu_dn = of_get_cpu_node(cpu, NULL);
146 prop = of_get_property(cpu_dn, "at-node", NULL);
152 dn = of_find_node_by_phandle(*prop);
155 chip = wsp_get_chip_id(dn);
157 cpumask_set_cpu(cpu, ret);
163 /* Store a suitable CPU to handle a hwirq in the ics->hwirq_cpu_map cache */
164 static int cache_hwirq_map(struct wsp_ics *ics, unsigned int hwirq,
165 const cpumask_t *affinity)
167 cpumask_var_t avail, newmask;
168 int ret = -ENOMEM, cpu, cpu_rover = 0, target;
169 int index = hwirq - ics->hwirq_start;
172 BUG_ON(index < 0 || index >= ics->count);
174 if (!ics->hwirq_cpu_map)
177 if (!distribute_irqs) {
178 ics->hwirq_cpu_map[hwirq - ics->hwirq_start] = xics_default_server;
182 /* Allocate needed CPU masks */
183 if (!alloc_cpumask_var(&avail, GFP_KERNEL))
185 if (!alloc_cpumask_var(&newmask, GFP_KERNEL))
188 /* Find PBus attached to the source of this IRQ */
189 nodeid = (hwirq >> WSP_ICS_CHIP_SHIFT) & 0x3; /* 12:14 */
191 /* Find CPUs that could handle this IRQ */
193 cpumask_and(avail, cpu_online_mask, affinity);
195 cpumask_copy(avail, cpu_online_mask);
197 /* Narrow selection down to logical CPUs on the same chip */
198 cpus_on_chip(nodeid, avail, newmask);
200 /* Ensure we haven't narrowed it down to 0 */
201 if (unlikely(cpumask_empty(newmask))) {
202 if (unlikely(cpumask_empty(avail))) {
206 cpumask_copy(newmask, avail);
209 /* Choose a CPU out of those we narrowed it down to in round robin */
210 target = hwirq % cpumask_weight(newmask);
211 for_each_cpu(cpu, newmask) {
212 if (cpu_rover++ >= target) {
213 ics->hwirq_cpu_map[index] = get_hard_smp_processor_id(cpu);
219 /* Shouldn't happen */
223 free_cpumask_var(newmask);
225 free_cpumask_var(avail);
228 ics->hwirq_cpu_map[index] = cpumask_first(cpu_online_mask);
229 pr_warning("Error, falling hwirq 0x%x routing back to CPU %i\n",
230 hwirq, ics->hwirq_cpu_map[index]);
235 static void alloc_irq_map(struct wsp_ics *ics)
239 ics->hwirq_cpu_map = kmalloc(sizeof(int) * ics->count, GFP_KERNEL);
240 if (!ics->hwirq_cpu_map) {
241 pr_warning("Allocate hwirq_cpu_map failed, "
242 "IRQ balancing disabled\n");
246 for (i=0; i < ics->count; i++)
247 ics->hwirq_cpu_map[i] = xics_default_server;
250 static int get_irq_server(struct wsp_ics *ics, unsigned int hwirq)
252 int index = hwirq - ics->hwirq_start;
254 BUG_ON(index < 0 || index >= ics->count);
256 if (!ics->hwirq_cpu_map)
257 return xics_default_server;
259 return ics->hwirq_cpu_map[index];
261 #else /* !CONFIG_SMP */
262 static int cache_hwirq_map(struct wsp_ics *ics, unsigned int hwirq,
263 const cpumask_t *affinity)
268 static int get_irq_server(struct wsp_ics *ics, unsigned int hwirq)
270 return xics_default_server;
273 static void alloc_irq_map(struct wsp_ics *ics) { }
276 static void wsp_chip_unmask_irq(struct irq_data *d)
278 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
283 if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
290 server = get_irq_server(ics, hw_irq);
292 xive = wsp_ics_get_xive(ics, hw_irq);
293 xive = xive_set_server(xive, server);
294 xive = xive_set_priority(xive, DEFAULT_PRIORITY);
295 wsp_ics_set_xive(ics, hw_irq, xive);
298 static unsigned int wsp_chip_startup(struct irq_data *d)
301 wsp_chip_unmask_irq(d);
305 static void wsp_mask_real_irq(unsigned int hw_irq, struct wsp_ics *ics)
309 if (hw_irq == XICS_IPI)
314 xive = wsp_ics_get_xive(ics, hw_irq);
315 xive = xive_set_server(xive, xics_default_server);
316 xive = xive_set_priority(xive, LOWEST_PRIORITY);
317 wsp_ics_set_xive(ics, hw_irq, xive);
320 static void wsp_chip_mask_irq(struct irq_data *d)
322 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
323 struct wsp_ics *ics = d->chip_data;
325 if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
328 wsp_mask_real_irq(hw_irq, ics);
331 static int wsp_chip_set_affinity(struct irq_data *d,
332 const struct cpumask *cpumask, bool force)
334 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
339 if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
345 xive = wsp_ics_get_xive(ics, hw_irq);
348 * For the moment only implement delivery to all cpus or one cpu.
349 * Get current irq_server for the given irq
351 ret = cache_hwirq_map(ics, hw_irq, cpumask);
354 cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask);
355 pr_warning("%s: No online cpus in the mask %s for irq %d\n",
356 __func__, cpulist, d->irq);
358 } else if (ret == -ENOMEM) {
359 pr_warning("%s: Out of memory\n", __func__);
363 xive = xive_set_server(xive, get_irq_server(ics, hw_irq));
364 wsp_ics_set_xive(ics, hw_irq, xive);
366 return IRQ_SET_MASK_OK;
369 static struct irq_chip wsp_irq_chip = {
371 .irq_startup = wsp_chip_startup,
372 .irq_mask = wsp_chip_mask_irq,
373 .irq_unmask = wsp_chip_unmask_irq,
374 .irq_set_affinity = wsp_chip_set_affinity
377 static int wsp_ics_host_match(struct ics *ics, struct device_node *dn)
379 /* All ICSs in the system implement a global irq number space,
380 * so match against them all. */
381 return of_device_is_compatible(dn, "ibm,ppc-xics");
384 static int wsp_ics_match_hwirq(struct wsp_ics *wsp_ics, unsigned int hwirq)
386 if (hwirq >= wsp_ics->hwirq_start &&
387 hwirq < wsp_ics->hwirq_start + wsp_ics->count)
393 static int wsp_ics_map(struct ics *ics, unsigned int virq)
395 struct wsp_ics *wsp_ics = to_wsp_ics(ics);
396 unsigned int hw_irq = virq_to_hw(virq);
399 if (!wsp_ics_match_hwirq(wsp_ics, hw_irq))
402 irq_set_chip_and_handler(virq, &wsp_irq_chip, handle_fasteoi_irq);
404 irq_set_chip_data(virq, wsp_ics);
406 spin_lock_irqsave(&wsp_ics->lock, flags);
407 bitmap_allocate_region(wsp_ics->bitmap, hw_irq - wsp_ics->hwirq_start, 0);
408 spin_unlock_irqrestore(&wsp_ics->lock, flags);
413 static void wsp_ics_mask_unknown(struct ics *ics, unsigned long hw_irq)
415 struct wsp_ics *wsp_ics = to_wsp_ics(ics);
417 if (!wsp_ics_match_hwirq(wsp_ics, hw_irq))
420 pr_err("%s: IRQ %lu (real) is invalid, disabling it.\n", __func__, hw_irq);
421 wsp_mask_real_irq(hw_irq, wsp_ics);
424 static long wsp_ics_get_server(struct ics *ics, unsigned long hw_irq)
426 struct wsp_ics *wsp_ics = to_wsp_ics(ics);
428 if (!wsp_ics_match_hwirq(wsp_ics, hw_irq))
431 return get_irq_server(wsp_ics, hw_irq);
434 /* HW Number allocation API */
436 static struct wsp_ics *wsp_ics_find_dn_ics(struct device_node *dn)
438 struct device_node *iparent;
441 iparent = of_irq_find_parent(dn);
443 pr_err("wsp_ics: Failed to find interrupt parent!\n");
447 for(i = 0; i < num_ics; i++) {
448 if(ics_list[i].dn == iparent)
453 pr_err("wsp_ics: Unable to find parent bitmap!\n");
460 int wsp_ics_alloc_irq(struct device_node *dn, int num)
465 ics = wsp_ics_find_dn_ics(dn);
469 /* Fast, but overly strict if num isn't a power of two */
470 order = get_count_order(num);
472 spin_lock_irq(&ics->lock);
473 offset = bitmap_find_free_region(ics->bitmap, ics->count, order);
474 spin_unlock_irq(&ics->lock);
479 return offset + ics->hwirq_start;
482 void wsp_ics_free_irq(struct device_node *dn, unsigned int irq)
486 ics = wsp_ics_find_dn_ics(dn);
490 spin_lock_irq(&ics->lock);
491 bitmap_release_region(ics->bitmap, irq, 0);
492 spin_unlock_irq(&ics->lock);
497 static int __init wsp_ics_bitmap_setup(struct wsp_ics *ics,
498 struct device_node *dn)
504 size = BITS_TO_LONGS(ics->count) * sizeof(long);
505 ics->bitmap = kzalloc(size, GFP_KERNEL);
507 pr_err("wsp_ics: ENOMEM allocating IRQ bitmap!\n");
511 spin_lock_init(&ics->lock);
513 p = of_get_property(dn, "available-ranges", &len);
515 /* FIXME this should be a WARN() once mambo is updated */
516 pr_err("wsp_ics: No available-ranges defined for %s\n",
521 if (len % (2 * sizeof(u32)) != 0) {
522 /* FIXME this should be a WARN() once mambo is updated */
523 pr_err("wsp_ics: Invalid available-ranges for %s\n",
528 bitmap_fill(ics->bitmap, ics->count);
530 for (i = 0; i < len / sizeof(u32); i += 2) {
531 start = of_read_number(p + i, 1);
532 count = of_read_number(p + i + 1, 1);
534 pr_devel("%s: start: %d count: %d\n", __func__, start, count);
536 if ((start + count) > (ics->hwirq_start + ics->count) ||
537 start < ics->hwirq_start) {
538 pr_err("wsp_ics: Invalid range! -> %d to %d\n",
539 start, start + count);
543 for (j = 0; j < count; j++)
544 bitmap_release_region(ics->bitmap,
545 (start + j) - ics->hwirq_start, 0);
548 /* Ensure LSIs are not available for allocation */
549 bitmap_allocate_region(ics->bitmap, ics->lsi_base,
550 get_count_order(ics->lsi_count));
555 static int __init wsp_ics_setup(struct wsp_ics *ics, struct device_node *dn)
557 u32 lsi_buid, msi_buid, msi_base, msi_count;
563 p = of_get_property(dn, "interrupt-ranges", &len);
564 if (!p || len < (2 * sizeof(u32))) {
565 pr_err("wsp_ics: No/bad interrupt-ranges found on %s\n",
570 if (len > (2 * sizeof(u32))) {
571 pr_err("wsp_ics: Multiple ics ranges not supported.\n");
575 regs = of_iomap(dn, 0);
577 pr_err("wsp_ics: of_iomap(%s) failed\n", dn->full_name);
581 ics->hwirq_start = of_read_number(p, 1);
582 ics->count = of_read_number(p + 1, 1);
585 ics->chip_id = wsp_get_chip_id(dn);
586 if (WARN_ON(ics->chip_id < 0))
589 /* Get some informations about the critter */
590 caps = in_be64(ICS_INT_CAPS_REG(ics->regs));
591 buid = in_be64(INT_SRC_LAYER_BUID_REG(ics->regs));
592 ics->lsi_count = caps >> 56;
593 msi_count = (caps >> 44) & 0x7ff;
595 /* Note: LSI BUID is 9 bits, but really only 3 are BUID and the
596 * rest is mixed in the interrupt number. We store the whole
599 lsi_buid = (buid >> 48) & 0x1ff;
600 ics->lsi_base = (ics->chip_id << WSP_ICS_CHIP_SHIFT) | lsi_buid << 5;
601 msi_buid = (buid >> 37) & 0x7;
602 msi_base = (ics->chip_id << WSP_ICS_CHIP_SHIFT) | msi_buid << 11;
604 pr_info("wsp_ics: Found %s\n", dn->full_name);
605 pr_info("wsp_ics: irq range : 0x%06llx..0x%06llx\n",
606 ics->hwirq_start, ics->hwirq_start + ics->count - 1);
607 pr_info("wsp_ics: %4d LSIs : 0x%06x..0x%06x\n",
608 ics->lsi_count, ics->lsi_base,
609 ics->lsi_base + ics->lsi_count - 1);
610 pr_info("wsp_ics: %4d MSIs : 0x%06x..0x%06x\n",
612 msi_base + msi_count - 1);
614 /* Let's check the HW config is sane */
615 if (ics->lsi_base < ics->hwirq_start ||
616 (ics->lsi_base + ics->lsi_count) > (ics->hwirq_start + ics->count))
617 pr_warning("wsp_ics: WARNING ! LSIs out of interrupt-ranges !\n");
618 if (msi_base < ics->hwirq_start ||
619 (msi_base + msi_count) > (ics->hwirq_start + ics->count))
620 pr_warning("wsp_ics: WARNING ! MSIs out of interrupt-ranges !\n");
622 /* We don't check for overlap between LSI and MSI, which will happen
623 * if we use the same BUID, I'm not sure yet how legit that is.
626 rc = wsp_ics_bitmap_setup(ics, dn);
632 ics->dn = of_node_get(dn);
635 for(i = 0; i < ics->count; i++)
636 wsp_mask_real_irq(ics->hwirq_start + i, ics);
638 ics->ics.map = wsp_ics_map;
639 ics->ics.mask_unknown = wsp_ics_mask_unknown;
640 ics->ics.get_server = wsp_ics_get_server;
641 ics->ics.host_match = wsp_ics_host_match;
643 xics_register_ics(&ics->ics);
648 static void __init wsp_ics_set_default_server(void)
650 struct device_node *np;
653 /* Find the server number for the boot cpu. */
654 np = of_get_cpu_node(boot_cpuid, NULL);
657 hwid = get_hard_smp_processor_id(boot_cpuid);
659 pr_info("wsp_ics: default server is %#x, CPU %s\n", hwid, np->full_name);
660 xics_default_server = hwid;
665 static int __init wsp_ics_init(void)
667 struct device_node *dn;
671 wsp_ics_set_default_server();
674 for_each_compatible_node(dn, NULL, "ibm,ppc-xics")
678 pr_err("wsp_ics: No ICS's found!\n");
682 ics_list = kmalloc(sizeof(*ics) * found, GFP_KERNEL);
684 pr_err("wsp_ics: No memory for structs.\n");
690 for_each_compatible_node(dn, NULL, "ibm,wsp-xics") {
691 rc = wsp_ics_setup(ics, dn);
698 if (found != num_ics) {
699 pr_err("wsp_ics: Failed setting up %d ICS's\n",
707 void __init wsp_init_irq(void)
712 /* We need to patch our irq chip's EOI to point to the right ICP */
713 wsp_irq_chip.irq_eoi = icp_ops->eoi;
716 #ifdef CONFIG_PCI_MSI
717 static void wsp_ics_msi_unmask_irq(struct irq_data *d)
719 wsp_chip_unmask_irq(d);
723 static unsigned int wsp_ics_msi_startup(struct irq_data *d)
725 wsp_ics_msi_unmask_irq(d);
729 static void wsp_ics_msi_mask_irq(struct irq_data *d)
732 wsp_chip_mask_irq(d);
736 * we do it this way because we reassinge default EOI handling in
739 static void wsp_ics_eoi(struct irq_data *data)
741 wsp_irq_chip.irq_eoi(data);
744 static struct irq_chip wsp_ics_msi = {
745 .name = "WSP ICS MSI",
746 .irq_startup = wsp_ics_msi_startup,
747 .irq_mask = wsp_ics_msi_mask_irq,
748 .irq_unmask = wsp_ics_msi_unmask_irq,
749 .irq_eoi = wsp_ics_eoi,
750 .irq_set_affinity = wsp_chip_set_affinity
753 void wsp_ics_set_msi_chip(unsigned int irq)
755 irq_set_chip(irq, &wsp_ics_msi);
758 void wsp_ics_set_std_chip(unsigned int irq)
760 irq_set_chip(irq, &wsp_irq_chip);
762 #endif /* CONFIG_PCI_MSI */